JP7260444B2 - memory access device - Google Patents

Description

The present invention relates to a memory access device that accesses a memory having multiple banks.

Random Access Memory (RAM) is used as the main memory of a computer. A memory access device reads data from the RAM and writes data to the RAM in response to a request from a CPU (Central Processing Unit). For example, Patent Literature 1 discloses a memory control circuit that writes data to a memory having multiple banks.

As the processing speed of CPUs (Central Processing Units) improves, efforts are being made to shorten the computation time. However, the time taken by the memory access device to read data from the RAM sometimes occupies nearly half of the CPU's operation time. Since reading data from RAM is a bottleneck in shortening the operation time, it is required to shorten the time to read data from RAM.

Japanese Patent Application Laid-Open No. 2004-199608

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access device capable of shortening the data read time.

In order to solve the above problems, a first invention is a memory access device for accessing memory. The memory comprises a main area and a sub-area. The main area stores first to N-th data with data numbers 1 to N (N is a natural number of 3 or more), and a plurality of unit areas each set to one of a plurality of banks. including. The sub-region stores second to N-th data and includes a plurality of unit regions each set in one of a plurality of banks. Each of the unit areas of the main area stores two pieces of data whose top data has an odd data number and whose data numbers are consecutive. Each unit area of the sub-area stores two pieces of data whose leading data has an even data number and whose data numbers are consecutive. The memory access device includes a determination section, an area determination section, and a read control section. The judging unit judges whether or not the smallest data number among the data numbers of the two or more pieces of data is an odd number when reading two or more consecutive pieces of data out of the first to Nth data. The area determination unit determines to read two or more data from the unit area of the main area when the determination unit determines that the smallest data number is an odd number. The region determination unit determines to read two or more pieces of data from the unit region of the sub-region when the determination unit determines that the smallest data number is an even number. The read control unit reads two or more pieces of data from the unit area determined by the area determination unit.

According to the first invention, the read control unit does not have to access a plurality of banks when reading data from one unit area. Therefore, the first invention can shorten the data read time.

A second invention is the first invention, wherein the determination unit determines whether or not the number of data equal to or greater than 2 is an odd number. If the determination unit determines that the minimum data number is odd and the number of data equal to or greater than 2 is odd, the region determination unit removes the maximum data number among the data numbers equal to or greater than 2. Data corresponding to the data number is read from the unit area of the main area, and data corresponding to the maximum data number is read from the unit area of the sub area.

According to the second invention, it is possible to prevent data other than two or more data to be read from being read from the memory.

A third invention is the first or second invention, wherein the determination unit determines whether or not the number of data equal to or greater than 2 is an odd number. If the determination unit determines that the minimum data number is even and the number of data equal to or greater than 2 is odd, the area determination unit removes the maximum data number among the data numbers equal to or greater than 2. Data corresponding to the data number is read from the unit areas of the sub-areas, and data corresponding to the maximum data number is read from the unit areas of the main area.

According to the third aspect, it is possible to prevent data other than two or more data to be read from being read from the memory.

A fourth invention is the first to third inventions, further comprising a write control section. The write control unit writes two pieces of data having an odd data number and consecutive data numbers among the first to Nth data into the unit area of the main area, and writes the first data among the second to Nth data. Two data whose data numbers are even numbers and whose data numbers are consecutive are written in the unit area of the sub-area.

According to the fourth invention, the first to N-th data can be written into the memory so that the number of accesses to the bank can be reduced when the read control section reads data from the unit area.

A fifth invention is a memory access method comprising a main area and a sub-area. The main area stores first to N-th data with data numbers 1 to N (N is a natural number of 3 or more), and a plurality of unit areas each set to one of a plurality of banks. including. The sub-region stores second to N-th data and includes a plurality of unit regions each set in one of a plurality of banks. Each of the unit areas of the main area stores two pieces of data whose top data has an odd data number and whose data numbers are consecutive. Each unit area of the sub-area stores two pieces of data whose leading data has an even data number and whose data numbers are consecutive. The memory access method comprises steps a), b), and c). The a) step receives an instruction to read data stored in the memory. The step b) determines whether or not the smallest data number among the data numbers of the two or more pieces of data is an odd number when a readout instruction for two or more consecutive pieces of data among the first to Nth data is received. . In step c), if the smallest data number is determined to be an odd number, data of 2 or more are read from the unit area of the main area, and if the smallest data number is determined to be an even number, the data of 2 or more are read. is read from the unit area of the sub-area.

A fifth invention is used for the first invention.

According to the present invention, it is possible to provide a memory access device capable of shortening the data read time.

1 is a functional block diagram showing the configuration of a simulation system according to an embodiment of the present invention; FIG. 2 is a functional block diagram showing the configuration of the simulator shown in FIG. 1; FIG. 3 is a diagram showing an example of parameters used by the calculation unit shown in FIG. 2; FIG. 3 is a diagram showing a main area and sub-areas set in the memory shown in FIG. 2; FIG. 3 is a functional block diagram showing the configuration of the memory access device shown in FIG. 2; FIG. FIG. 3 is a flow chart showing an operation when the memory access device shown in FIG. 2 reads parameters; FIG. FIG. 4 is a diagram showing an example of a memory in which unit areas are set using a plurality of banks; FIG. 3 is a flow chart showing an operation when the memory access device shown in FIG. 2 writes parameters; FIG. FIG. 2 is a diagram showing a CPU bus configuration; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated.

[1. composition]
[1.1. Configuration of simulation system 100]
FIG. 1 is a functional block diagram showing the configuration of a simulation system 100 according to one embodiment of the invention. Referring to FIG. 1, a simulation system 100 is used to evaluate an ECU (Electronic Control Unit) 2 mounted on a vehicle such as an automobile. A simulation system 100 includes a simulator 1 , an ECU 2 , a user terminal 3 and a relay device 4 .

Simulator 1 is connected to ECU 2 . The simulator 1 simulates operations of a motor and an inverter mounted on the vehicle in accordance with control signals output from the ECU 2 .

The ECU 2 is an evaluation target in the simulation system 100 . The ECU 2 acquires an operation instruction from the user terminal 3 via the relay device 4 and outputs a control signal to the simulator 1 according to the acquired operation instruction.

The user terminal 3 is a computer used by an evaluator of the ECU 2 . The user terminal 3 outputs operation instructions to the simulator 1 and the ECU 2 via the relay device 4 . The user terminal 3 acquires the simulated computation result from the simulator 1 via the relay device 4 and displays the acquired simulated computation result on a monitor (not shown).

The relay device 4 relays communication between the simulator 1 and the user terminal 3 and relays communication between the ECU 2 and the user terminal 3 .

In the simulation system 100, the communication method between devices is not particularly limited. For example, the simulator 1 communicates with the ECU 2 using CAN (Controller Area Network). The relay device 4 communicates with the simulator 1 and user terminals using a LAN (Local Area Network). The relay device 4 communicates with the ECU 2 via a protocol conversion device (not shown). The protocol conversion device mutually converts communication conforming to LAN and communication conforming to CAN. The relay device 4 communicates with the protocol conversion device using a LAN. The ECU 2 communicates with the protocol converter using CAN.

[1.2. Configuration of Simulator 1]
FIG. 2 is a functional block diagram showing the configuration of the simulator 1 shown in FIG. 1. As shown in FIG. With reference to FIG. 2, simulator 1 includes an arithmetic unit 11, a memory access device 12, a memory controller 13, and a memory .

The calculation unit 11 receives a PWM (Pulse Width Modulation) signal 22V from the ECU 2 and simulates the operation of the inverter and motor mounted on the vehicle based on the received PWM signal 22V.

Specifically, the calculation unit 11 simulates the operation of the inverter based on the received PWM signal 22V. The PWM signal 22V is a control signal for the inverter to generate three-phase alternating current from direct current, and includes signals corresponding to voltages of the U-phase, V-phase and W-phase. The calculation unit 11 generates the current signal 24i as a result of simulating the operation of the inverter. The current signal 24i indicates a three-phase AC current supplied from the inverter to the motor, and includes current values of each of U-phase, V-phase and W-phase.

After generating the current signal 24 i , the calculation unit 11 simulates the operation of the motor based on the generated current signal 24 i and the parameter 25 P received from the memory access device 12 . Although details will be described later, the parameter 25P is stored in the memory 14 . The computing unit 11 generates the position signal 24θ as a result of simulating the operation of the motor. The position signal 24θ indicates the rotational position of the rotor included in the motor.

The calculation unit 11 receives the initial conditions 23 from the user terminal 3 and starts simulating the operation of the inverter and the motor based on the received initial conditions 23 . For example, the initial conditions 23 include the initial rotational position of the rotor included in the motor and the state of switching elements included in the inverter.

The motor simulation will be described in more detail. FIG. 3 is a table 51 showing an example of parameters 25P used for simulation by the calculation unit 11. As shown in FIG. Referring to FIG. 3, a data number is assigned to each parameter 25P. The data number is a natural number of 1 or more and corresponds to the identification information of the parameter 25P. There are five types of parameters 25P, one of flux linkage, d-axis current, q-axis current, d-axis inductance, and q-axis inductance. These five types of parameters 25P are uniquely determined by the U-phase current, the V-phase current, the W-phase current, and the rotational position of the rotor.

The calculation unit 11 uses the interlinkage magnetic flux, d-axis current, q-axis current, d-axis inductance, and q-axis inductance to calculate the U-phase current, V-phase current, W-phase current, and rotational position of the rotor at one time. calculate. The calculation unit 11 uses the calculated U-phase current, the V-phase current, the W-phase current, and the parameter 25P specified based on the rotational position of the rotor to calculate the U-phase current at a time after the first time, A V-phase current, a W-phase current, and the rotational position of the rotor are calculated.

Referring to FIG. 2 again, memory access device 12 receives current signal 24 i and position signal 24 θ from calculation unit 11 . The memory access device 12 outputs the read instruction 27 to the memory controller 13 to acquire the parameter 25P corresponding to the received current signal 24i and position signal 24θ from the memory 14 .

When the memory access device 12 acquires a plurality of parameters 25P from the user terminal 3, the memory access device 12 writes the acquired parameters 25P to the memory 14 by outputting a write instruction 28 to the memory controller 13. FIG. The parameter 25P is written into the memory 14 when the simulator 1 starts operating.

That is, in the simulator 1, the simulated calculation of the motor operation using the parameters 25P and the specification of the parameters 25P based on the result of the simulated calculation are repeated. As a result, the operation of the motor mounted on the vehicle can be virtually realized.

The memory controller 13 accesses the memory 14 under the control of the memory access device 12 . Specifically, when the memory controller 13 receives the read instruction 27 from the memory access device 12 , it reads data from the address included in the received read instruction 27 . When receiving the write instruction 28 from the memory access device 12 , the memory controller 13 writes the data included in the received write instruction 28 to the memory 14 .

The memory 14 is a RAM (Random Access Memory) and is the main memory of the simulator 1 . The memory 14 stores programs executed by the simulator 1 and parameters 25P. Therefore, although not shown in FIG. 2, the computing unit 11 may access the memory 14 via the memory controller 13 . The memory 14 comprises banks 141-143. In this embodiment, each of banks 141-143 is a memory module.

[1.3. Storage area of memory 14]
FIG. 4 is a diagram showing an example of data stored in memory 14 shown in FIG. Referring to FIG. 4, memory 14 includes a main area 41 and a sub-area 42 . The main area 41 and sub-area 42 are used to store the parameters 25P and are divided into a plurality of unit areas. When reading the parameters 25P from the memory 14, the memory access device 12 reads all the parameters 25P included in the unit area. The addresses shown in FIG. 4 are logical addresses.

The main area 41 stores parameters 25P with data numbers "1" to "360". The sub-area 42 stores parameters 25P with data numbers "2" to "360". The data number of the parameter 25P is indicated using "k".

The main area 41 is divided into a plurality of unit areas 61 . Each of unit regions 61 is set in one of banks 141-143. For example, the unit area 61A is a storage area in which addresses from “0001” to “0002” are set, and is set in the bank 141 . The unit area 61B is a storage area in which addresses from “0003” to “0004” are set, and is set in the bank 142 . The unit area 61C is a storage area in which addresses from “0005” to “0006” are set, and is set in the bank 143 .

Each unit area 61 stores two parameters 25P with consecutive data numbers. For example, the unit area 61A stores parameters 25P whose data numbers are "1" to "2". The unit area 61B stores parameters 25P whose data numbers are "3" to "4". The unit area 61C stores parameters 25P whose data numbers are "5" to "6". That is, the data number of the parameter 25P stored at the top address of the unit area 61 is odd.

The sub-region 42 is divided into a plurality of unit regions 62 like the main region 41 . Each of the plurality of unit regions 62 is set in one of banks 141-143. For example, the unit area 62A is a storage area in which addresses from "2001" to "2002" are set, and is set in the bank 141. FIG. The unit area 61B is a storage area in which addresses from “2003” to “2004” are set, and is set in the bank 142 . The unit area 61C is a storage area in which addresses from “2005” to “2006” are set, and is set in the bank 143 .

Each unit area 62 stores two parameters 25P with consecutive data numbers. For example, the unit area 62A stores parameters 25P with data numbers "2" to "3". The unit area 62B stores parameters 25P whose data numbers are "4" to "5". The unit area 62C stores parameters 25P with data numbers "6" to "7". That is, in the unit area 62, the data number of the parameter 25P stored at the top address is an even number.

[1.4. Configuration of memory access device 12]
FIG. 5 is a functional block diagram showing a configuration of memory access device 12 shown in FIG. 2. Referring to FIG. Referring to FIG. 5 , memory access device 12 includes data number identification unit 121 , determination unit 122 , area determination unit 123 , read control unit 124 and write control unit 125 .

The data number identification unit 121 receives the current signal 24 i and the position signal 24 θ from the calculation unit 11 . The data number identification unit 121 determines the data number of the parameter 25P corresponding to the received current signal 24i and position signal 24θ. Since the calculation unit 11 performs simulation using five types of parameters 25P, the data number identification unit 121 determines five data numbers corresponding to the five types. The data number identification unit 121 outputs number information 31 recording the determined data number to the determination unit 122 and the area determination unit 123 .

The determination unit 122 identifies the leading data number among the data numbers recorded in the number information 31 . The determination unit 122 determines whether or not the specified top data number is an odd number. Judgment section 122 outputs judgment information 32 indicating whether or not the data number of the specified head data is odd to area determination section 123 .

Based on the number information 31 received from the data number identification unit 121 and the determination information 32 received from the determination unit 122, the area determination unit 123 determines the address from which the parameter 25P is read.

Specifically, when the determination information 32 indicates that the leading data number is an odd number, the region determination unit 123 selects the data number specified by the data number specifying unit 121 that corresponds to the last data number. It is determined to read the parameters 25P from the unit area of the main area 41 except for the parameters 25P to be read. The area determination unit 123 determines to read the parameter 25P corresponding to the last data number from the unit area of the sub-area 42 .

If the determination information 32 indicates that the leading data number is an even number, the area determination unit 123 excludes the parameter 25P corresponding to the last data number from among the data numbers specified by the data number specifying unit 121. It is decided to read the parameter 25P from the unit area of the sub-area 42 . The area determination unit 123 determines to read the parameter 25P corresponding to the last data number from the unit area of the main area 41 .

The area determination unit 123 outputs the readout address 33 indicating each determined unit area to the readout control unit 124 . The read address 33 is determined based on the address data 34 that associates the data number of the parameter 25P with the address where the parameter 25P is written. The address data 34 is generated by the write controller 125 when the parameter 25P is written to the memory 14. FIG.

The read control unit 124 receives the read address 33 from the area determination unit 123 and reads the parameter 25P from the memory 14 based on the received read address 33 . Specifically, the read control unit 124 outputs the read instruction 27 including the received read address 33 to the memory controller 13 . The readout control unit 124 receives the parameter 25P as a response to the readout instruction 27 and outputs the received parameter 25P to the calculation unit 11 .

When receiving the parameter 25P from the user terminal 3, the write control unit 125 outputs to the memory controller 13 a write instruction 28 instructing the writing of the received parameter 25P. The write control unit 125 generates address data 34 and outputs the generated address data 34 to the area determination unit 123 . The address data 34 is data that associates the data number of the parameter 25P with the address in which the parameter 25P is written.

[2. motion]
[2.1. Operation when reading parameters]
FIG. 6 is a flow chart showing the operation when the memory access device 12 shown in FIG. 2 reads the parameter 25P. The operation of the memory access device 12 for reading the parameter 25P will be described with reference to FIGS. 3 to 6. FIG.

When the data number identification unit 121 receives the current signal 24i and the position signal 24θ from the calculation unit 11, the memory access device 12 starts the processing shown in FIG.

The data number identification unit 121 identifies the data number corresponding to the current signal 24i and the position signal 24θ received from the calculation unit 11 (step S101). Specifically, the data number specifying unit 121 holds a table 51 in which the current signal 24i and the position signal 24θ are associated with the data number of the parameter 25P. The data number specifying unit 121 refers to the table 51 shown in FIG. 3 to specify the data number of the parameter 25P corresponding to the current signal 24i and the position signal 24θ.

In step S101, data numbers corresponding to each of the flux linkage, d-axis current, q-axis current, d-axis inductance, and q-axis inductance are specified based on the current signal 24i and the position signal 24θ. That is, the data number identification unit 121 identifies five data numbers in step S101. The specified five data numbers are consecutive. The data number identification unit 121 outputs number information 31 recording five consecutive data numbers to the determination unit 122 and the area determination unit 123 .

Determination unit 122 receives number information 31 from data number identification unit 121 . The determination unit 122 identifies the leading data number and the trailing data number among the data numbers recorded in the received number information 31 (step S102). The leading data number is the smallest number among the data numbers recorded in the number information 31 . The data number at the end is the largest number among the data numbers recorded in the number information 31 . For example, when the data numbers included in the number information 31 are "3" to "7", the top data number is "3". The last data number is "7".

The determination unit 122 determines whether or not the number of parameters 25P read from the memory 14 is an odd number (step S103). Specifically, the determination unit 122 determines whether or not the value obtained by counting the data numbers recorded in the number information 31 is an odd number.

The operation of the memory access device 12 will now be described separately for when the number of parameters 25P read from the memory 14 is an odd number and when it is an even number.

(When the number of parameters 25P to be read is an odd number)
In order to determine from which of the main area 41 or the sub-area 42 the parameter 25P corresponding to the leading data number is to be read, the determination unit 122 determines whether the leading data number specified in step S102 is an odd number. It judges (step S104). The reason for changing the area from which the parameter 25P corresponding to the leading data number is read depending on whether the leading data number is an odd number will be described later.

If the leading data number is an odd number (Yes in step S104), the determination unit 122 determines that the number of parameters 25P to be read is an odd number and that the leading data number is an odd number. Output to the unit 123 .

Based on the judgment information 32 received from the judgment section 122, the area determination section 123 determines to read the parameter 25P corresponding to the data number excluding the last data number from the main area 41 (step S105). Based on the judgment information 32 received from the judgment section 122, the area determination section 123 determines to read the parameter 25P corresponding to the last data number from the sub-area 42 (step S106).

Steps S105 and S106 will be described in detail by taking as an example the case where the data numbers recorded in the number information 31 are "3" to "7".

Since the last data number is "7", the area determination unit 123 determines to read out from the main area 41 the unit areas in which the parameters 25P with data numbers "3" to "6" are recorded ( step S105). Since the memory access device 12 reads the parameter 25P for each unit area, the unit areas 61B and 61C set in the main area 41 are determined as read targets.

The area determining unit 123 determines to read the unit area in which the parameter 25P having the data number "7" is recorded from the sub area 42 (step S106). Since the memory access device 12 reads the parameter 25P for each unit area, the unit area 62C set in the sub-area 42 is determined as the read target.

As a result of steps S105 and S106, the area determination unit 123 outputs the read addresses 33 of the unit areas 61B, 61C, and 62C determined to be read targets to the read control unit 124 .

The read control unit 124 uses the read address 33 received from the area determination unit 123 to read the parameter 25P from the memory 14 (step S109). Specifically, the read control unit 124 generates a read instruction 27 including the read address 33 received from the area determination unit 123 and outputs the generated read instruction 27 to the memory controller 13 . The memory controller 13 reads the parameter 25P based on the read instruction 27 received from the area determination unit 123 and outputs the read parameter 25P to the read control unit 124 . The read control unit 124 outputs the parameters 25P received from the memory controller 13 to the calculation unit 11 .

When the data numbers recorded in the number information 31 are "3" to "7", the read control unit 124 first reads the unit area 61B and then reads the unit area 61C. Finally, the unit area 62C is read.

As a result, the parameter 25P whose data number is “6” is read from each of the main area 41 and the sub-area 42 . The parameter 25P whose data number is "6" is output to the calculation unit 11 twice. When the calculation unit 11 receives the same parameters 25P in duplicate, it discards one of the same parameters 25P.

The reason why the memory access device 12 reads out the parameters 25P whose data numbers are "6" to "7" from the sub-area 42 will be explained.

The read control unit 124 reads data for each unit area as described above. Therefore, assuming that the parameter 25P whose data number is "7" is read from the main area 41, the read control unit 124 reads the unit area 61D. The unit area 61D stores a parameter 25P with a data number of "7" and a parameter 25P with a data number of "8".

When reading the parameter 25P with the data number "7" from the main area 41, the read control unit 124 reads the parameter 25P with the data number "8" in addition to the parameter 25P with the data number "7". There is a need. Data number "8" does not correspond to data numbers "3" to "7" specified in step S101. If the parameter 25P whose data number is "8" is output to the calculation unit 11, the calculation unit 11 may perform an erroneous simulation.

Therefore, the memory access device 12 reads out the parameters 25P whose data numbers are “6” to “7” from the unit area 62C of the sub-area 42 . The parameter 25P whose data number is "6" is included in the data numbers "3" to "7" identified in step S101. In other words, by reading the parameters 25P with data numbers "6" to "7" from the sub-area 42, it is possible to prevent the calculation unit 11 from executing an erroneous simulation.

By reading the parameters 25P with data numbers "6" to "7" from the sub area 42, the memory access device 12 can prevent the operation unit 11, which is the host, from outputting the parameters 25P not requested. can.

The reason why the parameter 25P corresponding to the leading data number is read from the main area 41 when the leading data number is an odd number will be explained. If the leading data number is an odd number, the memory access device 12 stores the parameter 25P corresponding to the leading data number in the main area 41 in order to prevent the parameter 25P having a number other than the data number specified in step S101 from being read. read from

For example, assume that data numbers "3" to "7" are identified in step S101. In this assumption, if the unit area 62A in the sub-area 42 is determined to be read, the memory access device 12 needs to read the parameter 25P of data number "2" which was not specified in step S101. When the unit area 61B in the main area 41 is determined to be read, the memory access device 12 does not have to read the parameter 25P of the data number "2" that was not specified in step S101. As a result, the memory access device 12 can be prevented from outputting the parameter 25P not requested by the computing section 11, which is the host.

It returns to description of step S104. If the head data number is even (No in step S104), determination unit 122 reads determination information 32 indicating that the number of parameters 25P read from memory 14 is odd and that the head data number is even. is output to the region determination unit 123 .

Based on the determination information 32 received from the determination unit 122, the region determination unit 123 determines to read the parameters 25P corresponding to the data numbers excluding the last data number from the sub-region 42 (step S107). Based on the judgment information 32 received from the judgment section 122, the area determination section 123 determines to read the parameter 25P corresponding to the last data number from the main area 41 (step S108).

For example, when the data numbers recorded in the number information 31 are "4" to "8", the area determining unit 123 reads the parameters 25P with the data numbers "4" to "7" from the sub area 42. is determined (step S107). That is, the unit areas 62B and 62C set in the sub-area 42 are determined as read targets.

The area determination unit 123 determines to read the parameters 25P with data numbers "7" to "8" from the main area 41 (step S108). That is, the unit area 61D set in the main area 41 is determined to be read. The area determination unit 123 outputs the address 33 of each of the unit areas 62B, 62C, and 61C determined to be read targets to the read control unit 124 .

The read control unit 124 uses the address 33 received from the area determination unit 123 to read the parameter 25P from the memory 14 (step S109). The read control unit 124 outputs the read parameters 25P to the calculation unit 11 . As a result, the parameter 25P whose data number is “7” is read from each of the main area 41 and the sub-area 42 . The computing unit 11 discards one of the parameters received in duplicate, as described above. As a result, similarly to the case where the head data number is an odd number and the number of parameters to be read is an odd number, it is possible to prevent the computing unit 11, which is the host, from outputting parameters 25P not requested.

(When the number of parameters 25P to be read is an even number)
The operation of the memory access device 12 when the number of parameters 25P to be read is an even number (No in step S103) will be described. In this case, the determination unit 122 determines whether or not the top data number identified in step S102 is an odd number (step S110).

If the leading data number is an odd number (Yes in step S110), determination unit 122 sends determination information 32 indicating that the number of parameters to be read is an even number and that the leading data number is odd. 123.

Based on the determination information 32 received from the determination unit 122, the area determination unit 123 determines to read the parameter 25P corresponding to the data number recorded in the number information 31 from the main area 41 (step S111). For example, when the data numbers recorded in the number information 31 are "3" to "10", the area determination unit 123 determines the unit areas 61B to 61E as read targets. The area determination unit 123 outputs the addresses 33 corresponding to the unit areas 61B to 61E determined as read targets to the read control unit 124 .

Thus, when the number of parameters 25P to be read is even and the top data number is even, the memory access device 12 does not read the parameters 25P from the sub-area . This is because the memory access device 12 can read all the parameters 25P corresponding to the data numbers identified in step S101 without accessing the sub-area 42. FIG.

If the head data number is an even number (No in step S110), determination unit 122 sends determination information 32 indicating that the number of parameters to be read is an even number and that the head data number is even. 123.

Based on the determination information 32 received from the determination unit 122, the area determination unit 123 determines to read the parameter 25P corresponding to the data number recorded in the number information 31 from the sub-area 42 (step S112). For example, when the data numbers recorded in the number information 31 are "2" to "9", the area determination unit 123 determines the unit areas 62A to 62D as read targets. In this case, the memory access device 12 can read from the sub-area 42 all the parameters 25P corresponding to the data number specified in step S101. Memory access device 12 does not have to access main area 41 to read parameter 25P.

The read control unit 124 uses the address received from the area determination unit 123 to read the parameter 25P from the unit area determined in step S111 or S112 (step S109).

The reason why the parameter 25P corresponding to the leading data number is read from the sub-area 42 when the leading data number is an even number will be explained. If the leading data number is an even number, the memory access device 12 stores the parameter 25P corresponding to the leading data number in the sub-area 42 in order to prevent the parameter 25P with a number other than the data number specified in step S101 from being read. read from

For example, assume that data numbers "4" to "8" are identified in step S101. In this assumption, when the unit area 61B in the main area 41 is determined to be read, the memory access device 12 needs to read the parameter 25P of data number "3" which was not specified in step S101. When the unit area 62B in the sub-area 42 is determined to be read, the memory access device 12 does not have to read the parameter 25P with the data number "3". As a result, the memory access device 12 can be prevented from outputting the parameter 25P not requested by the computing section 11, which is the host.

As described above, when reading two consecutive parameters 25P, the memory access device 12 identifies the first data number in the parameters 25P to be read and the number of parameters 25P to be read. The memory access device 12 determines from which of the main area 41 or the sub area 42 to read the parameters 25P based on the specified first data number and the number of specified parameters 25P.

Thereby, the memory access device 12 can read the consecutive parameters 25P from the memory 14 at high speed. The reason why the memory access device 12 can read the continuous parameters 25P at high speed will be described in more detail below.

When one unit area is set by a plurality of banks, a delay occurs in reading data. FIG. 7 is a diagram showing an example of a memory including unit areas set by a plurality of banks.

Referring to FIG. 7, memory 14a has an address space from "2001" to "2010". Unit areas 63A to 63E are set in the memory 14a. Unit regions 63A and 63D are set in banks 141 and 142, respectively. Unit regions 63B and 63E are set in banks 142 and 143, respectively. The unit area 63C is set in the banks 143 and 141. FIG.

The data numbers of the parameters 25P stored in the unit area 63A are "1" to "2". The data numbers of the parameters 25P stored in the unit area 63B are "3" to "4". The data numbers of the parameters 25P stored in the unit area 63C are "5" to "6". The data numbers of the parameters 25P stored in the unit area 63D are "7" to "8". The data numbers of the parameters 25P stored in the unit area 63E are "9" to "10".

The operation of the memory access device 12 when reading the parameters 25P with data numbers "1" to "4" from the memory 14a shown in FIG. 7 will be described. The memory access device 12 reads the parameter 25P from the memory 14a for each unit area as described above.

First, the read control unit 124 instructs the memory controller 13 to read the unit area 63A. The memory controller 13 accesses the bank 141 to read the parameter 25P whose data number is "1", and accesses the bank 142 to read the parameter 25P whose data number is "2".

Next, the read control unit 124 instructs the memory controller 13 to read the unit area 63B. The memory controller 13 accesses the banks 142 and 143 to read the unit area 63B in the same manner as the unit area 63A.

The memory controller 13 must access multiple banks each time it reads a unit area. As a result, the round-trip delay time increases and the efficiency of reading the parameter 25P decreases. The round-trip delay time is the time from when the memory access device 12 instructs to read the parameter 25P to when the parameter 25P is acquired.

In contrast, memory 14 includes a primary area 41 and a secondary area 42 . The main region 41 and the subregion 42 include multiple unit regions. Each unit area is set in one of the banks 141 to 143 and stores two consecutive parameters 25P. In the unit area set in the main area 41, the top data number is an odd number. In the unit area set in the sub-area 42, the top data number is an even number.

If the leading data number is an odd number, the data corresponding to the data number excluding the trailing data number is read from the main area 41 . If the leading data number is an even number, the data corresponding to the data number excluding the trailing data number is read from the sub-area 42 . As a result, the memory access device 12 does not have to access a plurality of banks each time data is read from the unit area, so the parameter 25P can be read at high speed.

[2.2. Write parameter 25P]
FIG. 8 is a flow chart showing the operation of the memory access device 12 for writing the parameter 25P to the memory 14. As shown in FIG. The operation of the memory access device 12 for writing the parameter 25P will be described below with reference to FIGS. 4 and 8. FIG.

In the memory access device 12, the write controller 125 sets the address space of the memory 14 via the memory controller 13 (step S201). Specifically, the write control unit 125 sets the address space so that two consecutive logical addresses are assigned to one bank. For example, referring to FIG. 4, write control unit 125 assigns logical addresses “0001” and “0002” to bank 141 and assigns logical addresses “2001” and “2002” to bank 141 .

The write control unit 125 sets two consecutive logical addresses among the logical addresses set in step S201 to the unit area (step S202). Two consecutive logical addresses are addresses set in the same bank in step S201. As a result, unit areas 61 and 62 are set as shown in FIG.

The write control unit 125 allocates the unit area set in step S202 to either the main area 41 or the sub area 42 (step S203). In this embodiment, a plurality of unit areas with consecutive logical addresses are assigned to the main area 41 or the sub area 42 as shown in FIG. However, it is not prevented that the logical addresses of the unit areas assigned to the main area 41 or the subarea 42 are discontinuous.

The write controller 125 writes the parameters 25P with data numbers "1" to "360" in the unit area 61 set in the main area 41 in step S203 (step S204). At this time, the write control unit 125 writes two parameters 25P having consecutive data numbers to the unit area 61 . The data number of the parameter 25P written to the top address of the unit area 61 is an odd number. When the logical addresses of the unit area 61 are consecutive, the logical address of the storage area storing the parameter 25P increases as the data number increases, as shown in FIG.

The write control unit 125 writes the parameters 25P with data numbers "2" to "360" in the unit area 62 set in the sub area 42 in step S203 (step S205). At this time, the write control unit 125 writes two parameters 25P having consecutive data numbers into the unit area 62 . The data number of the parameter 25P written to the top address of the unit area 62 is an even number. When the logical addresses of the unit area 62 are consecutive, the logical address of the storage area storing the parameter 25P increases as the data number increases, as shown in FIG.

The write control unit 125 associates the data number of one parameter 25P with the logical address in which the one parameter 25P is written (step S206). As a result of step S206, address data 34 is generated. The write control section 125 outputs the generated address data 34 to the area determining section 123 . After that, the write control unit 125 terminates the write processing shown in FIG.

The write control unit 125 writes the parameter 25P into the memory 14 based on the flowchart shown in FIG. 8, so that the read control unit 124 can execute the processing shown in FIG. That is, the write control unit 125 can write the parameter 25P into the memory so that the read control unit 124 can reduce the number of bank accesses.

[Modification]
Although an example in which a plurality of parameters 25P are written in the memory 14 has been described in the above embodiment, the present invention is not limited to this. Data written to the memory 14 is not particularly limited. That is, the data to be written in the memory 14 may be the first to N-th data with data numbers 1 to N (N is a natural number of 3 or more). The main area 41 stores 1st to Nth data and includes a plurality of unit areas 61 each set in one of a plurality of banks. The sub-region 42 stores the 2nd to N-th data and includes a plurality of unit regions 62 each set in one of the plurality of banks.

Although the memory access device 12 is mounted on the simulator 1 in the above embodiment, it is not limited to this. The memory access device 12 may be installed in an information processing device in which the memory 14 is installed.

In the above embodiment, an example in which the memory 14 is a RAM has been described, but the present invention is not limited to this. The type of the memory 14 is not particularly limited as long as the memory access device 12 is a storage device to which data can be written and read.

Further, in the above embodiment, each functional block of the memory access device 12 may be individually integrated into one chip by a semiconductor device such as LSI, or may be integrated into one chip so as to include part or all of them. . Although LSI is used here, it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

The method of circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connections and settings of the circuit cells inside the LSI may be used.

Also, part or all of the processing executed by the memory access device 12 may be realized by a program. Part or all of the processing of each functional block in each of the above embodiments is performed by a central processing unit (CPU) in a computer. A program for performing each process is stored in a storage device such as a hard disk or ROM, and is read from the ROM or RAM and executed.

Further, each process of the above embodiment may be realized by hardware, or may be realized by software (including cases where it is realized together with an OS (operating system), middleware, or a predetermined library). . Furthermore, it may be realized by mixed processing of software and hardware.

For example, when each functional block of the memory access device 12 is implemented by software, the hardware configuration shown in FIG. Each functional unit may be realized by software processing using a hardware configuration that is described in the above).

Also, the execution order of the processing methods in the above embodiments is not limited to the description of the above embodiments, and the execution order may be changed without departing from the spirit of the invention.

A computer program that causes a computer to execute the method described above and a computer-readable recording medium that records the program are included in the scope of the present invention. Examples of computer-readable recording media include flexible disks, hard disks, CD-ROMs, MOs, DVDs, DVD-ROMs, DVD-RAMs, large-capacity DVDs, next-generation DVDs, and semiconductor memories. .

Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit of the present invention.

1 Simulator 11 Operation Unit 12 Memory Access Device 13 Memory Controller 14 Memory 121 Data Number Identification Unit 122 Judgment Unit 123 Area Determination Unit 124 Read Control Unit 125 Write Control Unit

Claims (5)

A memory access device for accessing memory,
The memory is
a main area that stores first to Nth data with data numbers of 1 to N (N is a natural number of 3 or more) and includes a plurality of unit areas each set in one of a plurality of banks; and,
a sub-region storing second to N-th data and including a plurality of unit regions each set in one of the plurality of banks;
each of the unit areas of the main area stores two pieces of data in which the data number of the leading data is an odd number and the data numbers are consecutive;
each of the unit areas of the sub-area stores two pieces of data in which the data number of the head data is an even number and the data numbers are consecutive;
The memory access device
a judging unit for judging whether or not the smallest data number among the data numbers of the two or more data is an odd number when reading two or more consecutive data out of the first to Nth data;
determining that the two or more pieces of data are read from the unit area of the main area when the determination unit determines that the minimum data number is an odd number, and determining that the minimum data number is an even number; an area determination unit that determines to read the two or more pieces of data from the unit area of the sub-area if determined by the unit;
a read control unit that reads the two or more pieces of data from the unit area determined by the area determination unit. 2. The memory access device according to claim 1, comprising:
The determination unit determines whether the number of the two or more data is an odd number,
If the determining unit determines that the minimum data number is an odd number and that the number of data of 2 or more is an odd number, the area determination unit determines that the data number of the data of 2 or more is the maximum reading data corresponding to the data numbers other than the data number from the unit area of the main area, and reading data corresponding to the maximum data number from the unit areas of the sub areas. 3. The memory access device according to claim 1 or 2,
The determination unit determines whether the number of the two or more data is an odd number,
If the determination unit determines that the minimum data number is an even number and that the number of data equal to or greater than 2 is an odd number, the region determination unit selects the maximum data number of the data equal to or greater than 2. reading data corresponding to the data numbers other than the data number from the unit area of the sub area, and reading data corresponding to the maximum data number from the unit area of the main area. The memory access device according to any one of claims 1 to 3, further comprising:
Two pieces of data having an odd data number of the leading data among the first to Nth data and consecutive data numbers are written in the unit area of the main area, and the data of the leading data among the second to Nth data. A memory access device comprising a write control unit that writes two pieces of data having even numbers and consecutive data numbers into the unit area of the sub-area. a main area that stores first to Nth data with data numbers of 1 to N (N is a natural number of 3 or more) and includes a plurality of unit areas each set in one of a plurality of banks; and a sub-area storing second to N-th data and including a plurality of unit areas each set in one of the plurality of banks, wherein
each of the unit areas of the main area stores two pieces of data in which the data number of the leading data is an odd number and the data numbers are consecutive;
each of the unit areas of the sub-area stores two pieces of data in which the data number of the head data is an even number and the data numbers are consecutive;
The memory access method includes:
receiving an instruction to read data stored in the memory;
determining whether or not the smallest data number among the data numbers of the two or more data is an odd number, when an instruction to read two or more consecutive data out of the first to Nth data is received;
When the minimum data number is determined to be an odd number, the data of 2 or more are read from the unit area of the main area, and when the minimum data number is determined to be an even number, the data of 2 or more from the unit area of the sub-area.

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