JP7259715B2 - pulse transformer - Google Patents

Description

The disclosure in this specification relates to a pulse transformer for driving a semiconductor switching device.

Patent Literature 1 discloses a printed coil having a configuration in which windings are formed by wiring patterns of printed circuit boards and printed circuit boards are stacked. Adjacent the substrate of the primary winding and the substrate of the secondary winding of the transformer improve the magnetic coupling.

JP-A-7-99123

In the transformer using the printed coils of Patent Document 1, some coils of adjacent printed circuit boards flow in the same direction, and the leakage magnetic flux is not canceled, resulting in a decrease in the degree of coupling. When the degree of coupling is lowered, resonance between the leakage inductance of the pulse transformer and the parasitic capacitance of the element causes the oscillation of the gate voltage to increase, leading to erroneous firing of the semiconductor switching element.

An object of the present disclosure is to provide a pulse transformer that has a high degree of coupling and can reduce the occurrence of false ignitions.

A pulse transformer according to an aspect of the present disclosure is a pulse transformer that drives a plurality of semiconductor switching elements (3, 4) with a pulse voltage from a driving IC (2), in which a primary winding (101 , 201), a plurality of secondary windings (102, 103, 202, 203) connected respectively to a plurality of semiconductor switching elements (3, 4), and the primary winding divided into at least three, A plurality of first wiring layers (L3, L5, L7) in which divided primary windings are respectively arranged, and a plurality of secondary windings are each divided into at least two and divided secondary windings. and a plurality of second wiring layers (L2, L4, L6, L8) in which lines are respectively arranged, wherein the plurality of first wiring layers and the plurality of second wiring layers are all alternately laminated. there is

According to this, the pulse transformer of the present disclosure can prevent deterioration of the degree of coupling and reduce the occurrence of false ignition.

The multiple aspects disclosed in this specification employ different technical means to achieve their respective objectives. Reference numerals in parentheses described in the claims and this section are intended to exemplify the correspondence with portions of the embodiments described later, and are not intended to limit the technical scope. Objects, features, and advantages disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings.

1 is a circuit diagram showing a schematic configuration example of a semiconductor module including a pulse transformer according to a first embodiment; FIG. FIG. 3 is a diagram showing layer-by-layer structures of a primary winding and a secondary winding of the pulse transformer according to the first embodiment; FIG. 2 is a cross-sectional view of the structure of the pulse transformer according to the first embodiment and a diagram showing the relationship between the strength of the magnetic field; FIG. 4 is a diagram showing a cross-sectional view of the structure of the pulse transformer shown in FIG. 3 and a comparative example with the strength of the magnetic field; FIG. 5 is a diagram showing another example of layer-by-layer structures of the primary and secondary windings of the pulse transformer according to the first embodiment; FIG. 6 is a diagram showing a cross-sectional view of the structure of the pulse transformer shown in FIG. 5; It is a figure which shows the structure of the primary winding of the pulse transformer concerning 2nd Embodiment, and a secondary winding for every layer. It is a figure which shows sectional drawing of the structure of the pulse transformer concerning 2nd Embodiment.

A number of embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding and/or related parts may be labeled with the same reference numerals or reference numerals differing by one hundred or more places. For corresponding and/or associated parts, reference can be made to the description of other embodiments.

(First embodiment)
A semiconductor module 1 shown in FIG. 1 includes a drive IC 2 , an upper arm element 3 , a lower arm element 4 , a microcomputer 6 and a pulse transformer 100 . Upper arm element 3 and lower arm element 4 correspond to semiconductor switching elements.

The pulse transformer 100 has a primary winding 101 connected to the driving IC2. Pulse transformer 100 also includes secondary windings 102 and 103 connected to upper arm element 3 and lower arm element 4, respectively. The pulse transformer 100 further comprises a core 7 (iron core) incorporated to enhance the magnetic coupling between the primary winding 101 and the secondary windings 102,103. An inductance 5 is a parasitic inductance caused by wiring between the drive IC 2 and the pulse transformer 100 .

The drive IC 2 inputs a voltage from the microcomputer 6, waveform-shapes the voltage, and outputs a rectangular pulse voltage. The output voltage of the drive IC 2 becomes the input voltage Vin to the pulse transformer 100 , and this input voltage Vin is applied to the primary winding 101 of the pulse transformer 100 . A voltage Vn1 generated in the primary winding 101 of the pulse transformer 100 is a voltage in which the input voltage Vin is affected by the component of the inductance 5 .

The pulse transformer 100 transmits the applied voltage from the primary winding 101 of the pulse transformer 100 to the secondary windings 102 and 103 according to the pulse voltage from the driving IC 2 . A voltage Vn2 is applied to the secondary winding 102 . Also, a voltage Vn3 is applied to the secondary winding 103 .

The voltages transmitted to secondary windings 102 and 103 drive upper arm element 3 and lower arm element 4, respectively. Specifically, the currents in2 and in3 flow under the influence of the induced electromotive force generated in the secondary windings 102 and 103 . A voltage Vgs2 is applied to the gate terminal of the upper arm element 3 by this current in2. A voltage Vgs3 is applied to the gate terminal of the lower arm element 4 by the current in3. Here, the directions of the current in1 flowing through the primary winding 101 and the currents in2 and in3 flowing through the secondary windings 102 and 103 are opposite to each other.

Next, the structures of primary winding 101, secondary winding 102 and secondary winding 103 of pulse transformer 100 will be described with reference to FIG. The pulse transformer 100 according to the first embodiment is composed of a multilayer wiring board in which eight wiring layers L1 to L8 shown in FIG. 2 are laminated. The multilayer wiring board is laminated in the order of L1 to L8, with the wiring layer L1 on the upper side and the wiring layer L8 on the lower side.

The primary winding 101 is divided into three and arranged on the wiring layer L3, the wiring layer L5, and the wiring layer L7. That is, the primary winding 101 is divided into primary windings 101a, 101b, and 101c. The secondary winding 102 is divided into two and arranged on the wiring layer L2 and the wiring layer L4. That is, the secondary winding 102 is divided into secondary windings 102a and 102b. Further, the secondary winding 103 is divided into two and arranged on the wiring layer L6 and the wiring layer L8. That is, the secondary winding 103 is divided into secondary windings 103a and 103b. It should be noted that the term "division" here does not mean that one winding is cut and divided into a plurality of parts, but that the function as a primary winding or a secondary winding is divided into a plurality of parts. means

The wiring layer L3, the wiring layer L5, and the wiring layer L7 correspond to the first wiring layer. Also, the wiring layer L2, the wiring layer L4, the wiring layer L6, and the wiring layer L8 correspond to the second wiring layer. Note that the wiring layer L1 does not correspond to either the first wiring layer or the second wiring layer. In the wiring layers L2 to L8, the first wiring layers on which the primary windings are arranged and the second wiring layers on which the secondary windings are arranged are all alternately laminated. In other words, the first wiring layers or the second wiring layers are not adjacent to each other in the stacking direction.

A core 7 is incorporated in the multilayer wiring board to enhance magnetic coupling between the primary winding 101 and the secondary windings 102 and 103 of the pulse transformer 100 . The multilayer wiring board is also provided with vias V1 (V1a, V1b, V1c) for the primary winding 101 for through-connecting the wiring layers L1 to L8. Similarly, the multilayer wiring board is provided with vias V2 (V2a, V2b, V2c) and vias V3 (V3a, V3b, V3c) for the secondary windings 102, 103. FIG. Hereinafter, vias V1a, V1b, and V1c are collectively referred to as via V1 as necessary. Similarly, vias V2a, V2b, and V2c will be collectively referred to as via V2 as required, and vias V3a, V3b, and V3c will be collectively referred to as via V3 as required.

The vias V1, V2, and V3 are through-connected from the wiring layer L1 to the wiring layer L8. A primary winding 101 is connected to the via V1. A via V1a in the wiring layer L1 is connected to the drive IC2. A wiring 101x extending from one end of the primary winding 101 connects the via V1a and the via V1b in the wiring layer L1. The wiring 101x is connected to the primary winding 101a of the wiring layer L3 through the via V1b. Further, the wiring 101x is connected to the primary winding 101b of the wiring layer L5 through the via V1b. The wiring 101x is connected to the primary winding 101c of the wiring layer L7 through the via V1b. Further, the via V1c of the wiring layer L1 and the primary windings 101a, 101b, 101c are connected through the via V1c. Then, it is connected to the driving IC 2 through the via V1c of the wiring layer L1.

A secondary winding 102 is connected to the via V2. Via V<b>2 a in wiring layer L<b>1 is connected to upper arm element 3 . A wiring 102x extending from one end of the secondary winding 102 connects the via V2a and the via V2b in the wiring layer L1. The wiring 102x is connected to the secondary winding 102a of the wiring layer L2 through the via V2b. Furthermore, the wiring 102x is connected to the secondary winding 102b of the wiring layer L4 through the via V2b. Further, the via V2c of the wiring layer L1 and the secondary windings 102a and 102b are connected through the via V2c. Then, it is connected to the upper arm element 3 through the via V2c of the wiring layer L1.

A secondary winding 103 is connected to the via V3. Via V3a of wiring layer L1 is connected to lower arm element 4. FIG. A wiring 103x extending from one end of the secondary winding 103 connects the via V3a and the via V3b in the wiring layer L1. The wiring 103x is connected to the secondary winding 103a of the wiring layer L6 through the via V3b. Furthermore, the wiring 103x is connected to the secondary winding 103b of the wiring layer L8 through the via V3b. Further, the via V3c of the wiring layer L1 and the secondary windings 103a and 103b are connected through the via V3c. Then, it is connected to the lower arm element 4 through the via V3c of the wiring layer L1.

As shown in FIG. 2, the primary winding 101 is divided into three layers 101a, 101b and 101c, respectively, wiring layer L3, wiring layer L5 and wiring layer L7. Secondary winding 102 is divided into 102a and 102b in wiring layer L2 and wiring layer L4. Similarly, secondary winding 103 is divided into 103a and 103b in wiring layer L6 and wiring layer L8. That is, the wiring layers in which the primary windings are arranged and the wiring layers in which the secondary windings are arranged are all alternately laminated. Here, the energy E due to the leakage magnetic field in the pulse transformer 100 is expressed by the following formula (1). μ ₀ is the magnetic permeability of the vacuum and H is the strength of the magnetic field.

この場合、巻線電流Ｉは一定であるため、式（２）の左辺の漏れ磁界によるエネルギーＥが小さくなると、漏れインダクタンスＬｌｅａｋが小さくなることがわかる。 FIG. 3 shows a cross-sectional view along the dashed-dotted line III-III of FIG. FIG. 4 shows, as a comparative example, a cross-sectional view and a graph showing magnetic field strength when the primary winding 101, secondary winding 102 and secondary winding 103 are not divided. If the winding is split, the current flowing through the split winding will be less. Also, the strength of the magnetic field is proportional to the current value. Therefore, as shown in FIG. 3, the magnetic field strength H when the winding is divided is smaller than the magnetic field strength H when the winding is not divided as shown in FIG. Therefore, the energy E due to the leakage magnetic field shown in Equation (1) is reduced. Here, the energy E due to the leakage magnetic field can also be expressed by the following formula (2). Lleak is the leakage inductance and I is the value of the winding current.

In this case, since the winding current I is constant, it can be seen that the leakage inductance Lleak decreases as the energy E due to the leakage magnetic field on the left side of Equation (2) decreases.

In the first embodiment, the primary winding 101 is divided into three and arranged in three wiring layers. Secondary winding 102 and secondary winding 103 are each divided into two and arranged in two wiring layers. Also, the wiring layers in which the primary winding 101 is arranged and the wiring layers in which the secondary windings 102 and 103 are arranged are all alternately laminated. By dividing the winding, it is possible to reduce the current flowing in one winding and the magnetic flux generated by the current. As a result, leakage inductance can be reduced, and reduction in output voltage to the secondary winding side can be suppressed.

The number of divisions of primary winding 101 and secondary windings 102 and 103 is not limited to three and two. As long as the first wiring layer on which the primary winding 101 is arranged and the second wiring layer on which the secondary windings 102 and 103 are arranged are all alternately laminated, the number of divisions of each winding can be increased. can be As the number of divided windings increases, the current flowing in one winding and the magnetic flux generated by the current decrease, the leakage inductance decreases, and the reduction in output power to the secondary winding side is suppressed. In the laminated multilayer wiring board, the uppermost and lowermost wiring layers among the wiring layers in which the windings are arranged may be the first wiring layer or the second wiring layer. Also good. For example, the first wiring layer and the second wiring layer may be alternately laminated so that both the uppermost wiring layer and the lowermost wiring layer are the first wiring layer. . Alternatively, the first wiring layer and the second wiring layer may be alternately stacked such that both the uppermost wiring layer and the lowermost wiring layer are the second wiring layer. . Alternatively, the first wiring layer and the second wiring layer are alternately arranged such that one of the uppermost wiring layer and the lowermost wiring layer is the first wiring layer and the other is the second wiring layer. A stacked structure may also be used.

As described above, the pulse transformer 100 includes a primary winding 101 connected to the drive IC 2 and a plurality of secondary windings 102 and 103 respectively connected to a plurality of semiconductor switching elements. A primary winding 101 is divided into at least three, and the divided primary windings 101 are respectively arranged in a plurality of first wiring layers (wiring layer L3, wiring layer L5, wiring layer L7). A plurality of secondary windings are each divided into at least two, and the divided secondary windings are each divided into a plurality of second wiring layers (wiring layer L2, wiring layer L4, wiring layer L6, wiring layer L8). placed. A plurality of first wiring layers and a plurality of second wiring layers are laminated so as to be alternately arranged in the lamination direction of the multilayer wiring board. By dividing the primary winding 101 and the secondary windings 102 and 103 and stacking them as described above, the current and magnetic flux are reduced, and the magnetic flux that does not interlink the windings can be reduced. Thereby, the degree of coupling between the primary winding 101 of the pulse transformer 100 and the secondary windings 102 and 103 can be improved. The improved coupling reduces the leakage inductance of the pulse transformer 100 and reduces the resonance with the parasitic capacitance of the semiconductor switching element. As a result, it is possible to prevent the oscillation of the gate voltage of the semiconductor switching element from becoming large, and to prevent the semiconductor switching element from erroneously firing.

In pulse transformer 100, the number of semiconductor switching elements and secondary windings 102 and 103 is N (N is an integer equal to or greater than 2). Also, each of the N secondary windings 102 and 103 is divided into M (M is an integer equal to or greater than 2). In this case, the primary winding 101 can be divided into (M×N−1) pieces, (M×N) pieces, or (M×N+1) pieces. Further, the wiring layers in which the primary winding 101 is arranged and the wiring layers in which the secondary windings 102 and 103 are arranged are all alternately laminated. Under this condition, when the primary winding 101 is divided into (M×N−1) pieces, the uppermost and lowermost wiring layers in which the windings are arranged are the secondary windings. It becomes a wiring layer in which 102 or 103 is arranged. Further, when the primary winding 101 is divided into (M×N) pieces, one of the top surface and the bottom surface of the wiring layer in which the windings are arranged is the divided primary winding 101. It becomes an arranged wiring layer. Further, when the primary winding 101 is divided into (M×N+1) pieces, the divided primary windings 101 are arranged in the uppermost and lowermost wiring layers among the wiring layers in which the windings are arranged. It becomes a wiring layer that has been processed.

FIG. 5 shows each layer when the number of secondary windings is four, the primary winding 101 is divided into seven, and each of the four secondary windings 102 to 105 is divided into two and arranged in wiring layers. is viewed from above. FIG. 6 shows a cross-sectional view along the dashed-dotted line VI-VI in FIG. As shown in FIGS. 5 and 6, the primary winding 101 is divided into seven wiring layers L3, L5, L7, L9, L11, L13 and L15 into 101a-101g, respectively. Secondary winding 102 is divided into 102a and 102b in wiring layer L2 and wiring layer L4. Secondary winding 103 is divided into 103a and 103b in wiring layer L6 and wiring layer L8. Secondary winding 104 is divided into 104a and 104b in wiring layer L10 and wiring layer L12. Secondary winding 105 is divided into 105a and 105b in wiring layer L14 and wiring layer L16. That is, the wiring layers in which the primary windings are arranged and the wiring layers in which the secondary windings are arranged are all alternately laminated.

Further, in the present embodiment, the secondary windings divided from one secondary winding are arranged in the second wiring layers that are continuous in the stacking direction among the plurality of second wiring layers in the multilayer wiring board. ing. For example, as shown in FIG. 2, secondary windings 102a and 102b divided from the secondary winding 102 are arranged on wiring layers L2 and L4. The wiring layer L2 and the wiring layer L4 are second wiring layers that are continuous in the stacking direction among the wiring layers L1 to L8 of the multilayer wiring board. Similarly, secondary windings 103a and 103b divided from secondary winding 103 are arranged on wiring layers L6 and L8. The wiring layer L6 and the wiring layer L8 are second wiring layers that are continuous in the stacking direction among the wiring layers L1 to L8 of the multilayer wiring board.

In other words, between a plurality of wiring layers in which secondary windings divided from one secondary winding are arranged, there are wiring layers in which secondary windings divided from other secondary windings are arranged. does not intervene. With such an arrangement, a plurality of secondary windings divided from one secondary winding can be arranged at positions close to each other in the multilayer wiring board. As a result, the degree of coupling between the primary winding and each of the plurality of secondary windings necessary for transmitting the gate voltages of the upper and lower arm elements 3 and 4 can be improved.

Further, between the wiring layers in which the plurality of secondary windings are divided and arranged, there is a wiring layer in which the divided primary windings are arranged. For example, between a wiring layer L4 divided from the secondary winding 102 and a wiring layer L6 divided from the secondary winding 103, there is a wiring layer L5 of the divided primary winding 101. exist. As a result, the degree of coupling between the secondary windings unnecessary for transmission of the gate voltages of the upper and lower arm elements 3 and 4 can be reduced.

The currents flowing through the primary winding 101 and the secondary windings 102 and 103 flow in opposite directions (different directions) between adjacent wiring layers in the lamination direction when viewed from the lamination direction. Specifically, as shown in FIG. 3, in the wiring layers L2 to L8, currents flow in mutually opposite directions (different directions) in the adjacent wiring layers. As a result, leakage magnetic flux that does not interlink each winding is canceled, leading to an improvement in coupling between the primary and secondary windings.

(Second embodiment)
Next, a second embodiment will be described. In the following description, when the same reference numerals as in the first embodiment are used, they indicate the same configurations as in the first embodiment, and the preceding description will be referred to unless otherwise specified. As shown in FIG. 7, in the pulse transformer 200 according to the second embodiment, the number of turns of the secondary winding of each layer is smaller than the number of turns of the primary winding.

FIG. 7 is a plan view of each layer of the pulse transformer 200 according to the second embodiment. FIG. 8 shows a cross-sectional view along the dashed-dotted line VIII-VIII in FIG. The number of turns of each secondary winding 202a, 202b in wiring layer L2 and wiring layer L4 is two. On the other hand, the number of turns of primary windings 201a, 201b and 201c in wiring layer L3, wiring layer L5 and wiring layer L7 is four. Therefore, the number of turns of the secondary windings 202a, 202b is less than the number of turns of the primary windings 201a, 201b, 201c. The number of turns of secondary windings 203a and 203b in wiring layer L6 and wiring layer L8 is two. On the other hand, as described above, the number of turns of primary windings 201a, 201b and 201c in wiring layer L3, wiring layer L5 and wiring layer L7 is four. Therefore, the number of turns of the secondary windings 203a, 203b is less than the number of turns of the primary windings 201a, 201b, 201c. The ratio of the number of turns of the primary winding 201, the secondary winding 202 and the secondary winding 203 of each wiring layer in the second embodiment shown in FIGS. 7 and 8 is 4:2:2. : 1:1. In this case, the turns ratio is two. Note that the arrangement of the vias V1, V2, and V3 is the same as in FIG. 2, so the explanation is omitted.

Now assume that the pulse transformer 200 is an ideal transformer with no loss. When the turns ratio between the primary winding 201 and the secondary windings 202 and 203 is m, the relationship between the voltage Vn2 of the secondary windings 202 and 203 and the voltage of the primary winding 201 is Vn2=(Vn1) / m. Further, the currents in2 and in3 of the secondary windings 202 and 203 and the current in1 flowing through the primary winding 201 satisfy the relationship of in2+in3=m×in1. Here, the voltage generated across the inductance 5 is Vn1, which is substantially the same as the voltage across the primary winding 201 . Therefore, secondary windings 202 and 203 generate a voltage that is 1/m of the voltage Vn1 generated in inductance 5 . Also, the current flowing through the inductance 5 between the drive IC 2 and the primary winding 201 is 1/m of the current flowing through the secondary windings 202 and 203 . At this time, the voltage Vn1 of the primary winding 201 can be expressed by the following equation (3).

電圧Ｖｇｓ３も同様に表すことができる。 In addition, an induced current flows due to the influence of the induced electromotive force generated in the secondary windings 202 and 203 . Voltages Vgs2 and Vgs3 are generated between the gates and sources of the upper arm element 3 and the lower arm element 4 by this induced current. Here, Vgs2 can be represented by the following formula (4). L is the parasitic inductance value of inductance 5;

Voltage Vgs3 can be represented similarly.

Therefore, although the gate-source voltages Vgs2 and Vgs3 of the upper and lower arm elements 3 and 4 rise due to the influence of the second term of the equation (4) caused by the parasitic inductance L, the influence of 1/square of the turns ratio m Only disappear. That is, by increasing the turns ratio m, the influence of the parasitic inductance L can be suppressed, the oscillation of the gate voltage can be suppressed, and erroneous ignition can be prevented.

Furthermore, the turns ratio m between the primary winding 201 and the secondary windings 202 and 203 is set to satisfy m≧SQRT(N) (where SQRT(N) represents the square root of N). It is desirable that Note that N is the number of semiconductor switching elements. By configuring the turns ratio m to satisfy m≧SQRT(N), the influence of the parasitic inductance L can be made equal to or less than that in the case of one semiconductor switching element.

As described above, in the pulse transformer 200, the number of turns of the secondary windings 202 and 203 arranged in each wiring layer of the multilayer wiring board is smaller than the number of turns of the primary winding 201. FIG. For example, in the examples shown in FIGS. 7 and 8, the turns ratio between the primary winding 201 and the secondary windings 202 and 203 is two. By increasing the turns ratio of primary winding 201 and secondary windings 202 and 203, the influence of parasitic inductance L on gate-source voltage Vgs2 in equation (4) can be reduced. By reducing the influence of the parasitic inductance L, the oscillation of the gate voltage is suppressed and erroneous ignition can be prevented.

Furthermore, it is desirable that the turns ratio m between the primary winding 201 and the secondary windings 202 and 203 is set so as to satisfy m≧SQRT(N). For example, when N is 4, m is preferably 2 or more, and when N is 6, m is preferably 3 or more. As a result, the gate-source voltages Vgs2 and Vgs3 are further suppressed, and erroneous ignition can be prevented. The effect of preventing erroneous ignition can be obtained by increasing the number of semiconductor switching elements.

(Other embodiments)
The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure encompasses the illustrated embodiments and variations thereon by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses omitting parts and/or elements of the embodiments. The disclosure encompasses permutations or combinations of parts and/or elements between one embodiment and another. The disclosed technical scope is not limited to the description of the embodiments. The disclosed technical scope is indicated by the description of the claims, and should be understood to include all changes within the meaning and range of equivalents to the description of the claims.

Further, the drive IC 2 of each embodiment described above is configured by one or a plurality of control devices. For example, the controller includes a memory and a processor that executes programs stored in the memory. Also for example, the control device comprises a logic circuit constituted by a digital circuit containing a number of programmed logic units (gate circuits).

1 semiconductor module 2 drive IC 3 upper arm element 4 lower arm element 5 inductance 6 microcomputer 7 core 100 pulse transformer 101 primary winding 102 secondary winding 103 secondary winding 200 pulse transformer, 201 primary winding, 202 secondary winding, 203 secondary winding

Claims (5)

In a pulse transformer that drives a plurality of semiconductor switching elements (3, 4) with a pulse voltage from a driving IC (2),
a primary winding (101, 201) connected to the driving IC;
a plurality of secondary windings (102, 103, 202, 203) respectively connected to the plurality of semiconductor switching elements (3, 4);
a plurality of first wiring layers (L3, L5, L7) in which the primary winding is divided into at least three, and the divided primary windings are arranged respectively;
a plurality of second wiring layers (L2, L4, L6, L8) in which each of the plurality of secondary windings is divided into at least two, and the divided secondary windings are arranged respectively; ,
A pulse transformer in which all of the plurality of first wiring layers and the plurality of second wiring layers are alternately laminated. A secondary winding divided from one of the plurality of secondary windings is arranged in a second wiring layer that is continuous in the stacking direction among the plurality of second wiring layers. A pulse transformer according to claim 1. 3. The pulse transformer according to claim 1, wherein the current in said primary winding and the current in said secondary winding flow in opposite directions when viewed from the stacking direction. 2. The number of turns of said secondary winding arranged on each of said plurality of second wiring layers is smaller than the number of turns of said primary winding arranged on each of said plurality of first wiring layers. 4. The pulse transformer according to any one of 1 to 3. 2. The turns ratio between the primary winding and the secondary winding is equal to or greater than the square root of N, where N is the number of the plurality of secondary windings (N is an integer equal to or greater than 2). 5. The pulse transformer according to any one of 4.

Images