JP7256089B2 - gate drive circuit - Google Patents

Description

The present invention relates to gate drive circuits for resonant inverters.

Conventionally, there is a resonance inverter that is a DC/AC converter that converts DC power into AC power using LC resonance (for example, Patent Document 1).

The resonance inverter has a high-side transistor on the DC power supply voltage side and a low-side transistor on the reference potential side, and performs switching between the high-side transistor and the low-side transistor. If the high-side transistor and the low-side transistor are turned on at the same time, the power supply voltage side and the reference potential side are short-circuited. This simultaneous off period is called dead time.

In the resonant inverter, the switch voltage, which is the voltage at the node where the high-side transistor and the low-side transistor are connected, can be lowered from the power supply voltage to the reference potential (0 V) during the dead time. Zero-volt switching (soft switching) that turns on the low-side transistor when the applied voltage is 0V becomes possible. In addition, since the switch voltage can be raised from the reference potential to the power supply voltage during the dead time, zero-volt switching is also possible in which the high-side transistor is turned on when the voltage applied to the high-side transistor is 0V.

JP 2005-183348 A JP-A-2001-258269

Here, for example, Patent Document 2 discloses a dead time adjustment circuit used in a soft switching converter. However, in the dead time adjustment circuit, since an IC such as a comparator is used to generate a signal for driving the gate of the transistor, the timing at which the transistor is actually turned on lags behind the ideal timing. There is fear. In the resonant converter described above, when the delay becomes large, current flows through the body diode of the transistor, resulting in an increase in diode loss. In particular, the higher the switching frequency, the more remarkable the increase in the diode loss.

SUMMARY OF THE INVENTION In view of the above situation, it is an object of the present invention to provide a gate drive circuit for a resonant inverter that can reduce loss by appropriately adjusting dead time.

A gate drive circuit according to a first aspect of the present invention is a gate drive circuit that is used in a resonant inverter having a high-side transistor on the input voltage side and a low-side transistor on the ground potential side, and drives the gate of the low-side transistor. There is
a first capacitor to one end of which a switch voltage generated at a first node where the high-side transistor and the low-side transistor are connected is applied;
a first resistor having one end connected to the other end of the first capacitor and having the other end applied with a voltage obtained by adding an offset voltage from a reference ground potential;
a first diode having an anode connected to a second node where the other end of the first capacitor and one end of the first resistor are connected, and a cathode connected to the other end of the first resistor;
and a fall detector for detecting the fall of the switch voltage (first structure).

Further, in the first configuration, the fall detector has a cathode connected to a third node to which the other end of the first resistor and the cathode of the first diode are connected, and an anode to which a ground potential is applied. It may further have a second diode connected to the end (second configuration).

Further, in the above first or second configuration, further comprising a low side gate signal generation section that generates a low side gate signal for driving the low side transistor based on the fall detection signal generated by the fall detection section,
The low side gate signal generation unit
a CMOS configuration configured between a first power supply voltage and a ground potential and receiving the fall detection signal;
a first p-channel MOSFET having a gate to which the output terminal of the CMOS configuration is connected, and a source to which the application terminal of the first power supply voltage is connected;
a first n-channel MOSFET having a gate connected to the output end of the CMOS structure, a drain connected to the drain of the first p-channel MOSFET, and a source connected to a ground potential application end;
a second n-channel MOSFET having a gate connected to the output terminal of the CMOS structure and a source connected to the application terminal of the ground potential;
a third n-channel MOSFET having a gate connected to the drain of the second n-channel MOSFET, a drain connected to the drain of the first n-channel MOSFET, and a source connected to a ground potential application terminal;
(third configuration).

In the third configuration, the low-side gate signal generator may further include a second resistor connected between the drain of the second n-channel MOSFET and a ground potential application terminal (fourth configuration).

In the third or fourth configuration, the low-side gate signal generator includes a source connected to the application terminal of the first power supply voltage, a drain connected to the drain of the second n-channel MOSFET, and a low-side gate signal generator. It may further include a second p-channel MOSFET having a gate to which an off signal is applied (fifth configuration).

In any one of the third to fifth configurations, the low-side gate signal generator includes a drain connected to the drain of the second n-channel MOSFET, a source connected to a ground potential application terminal, and a low-side gate signal generator. It may further include a fourth n-channel MOSFET having a gate to which an ON signal is applied (sixth configuration).

Further, a power supply control device according to a second aspect of the present invention is a power supply control device including a gate drive circuit having the fifth configuration and an off generation circuit for generating the low side off signal,
The off generation circuit is
a first flip-flop;
a triangular wave generator that generates a triangular wave signal based on the output of the first flip-flop;
a first comparator to which the triangular wave signal and the reference voltage are input;
a second comparator to which the triangular wave signal and a feedback voltage based on the output voltage of the resonant inverter are input;
has
The first flip-flop is reset by the output of the first comparator,
The first flip-flop is set by the output of the second comparator,
The low side off signal is based on the output of the first comparator,
The high side off signal is configured based on the output of the second comparator (seventh configuration).

Further, a power supply control device according to a third aspect of the present invention is a power supply control device including a gate drive circuit having the sixth configuration and a low side on generation circuit for generating the low side on signal,
The low-side on generation circuit is
a first RC circuit to which a high side off signal is input;
a second flip-flop;
a second RC circuit to which the output of the second flip-flop is input;
has
The second flip-flop is set by the output of the first RC circuit,
The second flip-flop is reset by the output of the second RC circuit,
The low-side ON signal is configured based on the output of the second flip-flop (eighth configuration).

A gate drive circuit according to a fourth aspect of the present invention is used in a resonant inverter having a high-side transistor on the input voltage side and a low-side transistor on the ground potential side, and drives the gate of the high-side transistor. A drive circuit,
a first capacitor to one end of which the input voltage is applied;
A first capacitor having one end connected to the other end of the first capacitor and having the other end applied with an offset voltage based on a switch voltage generated at a first node where the high-side transistor and the low-side transistor are connected. resistance and
a first diode having an anode connected to a second node where the other end of the first capacitor and one end of the first resistor are connected, and a cathode connected to the other end of the first resistor;
and a rise detector for detecting the rise of the switch voltage (ninth structure).

In the ninth configuration, the rise detector has a cathode connected to a third node to which the other end of the first resistor and the cathode of the first diode are connected, and an anode to which the switch voltage is applied. It may further have a second diode connected to the end (tenth configuration).

In the ninth or tenth configuration, further comprising a high side gate signal generating section for generating a high side gate signal for driving the high side transistor based on the rising edge detection signal generated by the rising edge detecting section,
The high side gate signal generation unit
a CMOS configuration configured between a first power supply voltage and the switch voltage and receiving the rise detection signal;
a first p-channel MOSFET having a gate to which the output terminal of the CMOS configuration is connected, and a source to which the application terminal of the first power supply voltage is connected;
a first n-channel MOSFET having a gate connected to the output terminal of the CMOS configuration, a drain connected to the drain of the first p-channel MOSFET, and a source connected to the application terminal of the switch voltage;
a second n-channel MOSFET having a gate connected to the output terminal of the CMOS configuration and a source connected to the application terminal of the switch voltage;
a third n-channel MOSFET having a gate to which the drain of the second n-channel MOSFET is connected, a drain to which the drain of the first n-channel MOSFET is connected, and a source to which the switch voltage application terminal is connected;
(eleventh configuration).

In the eleventh configuration, the high-side gate signal generator may further include a second resistor connected between the drain of the second n-channel MOSFET and the switch voltage application terminal ( 12th configuration).

In the eleventh or twelfth configuration, the high-side gate signal generator includes a source connected to the application terminal of the first power supply voltage, a drain connected to the drain of the second n-channel MOSFET, It may further include a second p-channel MOSFET having a gate to which a high-side off signal is applied (13th configuration).

In any one of the eleventh to thirteenth configurations, the high-side gate signal generator includes a drain connected to the drain of the second n-channel MOSFET and a source connected to the switch voltage application terminal. , and a fourth n-channel MOSFET having a gate to which a high-side ON signal is applied (14th configuration).

Further, a power control device according to a fifth aspect of the present invention is a power control device including a gate drive circuit having the thirteenth configuration and an off generation circuit for generating the high side off signal,
The off generation circuit is
a first flip-flop;
a triangular wave generator that generates a triangular wave signal based on the output of the first flip-flop;
a first comparator to which the triangular wave signal and the reference voltage are input;
a second comparator to which the triangular wave signal and a feedback voltage based on the output voltage of the resonant inverter are input;
has
The first flip-flop is reset by the output of the first comparator,
The first flip-flop is set by the output of the second comparator,
The low side off signal is based on the output of the first comparator,
The high side off signal is configured based on the output of the second comparator (15th configuration).

Further, a power supply control device according to a sixth aspect of the present invention is a power supply control device including a gate drive circuit having the fourteenth configuration, and a high side-on generation circuit for generating a previous high side-on signal, ,
The high side-on generation circuit is
a first RC circuit to which a low-side off signal is input;
a second flip-flop;
a second RC circuit to which the output of the second flip-flop is input;
has
The second flip-flop is set by the output of the first RC circuit,
The second flip-flop is reset by the output of the second RC circuit,
The high-side ON signal is configured based on the output of the second flip-flop (sixteenth configuration).

A seventh aspect of the present invention is a power supply control device having a gate drive circuit having any one of the first to sixth and ninth to fourteenth configurations (seventeenth configuration).

An eighth aspect of the present invention is a resonance inverter including the power control device having the seventeenth configuration, and a high-side transistor and a low-side transistor driven and controlled by the power control device (eighteenth configuration ).

In the eighteenth configuration, the high-side transistor and the low-side transistor may be configured using GaN (gallium nitride) as a semiconductor material (nineteenth configuration).

A ninth aspect of the present invention is a plasma processing apparatus having the resonant inverter having the eighteenth or nineteenth configuration, and a plasma processing section serving as a load of the resonant inverter.

A tenth aspect of the present invention is a first rectifying/smoothing section; a power supply device including a power transmission coil that serves as a load of the resonance inverter;
a power-supplied device having a power receiving coil and a second rectifying/smoothing section to which the output of the power receiving coil is input;
A wireless power supply system having

According to the gate drive circuit of the present invention, loss can be reduced by appropriately adjusting the dead time.

1 is a circuit diagram showing a basic configuration of a resonance inverter; FIG. Fig. 3 shows (a) a first switching state of the resonant inverter, and (b) the switch voltage in the first switching state; Fig. 2(a) shows the second switching state of the resonant inverter, and (b) the switch voltage in the second switching state; Fig. 3(a) shows the third switching state of the resonant inverter, and (b) the switch voltage in the third switching state; FIG. 11 shows (a) a fourth switching state of the resonant inverter, and (b) the switch voltage in the fourth switching state; FIG. 11 shows (a) a fifth switching state of the resonant inverter, and (b) the switch voltage in the fifth switching state; FIG. 11 shows (a) a sixth switching state of the resonant inverter, and (b) the switch voltage in the sixth switching state; FIG. 11 shows (a) the seventh switching state of the resonant inverter, and (b) the switch voltage in the seventh switching state. FIG. 11 shows (a) the eighth switching state of the resonant inverter, (b) the switch voltage in the eighth switching state; It is a figure for demonstrating the subject of a resonance inverter. It is a figure for demonstrating the subject of a resonance inverter. FIG. 4 is a diagram showing a configuration of a resonant inverter according to an exemplary embodiment of the invention; It is a circuit diagram which shows one structural example of a low side gate drive circuit. It is a circuit diagram which shows one structural example of a high side gate drive circuit. 4 is a timing chart showing signal behavior of each part of the low-side gate drive circuit in steady operation; 4 is a timing chart showing signal behavior of each part of the low-side gate drive circuit in a transient state; 4 is a timing chart showing signal behavior of each part of the high-side gate drive circuit in steady operation; 4 is a timing chart showing signal behavior of each part of the high-side gate drive circuit in a transient state; 4 is a circuit diagram showing a configuration example of an off generation circuit; FIG. 4 is a timing chart showing generation of an off signal by an off generation circuit; FIG. 3 is a circuit diagram showing a configuration example of a high side-on generation circuit; It is a circuit diagram which shows one structural example of a low side ON generation circuit. It is a figure which shows the differentiation circuit for analysis. 24 is a diagram showing input voltages to be input to the circuit shown in FIG. 23 for analysis; FIG. FIG. 4 is a diagram for explaining circuit constant conditions; It is a figure which shows the structure of the plasma processing apparatus concerning exemplary embodiment of this invention. 1 is a diagram showing the configuration of a wireless power supply system according to an exemplary embodiment of the present invention; FIG. 1 is a perspective view of a semiconductor device; FIG. 29 is a plan view of a transistor in the semiconductor device shown in FIG. 28; FIG.

An embodiment of the present invention will be described below with reference to the drawings.

<1. Basic Configuration and Basic Operation of Resonant Inverter>
Before describing the embodiments of the present invention, first, the basic configuration and basic operation of the resonant inverter will be described. FIG. 1 is a circuit diagram showing the basic configuration of a resonant inverter.

The resonant inverter shown in FIG. 1 is a DC/AC converter that uses LC resonance to convert an input voltage Vin, which is a DC voltage, into an output voltage Vout, which is an AC voltage, and supplies the load Z with the output voltage Vout. The resonant inverter shown in FIG. 1 has a high-side transistor HS on the input voltage Vin (power supply voltage) side, a low-side transistor BS on the reference potential side, an inductor L1, and a capacitor CR1.

The drain of the high-side transistor HS composed of an n-channel MOSFET is connected to the application terminal of the input voltage Vin. The source of the high side transistor HS is connected at a node N1 to the drain of the low side transistor BS composed of an n-channel MOSFET. The source of the low-side transistor BS is connected to the reference potential application terminal.

One end of inductor L1 is connected to node N1. The other end of inductor L1 is connected to one end of capacitor CR1. A load Z is connected between the other end of the capacitor CR1 and the application end of the reference potential.

Also, the high-side transistor HS and the low-side transistor BS have body diodes (parasitic diodes) HBD, BBD and parasitic capacitances HCds, BCds between their drains and sources, respectively.

In the resonance inverter having such a configuration, the gate of the high side transistor HS and the gate of the low side transistor BS are each driven by a gate driving circuit (not shown). Thereby, the high side transistor HS and the low side transistor BS are switched.

Next, the basic operation of the resonant inverter having such a configuration will be described with reference to FIGS. 2 to 9. FIG. FIGS. 2-9 show the switching states and transitions of the switch voltage SW occurring at node N1. 2(a) to 9(a), thick arrows indicate currents generated.

First, as shown in FIG. 2A, when the high-side transistor HS is on and the low-side transistor BS is off, the current flows through the order of the high-side transistor HS, the node N1, the inductor L1, the capacitor CR1, and the load Z. flows. At this time, as shown in FIG. 2B, the switch voltage SW becomes the input voltage Vin.

Next, as shown in FIG. 3A, the high side transistor HS is turned off while the low side transistor BS is turned off, and the dead time starts. At this time, currents flowing through the parasitic capacitance HCds of the high-side transistor HS from the input voltage Vin side and flowing through the parasitic capacitance BCds of the low-side transistor BS from the reference potential side merge at the node N1, and the inductor L1, the capacitor CR1, and the load Z are connected. flow. That is, the parasitic capacitance HCds of the high side transistor HS is charged and the parasitic capacitance BCds of the low side transistor BS is discharged. As a result, the switch voltage SW falls from the input voltage Vin to 0 V, as shown in FIG. 3(b).

Even after the switch voltage SW has fallen to 0 V, as shown in FIG. 4A, both the high-side transistor HS and the low-side transistor BS are off, and if the dead time continues, the body diode BBD of the low-side transistor BS , inductor L1, capacitor CR1, and load Z in that order. At this time, as shown in FIG. 4B, the switch voltage SW is maintained at 0V.

Next, as shown in FIG. 5A, when the low-side transistor BS is turned on while the high-side transistor HS is off, the dead time ends and the low-side transistor BS, inductor L1, capacitor CR1, and load Z Current flows in the order of At this time, as shown in FIG. 5B, the switch voltage SW maintains 0V.

Then, as shown in FIG. 6(a), when the switching state of FIG. 5(a) is maintained, the current flows backward due to the LC resonance, and the current flows through the load Z, the capacitor CR1, the inductor L1, and the low-side transistor BS in this order. flows. At this time, as shown in FIG. 6B, the switch voltage SW maintains 0V.

Next, as shown in FIG. 7A, when the low-side transistor BS is turned off while the high-side transistor HS is off and the dead time starts, the current flowing through the load Z, the capacitor CR1, and the inductor L1 in this order is is divided into a current flowing through the parasitic capacitance HCds of the high-side transistor HS and a current flowing through the parasitic capacitance BCds of the low-side transistor BS. That is, the parasitic capacitance HCds of the high side transistor HS is discharged and the parasitic capacitance BCds of the low side transistor BS is charged. As a result, as shown in FIG. 7B, the switch voltage SW rises from 0V to the input voltage Vin.

Then, as shown in FIG. 8A, when the dead time in which both the high-side transistor HS and the low-side transistor BS are off continues even after the switch voltage SW has risen to the input voltage Vin, the load Z and the capacitor CR1 , inductor L1, and body diode HBD of high-side transistor HS. At this time, as shown in FIG. 8B, the switch voltage SW maintains the input voltage Vin.

Next, as shown in FIG. 9A, when the high side transistor HS is turned on while the low side transistor BS is turned off, the dead time ends and the load Z, the capacitor CR1, the inductor L1, and the high side transistor HS are turned on. Current flows in order. At this time, as shown in FIG. 9B, the switch voltage SW maintains the input voltage Vin.

After that, when the switching state of FIG. 9(a) continues, the current flows backward due to the LC resonance, and the state returns to the state shown in FIG. 2(a).

<2. Issues of Resonant Inverter>
Here, FIG. 10 shows the switch voltage SW having the behavior described above. Switching is achieved.

However, as shown in FIG. 11, when the timing at which the low-side transistor BS is turned on is timing tp11, which is earlier than timing tp1, zero-volt switching does not occur. Also, as shown in FIG. 11, when the timing to turn on the low-side transistor BS is timing tp12, which is later than timing tp1, zero-volt switching is achieved, but as shown in FIG. Thus, a current flows through the body diode BBD of the low-side transistor BS, resulting in diode loss. Therefore, as shown in FIG. 10, the timing tp1 is the ideal timing for turning on the low-side transistor BS, that is, the dead time DT1 is desirably matched with the falling period of the switch voltage SW.

Further, as shown in FIG. 10, when the high-side transistor HS is turned on at timing tp2 when the switch voltage SW rises to the input voltage Vin after the dead time DT2 starts, zero-volt switching is achieved.

However, as shown in FIG. 11, when the timing to turn on the high-side transistor HS is timing tp21 earlier than timing tp2, the zero-volt switch does not work. When the timing to turn on the high-side transistor HS is timing tp22, which is later than timing tp2, zero-volt switching is achieved, but the high-side transistor HS is turned on as shown in FIG. A current flows through the body diode HBD of , resulting in diode loss. Therefore, as shown in FIG. 10, the timing tp2 is the ideal timing for turning on the high-side transistor HS, that is, it is desirable that the dead time DT2 coincide with the rising period of the switch voltage SW.

Accordingly, the present invention aims at suppressing the deviation of the timing for turning on the switching transistor from the ideal timing, in particular, suppressing the delay from the ideal timing to reduce the diode loss. do. That is, the object is to appropriately adjust the dead time.

<3. Resonance Inverter According to Embodiment of the Present Invention>
FIG. 12 is a diagram illustrating a configuration of a resonant inverter according to an exemplary embodiment of the invention. The resonant inverter 50 shown in FIG. 12 has a high-side transistor HS, a low-side transistor BS, an inductor L1, and a capacitor CR1, similarly to the resonant inverter having the basic configuration described above. The DC input voltage Vin is converted into an AC output voltage Vout by switching the BS.

A diode loss due to a delay in turning on timing of a switching transistor becomes significant in high-frequency switching driving. Therefore, in this embodiment, as the high-side transistor HS and the low-side transistor BS, it is desirable to use a device using GaN (gallium nitride) as a semiconductor material, which is particularly advantageous for switching at high frequencies.

In addition, since a transistor using GaN as a semiconductor material has a relatively large forward voltage (Vf) of the body diode, the diode loss tends to increase, and in that sense, the transistor is suitable as the object of the present invention. However, an external diode may be connected to the transistor, for example, in order to reduce Vf of the diode.

In addition, the present invention does not limit the use of semiconductor materials other than GaN, such as SiC and Si, for transistors.

In particular, the resonant inverter 50 shown in FIG. 12 has a power control device 51 . The power supply control device 51 generates a high side gate signal HG that drives the gate of the high side transistor HS and a low side gate signal BG that drives the gate of the low side transistor BS.

The power supply control device 51 has a low side gate drive circuit 52 , a high side gate drive circuit 53 , an OFF generation circuit 54 , a high side ON generation circuit 55 and a low side ON generation circuit 56 .

The low side gate drive circuit 52 is a circuit that generates a low side gate signal BG. The high side gate drive circuit 53 is a circuit that generates a high side gate signal HG.

The off generation circuit 54 is a circuit that generates a high side off signal HS-OFF for turning off the high side transistor HS and a low side off signal BS-OFF for turning off the low side transistor BS.

The low-side on generation circuit 56 is a circuit that generates a low-side on signal BS-ON for forcibly turning on the low-side transistor BS, as will be described later. The high-side-on generation circuit 55 is a circuit that generates a high-side-on signal HS-ON for forcibly turning on the high-side transistor HS, as will be described later.

Details of the circuits included in the power supply control device 51 will be described later.

Note that, as shown in FIG. 12, the resonance inverter 50 also has voltage dividing resistors Rd1 and Rd2 for dividing the output voltage Vout, and a rectifying/smoothing section 57 . A voltage obtained by dividing the output voltage Vout by the voltage dividing resistors Rd1 and Rd2 is rectified and smoothed by the rectifying/smoothing section 57 to be the feedback voltage FB. The feedback voltage FB is used in the off generation circuit 54 as will be described later.

<4. Low-side gate drive circuit>
Next, details of the low-side gate drive circuit 52 included in the power supply control device 51 will be described. FIG. 13 is a circuit diagram showing a configuration example of the low-side gate drive circuit 52. As shown in FIG.

As shown in FIG. 13, the low-side gate drive circuit 52 generates a low-side gate signal based on a fall detection signal VB1 generated by a fall detection section 521 that detects a fall of the switch voltage SW and a fall detection signal VB1 generated by the fall detection section 521. and a low-side gate signal generator 522 that generates BG.

The fall detector 521 has a capacitor C11, a resistor R11, a diode D11, and a diode D12. A switch voltage SW is applied to one end of the capacitor C11. The other end of capacitor C11 is connected to one end of resistor R11. The other end of the resistor R11 is connected to an application end of an offset voltage E for offsetting based on the ground potential. The anode of diode D11 is connected at node ND1 and node ND11 to which capacitor C11 and resistor R11 are connected. The cathode of diode D11 is connected to the cathode of diode D12. The anode of the diode D12 is connected to the ground potential application terminal. A node ND2 to which the resistor R11 and the end to which the offset voltage E is applied is connected to a node ND3 to which the diodes D11 and D12 are connected.

Fall detection signal VB1 is generated at node ND11.

The low-side gate signal generator 522 also has transistors P11 to P13 formed of p-channel MOSFETs, transistors N11 to N15 formed of n-channel MOSFETs, and a resistor R12.

The transistors P11 and N11 constitute a CMOS between the application terminal of the predetermined power supply voltage V11 and the application terminal of the ground potential. That is, the source of the transistor P11 is connected to the application terminal of the power supply voltage V11. The drain of transistor P11 is connected to the drain of transistor N11. The source of the transistor N11 is connected to the ground potential application terminal. A node ND12 to which the gate of the transistor P11 and the gate of the transistor N11 are connected is connected to the node ND11. That is, the fall detection signal VB1 is applied to the node ND12.

A node N1D3 to which the drains of the transistors P11 and N11 are connected is connected to a node ND14 to which the gates of the transistors P12 and N12 are connected. The source of the transistor P12 is connected to the application terminal of the power supply voltage V11 at the node ND15.

The drain of transistor N12 is connected to the drain of transistor P12 at node ND16. The source of the transistor N12 is connected to the ground potential application terminal.

A gate of the transistor N13 is connected to the node ND14. The drain of transistor N13 is connected to the drain of transistor P13 at node ND17. The source of transistor P13 is connected to node ND16. A low-side off signal BS-OFF is applied to the gate of the transistor P13. The source of the transistor N13 is connected to the ground potential application terminal.

The connection node ND17 is connected to one end of the resistor R12, the drain of the transistor N14, and the gate of the transistor N15. The other end of the resistor R12, the source of the transistor N14, and the source of the transistor N15 are connected to the ground potential application end. A low-side on signal BS-ON is applied to the gate of the transistor N14.

The drain of transistor N15 is connected at node ND16 and node ND18. A low-side gate signal BG is generated at a node ND18.

Here, FIG. 15 is a timing chart showing signal behavior of each part of the low-side gate drive circuit 52 in steady operation. FIG. 15 shows, from the top, the switch voltage SW, the fall detection signal VB1, the gate signal VC1 of the transistor N13 (the voltage generated at the node ND14), the low side off signal BS-OFF, the low side on signal BS-ON, and the voltage of the transistor N15. Gate signal VD1 (the voltage developed at node ND17) and low-side gate signal BG are shown.

First, when the high-side transistor HS is on, the low-side transistor BS is off, and the switch voltage SW is equal to the input voltage Vin (before timing t1), A voltage obtained by raising the output 0 V by the offset voltage E is generated as the fall detection signal VB1 (fall detection signal VB1=High).

As a result, the level of the fall detection signal VB1 is inverted by the CMOS configuration of the transistors P11 and N11, and the gate signal VC1 becomes Low. The low side off signal BS-OFF is High and the low side on signal BS-ON is Low. Therefore, the transistors N13, P13, and N14 are off, and the voltage of the node ND17 (=gate signal VD1) is kept High. Here, although the resistor R12 is not essential, it is desirable to provide the resistor R12 because the voltage of the node ND17 becomes unstable if the resistor R12 is not provided.

Since the gate signal VD1 is High, the transistor N15 is on and the low-side gate signal BG is Low.

Then, when the high-side transistor HS is turned off at timing t1, the dead time starts, and the switch voltage SW starts falling. At this time, the negative voltage output from the differentiating circuit is raised by the offset voltage E and becomes a voltage of 0V or less, but the fall detection signal VB1 is set to 0V by the diode D12. The diode D12 is provided to limit the voltage to 0 V even in such a case because a large negative voltage is generated when the switch voltage SW has a steep fall slope. However, the diode D12 is not essential.

At this time, the gate signal VC1 becomes High due to the above CMOS configuration. As a result, the transistor N13 is turned on and the gate signal VD1 becomes Low. Since the transistor N12 is turned on by the gate signal VC1, the low-side gate signal BG becomes Low.

Then, when the switch voltage SW reaches 0 V at timing t2, a voltage obtained by raising the 0 V output by the differentiating circuit by the offset voltage E is generated as the fall detection signal VB1. That is, the fall detection signal VB1 rises from 0V to E. Then, the gate signal VC1 becomes Low, the low-side off signal BS-OFF is High, and the low-side on signal BS-ON is Low, so the gate signal VD1 maintains Low. Since the transistor P12 is turned on by the gate signal VC1, the low-side gate signal BG becomes High. This turns on the low-side transistor BS, ending the dead time.

After that, even if the low-side-on signal BS-ON rises to high at timing t3 and then falls to low, the gate signal VD1 remains low because the transistor N14 turns on and then turns off.

Then, when the low-side off signal BS-OFF falls to Low at timing t4, the transistor P13 is turned on and the gate signal VD1 is set to High. As a result, the transistor N15 is turned on, and the low-side gate signal BG becomes Low. Therefore, the low-side transistor BS is turned off and dead time begins. As a result, the switch voltage SW starts to rise.

Then, a positive voltage is output by the differentiating circuit, but the voltage is limited to 0 V by the diode D11 and raised by the offset voltage E to generate the fall detection signal VB1 (fall detection signal VB1=High).

After that, even if the low-side off signal BS-OFF rises to High, the gate signal VD1 remains High because the transistor P13 is turned off.

When the switch voltage SW reaches the input voltage Vin at timing t5, the high-side transistor HS is turned on by the high-side gate drive circuit 53, which will be described later, and the dead time ends. After that, since the switch voltage SW maintains the input voltage Vin, the fall detection signal VB1=High, the gate signal VC1=Low, and the gate signal VD1 maintains High.

As described above, the low-side gate drive circuit 52 of this embodiment is composed of transistors, diodes, resistors, and capacitors, and does not use an IC. By raising VB1 to High, the low-side gate signal BG can be set to High to turn on the low-side transistor BS. Therefore, the delay from the ideal timing t2 of the ON timing of the low-side transistor BS can be suppressed, and the diode loss can be reduced.

According to simulation results, the delay from the ideal timing of turning on the low-side transistor BS was 20 to 30 ns in the conventional configuration using an IC, but in the configuration of the present invention, it is reduced to 5 ns. It was confirmed that From this result, considering the rate of delay with respect to the switching period, the present invention is particularly effective when the switching frequency of the resonant inverter is 5 MHz or higher.

FIG. 16 is a timing chart showing signal behavior of each part of the low-side gate drive circuit 52 in a transient state immediately after the input voltage Vin is turned on. Here, when the dead time starts at timing t11, since the amount of current is small, the falling slope of the switch voltage SW becomes gentle, and the fall detection signal VB1 is maintained at High. As a result, the gate signal VC1 is kept Low, the gate signal VD1 is kept High, and the low-side gate signal BG is kept Low.

However, since the low-side on signal BS-ON rises to High at timing t12, the transistor N14 is turned on and the gate signal VD1 becomes Low. At this time, since the transistor P12 is turned on by the low gate signal VC1, the low-side gate signal BG is set high. Therefore, the low side transistor BS can be forcibly turned on by the low side on signal BS-ON.

<5. High side gate drive circuit>
Next, the details of the high-side gate drive circuit 53 included in the power supply control device 51 will be described. FIG. 14 is a circuit diagram showing a configuration example of the high-side gate drive circuit 53. As shown in FIG.

As shown in FIG. 14, the high-side gate drive circuit 53 generates a high-side gate signal HG based on a rise detection section 531 that detects the rise of the switch voltage SW and a rise detection signal VB2 generated by the rise detection section 531. and a high-side gate signal generation unit 532 for generating.

The basic configuration of both the rising edge detection unit 531 and the high side gate signal generation unit 532 is the same as that of the low side gate drive circuit 52 shown in FIG. The reference of the offset voltage E is the switch voltage SW, and the reference of the predetermined power supply voltage V21 is the switch voltage SW.

Here, FIG. 17 is a timing chart showing signal behavior of each part of the high-side gate drive circuit 53 in steady operation. FIG. 17 shows, from the top, the switch voltage SW, the voltage difference between the input voltage Vin and the switch voltage SW (Vin-SW), the rise detection signal VB2, the gate signal VC2, the high side off signal HS-OFF, and the high side on. Signal HS-ON, gate signal VD2, and high side gate signal HG are shown.

First, when the high-side transistor HS is off, the low-side transistor BS is on, and the switch voltage SW is 0 V, Vin−SW becomes Vin (before timing t21), and the rise detection unit 531 consists of the capacitor C21 and the resistor R21. A voltage obtained by raising the output SW by the differentiating circuit by the offset voltage E is generated as the rising edge detection signal VB2 (rising edge detection signal VB2=High).

As a result, the level of the rise detection signal VB2 is inverted by the CMOS configuration of the transistors P21 and N21, and the gate signal VC2 becomes Low. The high side off signal HS-OFF is High and the high side on signal HS-ON is Low. Therefore, the transistors N23, P23, and N24 are off, and the voltage of the node ND27 (=gate signal VD2) is kept High. Here, although the resistor R22 is not essential, it is desirable to provide the resistor R22 because the voltage of the node ND27 becomes unstable if the resistor R22 is not provided.

Since the gate signal VD2 is High, the transistor N25 is on and the high side gate signal HG is Low.

Then, when the low-side transistor BS is turned off at timing t21, the dead time starts, the switch voltage SW starts rising, and Vin-SW starts falling. At this time, the voltage lower than SW output by the differentiating circuit is raised by the offset voltage E to become a voltage lower than SW, but the rising detection signal VB2 is set to SW by the diode D22. The diode D22 is provided in order to limit the voltage to SW even in such a case because a voltage considerably lower than SW occurs when the rising slope of the switch voltage SW is large. However, the diode D22 is not essential.

At this time, the gate signal VC2 becomes High due to the above CMOS configuration. As a result, the transistor N23 is turned on and the gate signal VD2 becomes Low. Since the transistor N22 is turned on by the gate signal VC2, the high side gate signal HG becomes Low.

Then, when the switch voltage SW reaches Vin at timing t22, a voltage obtained by raising the SW output by the differentiating circuit by the offset voltage E is generated as the rise detection signal VB2. That is, the rise detection signal VB2 rises from SW to SW+E. Then, the gate signal VC2 becomes Low, the high-side OFF signal HS-OFF is High, and the high-side ON signal HS-ON is Low, so the gate signal VD2 maintains Low. Since the transistor P22 is turned on by the gate signal VC2, the high side gate signal HG becomes High. As a result, the high-side transistor HS is turned on and the dead time ends.

After that, even if the high-side ON signal HS-ON rises to High at timing t23 and then falls to Low, the gate signal VD2 maintains Low because the transistor N24 turns on and then turns off.

Then, when the high-side off signal HS-OFF falls to Low at timing t24, the transistor P23 is turned on and the gate signal VD2 is set to High. As a result, the transistor N25 is turned on, and the high-side gate signal HG becomes Low. Therefore, the high-side transistor HS is turned off and dead time begins. As a result, the switch voltage SW starts to fall, and Vin-SW starts to rise.

Then, a voltage higher than SW is output by the differentiating circuit, but a voltage that is limited to SW by the diode D21 and raised by the offset voltage E is generated as the rising edge detection signal VB2 (rising edge detection signal VB2=High).

After that, even if the high-side off signal HS-OFF rises to High, the gate signal VD2 remains High because the transistor P23 is turned off.

Then, when the switch voltage SW reaches 0 V at timing t25, the low side transistor BS is turned on by the low side gate drive circuit 52, and the dead time ends. After that, since the switch voltage SW maintains 0V, the rise detection signal VB2=High, the gate signal VC2=Low, and the gate signal VD2 maintains High.

As described above, the high-side gate drive circuit 53 of the present embodiment is composed of a transistor, a diode, a resistor, and a capacitor, and does not use an IC. is raised to High, the high-side gate signal HG is set to High, and the high-side transistor HS can be turned on. Therefore, the delay from the ideal timing t22 of the ON timing of the high-side transistor HS can be suppressed, and the diode loss can be reduced.

FIG. 18 is a timing chart showing signal behavior of each part of the high-side gate drive circuit 53 in a transient state immediately after input voltage Vin is applied. Here, when the dead time starts at timing t31, since the amount of current is small, the rising slope of the switch voltage SW becomes gentle, the falling slope of Vin-SW becomes gentle, and the rise detection signal VB2 is High. maintained. As a result, the gate signal VC2 is kept Low, the gate signal VD2 is kept High, and the high-side gate signal HG is kept Low.

However, since the high-side ON signal HS-ON rises to High at timing t32, the transistor N24 is turned on and the gate signal VD2 becomes Low. At this time, since the transistor P22 is turned on by the low gate signal VC2, the high side gate signal HG is set high. Therefore, the high side transistor HS can be forcibly turned on by the high side on signal HS-ON.

<6. OFF Generation Circuit>
Next, the details of the off generation circuit 54 included in the power control device 51 will be described. FIG. 19 is a circuit diagram showing a configuration example of the off generation circuit 54. As shown in FIG.

The off generation circuit 54 shown in FIG. 19 has a flip-flop 54A, a triangular wave generator 54B, a comparator 54C, and a comparator 54D.

A high side off signal HS- ^OFF- is input to the set terminal (S) of the flip-flop 54A. A low-side off signal BS- ^OFF- is input to the reset terminal (R) of the flip-flop 54A. A Q output terminal of the flip-flop 54A is input to the triangular wave generator 54B. The triangular wave generator 54B is configured by connecting two RC circuits, for example. The triangular wave generator 54B generates a triangular wave signal SS based on the input from the Q output terminal.

A triangular wave signal SS is input to the non-inverting input terminal (+) of the comparator 54C. A reference voltage Vref is applied to the inverting input terminal (-) of the comparator 54C. The output of the comparator 54C becomes the low side off signal BS- ^OFF- . The comparator 54C also outputs a low side off signal BS- ^OFF obtained by inverting the low side off signal BS-OFF. This low side off signal BS-OFF is used in the low side gate driving circuit 52 .

The aforementioned feedback voltage FB (FIG. 12) is applied to the non-inverting input terminal (+) of the comparator 54D. A triangular wave signal SS is input to the inverting input terminal (-) of the comparator 54D. The output of the comparator 54D becomes the high side off signal HS- ^OFF- . A high side off signal HS- ^OFF obtained by inverting the high side off signal HS-OFF- is also output from the comparator 54D. This high side off signal HS-OFF is used in the high side gate drive circuit 53 .

FIG. 20 is a timing chart showing generation of an off signal by the off generation circuit 54 shown in FIG. When the triangular wave signal SS falls below the feedback voltage FB at timing t41, the high side off signal HS- ^OFF- becomes High and the flip-flop 54A is set. As a result, the output from the Q output terminal becomes High, and the triangular wave signal SS starts rising. Then, when the triangular wave signal SS exceeds the feedback voltage FB at timing t42, the high side off signal HS- ^OFF- becomes Low.

Thereafter, when the triangular wave signal SS continues to rise and reaches the reference voltage Vref at timing t43, the low-side off signal BS- ^OFF- becomes High. As a result, the flip-flop 54A is reset, the output from the Q output terminal becomes Low, and the triangular wave signal SS starts to drop. Then, when the triangular wave signal SS falls below the reference voltage Vref at timing t44, the low side off signal BS- ^OFF- becomes Low.

Thereafter, the triangular wave signal SS continues to drop, and when the triangular wave signal SS falls below the feedback voltage FB at timing t45, the high side off signal HS- ^OFF- becomes High.

<7. ON generation circuit>
Next, the details of the high-side on generation circuit 55 and the low-side on generation circuit 56 included in the power supply control device 51 will be described.

FIG. 21 is a circuit diagram showing a configuration example of the high side-on generation circuit 55. As shown in FIG. The high-side-on generation circuit 55 shown in FIG. 21 has an RC circuit 55A consisting of a resistor R551 and a capacitor C551, a flip-flop 55B, and an RC circuit 55C consisting of a resistor R552 and a capacitor C552.

The low side off signal BS- ^OFF- is input to the RC circuit 55A. The output of the RC circuit 55A is input to the set terminal (S) of the flip-flop 55B. The Q output of the flip-flop 55B becomes the high side ON signal HS-ON and is input to the RC circuit 55C. The output of the RC circuit 55C is input to the reset terminal (R) of the flip-flop 55B.

With such a configuration, when the low-side off signal BS- ^OFF- rises to High, the output of the RC circuit 55A rises according to the time constant and the flip-flop 55B is set. As a result, the high side on signal HS-ON can be raised to High after a certain period of time has passed since the low side off signal BS- ^OFF- rises.

When the high-side ON signal HS-ON becomes High, the output of the RC circuit 55C rises according to the time constant and the flip-flop 55B is reset. As a result, the high side on signal HS-ON falls to Low.

FIG. 22 is a circuit diagram showing a configuration example of the low-side-on generation circuit 56. As shown in FIG. The low-side-on generation circuit 56 shown in FIG. 22 has an RC circuit 56A consisting of a resistor R561 and a capacitor C561, a flip-flop 56B, and an RC circuit 56C consisting of a resistor R562 and a capacitor C562.

The high side off signal HS- ^OFF- is input to the RC circuit 56A. The output of RC circuit 56A is input to the set terminal (S) of flip-flop 56B. The Q output of the flip-flop 56B becomes the low side ON signal BS-ON and is input to the RC circuit 56C. The output of the RC circuit 56C is input to the reset terminal (R) of the flip-flop 56B.

With such a configuration, when the high-side off signal HS- ^OFF- rises to High, the output of the RC circuit 56A rises according to the time constant and the flip-flop 56B is set. As a result, the low-side on signal BS- ^ON can be raised to a high level after a certain period of time has passed since the high-side off signal HS-OFF- has risen.

When the low-side on signal BS-ON becomes High, the output of the RC circuit 56C rises according to the time constant and the flip-flop 56B is reset. As a result, the low side on signal BS-ON falls to Low.

<8. Circuit constant setting>
Next, as an example, a method of setting circuit constants for the differentiating circuit included in the falling edge detection unit 521 in the low-side gate drive circuit 52 described above will be described.

Here, FIG. 23 shows a differentiating circuit consisting of a capacitor C1 and a resistor R. FIG. This corresponds to a differentiating circuit consisting of a capacitor C11 and a resistor R11 in the fall detecting section 521. FIG. Furthermore, FIG. 23 shows a parasitic capacitance C2. This parasitic capacitance C2 represents a combined capacitance of the parasitic capacitances of the diodes D11 and D12 and the parasitic capacitance of the transistor N11 as shown in FIG.

In FIG. 23, let Vo be the output voltage when the input voltage Vi is applied to the capacitor C1. Here, as shown in FIG. 24, the output voltage Vo when the input voltage Vi that is tilted with time is applied is represented by the formula (1).

The Laplace transformation of formula (1) yields formula (2).

Equation (2) further becomes Equation (3).

When formula (3) is inversely Laplace-transformed and returned to the time domain, formula (4) is obtained.

となる。 From the equation (4), the amplitude of the output voltage Vo is

becomes.

Here, as shown in FIG. 25, when the switch voltage SW corresponding to the input voltage Vi is input to the differentiating circuit of the falling edge detection unit 521, the falling edge detection signal VB1 corresponding to the output voltage Vo is generated by the offset voltage E , then falls with the above voltage amplitude.

Although it is possible to turn off the transistor N11 if the voltage amplitude is lower than the threshold voltage Vth of the transistor N11 shown in FIG. Therefore, in this case, it is necessary to satisfy the expression (5).

Also, according to the equation (4), the output voltage Vo changes according to the time constant (C1+C2)R. Therefore, as shown in FIG. 25, when the voltage change reaches 63.2% (time constant), the threshold value Vth is considered to be exceeded, and the time constant is set below the allowable time Td. In this case, it is necessary to satisfy the expression (6).

The condition that satisfies both the above conditions (5) and (6) is the expression (7).

となる。 C1 and R are derived from the condition of expression (7). For example, Vin = 500 V, Δt = 10 ns, Td = 2 ns, Vgo = 5 V, C2 = 60 pF, equation (7) is

becomes.

となり、条件を満たす。 Here, if R=20Ω and C1=20pF,

and satisfies the conditions.

となり、条件を満たす。 Also, even if the constants of C1 and R deviate by ±20%,

and satisfies the conditions.

<9. Application to plasma processing apparatus>
Next, an example of applying the resonant inverter 50 according to the embodiment of the present invention to a plasma processing apparatus will be described with reference to FIG.

A plasma processing apparatus 65 shown in FIG. 26 has a resonance inverter 50 and a plasma processing section 60 . A plasma processor 60 is used as a load of the resonant inverter 50 .

The plasma processing unit 60 is, for example, a device for processing (etching, surface modification, etc.) a workpiece such as a wafer carried inside. In this case, the plasma processing section 60 is introduced with a gas for plasma discharge, and uses the high-frequency alternating current output from the resonance inverter 50 to bring the gas for plasma discharge into a plasma state. Then, the workpiece is processed using the generated plasma.

In addition, the plasma processing unit 60 can also be used for medical purposes such as sterilization.

<10. Application to wireless power supply system>
Next, an example of applying the resonance inverter 50 according to the embodiment of the present invention to a wireless power supply system will be described with reference to FIG. Wireless power supply is also called contactless power supply.

A wireless power supply system 70 shown in FIG. 27 includes a power supply device 701 and a battery pack 702 as an example of a power-supplied device. The power supply device 701 has a diode bridge 701A, a smoothing capacitor 701B, a resonance inverter 50, and a power transmission coil 701C.

The battery pack 702 also includes a power receiving coil 702A, a diode bridge 702B, a smoothing capacitor 702C, a charging circuit 702D, and a battery 702E.

The AC voltage from AC power supply 75 is rectified and smoothed by diode bridge 701A and smoothing capacitor 701B, and converted to DC input voltage Vin. The input voltage Vin is converted into an AC output voltage Vout by the resonance inverter 50 and applied to the power transmission coil 701C.

The power transmission coil 701C transmits power to the power reception coil 702A side by magnetic coupling. The power received by the receiving coil 702A is rectified and smoothed by a diode bridge 702B and a smoothing capacitor 702C, and converted to DC power. The charging circuit 702D charges the battery 702E based on the DC power.

In addition to the battery pack, the power-supplied device may be, for example, a smartphone or a vehicle.

<11. Semiconductor device>
For the high-side transistor HS and the low-side transistor BS in the resonant inverter 50 of this embodiment, semiconductor devices such as those described below, for example, may be used.

FIG. 28 is a perspective view of a semiconductor device. 29 is a plan view of a transistor in the semiconductor device shown in FIG. 28. FIG.

As shown in FIG. 28, the semiconductor device 1 includes a lead frame 10 for electrically connecting to a circuit board (not shown in FIG. 28), a transistor 20 mounted on the lead frame 10, and the transistor 20 sealed. and a sealing resin 30 . The transistor 20 is a HEMT (High Electron Mobility Transistor) using a nitride semiconductor. The semiconductor device 1 has a dimension of approximately 5 mm in the first direction X, which is the horizontal direction of the semiconductor device 1, approximately 6 mm in the second direction Y, which is the vertical direction of the semiconductor device 1, and a height direction of the semiconductor device 1. It consists of a package (sealing resin 30) with Z of approximately 0.6 mm. The semiconductor device 1 is of a surface mount type, and is a so-called SOP (Small Outline Package) in which lead frames are taken out from two directions of the sealing resin 30 .

The operating frequency range of the semiconductor device 1 is 1 MHz or more and 100 MHz or less, preferably 1 MHz or more and 30 MHz or less. The semiconductor device 1 of this embodiment is used at 30 MHz. The semiconductor device 1 can be applied to a circuit with a drain current range of 1 A or more and 200 A or less, and preferably applied to a circuit with a drain current range of 10 A or more and 100 A or less.

The sealing resin 30 is made of, for example, epoxy resin and formed into a rectangular plate shape. The sealing resin 30 has a top surface 31 and a bottom surface 32 facing the top surface 31 in the height direction Z. As shown in FIG. The back surface 32 is the surface to be mounted on the circuit board. The sealing resin 30 has a first lateral side 33 that is one side in the first direction X, a second lateral side 34 that is the other side in the first direction X, and a second lateral side 34 . It has a first vertical side 35 that is one side in the Y direction and a second vertical side 36 that is the other side in the second Y direction.

The transistor 20 is formed in a rectangular plate shape. The shape of the transistor 20 in plan view is a rectangle. The transistor 20 is placed on the lead frame 10 such that the first direction X is the longitudinal direction. As shown in FIG. 29, an example of the external size of the transistor 20 is such that the length L1 of one side in the longitudinal direction is approximately 4200 μm and the length L2 of the other side is approximately 2100 μm in plan view. It is a 2:1 rectangle. In the following description of the transistor 20 , when the direction is indicated, it means the direction of the transistor 20 when the transistor 20 is placed on the lead frame 10 .

The transistor 20 has a front surface 20a (see FIG. 28), which is one surface facing the lead frame 10 (see FIG. 28), and a back surface 20b (see FIG. 28), which is the other surface facing the front surface 20a. Five drain electrode pads 21, four source electrode pads 22, and one gate electrode pad 23 for electrical connection with the lead frame 10 are provided on the surface 20a. The drain electrode pads 21 are composed of four drain electrode pads 21P having a long longitudinal length LD and one drain electrode pad 21Q having a short longitudinal length LDE. The numbers of drain electrode pads 21, source electrode pads 22, and gate electrode pads 23 are optional. Therefore, for example, the number of drain electrode pads 21 and the number of source electrode pads 22 may differ. Also, the transistor 20 may have a plurality of gate electrode pads 23 . Further, in the following description, when all five drain electrode pads are indicated, they are referred to as drain electrode pads 21 .

As shown in FIG. 29, the drain electrode pads 21 and the source electrode pads 22 are alternately arranged in the longitudinal direction (first direction X) of the transistor 20 in plan view. Each of the drain electrode pad 21 and the source electrode pad 22 is formed in a substantially rectangular shape whose longitudinal direction is the direction perpendicular to the longitudinal direction of the transistor 20 (the second direction Y). The drain electrode pad 21 and the source electrode pad 22 are parallel to each other. Drain electrode pads 21 are arranged at both ends of the transistor 20 in the first direction X, respectively.

The gate electrode pad 23 is arranged at one end of the transistor 20 in the first direction X. As shown in FIG. The gate electrode pad 23 faces the drain electrode pad 21Q disposed at one end of the transistor 20 in the first direction X with a gap in the second direction Y therebetween. The gate electrode pad 23 is arranged near one end of the transistor 20 in the second direction Y, and the drain electrode pad 21Q is arranged near the other end in the second direction Y of the transistor 20 .

The length LD of the four drain electrode pads 21P and the length LS of the four source electrode pads 22 are equal to each other. The length LDE of the drain electrode pad 21Q is less than half the length LD. The length LG of the gate electrode pad 23 is equal to the length LDE. The width WD of the drain electrode pad 21, the width WS of the source electrode pad 22, and the width WG of the gate electrode pad 23 are all equal. Both ends of the drain electrode pad 21, the source electrode pad 22, and the gate electrode pad 23 in the second direction Y are formed in an arcuate shape that protrudes in the second direction Y. As shown in FIG.

The drain electrode pads 21 are arranged at equal intervals in the first direction X, and the source electrode pads 22 are arranged at equal intervals in the first direction X. As shown in FIG. The four drain electrode pads 21P and the four source electrode pads 22 are arranged at the same position in the second direction Y. As shown in FIG. The distances Dds between the drain electrode pads 21 and the source electrode pads 22 adjacent to the drain electrode pads 21 in the first direction X are equal. A distance Dsg between the gate electrode pad 23 and the source electrode pad 22 adjacent to the gate electrode pad 23 in the first direction X is equal to the distance Dds.

The dimensional relationship of the transistor 20 of FIG. 29 is as follows. The length LD of the four drain electrode pads 21P and the length LS of the four source electrode pads 22 are approximately 1760 μm, and the length LDE of the drain electrode pads 21Q is approximately 755 μm. The length LG of the gate electrode pad 23 is approximately 755 μm. Each of the width WD of the drain electrode pad 21, the width WS of the source electrode pad 22, and the width WG of the gate electrode pad 23 is approximately 240 μm.

A distance Ddg between the gate electrode pad 23 and the drain electrode pad 21Q in the second direction Y is approximately 250 μm. Each of the distances Dds between the drain electrode pad 21 and the source electrode pad 22 adjacent to the drain electrode pad 21 in the first direction X is approximately 200 μm. A distance Dsg between the gate electrode pad 23 and the adjacent source electrode pad 22 in the first direction X is approximately 200 μm.

The lead frame 10 includes a drain frame 11 electrically connected to a drain electrode pad 21 (see FIG. 29), a source frame 12 electrically connected to a source electrode pad 22 (see FIG. 29), and a gate electrode pad 23. (see FIG. 29). Each of the drain frame 11, the source frame 12, and the gate frame 13 is formed by etching a copper plate, for example. The drain frame 11, the source frame 12, and the gate frame 13 are electrically insulated from each other by being spaced apart from each other.

The drain frame 11 is arranged near the first vertical side surface 35 of the sealing resin 30 in plan view. The drain frame 11 includes four drain terminals 11a, a drain connecting portion 11b connecting the drain terminals 11a, and five drain connecting portions 11b extending from the drain connecting portion 11b toward the second vertical side surface 36 in the second direction Y. and drain frame fingers 11c. The drain frame fingers 11c extend along the second direction Y. As shown in FIG. Thus, the drain frame 11 is formed in a comb shape. The four drain terminals 11a, the drain connecting portions 11b, and the five drain frame fingers 11c are formed, for example, from a single member. The number of drain terminals 11a and the number of drain frame fingers 11c are optional items. For example, the number of drain terminals 11a and the number of drain frame fingers 11c may be the same or different. Also, the number of drain frame fingers 11c is preferably set according to the number of drain electrode pads 21 of the transistor 20 in FIG.

The drain terminal 11a is formed in a rectangular shape whose longitudinal direction is the second direction Y in plan view. The drain terminals 11a are arranged at equal intervals in the first direction X. As shown in FIG. The drain terminal 11 a is arranged at a position adjacent to the first vertical side surface 35 of the sealing resin 30 . One end of the drain terminal 11 a in the second direction Y protrudes from the first vertical side surface 35 toward the outside of the sealing resin 30 . The other end of the drain terminal 11a in the second direction Y is connected to the drain connecting portion 11b.

At both end portions of the drain connecting portion 11b in the first direction X, a first tie bar portion 11d for connecting the steel plate and the drain frame 11 when forming the drain frame 11 from a steel plate (not shown) serving as the base material of the drain. It is provided integrally with the connecting portion 11b. The first tie bar portion 11d extends along the first direction X from both ends of the drain connecting portion 11b. One first tie bar portion 11 d is formed from the drain connecting portion 11 b to the first lateral side surface 33 . The other first tie bar portion 11 d is formed from the drain connecting portion 11 b to the second lateral side surface 34 .

The drain frame fingers 11c are composed of four drain frame fingers 11P having a long length in the second direction Y and one drain frame finger 11Q having a short length in the second direction Y. FIG.

Second tie bar portions 11i and 11j are provided on the drain frame finger 11P at the end of the drain frame finger 11P on the side of the first lateral side 33 and the drain frame finger 11Q. The second tie bar portion 11i provided on the drain frame finger 11P extends along the second direction Y from the center position of the sealing resin 30 in the second direction Y toward the first lateral side surface 33 . The second tie bar portion 11 i is exposed from the first lateral side surface 33 . The second tie bar portion 11j provided on the drain frame finger 11Q extends along the second direction Y from the center position of the sealing resin 30 in the second direction Y toward the second lateral side surface . The second tie bar portion 11 j is exposed from the second lateral side surface 34 .

The source frame 12 is arranged closer to the second vertical side surface 36 of the sealing resin 30 in plan view. The source frame 12 is arranged near the first lateral side surface 33 of the sealing resin 30 in plan view. The source frame 12 includes three source terminals 12a, a source connecting portion 12b connecting the source terminals 12a, and four lines extending from the source connecting portion 12b toward the first vertical side surface 35 in the second direction Y. of source frame fingers 12c. Source frame fingers 12c extend along the second direction Y; Thus, the source frame 12 is formed in a comb shape. The plurality of source terminals 12a, the source connecting portions 12b, and the plurality of source frame fingers 12c are formed, for example, from a single member. Note that the number of source terminals 12a and the number of source frame fingers 12c are arbitrary setting items. For example, the number of source terminals 12a and the number of source frame fingers 12c may be the same or different. The number of source frame fingers 12c is preferably set according to the number of source electrode pads 22 of transistor 20 in FIG.

The source terminal 12a is formed in a rectangular shape whose longitudinal direction is the second direction Y in plan view. The source terminals 12a are arranged at regular intervals in the first direction X. As shown in FIG. The source terminal 12 a is arranged at a position adjacent to the second vertical side surface 36 of the sealing resin 30 . One end of the source terminal 12 a in the second direction Y protrudes from the second vertical side surface 36 toward the outside of the sealing resin 30 . The other end of the source terminal 12a in the second direction Y is connected to the source connecting portion 12b. The position in the first direction X of the source terminal 12a is equal to the position in the first direction X of the drain terminal 11a. The width of the source terminal 12a (dimension of the source terminal 12a in the first direction X) is equal to the width of the drain terminal 11a.

At the end of the source connecting portion 12b on the side of the first lateral side 33, there is provided a tie bar portion 12d for connecting a steel plate (not shown) serving as a base material to the source frame 12 when the source frame 12 is formed. It is The tie bar portion 12d extends along the first direction X from the end portion of the source connecting portion 12b to the first lateral side surface 33. As shown in FIG.

The gate frame 13 is arranged near the second vertical side surface 36 of the sealing resin 30 in plan view. Further, the gate frame 13 is arranged closer to the second lateral side surface 34 of the sealing resin 30 in plan view. The gate frame 13 includes gate terminals 13a, gate connecting portions 13b, and gate frame fingers 13c. The gate frame 13 is arranged adjacent to the source frame 12 in the first direction X. As shown in FIG.

The gate terminal 13a is formed in a rectangular shape whose longitudinal direction is the second direction Y in plan view. The gate terminal 13 a is arranged at a position adjacent to the second vertical side surface 36 of the sealing resin 30 . One end of the gate terminal 13 a protrudes from the second vertical side surface 36 toward the outside of the sealing resin 30 in the second direction Y. As shown in FIG. The other end of the gate terminal 13a in the second direction Y is connected to the gate connecting portion 13b. The position of the gate terminal 13a in the first direction X is equal to the position in the first direction X of the drain terminal 11a arranged at the end portion of the drain terminal 11a on the side of the second lateral side 34 . The width of the gate terminal 13a (the dimension of the gate terminal 13a in the first direction X) is equal to the width of the drain terminal 11a.

The gate connecting portion 13b connects the gate terminal 13a and the gate frame fingers 13c. The position in the second direction Y of the gate connection portion 13b is equal to the position in the second direction Y of the source connection portion 12b. At the end of the gate connecting portion 13b on the side of the second side surface 34, a tie bar portion 13d is provided for connecting a steel plate (not shown) serving as a base material to the gate frame 13 when the gate frame 13 is formed. It is The tie bar portion 13d extends along the first direction X from the end portion of the gate connecting portion 13b to the second lateral side surface .

The gate frame finger 13c is arranged on the side opposite to the gate terminal 13a with respect to the gate connecting portion 13b. The gate frame finger 13c extends along the second direction Y from the end of the gate connecting portion 13b on the first side surface 33 side. The length of gate frame finger 13c is shorter than the length of source frame finger 12c.

The position in the first direction X of gate frame finger 13c is equal to the position in first direction X of drain frame finger 11Q. Gate frame fingers 13c are parallel to source frame fingers 12c. The gate frame finger 13c is arranged closer to the second vertical side surface 36 than the drain frame finger 11Q. That is, in the second direction Y, the tips of the gate frame fingers 13c face the tips of the drain frame fingers 11Q.

<12. Others>
Although the embodiments of the present invention have been described above, various modifications can be made to the embodiments within the scope of the present invention.

INDUSTRIAL APPLICABILITY The present invention can be used for resonance inverters used in various devices.

50 resonance inverter 51 power supply control device 52 low side gate drive circuit 521 fall detection unit 522 low side gate signal generation unit 53 high side gate drive circuit 531 rise detection unit 532 high side gate signal generation unit 54 off generation circuit 55 high side on generation circuit 56 Low-side ON generation circuit HS High-side transistor BS Low-side transistor L1 Inductor CR1 Capacitor Z Load 60 Plasma processing unit 65 Plasma processing device 70 Wireless power feeding system 701 Power feeding device 702 Battery pack

Claims (21)

A gate drive circuit used in a resonant inverter having a high-side transistor on the input voltage side and a low-side transistor on the ground potential side to drive the gate of the low-side transistor,
a first capacitor to one end of which a switch voltage generated at a first node where the high-side transistor and the low-side transistor are connected is applied;
a first resistor having one end connected to the other end of the first capacitor and having the other end applied with a voltage obtained by adding an offset voltage from a reference ground potential;
a first diode having an anode connected to a second node where the other end of the first capacitor and one end of the first resistor are connected, and a cathode connected to the other end of the first resistor;
and a fall detector that detects a fall of the switch voltage. The falling edge detection unit
2. The device according to claim 1, further comprising a second diode having a cathode connected to a third node to which the other end of said first resistor and the cathode of said first diode are connected, and having an anode connected to a ground potential application terminal. A gate drive circuit as described. further comprising a low side gate signal generation unit that generates a low side gate signal for driving the low side transistor based on the fall detection signal generated by the fall detection unit;
The low side gate signal generation unit
a CMOS configuration configured between a first power supply voltage and a ground potential and receiving the fall detection signal;
a first p-channel MOSFET having a gate to which the output terminal of the CMOS configuration is connected, and a source to which the application terminal of the first power supply voltage is connected;
a first n-channel MOSFET having a gate connected to the output end of the CMOS structure, a drain connected to the drain of the first p-channel MOSFET, and a source connected to a ground potential application end;
a second n-channel MOSFET having a gate connected to the output terminal of the CMOS structure and a source connected to the application terminal of the ground potential;
a third n-channel MOSFET having a gate connected to the drain of the second n-channel MOSFET, a drain connected to the drain of the first n-channel MOSFET, and a source connected to a ground potential application terminal;
3. A gate drive circuit as claimed in claim 1 or claim 2, comprising: 4. The gate drive circuit according to claim 3, wherein said low-side gate signal generator further comprises a second resistor connected between the drain of said second n-channel MOSFET and a ground potential application terminal. The low-side gate signal generation unit is a second p-channel having a source connected to the application terminal of the first power supply voltage, a drain connected to the drain of the second n-channel MOSFET, and a gate to which a low-side off signal is applied. 5. A gate drive circuit as claimed in claim 3 or claim 4, further comprising a MOSFET. The low-side gate signal generator further includes a fourth n-channel MOSFET having a drain to which the drain of the second n-channel MOSFET is connected, a source to which a ground potential application terminal is connected, and a gate to which a low-side on signal is applied. 6. A gate drive circuit as claimed in any one of claims 3 to 5, comprising: A power control device comprising the gate drive circuit according to claim 5 and an off generation circuit that generates the low side off signal,
The off generation circuit is
a first flip-flop;
a triangular wave generator that generates a triangular wave signal based on the output of the first flip-flop;
a first comparator to which the triangular wave signal and the reference voltage are input;
a second comparator to which the triangular wave signal and a feedback voltage based on the output voltage of the resonant inverter are input;
has
The first flip-flop is reset by the output of the first comparator,
The first flip-flop is set by the output of the second comparator,
The low side off signal is based on the output of the first comparator,
The power control device, wherein the high side off signal is based on the output of the second comparator. A power control device comprising the gate drive circuit according to claim 6 and a low side on generation circuit for generating the low side on signal,
The low-side on generation circuit is
a first RC circuit to which a high side off signal is input;
a second flip-flop;
a second RC circuit to which the output of the second flip-flop is input;
has
The second flip-flop is set by the output of the first RC circuit,
The second flip-flop is reset by the output of the second RC circuit,
The power control device, wherein the low-side on signal is based on the output of the second flip-flop. A gate drive circuit used in a resonant inverter having a high-side transistor on the input voltage side and a low-side transistor on the ground potential side to drive the gate of the high-side transistor,
a first capacitor to one end of which the input voltage is applied;
A first capacitor having one end connected to the other end of the first capacitor and having the other end applied with an offset voltage based on a switch voltage generated at a first node where the high-side transistor and the low-side transistor are connected. resistance and
a first diode having an anode connected to a second node where the other end of the first capacitor and one end of the first resistor are connected, and a cathode connected to the other end of the first resistor;
and a rise detector that detects the rise of the switch voltage. The rising edge detection unit
10. Further comprising a second diode having a cathode connected to a third node to which the other end of said first resistor and a cathode of said first diode are connected, and having an anode connected to said switch voltage application terminal. The gate drive circuit according to . further comprising a high side gate signal generation unit that generates a high side gate signal for driving the high side transistor based on the rising detection signal generated by the rising detection unit;
The high side gate signal generation unit
a CMOS configuration configured between a first power supply voltage and the switch voltage and receiving the rise detection signal;
a first p-channel MOSFET having a gate to which the output terminal of the CMOS configuration is connected, and a source to which the application terminal of the first power supply voltage is connected;
a first n-channel MOSFET having a gate connected to the output terminal of the CMOS configuration, a drain connected to the drain of the first p-channel MOSFET, and a source connected to the application terminal of the switch voltage;
a second n-channel MOSFET having a gate connected to the output terminal of the CMOS configuration and a source connected to the application terminal of the switch voltage;
a third n-channel MOSFET having a gate to which the drain of the second n-channel MOSFET is connected, a drain to which the drain of the first n-channel MOSFET is connected, and a source to which the switch voltage application terminal is connected;
11. A gate drive circuit as claimed in claim 9 or claim 10, comprising: 12. The gate drive circuit according to claim 11, wherein said high side gate signal generator further comprises a second resistor connected between the drain of said second n-channel MOSFET and said switch voltage application terminal. The high side gate signal generator has a source connected to the application terminal of the first power supply voltage, a drain connected to the drain of the second n-channel MOSFET, and a gate to which a high side off signal is applied. 13. A gate drive circuit as claimed in claim 11 or claim 12, further comprising a 2p-channel MOSFET. The high-side gate signal generating section is a fourth n-channel having a drain connected to the drain of the second n-channel MOSFET, a source connected to the application end of the switch voltage, and a gate to which a high-side ON signal is applied. 14. A gate drive circuit as claimed in any one of claims 11 to 13, further comprising a MOSFET. A power control device comprising the gate drive circuit according to claim 13 and an off generation circuit that generates the high side off signal,
The off generation circuit is
a first flip-flop;
a triangular wave generator that generates a triangular wave signal based on the output of the first flip-flop;
a first comparator to which the triangular wave signal and the reference voltage are input;
a second comparator to which the triangular wave signal and a feedback voltage based on the output voltage of the resonant inverter are input;
has
The first flip-flop is reset by the output of the first comparator,
The first flip-flop is set by the output of the second comparator,
The low side off signal is based on the output of the first comparator,
The power control device, wherein the high side off signal is based on the output of the second comparator. A power supply control device comprising the gate drive circuit according to claim 14 and a high side-on generation circuit that generates a front high side-on signal,
The high side-on generation circuit is
a first RC circuit to which a low-side off signal is input;
a second flip-flop;
a second RC circuit to which the output of the second flip-flop is input;
has
The second flip-flop is set by the output of the first RC circuit,
The second flip-flop is reset by the output of the second RC circuit,
The power control device, wherein the high side on signal is based on the output of the second flip-flop. 15. A power control device comprising the gate drive circuit according to any one of claims 1 to 6 and 9 to 14. A resonant inverter comprising: the power control device according to claim 17; and a high-side transistor and a low-side transistor driven and controlled by the power control device. 19. The resonant inverter according to claim 18, wherein said high-side transistor and said low-side transistor are configured with GaN (gallium nitride) as a semiconductor material. 20. A plasma processing apparatus comprising: the resonance inverter according to claim 18 or 19; and a plasma processing section serving as a load of the resonance inverter. A first rectifying/smoothing section, the resonant inverter according to claim 18 or claim 19, which receives a DC voltage output from the first rectifying/smoothing section as an input voltage, and a power transmitting coil that serves as a load of the resonant inverter. a power supply device having a
a power-supplied device having a power receiving coil and a second rectifying/smoothing section to which the output of the power receiving coil is input;
A wireless power supply system.

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