JP7255970B2 - LAMINATED SEMICONDUCTOR CHIP MANUFACTURING METHOD AND INTERMEDIATE SUBSTRATE - Google Patents

Description

The present technology relates to a method for manufacturing a laminated semiconductor chip in which a plurality of semiconductor chips are laminated, and relates to an intermediate substrate in which a plurality of semiconductor chips are laminated on a base material.

In recent years, in the method of manufacturing stacked semiconductor chips, in order to overcome the planar limit of integration density, multiple semiconductor chips are stacked via adhesive layers to increase the three-dimensional integration in the height direction. technology is being considered.

For example, a method of stacking semiconductor chips called COC (Chip on Chip), a method of stacking semiconductor chips on a glass stick called COS (Chip On glass Stick), and a method of stacking semiconductor chips on a glass stick called COW (Chip on Wafer) A method has been developed in which semiconductor chips are stacked on a shaped wafer and then divided.

For example, in the method of mounting a semiconductor chip of the COC method or the COS method, as shown in FIGS. 14 to 16, a method of mounting a semiconductor chip 105 on an interposer 110 and molding is used. For example, the interposer 110 can use a type of printed circuit board, and the material used is the same glass-fiber-filled epoxy as the printed circuit board.

In the COC method or COS method of mounting a semiconductor chip, as shown in FIG. 14, the lower connection terminals 107 of the semiconductor chip 105a are brought into contact with the electrodes 111 of the interposer 110 via an adhesive member 106 such as solder, and heat is applied. The semiconductor chip 105 is mounted on the interposer 110 by heat-pressing from above with a compression bonder (TC tool) 120 . After that, as shown in FIG. 15, the lower connection terminals 107 of another semiconductor chip 105b are brought into contact with the upper connection terminals 108 of the semiconductor chip 105a via an adhesive member 106 such as solder, and then bonded together by a thermocompression bonder 120. As shown in FIG. The semiconductor chip 105b is mounted on the interposer 110 by heating and pressing from above.

Then, the semiconductor chips 105 are stacked a required number of times, and are sequentially heat-pressed by the thermocompression bonder 120 to stack the semiconductor chips 105 on the interposer 110 up to the desired number of layers, thereby forming a semiconductor chip stack. . Note that FIG. 15 illustrates a four-layer laminated structure of the semiconductor chips 105a, 105b, 105c, and 105d.

After that, as shown in FIG. 16, an underfill material 130 is injected into the gaps between the stacked semiconductor chips 105 and thermally cured to form a mold, thereby completing the stacking of the semiconductor chips 105a, 105b, 105c, and 105d. do. As the underfill material 130, a composite resin mainly composed of epoxy resin is used.

17 and 18, in the method of mounting a semiconductor chip by the COC method or the COS method, after coating or attaching a film-like underfill material 131 to the semiconductor chip 105, an underfill material 131 is applied. There is also a method of stacking and mounting semiconductor chips by stacking a plurality of semiconductor chips 105 with a filling material 131 attached thereto and collectively heat-pressing them with a thermocompression bonder 120 .

In any of the above-described methods, the laminated semiconductor chip composed of the semiconductor chips 105 laminated on the interposer 110 is diced to cut out individual laminated semiconductor chips.

JP 2014-154697 A

However, in the method of manufacturing a laminated semiconductor chip by the COC method or the COS method described above, since the semiconductor chips are laminated layer by layer on the interposer using a thermocompression bonder, it takes a number of steps to complete the three-dimensional package. As a result, the manufacturing time is increased, which is not preferable for mass production.

In addition, there is a problem that, for example, a clearance of at least about 30 μm must be secured between the semiconductor chips in the stacking direction so that the underfill material can be injected into the stacked semiconductor chips.

In addition, it is necessary to provide a dam structure for blocking the underfill material in consideration of the overflow of the underfill material.

Therefore, it can be said that there is a limit to the improvement of mass productivity and the miniaturization of laminated semiconductor chips and interposers.

In the above-described COS method, COS method, or COW method, in the case of collectively stacking multiple semiconductor chips instead of stacking each layer, it is preferable from the viewpoint of mass production, but the gap between semiconductor chips during collective stacking is preferable. The underfill material applied or adhered to the surface melts and flows out in the planar direction during thermocompression bonding by a thermocompression bonder. As a result, the underfill material protrudes, and heat transfer from the thermocompression bonder causes misalignment of the semiconductor chip in the horizontal direction and voids in the underfill material. Therefore, it is necessary to secure the horizontal distance W1 between the semiconductor chips to some extent.

SUMMARY OF THE INVENTION Accordingly, the present invention provides a method for manufacturing laminated semiconductor chips and an intermediate substrate capable of improving the productivity of laminated semiconductor chips, miniaturizing the laminated semiconductor chips, and stabilizing the connection quality between the semiconductor chips. for the purpose.

In order to solve the above-described problems, a method for manufacturing a laminated semiconductor chip according to the present invention is a method for manufacturing a laminated semiconductor chip in which a plurality of semiconductor chips are laminated on a wiring board. a first stacking step of arranging the semiconductor chips in the horizontal direction and stacking the plurality of semiconductor chips on the mother wiring board via the first thermosetting adhesive film; A first thermocompression bonding step of collectively applying heat and pressure to form a first semiconductor chip layer with the base wiring board as a reference, and horizontally separating a plurality of other semiconductor chips on the first semiconductor chip layer. a second stacking step of stacking a plurality of other semiconductor chips on the first semiconductor chip layer via a second thermosetting adhesive film, and stacking a plurality of other semiconductor chips together; A second thermocompression bonding step of forming a second semiconductor chip layer with the base wiring board as a reference, and the second stacking step and the second thermocompression bonding step are repeated a desired number of times to form the base wiring. a dicing step of forming a plurality of semiconductor chip layers on the basis of the board, and then cutting out individual laminated semiconductor chips from the mother wiring board; , an organic peroxide, an epoxy resin, and an acid anhydride, and in the second lamination step, the second thermosetting adhesive film is laminated on the first semiconductor chip layer, Between the horizontally spaced semiconductor chips in the first semiconductor chip layer is filled with the second thermosetting adhesive film, and in the dicing step, between the horizontally spaced semiconductor chips in each of the semiconductor chip layers By vertically cutting each thermosetting adhesive film filled with , individual laminated semiconductor chips are cut out .

According to the method for manufacturing a laminated semiconductor chip according to the present invention, by laminating semiconductor chips, productivity of the laminated semiconductor chip can be improved, miniaturization of the laminated semiconductor chip can be achieved, and connection quality between the semiconductor chips can be achieved. can be stabilized.

Further, the intermediate substrate according to the present invention can cut out a larger number of laminated semiconductor chips from the intermediate substrate. It is possible to achieve both stabilization of connection quality between chips.

FIG. 1 is a cross-sectional view of an intermediate substrate for explaining a method of manufacturing a laminated semiconductor chip. FIG. 2 is a cross-sectional view for explaining a dicing process for cutting the laminated semiconductor chips from the intermediate substrate. FIG. 3 is a diagram for explaining the method of manufacturing the laminated semiconductor chip, and is a cross-sectional view for explaining a state in which the semiconductor chips of the first layer are placed on the interposer. FIG. 4 is a diagram for explaining a method for manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which a plurality of first-layer semiconductor chips are heat-pressed by a thermocompression bonder and bonded onto an interposer. FIG. 5 is a diagram for explaining a method of manufacturing a stacked semiconductor chip, and is a diagram for explaining a state in which a semiconductor chip of the second layer is placed on a semiconductor chip of the first layer. FIG. 6 is a diagram for explaining a method of manufacturing a laminated semiconductor chip, and explains a state in which a plurality of semiconductor chips in the second layer are heat-pressed by a thermocompression bonder and bonded onto the semiconductor chips in the first layer. It is a sectional view. FIG. 7 is a diagram for explaining a method of manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which a semiconductor chip of a third layer is placed on a plurality of semiconductor chips of a second layer. FIG. 8 is a diagram for explaining a method of manufacturing a laminated semiconductor chip, showing a state in which a plurality of semiconductor chips in the third layer are heat-pressed by a thermocompression bonder and bonded onto a plurality of semiconductor chips in the second layer. It is a sectional view explaining. FIG. 9 is a diagram for explaining the method of manufacturing the laminated semiconductor chip, and is a cross-sectional view for explaining a state in which the laminated semiconductor chip is cut out from the intermediate substrate. FIG. 10 is a flow chart for explaining the manufacturing process of the laminated semiconductor chip. FIG. 11 is a perspective view for explaining a step of mounting a semiconductor chip. FIG. 12 is a perspective view explaining a step of cutting out laminated semiconductor chips. FIG. 13 is a perspective view for explaining the process of picking up the cut laminated semiconductor. FIG. 14 is a diagram for explaining a conventional method for manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which a semiconductor chip is heated and pressed onto an interposer by a thermocompression bonder and bonded onto the interposer. FIG. 15 is a diagram for explaining a conventional method of manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which a plurality of semiconductor chips are laminated on an interposer. FIG. 16 is a diagram for explaining a conventional method of manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which the laminated semiconductor chip on the interposer is filled with an underfill material. FIG. 17 is a diagram for explaining a conventional method of manufacturing a laminated semiconductor chip, and is a cross-sectional view for explaining a state in which semiconductor chips coated or attached with an underfill material are laminated on an interposer. FIG. 18 is a diagram illustrating a conventional method for manufacturing a laminated semiconductor chip, in which a semiconductor chip coated or pasted with an underfill material is laminated on an interposer, heated and pressed by a thermocompression bonder, and bonded onto the interposer. It is a sectional view explaining a state to do.

Hereinafter, a method for manufacturing a laminated semiconductor chip and an intermediate substrate to which the present invention is applied will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and of course various modifications are possible without departing from the gist of the present invention. Also, the drawings are schematic, and the ratio of each dimension may differ from the actual one. Specific dimensions and the like should be determined with reference to the following description. In addition, it goes without saying that there are portions with different dimensional relationships and ratios between the drawings.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail in the following order.
1. Laminated semiconductor chip2. Intermediate substrate 3 . Arrangement of semiconductor chips4. Thermosetting adhesive film5. 6. Manufacturing method of laminated semiconductor chip. Example

<1. Laminated Semiconductor Chip>
As shown in FIG. 1, the intermediate substrate 40 is a substrate in an intermediate process of manufacturing the laminated semiconductor chip 1 in which the semiconductor chips 5 are stacked. can do. Since the step of cutting out the individual laminated semiconductor chips 1 from the intermediate substrate 40 will be explained in detail in the explanation of the laminated semiconductor chip manufacturing method, first, the structure of the intermediate substrate 40 will be explained in detail.

<2. Intermediate substrate>
Specifically, the intermediate substrate 40 is formed by attaching a plurality of semiconductor chips 5 to an interposer (hereinafter also referred to as a base wiring board) 10 via a first thermosetting adhesive film 31 , and attaching the plurality of semiconductor chips 5 to the main surface of the interposer 10 . First semiconductor chip layer 41 spaced apart in the horizontal direction of 10 a , and other semiconductor chips 5 on first semiconductor chip layer 41 via second thermosetting adhesive film 32 . A second semiconductor chip layer 42 in which a plurality of semiconductor chips 5 are horizontally spaced apart on the first semiconductor chip layer 41, and a second semiconductor chip layer 42 on the plurality of semiconductor chips 5 of the second semiconductor chip layer 42 A third semiconductor chip layer 43 on which a plurality of other semiconductor chips 5 are horizontally spaced apart on the second semiconductor chip layer 42 via three thermosetting adhesive films 33, and laminated Each of the thermosetting adhesive films 31, 32, 33 is configured to fill the space between the horizontally spaced semiconductor chips 5 in each of the semiconductor chip layers 41, 42, 43. As shown in FIG.

The semiconductor chip 5 has an integrated circuit formed on the surface of a semiconductor such as silicon, and has an upper electrode 8 and a lower electrode 7 with solder 6 for connection called a bump. The lower electrode 7 with solder 6 is formed by joining solder to an electrode made of copper or the like, and has a total thickness of the thickness of the electrode and the thickness of the solder. The upper electrode 8 is an electrode made of copper or the like, but is not provided with solder 6 and is connected to the lower electrode 7 with solder 6 of another semiconductor chip 5 via solder 6 . It should be noted that the semiconductor chip 5 arranged in the uppermost stacked layer does not necessarily need to have the upper electrode 8 .

As the solder 6, Sn-37Pb eutectic solder (melting point 183° C.), Sn—Bi solder (melting point 139° C.), Sn-3.5Ag (melting point 221° C.), Sn-3.0Ag-0.5Cu (melting point 217° C.), ° C.), Sn-5.0Sb (melting point 240° C.) and the like can be used.

The interposer 10 is, for example, a circuit board in which a circuit is formed on a base material such as a rigid board or a flexible board, and serves as a base wiring board on which the semiconductor chips 5 are laminated. In the interposer 10, a counter electrode 11 having a predetermined thickness is formed in a mounting portion on which the semiconductor chip 5 is mounted, at a position facing the lower electrode 7 with the solder 6 of the semiconductor chip 5. As shown in FIG.

The first to third thermosetting adhesive films 31, 32, 33 are adhesive layers containing a film-forming resin, an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide. .

The intermediate substrate 40 is configured to have a plurality of semiconductor chip layers in which a required number of thermosetting adhesive films and semiconductor chips are alternately laminated. Although FIG. 1 shows a stacked structure of up to three layers consisting of the first to third semiconductor chip layers 41, 42 and 43, it goes without saying that the present invention is not limited to this.

<3. Arrangement of Semiconductor Chip>
As shown in FIG. 1, a plurality of semiconductor chips 5 are provided in each of the first to third semiconductor chip layers 41, 42, and 43 with a predetermined interval W2 in the horizontal direction. Spaces separated from each other in the plurality of semiconductor chips 5 are filled with upper and lower first to third thermosetting adhesive films 31, 32, and 33. are electrically and mechanically isolated in the vertical direction. In addition, the plurality of semiconductor chips 5 are filled with first to third upper and lower thermosetting adhesive films 31, 32, 33 in spaces separated from each other in the horizontal direction, and are electrically and mechanically isolated.

The interval W2 can be made narrower than W1 shown in FIG. In the present embodiment, since the portion indicated by the interval W2 is filled with the first to third thermosetting adhesive films 31, 32, and 33, which are the underfill materials, it is necessary to consider the overflow of the underfill materials. This is because there is no need to provide a dam structure to dam the underfill material. In addition, in the present embodiment, since the portion indicated by the interval W2 is filled with the first to third thermosetting adhesive films 31, 32, and 33, which are underfill materials, the horizontal direction (two-dimensional direction) Therefore, it is possible to prevent the semiconductor chip 5 from being displaced, and it is possible to prevent voids from being generated in the underfill material.

The semiconductor chip 5 has a rectangular plate-like structure when viewed from the top of the interposer 10, and is horizontally oriented on the main surface 10a of the interposer 10, as will be described later in the manufacturing method of the semiconductor device. are arranged side by side in a grid pattern. That is, the semiconductor chips 5 are laid out in a grid pattern so as to increase the degree of integration in the horizontal direction (two-dimensional direction) of the mounting portion of the interposer 10 .

In addition, the semiconductor chip 5 is formed by alternately laminating the first to third thermosetting adhesive films 31, 32, 33 and the semiconductor chip 5, and the degree of integration in the vertical direction (three-dimensional direction) of the mounting portion of the interposer 10 is increased. are arranged to be higher.

In FIG. 1, two semiconductor chips 5 are arranged side by side in the horizontal direction (two-dimensional direction) in a cross-sectional view. Needless to say, it is preferable to increase the number of arrangement of .

Here, as shown in FIG. 1, the semiconductor chips 5 forming the first semiconductor chip layer 41, which is the bottom layer, are denoted by semiconductor chip 5a1, semiconductor chip 5a2, and so on. The semiconductor chips 5 forming the second semiconductor chip layer 42, which is an intermediate layer, are denoted by semiconductor chips 5b1, semiconductor chips 5b2, and so on. The semiconductor chips 5 forming the third semiconductor chip layer 43, which is the uppermost layer, are denoted by semiconductor chips 5c1, semiconductor chips 5c2, and so on. Moreover, it shall be similarly described also in subsequent drawings.

In addition, the intermediate substrate 40 is a semiconductor lamination in which the semiconductor chips 5a1, 5b1, and 5c1 are stacked in this order from the interposer 10 side, and the semiconductor chips 5a2, 5b2, and 5c2 are stacked in this order from the interposer 10 side in the vertical direction (three-dimensional direction). Two or more semiconductor laminated structures are arranged in the horizontal direction (two-dimensional direction).

It should be noted that four or more semiconductor chip layers can be stacked. In the present embodiment, a three-layer laminated structure is described for the sake of simplification of explanation, but the number of times of lamination can be set appropriately to stack up to a desired layer from the second semiconductor chip layer 42 onwards. is possible, but the description with the reference numerals turned down will be omitted.

The semiconductor chips 5a1 and 5b1 forming the first semiconductor chip layer 41 each have a lower electrode 7 on the lower surface and an upper electrode 8 on the upper surface, and the lower electrode 7 is provided with solder 6 as a connecting material. The semiconductor chips 5a2 and 5b2 forming the second semiconductor chip layer 42 each have a lower electrode 7 on the lower surface and an upper electrode 8 on the upper surface, and the lower electrode 7 is provided with solder 6 as a connecting material. The semiconductor chips 5c1 and 5c2 forming the third semiconductor chip layer 43 have lower electrodes 7 on their lower surfaces, and the lower electrodes 7 are provided with solder 6 as a connection material.

Here, the semiconductor chips 5c1 and 5c2 forming the third semiconductor chip layer 43 are not provided with the upper electrode 8. As shown in FIG. This is a configuration for receiving pressure from a thermocompression bonder in batch compression bonding, which will be described later, on the top surface of the semiconductor chips 5c1 and 5c2, that is, a wider area than the semiconductor chip when the upper electrode 8 is provided. be. That is, since the upper surfaces of the semiconductor chips 5c1 and 5c2 without the upper electrodes 8 are flat surfaces, the pressure during pressing can be dispersed, and the heat conduction can be made uniform, so that appropriate thermocompression bonding can be performed.

Since no semiconductor chips are stacked on the semiconductor chips 5c1 and 5c2 forming the third semiconductor chip layer 43, which is the uppermost layer, there is no need to electrically connect the upper electrode 8. FIG. Therefore, since it is not necessary to provide the upper electrode 8 from a functional point of view, it is preferable to omit the upper electrode 8 from the viewpoint of simplifying the structure.

As shown in FIG. 2, the above-described intermediate substrate 40 includes the first to third semiconductor chip layers 41, 42, 43 of the first to third thermosetting adhesive films 31, 32, 33. The dicing cutter 60 cuts the portions filling the spaces between the semiconductor chips 5a1 and 5a2, the spaces between the semiconductor chips 5b1 and 5b2, and the space between the semiconductor chips 5a1 and 5b1, so that the individual stacked semiconductor chips 1 can be separated. .

Here, the laminated semiconductor chip 1 has a semiconductor lamination structure composed of a plurality of semiconductor chips 5 laminated on an interposer 10, and is a so-called three-dimensionally mounted semiconductor.

<4. Thermosetting adhesive film>
The first thermosetting adhesive film 31 is applied before mounting the semiconductor chips 5a1 and 5a2 on which the lower electrodes 7 with solder 6 are formed on the counter electrodes 11 of the interposer 10 facing the lower electrodes 7 with solder 6. It is a single sheet that is attached in advance to the counter electrode 11 side of the interposer 10 .

In addition, the second thermosetting adhesive film 32 mounts the semiconductor chips 5b1 and 5b2 having the lower electrodes 7 with the solder 6 formed thereon on the lowermost semiconductor chips 5a1 and 5a2 having the upper electrodes 8 formed thereon. It is a single sheet that is preliminarily pasted on the upper portions of the semiconductor chips 5a1 and 5a2 before the semiconductor chips 5a1 and 5a2 are formed.

Further, the third thermosetting adhesive film 33 mounts the semiconductor chips 5c1 and 5c2 having the lower electrodes 7 with the solder 6 formed thereon, on the intermediate layer semiconductor chips 5b1 and 5b2 having the upper electrodes 8 formed thereon. It is a single sheet that is preliminarily attached to the upper portions of the semiconductor chips 5b1 and 5b2 before the semiconductor chips 5b1 and 5b2 are formed.

In the above description, the first to third thermosetting adhesive films 31, 32, 33 are attached to the opposing electrode 11 of the interposer 10 and the upper electrode 8 of each semiconductor chip 5, respectively. Alternatively, the semiconductor chip 5 may be laminated on the lower electrode 7 side of each semiconductor chip 5 in advance.

However, it can be said that it is preferable to stack the layers from the lower layer as the stacking order from the viewpoint of ease of manufacture. Moreover, since the thermosetting adhesive film before curing is soft, it is difficult to laminate the semiconductor chip on the thermosetting adhesive film first in terms of manufacturing. Therefore, also from this point of view, it can be said that it is preferable to sequentially stack layers from the bottom in the stacking order.

In this case, the first to third thermosetting adhesive films 31, 32, and 33 are pre-bonded to the semiconductor chips 5a1 and 5a2, the semiconductor chips 5b1 and 5b2, and the semiconductor chips 5c1 and 5c2, respectively. to form the third semiconductor chip layers 41, 42 and 43;

The composition of the thermosetting adhesive film will now be described in detail. The film-forming resin corresponds to a high-molecular-weight resin having an average molecular weight of 10,000 or more, and preferably has an average molecular weight of about 10,000 to 100,000 from the viewpoint of film-forming properties. Various resins such as phenoxy resin, epoxy resin, modified epoxy resin, urethane resin, and acrylic rubber can be used as the film-forming resin. These film-forming resins may be used singly or in combination of two or more. Among these resins, phenoxy resin is preferably used in the present embodiment from the viewpoint of film formation state, connection reliability, and the like.

Examples of epoxy resins include dicyclopentadiene type epoxy resins, glycidyl ether type epoxy resins, glycidylamine type epoxy resins, bisphenol A type epoxy resins, bisphenol F type epoxy resins, bisphenol S type epoxy resins, spirocyclic epoxy resins, Naphthalene type epoxy resin, biphenyl type epoxy resin, terpene type epoxy resin, tetrabromobisphenol A type epoxy resin, cresol novolak type epoxy resin, phenol novolac type epoxy resin, α-naphthol novolak type epoxy resin, brominated phenol novolac type epoxy resin etc. can be mentioned. These epoxy resins may be used singly or in combination of two or more. Among these, in the present embodiment, it is preferable to use a dicyclopentadiene type epoxy resin from the viewpoint of high adhesiveness and heat resistance.

The acid anhydride has a flux function of removing the oxide film on the surface of the solder, so excellent connection reliability can be obtained. Examples of acid anhydrides include aliphatic acid anhydrides such as tetrapropenyl succinic anhydride and dodecenyl succinic anhydride; alicyclic acid anhydrides such as hexahydrophthalic anhydride and methyltetrahydrophthalic anhydride; Aromatic acid anhydrides such as mellitic acid and pyromellitic anhydride can be used. These epoxy curing agents may be used alone or in combination of two or more. Among these epoxy curing agents, it is preferable to use an aliphatic acid anhydride from the viewpoint of solderability.

Moreover, it is preferable to add a curing accelerator. Specific examples of curing accelerators include imidazoles such as 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, and 1,8-diazabicyclo(5,4,0)undecene-7 salt. (DBU salt), tertiary amines such as 2-(dimethylaminomethyl)phenol, phosphines such as triphenylphosphine, and metal compounds such as tin octylate.

Monofunctional (meth)acrylates and bifunctional (meth)acrylates can be used as acrylic resins. Monofunctional (meth)acrylates include methyl (meth)acrylate, ethyl (meth)acrylate, n-propyl (meth)acrylate, i-propyl (meth)acrylate, n-butyl (meth)acrylate and the like. Bifunctional or higher (meth)acrylates include bisphenol F-EO-modified di(meth)acrylate, bisphenol A-EO-modified di(meth)acrylate, trimethylolpropane PO-modified (meth)acrylate, polyfunctional urethane (meth)acrylate. etc. can be mentioned. These acrylic resins may be used alone or in combination of two or more. Among these, bifunctional (meth)acrylates are preferably used in the present embodiment.

Examples of organic peroxides include peroxyesters, peroxyketals, hydroperoxides, dialkyl peroxides, diacyl peroxides, and peroxydicarbonates. These organic peroxides may be used alone or in combination of two or more. Among these, peroxyester is preferably used in the present embodiment.

Moreover, it is preferable to contain an inorganic filler as another additive composition. By containing the inorganic filler, it is possible to adjust the fluidity of the resin layer during pressure bonding. As inorganic fillers, silica, talc, titanium oxide, calcium carbonate, magnesium oxide and the like can be used.

Furthermore, if necessary, a silane coupling agent such as epoxy, amino, mercapto-sulfide, or ureide may be added.

In this way, by using an epoxy system with a relatively slow curing reaction and an acrylic system with a relatively fast curing reaction together, it is possible to reduce the change in the temperature at which the minimum melt viscosity is reached when measured under different temperature elevation conditions. It becomes possible, and a wide mounting margin can be realized.

Specifically, when the melt viscosity is measured at a temperature increase rate of 5 ° C./min or more and 50 ° C./min or less, the minimum melt viscosity reaching temperature is 80 ° C. or more and 150 ° C. or less, and the minimum melt viscosity is 10000 (Pa s) below. As a result, voidless mounting and good solderability can be achieved without strictly controlling the temperature profile during thermocompression bonding.

Also, the minimum melt viscosity is preferably 1000 (Pa·s) or more and 2000 (Pa·s) or less. This can suppress the generation of voids during thermocompression bonding.

Also, the ratio of the total weight of the acrylic resin and the organic peroxide to the total weight of the epoxy resin and the acid anhydride is preferably 9:1 to 4:6, more preferably 8:2 to 6:4. is more preferable. As a result, it is possible to obtain a thermosetting adhesive film that achieves voidless mounting and good solderability in the method of manufacturing a laminated semiconductor chip, which will be described later.

Next, a method for manufacturing a pre-supply type underfill film in which the thermosetting adhesive film described above is formed into a film will be described. First, an adhesive composition containing a film-forming resin, an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide is dissolved in a solvent. As the solvent, toluene, ethyl acetate, etc., or a mixed solvent thereof can be used. After preparing the resin composition, it is applied onto a release substrate using a bar coater, a coating device, or the like.

The release base material has, for example, a laminated structure in which a release agent such as silicone is applied to PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), etc. It prevents the composition from drying and maintains the shape of the composition.

Next, the resin composition applied on the release base material is dried using a heat oven, a heat drying device, or the like. Thereby, a pre-supply type underfill film having a predetermined thickness can be obtained.

<5. Manufacturing Method of Laminated Semiconductor Chip>
A method of manufacturing a semiconductor device using the pre-supply type underfill material described above will be briefly described with reference to FIGS.

FIG. 3 is a cross-sectional view schematically showing the semiconductor chips 5a1 and 5a2 before mounting and the interposer 10, and FIG. FIG. 5 is a cross-sectional view schematically showing a state in which a second thermosetting adhesive film 32 is attached to the semiconductor chips 5a1 and 5a2 after thermocompression bonding, and the semiconductor chips 5b1 and 5b2 are mounted. FIG. 6 is a cross-sectional view schematically showing a state in which the semiconductor chips 5b1 and 5b2 are mounted and thermocompression bonding is performed, and FIG. FIG. 8 is a cross-sectional view schematically showing a state in which a flexible adhesive film 33 is attached and semiconductor chips 5c1 and 5c2 are mounted, and FIG. It is a sectional view showing.

As shown in FIG. 3, the first thermosetting adhesive film 31 in the present embodiment is attached in advance to the upper surface 10a side of the interposer 10 on which the counter electrode 11 is formed.

That is, an adhesive layer is formed by a single sheet-like first thermosetting adhesive film 31 so as to cover the counter electrode 11 of the interposer 10 .

Next, the semiconductor chips 5a1 and 5a2 are positioned on the first thermosetting adhesive film 31 so that the lower electrodes 7 with solder 6 of the semiconductor chips 5a1 and 5a2 and the counter electrodes 11 of the interposer 10 are aligned. installed.

Next, as shown in FIG. 4, the upper electrodes 8 of the semiconductor chips 5a1 and 5a2 are collectively heated and pressed by the head of the thermocompression bonder 20, so that the lower electrodes 7 of the semiconductor chips 5a1 and 5a2 are provided at the tips. The solder 6 is pressed against the counter electrode 11 of the interposer 10 . The first thermosetting adhesive film 31 is cured by thermocompression, and the lower electrodes 7 of the semiconductor chips 5 a 1 and 5 a 2 and the counter electrodes 11 of the interposer 10 facing the lower electrodes 7 are joined via the solder 6 . Thereby, the semiconductor chips 5a1 and 5a2 are fixed on the interposer 10, respectively.

Next, as shown in FIG. 5, the second thermosetting adhesive film 32 is attached in advance to the sides of the semiconductor chips 5a1 and 5a2 on which the upper electrodes 8 are formed.

Next, the semiconductor chips 5b1 and 5b2 are placed on the second thermosetting adhesive film 32 so that the lower electrodes 7 with solder 6 of the semiconductor chips 5b1 and 5b2 and the upper electrodes 8 of the semiconductor chips 5a1 and 5a2 are aligned. is positioned and installed.

Next, as shown in FIG. 6, the upper electrodes 8 of the semiconductor chips 5b1 and 5b2 are collectively heated and pressed by the head of the thermocompression bonder 20, and the lower electrodes 7 of the semiconductor chips 5b1 and 5b2 are provided at the tips. The solder 6 is pressed against the upper electrodes 8 of the semiconductor chips 5a1 and 5a2. The second thermosetting adhesive film 32 is cured by thermocompression bonding, and the lower electrodes 7 of the semiconductor chips 5b1 and 5b2 and the upper electrodes 8 of the semiconductor chips 5a1 and 5a2 facing the lower electrodes 7 are joined via the solder 6. be done. Thereby, the semiconductor chips 5b1 and 5b2 are fixed on the semiconductor chips 5a1 and 5a2, respectively.

Next, as shown in FIG. 7, a third thermosetting adhesive film 33 is attached in advance to the sides of the semiconductor chips 5b1 and 5b2 on which the upper electrodes 8 are formed.

Next, the semiconductor chips 5c1 and 5c2 are placed on the third thermosetting adhesive film 33 so that the lower electrodes 7 with solder 6 of the semiconductor chips 5c1 and 5c2 and the upper electrodes 8 of the semiconductor chips 5b1 and 5b2 are aligned. is positioned and installed.

Next, as shown in FIG. 8, the upper portions of the semiconductor chips 5c1 and 5c2 are collectively heated and pressed by the head of the thermocompression bonder 20, and the solder provided at the tips of the lower electrodes 7 of the semiconductor chips 5c1 and 5c2 is removed. 6 is pressed against the upper electrodes 8 of the semiconductor chips 5b1 and 5b2. The third thermosetting adhesive film 33 is cured by thermocompression bonding, and the lower electrodes 7 of the semiconductor chips 5c1 and 5c2 and the upper electrodes 8 of the semiconductor chips 5b1 and 5b2 facing the lower electrodes 7 are joined via the solder 6. be done. As a result, the semiconductor chips 5c1 and 5c2 are fixed onto the semiconductor chips 5b1 and 5b2.

After forming the intermediate substrate 40 as described above, as shown in FIG. 9, the redundant thermosetting adhesive films 31, 32, 33 portions A, B, and C are diced by a dicing cutter 60 to obtain a laminated semiconductor. Chip 1 is cut out.

FIG. 10 is a flow chart showing a method of manufacturing a laminated semiconductor chip according to this embodiment. As shown in FIG. 10, the method of manufacturing a laminated semiconductor chip according to the present embodiment includes a first attaching step S1 of attaching a first thermosetting adhesive film 31 on an interposer 10, and a plurality of semiconductor chips 5a1. , 5a2 on the first thermosetting adhesive film 31, a first thermocompression bonding step S3 of thermocompression bonding the plurality of semiconductor chips 5a1, 5a2, a plurality of semiconductor chips 5a1, 5a2, A second attaching step S4 of attaching a second thermosetting adhesive film 32 onto 5a2, and a second mounting step of attaching a plurality of semiconductor chips 5b1 and 5b2 to the second thermosetting adhesive film 32. S5 and a second thermocompression bonding step S6 for thermocompression bonding the plurality of semiconductor chips 5b1 and 5b2, a step S7 for determining whether or not the stacking is completed, and a step S7 for determining whether the stacking is completed; After repeating the n-th attaching step S4, the n-th mounting step S5, and the n-th thermocompression bonding step S6 and completing the lamination, a dicing step S8 of cutting out the laminated semiconductor chip 1 is provided.

Here, n is an integer of 2 or more, and in this embodiment, up to three layers are laminated, so steps S4 to S6 are repeated twice. At least, the sticking process, the mounting process, and the pressure bonding process are repeated two or more times to form a laminated structure. Needless to say, the number of times of stacking can be appropriately adjusted according to the integration density in the vertical direction (three-dimensional direction) on the interposer 10 .

FIG. 11 is a perspective view schematically showing the process of attaching the underfill film 2 onto the interposer 10. As shown in FIG. Here, the underfill film 2 is a roll-shaped film material from which the first to third thermosetting adhesive films 31, 32, and 33 are formed. 31, 32, and 33 are unwound and cut out from the roll of the underfill film 2 in required amounts.

As shown in FIG. 11, in the step S1 of attaching the first thermosetting adhesive film 31, the interposer 10 is fixed by a jig 3 having a ring-shaped or frame-shaped frame with a diameter larger than that of the interposer 10. Then, the first thermosetting adhesive film 31 unwound from the roll of the underfill film 2 is adhered onto the interposer 10 . Although the step of cutting the underfill film 2 is not shown, the first thermosetting adhesive film 31 can be cut out using an appropriate method. It should be noted that the details of cutting out the first to third thermosetting adhesive films 31, 32, and 33 will not be described hereinafter, but they may be cut out in advance or may be cut out in each step. .

The first thermosetting adhesive film 31 functions as an adhesive when mounting the plurality of semiconductor chips 5a1 and 5a2 on the interposer 10. FIG. A large number of ICs (Integrated Circuits) are built into the interposer 10, and as shown in FIG. 11 is provided.

Next, in a first mounting step S2 for mounting the plurality of semiconductor chips 5a1 and 5a2 on the first thermosetting adhesive film 31, a plurality of semiconductor chips 5a1 and 5a2 are mounted on the interposer 10 so that the counter electrode 11 and the lower electrode 7 face each other. semiconductor chips 5a1 and 5a2 are mounted.

Next, in the first thermocompression bonding step S3, the plurality of semiconductor chips 5a1 and 5a2 are heat-pressed by the thermocompression bonder 20, the first thermosetting adhesive film 31 is cured, and the interposer 10 and the plurality of semiconductor chips 5a1 and 5a2 are bonded together. Semiconductor chips 5a1 and 5a2 are bonded. As a result, the lower electrodes 7 of the plurality of semiconductor chips 5a1 and 5a2 and the opposing electrodes 11 of the interposer 10 are electrically and mechanically connected via the solder 6. FIG.

Next, in the second attaching step S4 of the second thermosetting adhesive film 32, the second heat unrolled from the underfill film 2 is applied onto the plurality of semiconductor chips 5a1 and 5a2 adhered on the interposer 10. A curable adhesive film 32 is applied. The second thermosetting adhesive film 32 functions as an adhesive when mounting the plurality of semiconductor chips 5b1 and 5b2 on the plurality of semiconductor chips 5a1 and 5a2.

Here, the first thermosetting adhesive film 31 and the second thermosetting adhesive film 32 are laminated so as to fill the space between the plurality of semiconductor chips 5a1 and 5a2. That is, the second thermosetting adhesive film 32 is attached so that no voids remain between the plurality of semiconductor chips 5a1 and 5a2. Here, the corresponding portion of the first thermosetting adhesive film 31 filling the space between the plurality of semiconductor chips 5a1 and 5a2 is indicated by A in the drawing, and the second portion filling the space between the plurality of semiconductor chips 5a1 and 5a2 is shown. 2 is indicated by B in the drawing.

Next, in a second mounting step S5 for mounting the plurality of semiconductor chips 5b1 and 5b2 on the second thermosetting adhesive film 32, the upper electrodes 8 on the plurality of semiconductor chips 5a1 and 5a2 and the plurality of semiconductor chips 5b1 are mounted. A plurality of semiconductor chips 5b1 and 5b2 are mounted so that the lower electrodes 7 of the semiconductor chips 5b1 and 5b2 face each other.

Next, in a second thermocompression bonding step S6, the plurality of semiconductor chips 5b1 and 5b2 are heat-pressed by the thermocompression bonder 20, the second thermosetting adhesive film 32 is cured, and the plurality of semiconductor chips 5a1 are bonded together. , 5a2 and a plurality of semiconductor chips 5b1 and 5b2 are bonded. As a result, the lower electrodes 7 of the plurality of semiconductor chips 5b1 and 5b2 and the upper electrodes 8 of the plurality of semiconductor chips 5a1 and 5a2 are electrically and mechanically connected via the solder 6. FIG.

Next, in the step S4 of attaching the third thermosetting adhesive film 33, the third film unwound from the underfill film 2 onto the plurality of semiconductor chips 5b1 and 5b2 adhered onto the plurality of semiconductor chips 5a1 and 5a2. A thermosetting adhesive film 33 is attached. The third thermosetting adhesive film 33 functions as an adhesive when mounting the plurality of semiconductor chips 5c1 and 5c2 on the plurality of semiconductor chips 5b1 and 5b2.

Here, the second thermosetting adhesive film 32 and the third thermosetting adhesive film 33 are laminated so as to fill the space between the plurality of semiconductor chips 5b1 and 5b2. That is, the third thermosetting adhesive film 33 is attached so that no voids remain between the plurality of semiconductor chips 5b1 and 5b2. Here, the corresponding portion of the second thermosetting adhesive film 32 filling the space between the semiconductor chips 5b1 and 5b2 is indicated by B in the drawing, and the second thermosetting adhesive film 32 filling the space between the semiconductor chips 5b1 and 5b2 is shown. The corresponding portion of the thermosetting adhesive film 33 of 3 is indicated by C in the figure.

Next, in a third mounting step S5 for mounting the plurality of semiconductor chips 5c1 and 5c2 on the third thermosetting adhesive film 33, the upper electrodes 8 on the plurality of semiconductor chips 5b1 and 5b2 and the plurality of semiconductor chips 5c1 are mounted. A plurality of semiconductor chips 5c1 and 5c2 are mounted so that the lower electrodes 7 of the semiconductor chips 5c1 and 5c2 face each other.

Next, in a third thermocompression bonding step S6, the plurality of semiconductor chips 5c1 and 5c2 are thermally pressed by the thermocompression bonder 20, the third thermosetting adhesive film 33 is cured, and the plurality of semiconductor chips 5b1 are bonded together. , 5b2 and a plurality of semiconductor chips 5c1 and 5c2 are bonded. As a result, the lower electrodes 7 of the plurality of semiconductor chips 5c1 and 5c2 and the upper electrodes 8 of the plurality of semiconductor chips 5b1 and 5b2 are electrically and mechanically connected via the solder 6. FIG. Here, the corresponding portion of the third thermosetting adhesive film 33 filling the space between the plurality of semiconductor chips 5c1 and 5c2 is indicated by C in the drawing.

Furthermore, in the lamination end judging step S7, by judging whether or not lamination is to be completed, lamination can be carried out by sequentially repeating the step of attaching a thermosetting adhesive film, the step of mounting a plurality of semiconductor chips, and the thermocompression bonding step as necessary. can be planned. Through the above steps, the intermediate substrate 40 is produced.

Next, the intermediate substrate 40 is diced in a dicing step S8, and laminated semiconductor chips are cut out as shown in FIG. FIG. 12 is a perspective view schematically showing the process of dicing the intermediate substrate 40. As shown in FIG. In the dicing step S8, the intermediate substrate 40 is cut by pressing the dicing cutter 60 along the scribe line to divide into individual laminated semiconductor chips. The locations where dicing is performed by the dicing cutter 60 are, as shown in FIGS. B and C.

FIG. 13 is a perspective view schematically showing a process of picking up stacked semiconductor chips. As shown in FIG. 13, the laminated semiconductor chip 1 bonded with each thermosetting adhesive film is held and picked up by a pick-up mechanism 20 .

In addition, it is preferable that the temperature conditions of 1st sticking process S1 and n-th sticking process S4 are 80 degreeC or more and 150 degrees C or less. Moreover, the pressure condition is preferably 0.5 MPa or less.

In addition, the temperature conditions of the first mounting step S2 and the n-th mounting step S5 are preferably 30° C. or more and 155° C. or less. Also, the pressure condition is preferably 50N or less, more preferably 40N or less. Also, the time condition is preferably 0.1 seconds or more and 10 seconds or less, more preferably 0.1 seconds or more and 1.0 seconds or less. As a result, the lower electrode 7 with the solder 6 is not melted and is in contact with the counter electrode 11 on the interposer 10 side, and the first thermosetting adhesive film 31 is not completely cured. can be done. Moreover, since the fixing is performed at a low temperature, it is possible to suppress the generation of voids and reduce the damage to the semiconductor chips 5a1 and 5a2.

In the first thermocompression bonding step S3 and the n-th thermocompression bonding step S6, for example, the lower electrode 7 with the solder 6 is heated from the first temperature to the second temperature at a predetermined heating rate. The solder 6 is melted to form a metallic bond and the first thermosetting adhesive film 31 is completely cured.

Further, in the first thermocompression bonding step 3, the head of the thermocompression bonder 20 is kept at a constant high elastic modulus up to the melting start temperature of the first thermosetting adhesive film 31 after mounting the semiconductor chips 5a1 and 5a2. After being kept at the same height, the temperature rises and the resin melts, causing the head to drop abruptly and reach the lowest point of the head. This lowest point is determined by the relationship between the descending speed of the head and the curing speed of the resin. After curing of the resin further progresses, it gradually rises due to thermal expansion of the resin and the head. The same applies to the n-th thermocompression bonding step 6 .

<6. Example>
Examples of the present invention will be described below. In this example, a pre-supply type underfill film was produced as a thermosetting adhesive film, and the melt viscosity was measured under the condition of a temperature increase rate of 5° C./min or more and 50° C./min or less.

Then, the underfill film is used to connect the lower layer semiconductor chip having the soldered lower electrode and the interposer having the counter electrode facing thereto, and the underfill film is used to connect the intermediate layer having the soldered lower electrode. and a lower semiconductor chip having an upper electrode facing thereto are connected, and an upper semiconductor chip having a lower electrode with solder using an underfill film and an upper electrode facing the upper semiconductor chip are connected. A mounting body was produced by connecting the semiconductor chip in the middle layer, and the mounting misalignment and electrical connection of the semiconductor chip were evaluated. However, the present invention is not limited to these examples.

Preparation of the mounted body, measurement of the lowest melt viscosity attainment temperature, melt viscosity and hardening rate, evaluation of mounting misalignment of the semiconductor chip, and evaluation of electrical connection were performed as follows.

[Production of mounting body]
The underfill film is laminated on the interposer with a laminating device using an elastic body, laminated on the semiconductor chip and the interposer via the underfill film, and pressed with a press at 250° C./10 sec/1 chip at a pressure of 30 N. Heat pressing is collectively performed in the horizontal direction under the condition of Furthermore, an underfill film is further laminated on the mounted semiconductor chip, the upper semiconductor chip and the lower semiconductor chip are laminated via the underfill film, and heat pressing is performed collectively in the horizontal direction. Create an intermediate substrate. Then, the intermediate substrate was diced to obtain a laminated semiconductor chip as a mounted body.

Here, as the elastic body used in the laminating apparatus, a material having a hardness of 50 or less by an A-type rubber hardness tester was used. As a result, the underfill film can be pressed and laminated on the interposer and the semiconductor chip so as to be in close contact with each other.

[Measurement of Minimum Melt Viscosity Temperature and Minimum Melt Viscosity]
For the underfill film, using a rheometer (ARES manufactured by TA), the minimum melt viscosity of the sample and the temperature at which the minimum melt viscosity was reached were measured under the conditions of 5°C/min and 1 Hz.

[Upper semiconductor chip]
The upper semiconductor chip has a size of 6 mm square and a thickness of 200 μm, and a peripheral arrangement in which a 5 μm thick solder (Sn-3.5Ag, melting point 221° C.) is formed at the tip of a lower electrode made of Cu with a thickness of 7 μm. pillars (φ20 μm, 1000 pins) were used.

[Intermediate layer semiconductor chip]
The semiconductor chip of the intermediate layer has a size of 6 mm square and a thickness of 50 μm. An upper electrode made of Cu with a thickness of 7 μm is formed. .5 Ag, melting point 221° C.) with peripherally arranged pillars (φ20 μm, 1000 pins).

[Interposer]
The interposer has a wafer size of approximately 304.8 mm (12 inches) in diameter and a thickness of 200 μm, and has peripherally arranged pillars (φ20 μm, 1000 pins) in which the upper electrode made of Cu with a thickness of 20 μm is plated with Ni/Au. was used.

An NCF (Non Conductive Film) having a thickness of 20 μm was used as an underfill film that serves as an adhesive layer.

After thermocompression bonding, curing was further performed at 150° C. for 2 hours to obtain a mounted body. The temperature when using the flip chip bonder is the actual temperature of the sample measured with a thermocouple.

As for the composition of NCF, the components shown in Table 1 were used. In addition, the evaluation of each mounting body was as shown in Table 2.

[Evaluation of mounting deviation]
In the evaluation of the mounting misalignment of the semiconductor chip, the state of connection between the upper electrode and the lower electrode of each semiconductor chip in the mounted body after dicing, and the state of connection between the counter electrode of the interposer and the lower electrode of the semiconductor chip were observed with X-rays. A case in which a shift of 5 μm or more occurred in the horizontal direction was rated as “Δ”, and a case in which the shift was less than 5 μm was rated as “◯”.

[Evaluation of continuity resistance]
For the evaluation of the conduction resistance, the conduction resistance of the mounted body after dicing was measured. Concerning the conduction resistance, based on the conduction resistance of the sample mounted body in which there is no mounting misalignment, when the conduction resistance is lower than +20%, it is evaluated as "○", and when the conduction resistance is +20% or more was evaluated as "△".

[comprehensive evaluation]
When both the evaluation of mounting misalignment and the evaluation of conduction resistance were "○", the overall evaluation was "○", and the other cases were evaluated as "Δ". It should be noted that even if the overall evaluation was "Δ", the predetermined performance could be obtained although it was not as good as the overall evaluation of "○".

[Example 1]
As shown in Table 1, the NCF in Example 1 was composed of 40 parts by mass of an acrylic acid ester copolymer (product name: Teresan Resin SG-P3, manufactured by Nagase ChemteX Corporation) as a film component, and an acrylic resin (product name: Oxol EA). -0200, manufactured by Osaka Organic Chemical Co., Ltd.) 98 parts by mass, organic peroxide (product name: Perhexa V, manufactured by NOF Corporation) 2 parts by mass, curing accelerator (product name: U-CAT-5002, manufactured by San-Apro Co., Ltd.) and 15 parts by mass of a filler (product name: Aerosil R202, manufactured by Nippon Aerosil Co., Ltd.) to prepare a resin composition for an underfill film. This was applied to release-treated PET (polyethylene terephthalate) using a bar coater and dried in an oven at 80°C for 3 minutes to prepare an underfill film with a thickness of 20 µm (cover release PET (25 µm)/underfill Film (20 μm)/base release PET (50 μm)).

The minimum melt viscosity attainment temperature t of NCF in Example 1 is 90 ° C., the minimum melt viscosity is 1200 (Pa s), the curing rate after 1 hour at a lamination temperature of 80 ° C. is 30%, and heating at 250 ° C. The hardening rate after mounting by applying pressure for 10 seconds (30 N per chip) was 90%.

As shown in Table 2, the evaluation of the samples in Example 1 was as follows: evaluation of mounting misalignment was "O", conduction resistance evaluation was "Δ", and overall evaluation was "Δ".

[Example 2]
As shown in Table 1, the NCF in Example 2 was composed of 40 parts by mass of an acrylic acid ester copolymer (product name: Teresan Resin SG-P3, manufactured by Nagase ChemteX Corporation) as a film component, and an acrylic resin (product name: Oxol EA). -0200, manufactured by Osaka Organic Chemical Co., Ltd.) 68 parts by mass, organic peroxide (product name: Perhexa V, manufactured by NOF Corporation) 2 parts by mass, epoxy resin (product name: JER1031S, manufactured by Mitsubishi Chemical Corporation) 20 parts by mass , 10 parts by mass of methyltetrahydrophthalic anhydride as an acid anhydride, 1 part by mass of a curing accelerator (product name: U-CAT-5002, manufactured by San-Apro Co., Ltd.), and 15 parts by mass of a filler (product name: Aerosil R202, manufactured by Nippon Aerosil Co., Ltd.). Parts by mass were blended to prepare a resin composition for an underfill film. This was applied to release-treated PET (polyethylene terephthalate) using a bar coater and dried in an oven at 80°C for 3 minutes to prepare an underfill film with a thickness of 20 µm (cover release PET (25 µm)/underfill Film (20 μm)/base release PET (50 μm)).

The minimum melt viscosity attainment temperature t of NCF in Example 2 is 100 ° C., the minimum melt viscosity is 1250 (Pa s), the lamination temperature is 80 ° C., the curing rate after 1 hour is 20%, heating at 250 ° C. The hardening rate after mounting by applying pressure for 10 seconds (30 N per chip) was 85%.

As shown in Table 2, the evaluation of the sample in Example 2 was "○" for the evaluation of the mounting misalignment, "○" for the evaluation of the conduction resistance, and "○" for the overall evaluation.

[Example 3]
As shown in Table 1, the NCF in Example 3 was composed of 40 parts by mass of an acrylic acid ester copolymer (product name: Teresan Resin SG-P3, manufactured by Nagase ChemteX Corporation) as a film component, and an acrylic resin (product name: Oxol EA). -0200, manufactured by Osaka Organic Chemical Co., Ltd.) 49 parts by mass, organic peroxide (product name: Perhexa V, manufactured by NOF Corporation) 1 part by mass, epoxy resin (product name: JER1031S, manufactured by Mitsubishi Chemical Corporation) 30 parts by mass , 20 parts by mass of methyltetrahydrophthalic anhydride as an acid anhydride, 1 part by mass of a curing accelerator (product name: U-CAT-5002, manufactured by San-Apro Co., Ltd.), 15 parts by mass of a filler (product name: Aerosil R202, manufactured by Nippon Aerosil Co., Ltd.) Parts by mass were blended to prepare a resin composition for an underfill film. This was applied to release-treated PET (polyethylene terephthalate) using a bar coater and dried in an oven at 80°C for 3 minutes to prepare an underfill film with a thickness of 20 µm (cover release PET (25 µm)/underfill Film (20 μm)/base release PET (50 μm)).

The minimum melt viscosity attainment temperature t of NCF in Example 3 is 120 ° C., the minimum melt viscosity is 1200 (Pa s), the curing rate after 1 hour at a lamination temperature of 80 ° C. is 10%, and heating at 250 ° C. The hardening rate after mounting by applying pressure for 10 seconds (30 N per chip) was 70%.

As shown in Table 2, the evaluation of the samples in Example 3 was "x" for the evaluation of the mounting misalignment, "o" for the conduction resistance evaluation, and "poor" for the overall evaluation.

In the embodiment, since the spaces between the semiconductor chips are filled without gaps by the underfill film, the semiconductor chip space W2 can be reduced, voidless mounting and good solder jointability can be realized, and a wide mounting margin can be achieved. I was able to make it happen.

The above-described laminated mounting body is produced by alternately repeating the steps of two-dimensionally arranging a plurality of semiconductor chips on an underfill film and collectively crimping them, further laminating the underfill film, laminating a plurality of semiconductor chips, and collectively crimping them. Since it is formed, problems such as voids due to the difference in the state of the underfill film due to the temperature difference during pressure bonding in the vertical direction, which is a problem when pressure bonding is performed all at once, can be avoided.

In addition, in the above-described intermediate board, which is a laminated mounting body, the space between the semiconductor chips is filled with an underfill film, so there is no need to secure a space or to prevent the underfill material from protruding. Not only the chip interval but also the horizontal semiconductor chip interval W2 can be narrowed, and the degree of integration of the laminated semiconductor chip in the two-dimensional direction can be improved. An increase in the number of picks can be expected.

Reference Signs List 1 semiconductor device 2 underfill film 3 jig 5 semiconductor chip 6 solder 7 lower electrode 8 upper electrode 10 interposer 10a main surface 11 counter electrode 20 31 first thermosetting adhesive film, 32 second thermosetting adhesive film, 33 third thermosetting adhesive film, 40 intermediate substrate, 41 first semiconductor chip layer, 42 second semiconductor chip layer, 43 third semiconductor chip layer, 60 dicing cutter

Claims (7)

A method for manufacturing a laminated semiconductor chip in which a plurality of semiconductor chips are laminated on a wiring board,
A first method for arranging a plurality of semiconductor chips horizontally on a mother wiring board and stacking the plurality of semiconductor chips on the mother wiring board via a first thermosetting adhesive film. a lamination process;
a first thermocompression bonding step of collectively applying heat and pressure to the plurality of semiconductor chips to form a first semiconductor chip layer on the basis of the base wiring board;
A plurality of other semiconductor chips are horizontally spaced apart from each other on the first semiconductor chip layer, and the other semiconductor chips are arranged on the first semiconductor chip layer via a second thermosetting adhesive film. A second stacking step of stacking a plurality of semiconductor chips of
a second thermocompression bonding step of collectively heating and pressurizing the other plurality of semiconductor chips to form a second semiconductor chip layer with the base wiring board as a reference;
Further, after repeating the second lamination step and the second thermocompression bonding step a desired number of times to form a plurality of semiconductor chip layers with the mother wiring board as a reference, individual laminated semiconductor chips are separated from the mother wiring board. and a dicing step of cutting out,
each of the thermosetting adhesive films comprises a film-forming resin, an acrylic resin, an organic peroxide, an epoxy resin, and an acid anhydride;
In the second laminating step, the second thermosetting adhesive film is laminated on the first semiconductor chip layer, and the semiconductor chips spaced apart in the horizontal direction in the first semiconductor chip layer are separated from each other by the first semiconductor chip layer. filled with a thermosetting adhesive film of 2,
In the dicing step,
A method of manufacturing a laminated semiconductor chip, wherein the individual laminated semiconductor chips are cut out by vertically cutting each of the thermosetting adhesive films filling spaces between the horizontally spaced semiconductor chips in each of the semiconductor chip layers. 2. The method for manufacturing a laminated semiconductor chip according to claim 1, wherein said film-forming resin is a phenoxy resin. 3. The laminated semiconductor according to claim 1, wherein the ratio of the total mass of said acrylic resin and said organic peroxide to the total mass of said epoxy resin and said acid anhydride is 9:1 to 4:6. How the chips are made. In the first lamination step,
Laminating the first thermosetting adhesive film on the base wiring board,
3. The plurality of semiconductor chips are horizontally spaced apart from each other on the mother wiring board on the first thermosetting adhesive film laminated on the mother wiring board. 4. The method for manufacturing a laminated semiconductor chip according to any one of 1 to 3. In the second lamination step,
laminating the second thermosetting adhesive film on the first semiconductor chip layer;
arranging the plurality of other semiconductor chips horizontally spaced apart on the mother wiring board on the second thermosetting adhesive film laminated on the first semiconductor chip layer; 5. The method of manufacturing a laminated semiconductor chip according to claim 1. In the first lamination step,
Laminating the first thermosetting adhesive film on the base wiring board,
disposing the plurality of semiconductor chips horizontally on the first thermosetting adhesive film;
6. The method of manufacturing a laminated semiconductor chip according to claim 1, wherein said first thermosetting adhesive film having said plurality of semiconductor chips arranged thereon is laminated on said mother wiring board. In the second laminating step,
laminating the second thermosetting adhesive film on the first semiconductor chip layer;
disposing the plurality of other semiconductor chips on the second thermosetting adhesive film so as to be spaced apart in the horizontal direction;
7. The method of manufacturing a laminated semiconductor chip according to claim 1, wherein said first thermosetting adhesive film having said plurality of semiconductor chips arranged thereon is laminated on said mother wiring board.

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