JP7243612B2 - Pulse voltage generator - Google Patents

Description

The technology disclosed in this specification relates to a pulse voltage generation circuit.

Patent Documents 1 and 2 disclose a pulse voltage generation circuit for driving a capacitive load (piezoelectric actuator element). The capacitive load is driven by supplying a reference voltage to one input terminal of the capacitive load and supplying a pulse-like high voltage to the other input terminal.

JP 2012-55102 Unexamined-Japanese-Patent No. 2013-51343

A capacitive load is driven by being charged and discharged. When charging a capacitive load, energy proportional to the square of the pulse voltage amplitude is stored in the capacitive load, and the same amount of heat is lost in the circuit connecting the voltage source and the capacitive load (e.g. switch). occurs. Similarly, when the capacitive load is discharged, the same amount of circuit heat loss occurs as the energy stored in the capacitive load. Efficiency decreases.

A pulse voltage generation circuit disclosed herein includes a first output terminal and a second output terminal with a capacitive load connected between the terminals. The pulse voltage generation circuit includes a first power supply that outputs a first high voltage. The pulse voltage generation circuit has a second power supply that outputs a second high voltage. The pulse voltage generation circuit includes a switch capable of switching at least one connection destination of the first output terminal and the second output terminal between a reference voltage section that outputs a reference voltage, the first power supply, and the second power supply. When the pulse voltage output from the first output terminal and the second output terminal rises, the switch connects the first output terminal to the first power supply, and the switch connects the first output terminal or the second output terminal to the second output terminal. The operation of connecting to the power supply is performed with a difference of at least a predetermined time.

In the circuit disclosed in this specification, the application of the first high voltage and the application of the second high voltage to the input terminal of the capacitive load are performed with a difference of at least a predetermined time. As a result, a pulse voltage having a predetermined differential voltage, which is the sum of the absolute values of the first high voltage and the second high voltage, can be generated. Further, by setting the rise of the pulse voltage in two steps, the voltage amplitude of the pulse voltage per step can be reduced. The heat loss generated in the switch is proportional to the square of the pulse voltage amplitude. Therefore, when the pulse voltage is applied to the capacitive load in two stages of rise, each stage having a small voltage amplitude, compared to the case where the pulse voltage is applied to the capacitive load in one stage of rise having a large voltage amplitude. can suppress heat loss.

The switches include a first switch that connects the first output terminal to one of the reference voltage section and the first power supply, and a second switch that connects the second output terminal to one of the reference voltage section and the second power supply. and a switch. The first power supply may output a positive first high voltage. The second power supply may output a negative second high voltage. When the pulse voltage output from the first output terminal and the second output terminal rises, the first switch connects the first output terminal to the first power supply, and the second switch connects the second output terminal to the second power supply. may be performed with a difference of a predetermined time or more. When the pulse voltage falls, the operation of the first switch connecting the first output terminal to the reference voltage section and the operation of the second switch connecting the second output terminal to the reference voltage section have a difference of a predetermined time or longer. may be implemented with Details of the effect will be described in Examples.

The reference voltage section includes a first reference voltage section that outputs a first reference voltage and a second reference voltage section that outputs a second reference voltage that is higher than the first reference voltage and lower than the first high voltage. may The first switch may connect the first output terminal to the first reference voltage site. The second switch may connect the second output terminal to the second reference voltage portion. The first switch and the second switch may be controlled by a control signal having an amplitude of the first reference voltage and the second reference voltage. Details of the effect will be described in Examples.

It may have N (N is a natural number equal to or greater than 2) first output terminals and one second output terminal. N first switches may be provided for each of the N first output terminals. One second switch may be provided for one second output terminal. When the pulse voltage rises, each of the N operations in which the N first switches connect the N first output terminals to the first power supply may be performed with a difference of a predetermined time or more. good. At the fall of the pulse voltage, each of the N operations in which the N first switches connect the N first output terminals to the reference voltage section is performed with a difference of at least a predetermined time. good too. Details of the effect will be described in Examples.

It may have one first output terminal and N second output terminals (N is a natural number of 2 or more). One first switch may be provided for one first output terminal. N second switches may be provided for each of the N second output terminals. When the pulse voltage rises, each of the N operations in which the N second switches connect the N second output terminals to the second power supply may be performed with a difference of a predetermined time or longer. good. When the pulse voltage falls, each of the N operations in which the N second switches connect the N second output terminals to the reference voltage section is performed with a difference of a predetermined time or longer. good too. Details of the effect will be described in Examples.

A pulse voltage generation circuit disclosed herein includes a first output terminal and a second output terminal with a capacitive load connected between the terminals. A reference voltage is output from the second output terminal. The pulse voltage generation circuit includes a high voltage generation circuit that generates a high voltage of a predetermined voltage. The high voltage generating circuit outputs a reference voltage when stopped, outputs a voltage rising from the reference voltage to a predetermined voltage with a predetermined slope when starting operation, and outputs a predetermined voltage during steady operation. The pulse voltage generation circuit includes a switch that connects the first output terminal to one of the reference voltage section that outputs the reference voltage and the high voltage generation circuit. When the pulse voltage output from the first output terminal and the second output terminal rises, the switch connects the first output terminal to the high voltage generation circuit while the operation of the high voltage generation circuit is stopped. The high voltage generation circuit starts operating while the high voltage generation circuit is connected to the first output terminal. Details of the effect will be described in Examples.

At the fall of the pulse voltage, the operation of connecting the first output terminal to the reference voltage portion and the control of stopping the high voltage generating circuit may be performed substantially simultaneously.

It may have N (N is a natural number equal to or greater than 2) first output terminals and second output terminals. N switches may be provided for each of the N first output terminals. When the pulse voltage rises, the N switches may connect each of the N first output terminals to the high voltage generation circuit while the operation of the high voltage generation circuit is stopped. The high voltage generation circuit may start operating with the high voltage generation circuit connected to the N first output terminals. Details of the effect will be described in Examples.

1 is a diagram showing a piezoelectric actuator drive system 1 according to Example 1. FIG. It is a circuit configuration example of a first switch SW1. It is a circuit configuration example of a second switch SW2. 4 is a waveform diagram for explaining the operation of the pulse voltage generation circuit 2; FIG. FIG. 10 is a diagram showing a piezoelectric actuator drive system 1a according to Example 2; 4 is a waveform diagram for explaining the operation of the pulse voltage generation circuit 2a; FIG. FIG. 10 is a diagram showing a piezoelectric actuator drive system 1b according to Example 3; 4 is a waveform diagram for explaining the operation of the pulse voltage generation circuit 2b; FIG. FIG. 11 is a diagram showing a piezoelectric actuator drive system 1c according to Example 4; 4 is a waveform diagram for explaining the operation of the pulse voltage generation circuit 2c; FIG. FIG. 10 is a diagram showing a piezoelectric actuator drive system 1d according to a first modified example; It is a circuit configuration example of a switch SWd. 4 is a waveform diagram for explaining the operation of the pulse voltage generation circuit 2d; FIG.

(Configuration of Piezoelectric Actuator Driving System 1)
FIG. 1 shows a piezoelectric actuator driving system 1 according to the first embodiment. A piezoelectric actuator drive system 1 includes a pulse voltage generation circuit 2 and a piezoelectric actuator 3 .

The pulse voltage generation circuit 2 includes a first power supply 11, a second power supply 12, a second reference voltage section 13, a control circuit 14, a first switch SW1, a second switch SW2, a first output terminal 21, a second output terminal 22, Prepare. A piezoelectric actuator 3 is connected between the terminals of the first output terminal 21 and the second output terminal 22 . The piezoelectric actuator 3 is a capacitive element. An example of the piezoelectric actuator 3 is a piezoelectric element. An output voltage V1 is output from the first output terminal 21 . An output voltage V2 is output from the second output terminal 22 . A pulse voltage PV that is a difference voltage between the output voltage V1 and the output voltage V2 is applied to the piezoelectric actuator 3 .

The first reference voltage section GND is a section that outputs the first reference voltage VSS. In this embodiment, the first reference voltage VSS is 0 volts. The second reference voltage section 13 is a DC power supply that supplies a second reference voltage VDD. The second reference voltage portion 13 may be, for example, a battery. The second reference voltage VDD is a logic level constant voltage, eg, 3 volts. That is, the second reference voltage VDD is higher than the first reference voltage VSS and lower than the first high voltage VH.

A first reference voltage VSS and a second reference voltage VDD are input to the control circuit 14 . The control circuit 14 outputs a clock signal CK1 for controlling the first switch SW1 and a clock signal CK2 for controlling the second switch SW2. The clock signals CK1 and CK2 are control signals having amplitudes of the first reference voltage VSS and the second reference voltage VDD.

The first power supply 11 is a circuit that boosts the second reference voltage VDD to output a positive first high voltage VH. In this example, the first high voltage VH is +100 volts. The first switch SW1 is a circuit that connects one of the input terminals T11 and T12 to the output terminal T10 according to the clock signal CK1. Thereby, the first output terminal 21 can be connected to either the first reference voltage part GND or the first power supply 11 .

The second power supply 12 is a circuit that boosts the second reference voltage VDD and outputs a negative second high voltage VL. In this embodiment, the second high voltage VH is -100 volts. The second switch SW2 is a circuit that connects one of the input terminals T21 and T22 to the output terminal T20 according to the clock signal CK2. Thereby, the second output terminal 22 can be connected to either the second reference voltage section 13 or the second power supply 12 .

(Configuration example of first switch SW1 and second switch SW2)
FIG. 2 shows a circuit configuration example of the first switch SW1. The first switch SW1 includes a resistor R1, high-voltage n-type transistors Tr11 and Tr12, and a diode D1. One end of the resistor R1 is connected to the input terminal T11. The other end of the resistor R1 is connected to the gate terminal of the transistor Tr12, the drain terminal of the transistor Tr11, and the cathode electrode of the diode D1. A clock signal CK1 is input to the gate terminal of the transistor Tr11. The drain terminal of the transistor Tr12 is connected to the input terminal T11, and the source terminal is connected to the output terminal T10 and the anode electrode of the diode D1.

The first high voltage VH is output to the first output terminal 21 when the clock signal CK1 is at the first reference voltage VSS. On the other hand, the first reference voltage VSS is output to the first output terminal 21 when the clock signal CK1 is the second reference voltage VDD. As a result, the first switch SW1 can convert the logic level low voltage amplitude (0 to 3 volts) clock signal CK1 into the high voltage amplitude (100 volts) output voltage V1 and output it.

FIG. 3 shows a circuit configuration example of the second switch SW2. The second switch SW2 includes a resistor R2, high-voltage p-type transistors Tr21 and Tr22, and a diode D2. One end of the resistor R2 is connected to the input terminal T21. The other end of the resistor R2 is connected to the gate terminal of the transistor Tr22, the drain terminal of the transistor Tr21, and the anode electrode of the diode D1. A clock signal CK2 is input to the gate terminal of the transistor Tr21. The drain terminal of the transistor Tr22 is connected to the input terminal T21, and the source terminal is connected to the output terminal T20 and the cathode electrode of the diode D1.

The second reference voltage VDD is output to the second output terminal 22 when the clock signal CK2 is at the first reference voltage VSS. On the other hand, the second high voltage VL is output to the second output terminal 22 when the clock signal CK2 is the second reference voltage VDD. As a result, the second switch SW2 can convert the logic level low voltage amplitude (0 to 3 volts) clock signal CK2 into the high voltage amplitude (approximately 100 volts) output voltage V2 and output it.

(Operation of pulse voltage generation circuit 2)
The operation of the pulse voltage generation circuit 2 will be described with reference to the waveform diagram of FIG. FIG. 4 shows waveforms when the piezoelectric actuator 3 is driven by a high voltage pulse having a constant period and a duty ratio of 50%. The clock signals CK1 and CK2 are applied such that the phase in which the first high voltage VH is output as the output voltage V1 overlaps with the phase in which the second high voltage VL is output as the output voltage V2. ing.

In the steady state at time t0, the clock signal CK1 is at the second reference voltage VDD (3 volts) and the output voltage V1 is at the first reference voltage VSS (0 volts). The clock signal CK2 is the first reference voltage VSS, and the output voltage V2 is the second reference voltage VDD (3 volts).

The operation when the pulse voltage PV rises will be described at times t1 to t4. At time t1, when the clock signal CK1 is switched from the second reference voltage VDD to the first reference voltage VSS, the connection destination of the first output terminal 21 is changed from the first reference voltage portion GND to the first power supply 11 by the first switch SW1. can be switched to Immediately after this switching, the voltage on the input side (input terminal T11 side) of the first switch SW1 is the first high voltage VH, and the voltage on the output side (output voltage V1) is the first reference voltage VSS. Then, the potential difference between the input and output (that is, the voltage amplitude of the output voltage V1) is the first high voltage VH.

At time t2 when the predetermined time PT has elapsed from time t1, the output voltage V1 rises from the first reference voltage VSS to the first high voltage VH (region A1). The predetermined time PT is the time required to complete charging of the piezoelectric actuator 3, which is a capacitive load. When the piezoelectric actuator 3 is charged, energy proportional to the square of the amplitude of the output voltage V1 (that is, the first high voltage VH) is stored in the piezoelectric actuator 3, and the same amount of heat loss occurs in the first switch SW1. do. Therefore, the loss in the first switch SW1 between times t1 and t2 can be expressed by the following equation (1).
(C0×VH ² )/2 Expression (1)
C0 is the capacitance component of the piezoelectric actuator 3 here.

Further, when the clock signal CK2 is switched from the first reference voltage VSS to the second reference voltage VDD at the time t3, which is the time after the time t2, the connection destination of the second output terminal 22 is set to the second voltage by the second switch SW2. The reference voltage section 13 is switched to the second power supply 12 . That is, at time t11, the first switch SW1 connects the first output terminal 21 to the first power supply 11, and at time t13, the second switch SW2 connects the second output terminal 22 to the second power supply 12. , are executed with a difference equal to or greater than the predetermined time PT. Immediately after this switching, the voltage on the input side (input terminal T22 side) of the second switch SW2 is the second high voltage VL, and the voltage on the output side (output voltage V2) is the second reference voltage VDD. Then, the potential difference between the input and output (that is, the voltage amplitude of the output voltage V2) is (second reference voltage VDD-second high voltage VL).

At time t4, the output voltage V2 changes from the second reference voltage VDD to the negative second high voltage VL (area A2). During discharging of the piezoelectric actuator 3, similarly to during charging described above, an energy loss proportional to the square of the amplitude of the output voltage V2 (that is, VDD-VL) occurs in the second switch SW2. Therefore, the loss in the second switch SW2 from time t3 to time t4 can be expressed by the following equation (2).
{C0×(VDD−VL) ² }/2 Expression (2)

As described above, the pulse voltage PV rises in two stages from time t1 to t4 (region A3). The voltage amplitude of the pulse voltage PV is (output voltage V1-output voltage V2), specifically (VH-VL+VDD). Further, the total loss of the first switch SW1 and the second switch SW2 when the pulse voltage PV rises (that is, when the piezoelectric actuator 3 is charged) is given by the following equation (3).
C0×{VH ² +(VDD−VL) ² }/2 Expression (3)
Note that the piezoelectric actuator 3 accumulates the energy of the following formula (4).
{C0×(VH−VL+VDD) ² }/2 Expression (4)

The operation when the pulse voltage PV falls will be described at times t11 to t14. When the clock signal CK1 is switched from the first reference voltage VSS to the second reference voltage VDD at time t1, the output voltage V1 changes from the first high voltage VH to the first reference voltage at time t12 after a predetermined time PT has elapsed from time t11. It drops to voltage VSS (region A4). The loss in the first switch SW1 from time t11 to t12 can be expressed by the above equation (1). At time t13 after time t12, the clock signal CK2 is switched from the second reference voltage VDD to the first reference voltage VSS. At time t14, the output voltage V2 changes from the negative second high voltage VL to the first 2 changes to the reference voltage VDD (area A5). The loss in the second switch SW2 from time t3 to time t4 can be expressed by the above equation (2).

As described above, the pulse voltage PV falls in two stages from time t11 to t4 (area A6). The total loss of the first switch SW1 and the second switch SW2 when the pulse voltage PV falls (that is, when the piezoelectric actuator 3 is discharged) is given by the above equation (3), as in the case of charging described above.

(effect)
In the pulse voltage generation circuit 2 according to the first embodiment, the application of the positive first high voltage VH to the first output terminal 21 and the application of the negative second high voltage VL to the second output terminal 22 are phased. overlap (see Fig. 4). As a result, the pulse voltage PV having a predetermined differential voltage, which is the sum of the absolute values of the first high voltage VH and the second high voltage VL, can be generated. In the rise period of the pulse voltage PV, the rise of the first high voltage VH (time t1) and the rise of the second high voltage VL (time t3) are performed with a difference of at least the predetermined time PT. As a result, the voltage amplitude of the pulse voltage per stage can be reduced by performing the rise of the pulse voltage PV in two stages. As mentioned above, the heat loss generated in the first switch SW1 and the second switch SW2 is proportional to the square of the pulse voltage amplitude. Therefore, the case where the pulse voltage is applied to the piezoelectric actuator 3 in two stages of rise, each stage having a small voltage amplitude, is applied to the piezoelectric actuator 3 as compared with the case where the pulse voltage is applied to the piezoelectric actuator 3 in one stage of rise having a large voltage amplitude. can suppress the heat loss in the first switch SW1 and the second switch SW2. Similarly, during the fall period of the pulse voltage PV, the heat loss in the first switch SW1 and the second switch SW2 can be suppressed by performing the fall of the pulse voltage PV in two stages. When the second reference voltage section 13 is composed of a battery, it is important to reduce the weight of the battery and prolong its life, so the effect of reducing heat loss and increasing efficiency is particularly high.

A specific example will be used for explanation. A case will be described where the second reference voltage VDD is 3 volts, the first high voltage VH is +100 volts, and the second high voltage VL is -100 volts. As a comparative example, consider a case where one end of the piezoelectric actuator 3 is fixed to the first reference voltage VSS and a pulse voltage PV that rises to 200 volts in one step is applied to the other end. The loss in the switch in this case is given by the following equation (5).
{C0×(200) ² }/2 Expression (5)
Therefore, the loss value in the comparative example is "20000×C0". On the other hand, in Example 1, the loss generated in the first switch SW1 at the rise of 100 volts in the first stage (time t1 to t2) and the loss generated in the second switch SW1 at the rise of 100 volts in the second stage (time t3 to t4) Since the total value including the loss generated in SW2 is represented by the above formula (3), it becomes the following formula (6).
C0×{100 ² +(103) ² }/2 Expression (6)
Therefore, the loss value in Example 1 is "10304.5×C0". It can be seen that the switch loss at the time of rising of the pulse voltage PV (that is, at the time of charging the piezoelectric actuator 3) can be reduced to about 1/2. Similarly, when the pulse voltage PV falls (when the piezoelectric actuator 3 discharges), the switch loss can be reduced to about 1/2.

As an example, consider the case of generating a positive high voltage pulse voltage that rises in two stages. For example, the voltage rises from 0 volt to 100 volts in the first stage, and rises from 100 volts to 200 volts in the second stage. In this case, the clock signal controlling the first stage should have a logic level near 0 volts and the clock signal controlling the second stage should have a logic level near 100 volts. In order to generate such two types of logic levels, various additional circuits are required and the pulse voltage generation circuit becomes huge. On the other hand, in the technique of the first embodiment, the positive first high voltage VH is raised in the first stage, and the negative second high voltage VL is raised in the second stage. By combining the positive and negative in this way, as is apparent from FIGS. 3 volts) can be used as a reference to raise the second high voltage VL. Therefore, the common logic level of the first reference voltage VSS and the second reference voltage VDD can be used to control the rising of the first stage and the second stage. Since there is no need to add a separate circuit, the scale of the pulse voltage generation circuit 2 can be suppressed.

Embodiment 2 shows an example in which the pulse voltage generation circuit 2 of Embodiment 1 is extended to a circuit capable of independently driving a plurality of piezoelectric actuators 3 . Parts similar to those of the pulse voltage generation circuit 2 of the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted.

(Configuration of Piezoelectric Actuator Drive System 1a)
FIG. 5 shows a piezoelectric actuator driving system 1a according to the second embodiment. A piezoelectric actuator driving system 1a includes a pulse voltage generation circuit 2a and piezoelectric actuators 3A to 3C. The pulse voltage generation circuit 2a has three first switches SW1A to SW1C and three first output terminals 21A to 21C. Between each of the three first output terminals 21A-21C and one second output terminal 22, three piezoelectric actuators 3A-3C are connected. Output voltages V1A to V1C are output from the first output terminals 21A to 21C, respectively. Pulse voltages PVA to PVC, which are differential voltages between each of the output voltages V1A to V1C and the output voltage V2, are applied to the piezoelectric actuators 3A to 3C.

The first switches SW1A to SW1C are connected in parallel between the first power supply 11 and the first reference voltage section GND. The control circuit 14 outputs clock signals CK1A to CK1C that control the first switches SW1A to SW1C, respectively. Since other structures are the same as those of the piezoelectric actuator drive system 1 (FIG. 1) of the first embodiment, description thereof is omitted.

(Operation of pulse voltage generation circuit 2a)
The operation of the pulse voltage generation circuit 2a will be described with reference to the waveform diagram of FIG. In this circuit, the output voltage V2 outputting the negative second high voltage VL is commonly controlled by one second switch SW2. On the other hand, the duty ratios of the output voltages V1A to V1C from which the positive first high voltage VH is output are individually controlled using three first switches SW1A to SW1C.

The operation when the pulse voltages PVA to PVC rise will be described at time t20 to t23. When the clock signal CK2 is switched from the first reference voltage VSS to the second reference voltage VDD at time t21, the output voltage V2 changes from the second reference voltage VDD to the negative second high voltage VL (region A21). Therefore, the pulse voltages PVA to PVC can be raised in the first stage in common (arrow Y1).

At time t20, the first switch SW1A connects the first output terminal 21A to the first power supply 11 due to the transition of the clock signal CK1A to the first reference voltage VSS. Therefore, since the output voltage V1A rises from the first reference voltage VSS to the first high voltage VH (region A22), the pulse voltage PVA can be raised in the second step (arrow Y2). Similarly, at time t22, the clock signal CK1B transitions to the first reference voltage VSS, causing the first switch SW1B to connect the first output terminal 21B to the first power supply 11 (region A23). Therefore, the pulse voltage PVB can be raised in the second step (arrow Y3). Similarly, at time t23, the clock signal CK1C transitions to the first reference voltage VSS, causing the first switch SW1C to connect the first output terminal 21C to the first power supply 11 (area A24). Therefore, the pulse voltage PVC can be raised in the second step (arrow Y4).

Each of the operations for switching the first switches SW1A to SW1C and SW2 described above (four operations performed at times t20 to t23) is performed with a difference of at least the predetermined time PT described above. Further, since the details of the operation at the fall of the pulse voltages PVA to PVC are the same as the details of the operation at the time of rise described above, the description thereof will be omitted.

(effect)
The output voltage V2 supplied to the piezoelectric actuators 3A to 3C is commonly controlled by one second switch SW2. As a result, multi-channel output can be achieved without increasing the number of switch circuits for high voltage on the negative side. Also, the loss reduction effect of the first switch SW1 and the second switch SW2 is as described in the first embodiment. As described above, it is possible to reduce the loss and increase the number of output channels while suppressing the circuit scale.

Embodiment 3 describes a pulse voltage generation circuit 2b that generates a positive high voltage pulse. Parts similar to those of the pulse voltage generation circuit 2 of the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. In addition, parts unique to Example 3 are distinguished by adding "b" to the end of the reference numerals.

(Configuration of Piezoelectric Actuator Drive System 1b)
FIG. 7 shows a piezoelectric actuator drive system 1b according to the third embodiment. The pulse voltage generation circuit 2b includes a high voltage power supply 11b and a power supply control circuit 15b. A first reference voltage VSS and a second reference voltage VDD are input to the power control circuit 15b. A control signal CE output from the power supply control circuit 15b is input to the high voltage power supply 11b. The control signal CE is a signal for controlling the operation start and operation stop of the high voltage power supply 11b.

The high voltage power supply 11b is a switching power supply that generates a positive first high voltage VHb. When the control signal CE is at low level (first reference voltage VSS), the high voltage power supply 11b stops operating and outputs the first reference voltage VSS. When the control signal CE transitions to a high level (second reference voltage VDD), the high voltage power supply 11b starts operating and rises stepwise from the first reference voltage VSS to a predetermined positive voltage VHmax with a predetermined slope. output voltage. When the output voltage reaches the voltage VHmax, the high voltage power supply 11b continues to output the voltage VHmax while the control signal CE is at high level. The second output terminal 22 is connected to the first reference voltage section GND. An output voltage V2 that is the first reference voltage VSS is output from the second output terminal 22 . Since other configurations are the same as those of the piezoelectric actuator drive system 1 (FIG. 1) of the first embodiment, description thereof is omitted.

(Operation of pulse voltage generation circuit 2b)
The operation of the pulse voltage generation circuit 2b will be described with reference to the waveform diagram of FIG. At time t30, when the control signal CE is at the first reference voltage VSS and the high voltage power supply 11b is stopped, the output voltage V1 is at the first reference voltage VSS (0 volts).

At time t31, when the clock signal CK1 is switched from the second reference voltage VDD to the first reference voltage VSS, the connection destination of the first output terminal 21 is changed from the first reference voltage portion GND to the high voltage power supply 11b by the first switch SW1. can be switched to This switching operation is performed while the operation of the high-voltage power supply 11b is stopped. Both the input side (input terminal T11 side) and the output side voltage (output voltage V1) of the first switch SW1 are the first reference voltage VSS. Since the potential difference between the input and output is 0 volts, no switch loss occurs.

At time t32, when the control signal CE transitions to the second reference voltage VDD, the high voltage power supply 11b starts operating. That is, the high-voltage power supply 11b starts operating while the high-voltage power supply 11b is connected to the first output terminal 21 . First high voltage VHb rises from first reference voltage VSS to voltage VHmax in a constant time (region A31). Since the output voltage V1 is also connected to the high voltage power supply 11b through the first switch SW1, it rises to the voltage VHmax almost simultaneously (region A32).

At time t33, the control signal CE transitions to the first reference voltage VSS, and the clock signal CK1 transitions to the second reference voltage VDD. As a result, the operation of stopping the high voltage power supply 11b and the operation of the first switch SW1 connecting the first output terminal 21 to the first reference voltage part GND are performed substantially simultaneously. Immediately after this switching, the voltage on the input side (input terminal T11 side) of the first switch SW1 is the first reference voltage VSS (0 volts), and the voltage on the output side (output voltage V1) is the voltage VHmax. The potential difference between input and output (that is, the voltage amplitude of output voltage V1) is voltage VHmax. After a certain period of time, the output voltage V1 drops to the first reference voltage VSS. The loss in the first switch SW1 at this time can be expressed by the following formula (7).
(C0×VHmax ² )/2 Expression (7)
That is, the loss when the output voltage V1 falls (when the piezoelectric actuator 3 discharges) is equivalent to that of the conventional circuit.

(effect)
The high voltage power supply 11b is connected to the piezoelectric actuator 3 while the high voltage power supply 11b is not operating (time t31), and then the operation of the high voltage power supply 11b is started (time t32). As a result, the starting waveform at the start of the operation of the high-voltage power supply 11b can be used to give slopes to the rises of the first high voltage VHb and the output voltage V1 (areas A31 and A32 in FIG. 8). Thereby, it is possible to suppress the switching loss in the first switch SW1 described in the above equation (7). In addition, since the startup waveform of the high voltage power supply 11b is used, a dedicated circuit for controlling the rising slope of the output voltage V1 is not required. It is possible to suppress the circuit scale of the pulse voltage generation circuit 2b.

As the slope of the rise of the output voltage V1 becomes smaller, the effect of suppressing switching loss becomes higher, but the operating frequency of the piezoelectric actuator 3 becomes lower. Therefore, the slope of the rise should be determined in consideration of the required operating frequency of the piezoelectric actuator 3 and the required high efficiency. When the output voltage V1 rises, resistance loss (I ² R loss) occurs in the first switch SW1 due to current and on-resistance. However, this loss is so small that it can be ignored compared to the switching loss described in equation (7) above.

Example 4 shows an example in which the pulse voltage generation circuit 2b of Example 3 is extended to a circuit capable of independently driving a plurality of piezoelectric actuators 3. FIG. Parts similar to those of the pulse voltage generation circuit 2b of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

(Configuration of Piezoelectric Actuator Drive System 1c)
FIG. 9 shows a piezoelectric actuator driving system 1c according to the fourth embodiment. A piezoelectric actuator driving system 1c includes a pulse voltage generation circuit 2c and piezoelectric actuators 3A to 3C. Since the structures of the first switches SW1A to SW1C, the clock signals CK1A to CK1C, the first output terminals 21A to 21C, the pulse voltages PVA to PVC, etc. are the same as those of the piezoelectric actuator driving system 1a (FIG. 5) of the second embodiment, Description is omitted.

(Operation of pulse voltage generation circuit 2c)
The operation of the pulse voltage generation circuit 2c will be described with reference to the waveform diagram of FIG. In this circuit, rising of the output voltages V1A to V1C is commonly controlled by using the starting waveform of the high voltage power supply 11b as it is. On the other hand, the duty ratios of the output voltages V1A to V1C are controlled by individually controlling the fall timings of the output voltages V1A to V1C.

At time t41, when the clock signals CK1A-CK1C are switched from the second reference voltage VDD to the first reference voltage VSS, the connections of the first output terminals 21A-21C are switched from the first reference voltage part GND to the high voltage power supply 11b. be done. This switching operation is performed while the operation of the high-voltage power supply 11b is stopped. At time t42, when the control signal CE transitions to the second reference voltage VDD, the high voltage power supply 11b starts operating. The first high voltage VHb rises from the first reference voltage VSS to the voltage VHmax with a predetermined slope (region A41). The output voltages V1A to V1C also rise to the voltage VHmax almost simultaneously (area A42).

At time t43, the output voltage V1C falls (arrow Y11) in response to the transition of the clock signal CK1C to the second reference voltage VDD. At time t44, the output voltage V1B falls (arrow Y12) in response to the transition of the clock signal CK1B to the second reference voltage VDD. At time t45, the clock signal CK1A transitions to the second reference voltage VDD, and the control signal CE transitions to the first reference voltage VSS. As a result, the high voltage power supply 11b stops and the output voltage V1A falls (arrow Y13).

(effect)
A single high-voltage power supply 11b commonly controls the rising slopes of the output voltages V1A to V1C supplied to the piezoelectric actuators 3A to 3C. As a result, multi-channel output can be achieved without increasing the number of high-voltage power supplies 11b. Also, the loss reduction effect of the first switches SW1A to SW1C is as described in the third embodiment. As described above, it is possible to reduce the loss and increase the number of output channels while suppressing the circuit scale.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims as of the filing. In addition, the techniques exemplified in this specification or drawings can simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

(First modification)
In the first embodiment, a mode in which the high voltage is raised in two stages by a combination of positive and negative has been described, but the present invention is not limited to this mode. A mode in which the voltage on only one of the positive and negative sides is raised in two stages may be used. In the first modified example, an example is shown in which positive side two-stage start-up is performed. FIG. 11 shows a piezoelectric actuator drive system 1d according to the first modified example. Parts similar to those of the pulse voltage generation circuit 2 of the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. The first power supply 11d is a circuit that boosts the second reference voltage VDD and outputs a positive first high voltage VHd. In this embodiment, the first high voltage VHd is +200 volts. The second power supply 12d is a circuit that boosts the second reference voltage VDD and outputs a positive second high voltage VM. In this example, the second high voltage VM is +100 volts. Clock signals CK1d to CK3d for controlling the switches SWd are output from the control circuit 14d. The switch SWd is a circuit that connects one of the input terminals T31 to T33 to the output terminal T30 according to the clock signals CK1d to CK3d. Thereby, the first output terminal 21 can be connected to any one of the first power supply 11d, the second power supply 12d, and the first reference voltage section GND.

FIG. 12 shows a circuit configuration example of the switch SWd. The switch SWd includes an n-type transistor Tr31 and isolation switches IS1 and IS2. In this embodiment, isolation switches IS1 and IS2 are photo-MOS relays. The isolation switches IS1 and IS2 may be photocouplers or the like. The isolation switch IS1 is arranged between the connection path between the input terminal T31 and the output terminal T30, and receives the clock signal CK1d. The isolation switch IS2 is arranged between the connection path between the input terminal T32 and the output terminal T30, and receives the clock signal CK2d. The transistor Tr31 is arranged between the connection path between the input terminal T33 and the output terminal T30, and receives the clock signal CK3d. When each of the clock signals CK1d to CK3d is at high level (second reference voltage VDD), each of the insulation switch IS1, the insulation switch IS2, and the transistor Tr31 is turned on.

The operation of the pulse voltage generation circuit 2d will be described with reference to the waveform diagram of FIG. The operation when the pulse voltage PV rises will be described at times t1d to t4d. When the clock signal CK3d is switched to low level and the clock signal CK2d is switched to high level at time t1d, the connection destination of the output terminal T30 is switched from the input terminal T33 to the input terminal T32. Therefore, the pulse voltage PV changes from the first reference voltage VSS to the second high voltage VM at time t2d. A first stage start-up can be performed (arrow Y1d). When the clock signal CK2d is switched to low level and the clock signal CK1d is switched to high level at time t3d, the connection destination of the output terminal T30 is switched from the input terminal T32 to the input terminal T31. Therefore, the pulse voltage PV changes from the second high voltage VM to the first high voltage VH at time t4d. A second stage start-up can be performed (arrow Y2d). Further, since the details of the operation when the pulse voltage PV falls from time t11d to t14d are the same as the details of the operation when the pulse voltage PV rises, description thereof will be omitted.

Explain the effect. A positive high voltage pulse voltage PV that rises in two stages is generated using the insulation switch IS1 and the insulation switch IS2. Therefore, the clock signals CK2d and CK1d that control the first stage and the second stage can be set to a common logic level (first reference voltage VSS to second reference voltage VDD). There is no need to add various circuits to bring the clock signal CK1d to different logic levels. It is possible to suppress the scale of the pulse voltage generation circuit 2d.

(Other modifications)
In the second embodiment, the output voltage V2 is commonly controlled by one second switch SW2, but the configuration is not limited to this. For example, the output voltage V1 may be commonly controlled by one first switch SW1. It may also have three second switches SW2A to SW2C and three second output terminals 22A to 22C. The control circuit 14 may output clock signals CK2A to CK2C for controlling the second switches SW2A to SW2C, respectively. Output voltages V2A to V2C are output from the second output terminals 22A to 22C, respectively. The duty ratios of the output voltages V2A to V2C at which the negative second high voltage VL is output can be individually controlled using the three second switches SW2A to SW2C.

The rise and fall of the pulse voltage PV are not limited to two steps, and may be performed in multiple steps of three or more steps.

Various actuators such as a bending type piezoelectric actuator can be used as the piezoelectric actuator 3 .

(correspondence relationship)
The piezoelectric actuator 3 is an example of a capacitive load. The first reference voltage section GND and the second reference voltage section 13 are examples of reference voltage sections. The high voltage power supply 11b is an example of a high voltage generation circuit.

1: Piezoelectric Actuator Drive System 2: Pulse Voltage Generation Circuit 3: Piezoelectric Actuator 11: First Power Supply 12: Second Power Supply 13: Second Reference Voltage Part 14: Control Circuit GND: First Reference Voltage Part SW1: First Switch SW2 : second switch CK1, CK2: clock signal VH: first high voltage VL: second high voltage V1, V2: output voltage PV: pulse voltage VSS: first reference voltage VDD: second reference voltage

Claims (5)

N first output terminals, wherein N is a natural number equal to or greater than 2;
one second output terminal;
a first power supply that outputs a positive first high voltage;
a second power supply that outputs a negative second high voltage;
N first switches provided for each of the N first output terminals, wherein one of a first reference voltage section for outputting a first reference voltage and the first power supply is connected to the first switch. N first switches connecting one output terminal;
A second reference voltage that outputs a second reference voltage that is higher than the first reference voltage and lower than the first high voltage. one second switch that connects the second output terminal to one of the part and the second power supply;
a control circuit that controls operations of the N first switches and the one second switch;
A pulse voltage generation circuit comprising
N capacitive loads can be connected between the N first output terminals and one second output terminal,
The control circuit is
When the pulse voltage output from the first output terminal and the second output terminal rises, the N first switches connect each of the N first output terminals to the first power supply. controlling each of the operations and the operation of connecting the second output terminal by one of the second switches to the second power supply with a difference of at least a predetermined time ;
At the fall of the pulse voltage, each of the N operations in which the N first switches connect each of the N first output terminals to the first reference voltage portion, and one of the first 2 switch is controlled so that the operation of connecting the second output terminal to the second reference voltage part is performed with a difference of the predetermined time or more;
Pulse voltage generation circuit. one first output terminal;
N second output terminals, wherein N is a natural number equal to or greater than 2;
a first power supply that outputs a positive first high voltage;
a second power supply that outputs a negative second high voltage;
One first switch provided at one of the first output terminals, wherein the first output is connected to either one of a first reference voltage section for outputting a first reference voltage and the first power supply. one said first switch connecting terminals;
N second switches provided for each of the N second output terminals, the second switch outputting a second reference voltage higher than the first reference voltage and lower than the first high voltage. N second switches connecting the second output terminals to one of a reference voltage part and the second power supply;
a control circuit for controlling the operation of the one first switch and the N second switches;
A pulse voltage generation circuit comprising
N capacitive loads can be connected between the one first output terminal and the N second output terminals,
The control circuit is
When the pulse voltage output from the first output terminal and the second output terminal rises, one of the first switches connects the first output terminal to the first power supply; controlling so that each of the N operations in which the second switch connects each of the N second output terminals to the second power supply is performed with a difference of a predetermined time or longer;
When the pulse voltage falls, one of the first switches connects the first output terminal to the first reference voltage portion, and N of the second switches connect the N of the second outputs. controlling so that each of the N operations for connecting each of the terminals to the second reference voltage portion is performed with a difference of the predetermined time or more;
Pulse voltage generation circuit. 3. The pulse voltage generating circuit according to claim 1, wherein said first switch and said second switch are controlled by a control signal having an amplitude of said first reference voltage and said second reference voltage. N first output terminals, wherein N is a natural number equal to or greater than 2;
one second output terminal for outputting a reference voltage;
A high voltage generating circuit for generating a predetermined high voltage, which outputs the reference voltage during a stop and outputs a voltage rising from the reference voltage to the predetermined voltage with a predetermined slope when an operation is started. , the high voltage generation circuit that outputs the predetermined voltage during steady operation;
N switches provided for each of the N first output terminals, wherein the first output terminal is connected to either one of a reference voltage section for outputting the reference voltage and the high voltage generation circuit. N said switches to connect;
a control circuit for controlling the operation of the N switches;
A pulse voltage generation circuit comprising
N capacitive loads can be connected between the N first output terminals and one second output terminal,
When the pulse voltage output from the first output terminal and the second output terminal rises,
the N switches are controlled by the control circuit to connect each of the N first output terminals to the high voltage generation circuit while the high voltage generation circuit is inactive;
The high voltage generation circuit starts operating in a state in which the high voltage generation circuit is connected to each of the N first output terminals.
Pulse voltage generation circuit. In the control circuit, when the pulse voltage falls, each of the N operations in which the N switches connect the N first output terminals to the reference voltage section has a difference of a predetermined time or longer. 5. The pulse voltage generation circuit according to claim 4, wherein the pulse voltage generation circuit controls to be executed with

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