JP7231490B2 - Data transmission method and data transfer device - Google Patents

Description

The present invention relates to a data transmission method and a data transmission apparatus for sequentially acquiring data signals generated by slave devices in N stages (N is a positive integer equal to or greater than 2) connected in a daisy chain to a master device in chronological order.

Generally, a master device and a slave device are connected by interfaces such as SPI (Serial Peripheral Interface) and I2C. A slave device has a chip select port and a device address for receiving commands from a master device, and it is possible to connect a plurality of slave devices in parallel to the master device. A data transfer device consisting of a master device and a plurality of slave devices can select a specific slave device and directly control it, but the number of wires increases.

On the other hand, data transmission equipment using a daisy chain can reduce the number of wires and simplify the configuration by connecting N slave devices in a daisy chain and connecting them between the input side and the output side of the master device. It's becoming When a start signal is output from the master device, the first-stage slave device generates a data signal that measures a physical quantity such as the temperature of the object assigned to the slave device. The slave device in the second stage receives the data signal generated by the slave device in the first stage and sends it as it is to the slave device in the third stage. The slave device in the third stage sends the data signal input from the slave device in the second stage as it is to the slave device in the fourth stage. Subsequent slave devices operate in the same manner, so that the data signal generated by the first-stage slave device is output from the final N-stage slave device to the master device.

When the first-stage slave device finishes outputting the data signal, the first-stage slave device outputs a start signal for operating the second-stage slave device. As a result, the second-stage slave device generates a data signal obtained by measuring a physical quantity such as temperature. The slave device in the third stage inputs the data signal generated by the slave device in the second stage and passes it to the slave device in the fourth stage as it is. Furthermore, the slave device in the latter stage also operates in the same way, so that the output signal of the slave device in the second stage is output from the slave device in the final Nth stage to the master device.

By repeating the operation of generating the data signal and generating the start signal in each stage of the slave device, the N data signals generated by the N slave devices are sequentially output to the master device in time series. . A daisy chain device is described in Patent Document 1, for example.

JP 2017-126858 A

However, in a data transmission apparatus using a daisy chain, slave devices are connected in hundreds to thousands of stages in order to generate data signals sequentially from the slave device in the first stage to the final slave device in the Nth stage. In this case, there is a problem that the waiting time from the output of the start signal from the master device to the output of the data signal from the slave device becomes longer in the later slave devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission apparatus capable of reducing the waiting time for fetching a data signal generated by a slave device in a desired stage even when slave devices are connected in hundreds to thousands of stages. That is.

In order to achieve the above object, the invention according to claim 1 is a master device comprising a first port and a second port, one for outputting a start signal and the other for inputting a data signal. Between the ports, the third port and the fourth port of the slave device having the third port and the fourth port for data signal input/output are daisy-chained over N stages (N is a positive integer equal to or greater than 2). , connecting the third port of the first stage slave device to the first port of the master device, connecting the fourth port of the Nth stage slave device to the second port of the master device, and is, when the third port has a low impedance and the fourth port has a high impedance, the data signal input to the third port is transmitted to the fourth port until a start signal input to the third port is detected; When the start signal input to the third port is detected, the signal is cut off between the third port and the fourth port, and a desired data signal is generated and output from the fourth port. Subsequently, a new start signal is generated and output from the fourth port, and the slave device inputs the start signal to the fourth port when the third port has high impedance and the fourth port has low impedance. is detected, the data signal input to the fourth port is passed through the third port as it is, and when the start signal input to the fourth port is detected, between the third port and the fourth port is cut off, a desired data signal is generated and output from the third port, and a new start signal is generated and output from the third port.

The invention according to claim 2 has a master device comprising a first port and a second port, one for outputting a start signal and the other for inputting a data signal, and a third port and a fourth port for inputting and outputting a data signal. and N (N is a positive integer equal to or greater than 2) slave devices daisy-chained between the first port and the second port of the master device via the third port and the fourth port. and, wherein the slave device, when the third port has a low impedance and the fourth port has a high impedance, until a start signal input to the third port is detected A data signal input to the third port is passed through the fourth port as it is, and when a start signal input to the third port is detected, communication between the third port and the fourth port is cut off, and a desired signal is transmitted. is generated and output from the fourth port, and subsequently a new start signal is generated and output from the fourth port, and when the third port has high impedance and the fourth port has low impedance , until the start signal input to the fourth port is detected, the data signal input to the fourth port is passed through the third port as it is, and when the start signal input to the fourth port is detected, the disconnecting between the third port and the fourth port, generating a desired data signal and outputting it from the third port, and continuously generating a new start signal and outputting it from the third port; characterized by

The invention according to claim 3 is the data transfer apparatus according to claim 2, wherein the slave device includes a first impedance determination circuit that determines whether the impedance of the third port is high or low; an input port and an output port, and when the start signal is input to the input port, a data signal is generated after detecting it, output from the output port, and then a new a data signal generation circuit for generating a start signal and outputting it from the output port; and when the third port has a low impedance and the fourth port has a high impedance, the third port is connected to the input port and the 4 ports are connected to output ports, and when the third port is high impedance and the fourth port is low impedance, connecting the fourth port to the input port and connecting the third port to the output port; an input/output switching circuit that cuts off the connection of the third port and the fourth port to the input port and the output port when both the third port and the fourth port are in high impedance, the input/output switching circuit being connected to the third port; a first delay circuit having a delay time longer than the pulse width of the start signal; a second delay circuit connected to the fourth port and having a delay time longer than the pulse width of the start signal; is connected between the delay circuit and the second delay circuit, is turned off when the first and second impedance determination circuits perform impedance determination operation after power-on, and the first and second impedance determination circuits are connected to the impedance determination circuit; and a seventh switch that is turned on when the determination operation is completed and turned off when the start signal is detected.

According to the present invention, there is a forward mode in which data signals are generated sequentially from the slave device in the first stage to the slave device in the Nth stage, and a data signal is generated in sequence from the slave device in the Nth stage to the slave device in the first stage. Since one of the reverse order modes can be selected, even if the slave devices are connected in hundreds to thousands of stages, the waiting time for fetching the data signal generated by the slave device in the desired stage can be reduced. .

3 is a block diagram showing the flow of signals in the forward mode of the data transmission device of the embodiment; FIG. FIG. 2 is an operational waveform diagram of the forward mode of the data transmission device of FIG. 1; 2 is a circuit diagram of a slave device of the data transmission apparatus of FIG. 1; FIG. 2 is a flow chart of the operation of a slave device of the data transmission apparatus of FIG. 1; 4 is a circuit diagram of a temperature measurement circuit of a temperature sensor of the slave device of FIG. 3; FIG. 6 is an operation waveform diagram of the temperature measurement circuit of FIG. 5; FIG. 4 is a circuit diagram of a start signal detection circuit of the temperature sensor of the slave device of FIG. 3; FIG. 8 is an operation waveform diagram of the start signal detection circuit of FIG. 7; FIG. 3 is a block diagram showing the flow of signals in the reverse mode of the data transmission device of the embodiment; FIG. FIG. 10 is an operation waveform diagram of the data transmission device of FIG. 9 in a reverse order mode;

<Example>
FIG. 1 shows a connection configuration of a data transmission device using a daisy chain. A master device 10 has ports P1 and P2, one of which outputs a start signal START and the other of which inputs a data signal DATA. 20-1, 20-2, . . . , 20-N are slave devices cascaded in N stages (N is a positive integer equal to or greater than 2) and input/output a start signal START and a data signal DATA. They are cascade-connected via input/output ports P3 and P4.

The first-stage slave device 20-1 has a port P3 connected to the port P1 of the master device 10, and a port P4 connected to the port P3 of the second-stage slave device 20-2. The port P3 of the slave devices 20-2, 20-3, . . The port P4 of the N-th slave device 20-N is connected to the port P2 of the master device 10. FIG.

FIG. 3 shows the internal configuration of the slave device 20 commonly used as the above slave devices 20-1, 20-2, . . . , 20-N. Reference numeral 21 denotes a temperature sensor as a data signal generation circuit, which starts measuring the temperature of an object when it detects that a start signal START is input to an input port IN, and outputs the generated data signal DATA to an output port OUT when the measurement is completed. , and subsequently generates a start signal START for the next-stage slave device and outputs it from the output port OUT.

An input/output switching circuit 22 switches the contacts of the switches SW1 and SW2 to the a side when the port P5 becomes "H" and the port P6 becomes "L", and the signal input from the port P3 is sent to the temperature sensor 21. , and a signal output from the output port OUT of the temperature sensor 21 is output to the port P4. Further, when the port P5 becomes "L" and the port P6 becomes "H", the contacts of the switches SW1 and SW2 are switched to the "b" side so that the signal input from the port P4 is input to the input port IN of the temperature sensor 21. , the signal output from the output port OUT of the temperature sensor 21 is output to the port P3. When the ports P5 and P6 are both at "L", the contacts of the switches SW1 and SW2 are connected to c to disconnect the ports P3 and P4 from the input port IN and the output port OUT of the temperature sensor 21. FIG. Reference numeral 23 denotes a first impedance determination circuit for determining whether the impedance of the port P3 is high or low, and 24 is a second impedance determination circuit which determines whether the impedance of the port P4 is high or low.

The first impedance determination circuit 23 includes a current source I1, switches SW3 and SW4, a comparator CP1 in which a threshold voltage Vth1 is set, an inverting buffer circuit B1, and a control circuit 231. FIG. Then, when the power is turned on, the switch SW3 is turned off, the switch SW4 is turned on, and the current I1 of the current source I1 flows to the port P3 via the switch SW4. When the impedance of the port P3 is low, the voltage of the comparator CP1 becomes lower than the threshold voltage Vth1, the output thereof becomes "L", the inverting buffer circuit B1 becomes "H", and the control circuit 231 outputs "H" to the port P5. A signal of "H" is output to switch the switches SW1 and SW2 of the input/output switching circuit 22 to the contact a. When the impedance of the port P3 is high, the voltage of the comparator CP1 becomes higher than the threshold voltage Vth1, the output thereof becomes "H", the output of the inverting buffer circuit B1 becomes "L", and the control circuit 231 outputs "L" to the port P5. A signal of "L" is output. When the impedance determination is completed, the switch SW3 is turned ON and the switch SW4 is turned OFF.

The second impedance determination circuit 24 includes a current source I2, switches SW5 and SW6, a comparator CP2 in which a threshold voltage Vth2 is set, an inverting buffer circuit B2, and a control circuit 241. Then, when the power is turned on, the switch SW5 is turned off, the switch SW6 is turned on, and the current I2 of the current source I2 flows to the port P4 via the switch SW6. When the impedance of the port P4 is low, the voltage of the comparator CP2 becomes lower than the threshold voltage Vth2, the output thereof becomes "L", the inverting buffer circuit B2 becomes "H", and the control circuit 241 outputs "H" to the port P6. A signal of "H" is output to switch the switches SW1 and SW2 of the input/output switching circuit 22 to the contact b. When the impedance of the port P4 is high, the voltage of the comparator CP2 becomes higher than the threshold voltage Vth2, the output thereof becomes "H", the output of the inverting buffer circuit B2 becomes "L", and the control circuit 241 outputs "L" to the port P6. A signal of "L" is output. When the impedance determination is completed, the switch SW5 is turned ON and the switch SW6 is turned OFF.

25 is a delay circuit connected to the port P3, 26 is a delay circuit connected to the port P4, and the delay circuits 25 and 26 are set to have the same delay time in both directions. A switch SW7 is connected between the delay circuits 25 and 26. FIG. The switch SW7 is turned off when the power is turned on, turned on when the impedance level of the ports P3 and P4 is determined, and turned off when the start signal START is detected.

FIG. 4 shows a flow chart of the operation of the temperature sensor 21. As shown in FIG. When the start signal START inputted to the input port IN is detected (S1-Y), the temperature sensor 21 starts temperature measurement (S2), and when the temperature measurement is completed (S3-Y), it measures from the output port OUT. A data signal DATA indicating the value obtained is output (S4), and subsequently a start signal START for the slave device in the next stage is generated by one-shot multi or the like and output from the same output port OUT (S5).

FIG. 5 shows the configuration of the temperature measuring section 211 of the temperature sensor 21. As shown in FIG. A reference value generating circuit 2111 includes a fixed resistor R1, a capacitor C1, a reset switch SW8, a current source I3 with a current of I3, a comparator CP3 in which a threshold voltage Vth3 is set, and an inverting buffer circuit B3.

In the reference value generation circuit 2111, when the start signal START is detected, the switch SW8 is switched from ON to OFF, the capacitor C1 starts to be charged by the current I3 of the current source I3, and the charging voltage Vr increases with time. . When the charging voltage Vr exceeds the threshold voltage Vth3, the output voltage of the comparator CP1 changes from "H" to "L", and the output voltage Vrr of the inverting buffer circuit B3 changes from "L" to "H". . The switch SW8 is turned on after the output voltage Vrr becomes "H" to discharge the capacitor C1.

Reference numeral 2112 denotes a measurement signal generation circuit, which includes a temperature resistor R2 whose resistance value decreases as the temperature rises, a capacitor C2 (=C1), a reset switch SW9, a current source I4 (=I3) of the current I4, and a threshold voltage Vth4 (=Vth3). ) is set, and an inverting buffer circuit B4.

In this measured value generation circuit 2112, when the start signal START is detected, the switch SW9 is switched from ON to OFF, the capacitor C2 starts to be charged by the current I4 of the current source I4, and the charging voltage Vs increases with time. . When the charging voltage Vs exceeds the threshold voltage Vth4, the output voltage of the comparator CP2 changes from "H" to "L", and the output voltage Vss of the inverting buffer circuit B4 changes from "L" to "H". . The switch SW9 is turned on after the output voltage Vss becomes "H" to discharge the charge of the capacitor C2.

Reference numeral 2113 denotes a TDC (Time to Digital Converter) circuit, which converts the time from the rising timing of the output voltage Vrr of the inverting buffer circuit B3 to the rising timing of the output voltage Vss of the inverting buffer circuit B4 into a high-resolution digital serial signal. A data signal DATA of the measurement result is created.

FIG. 6 shows operating waveforms of the temperature measurement circuit 211 of the temperature sensor 21 described in FIG. When the start signal START is detected at time ta, the switches SW8 and SW9 are simultaneously switched from ON to OFF, and charging of the capacitors C1 and C2 by the currents I3 and I4 is started at the same time.

The resistance value of the fixed resistor R1 is set higher than the resistance value of the temperature resistor R2. Therefore, the charging current to capacitor C1 becomes larger than the charging current to capacitor C2, voltage Vr rises more steeply than voltage Vs, and voltage Vr exceeds threshold voltage Vth3 at time tb. Therefore, the voltage Vrr changes from "L" to "H" at the time tb.

On the other hand, when the temperature is low, the voltage Vs has a large resistance value of the temperature resistor R2, so that the charging current to the capacitor C2 increases. H”. When the temperature is high, the resistance value of the temperature resistor R2 becomes small, so the charging current to the capacitor C2 becomes small.

Therefore, when the temperature is low, the time T1 from time tb to tc is converted into the data signal DATA by the TDC circuit 2113, and when the temperature is high, the time T2 from time tb to td is converted into the data signal DATA. Become. Thus, the temperature sensor 21 outputs the measured serial data signal DATA from the output port OUT.

The start signal detection circuit 212 is shown in FIG. The input port INA is connected to the input port IN of the temperature sensor 21, and the signal of the output port TRG is used for controlling the switches SW8 and SW9 of the temperature measuring circuit 211 described with reference to FIG. B5 to B12 are inverting buffer circuits, 2121 is an integrating circuit composed of a resistor R3 and a capacitor C3, 2122 is a DFF circuit, and 2123 is an OR gate.

When the start signal START is input to the input port INA of the start signal detection circuit 212, the voltage obtained by inverting the voltage of the node N1 integrated by the integration circuit 2121 is output from the inverting inverter B12.

At this time, when the start signal START has a prescribed pulse width as shown in FIG. When the start signal START falls, the voltage STOP of the Q terminal of the DFF circuit 2122 remains "L" even if the CK terminal becomes "H" due to the output voltage of the inverting buffer circuit B11. Become. Since the signal INB obtained by delaying the start signal START by .DELTA.t by the inverting buffer circuits B5 to B10 is inputted to the OR gate 2123 as "L", the signal at the output port TRG of the OR gate 2123 becomes "L". TRG="L" is a signal that detects the start signal START, and turns off the switches SW8 and SW9 of the temperature measurement circuit 211. FIG.

On the other hand, when the start signal START is longer than the prescribed pulse width as shown in FIG. The voltage becomes "H", and when the CK terminal becomes "H" by the output voltage of the inverting buffer circuit B11, the voltage STOP of the Q terminal of the DFF circuit 2122 becomes "H". A signal INB obtained by delaying the start signal START by .DELTA.t by the inverting buffer circuits B5 to B10 is input to the OR gate 2123 as "L", but the signal at the output port TRG of the OR gate 2123 does not change from "H". That is, the normal start signal START is not detected.

In the slave devices 20-1, 20-2, . When the impedance determination circuit 23 determines that the node P3 has a low impedance and the impedance determination circuit 24 determines that the node P4 has a high impedance, the switches SW1 and SW2 of the input/output switching circuit 22 are switched to the contact a. The switch SW7 is turned ON. When the impedance determination circuit 23 determines that the port P3 has a high impedance and the impedance determination circuit 24 determines that the port P4 has a low impedance, the switches SW1 and SW2 of the input/output switching circuit 22 are connected to the contact b. As soon as it is switched, the switch SW7 is turned ON. Further, when the impedance determination circuit 23 determines that both the ports P3 and P4 have high impedance, the switches SW1 and SW2 of the input/output switching circuit 22 are switched to the contact c and the switch SW7 is turned ON. Furthermore, the switch SW7 is turned OFF when the start signal START is detected by the start signal detection circuit 212 in the temperature sensor 21 .

The master device 10 is set to either a forward mode in which port P1 is set to low impedance and port P2 to high impedance, or a reverse mode in which port P1 is set to high impedance and port P2 is set to low impedance. In forward mode, the start signal START is output from the port P1 and the data signal DATA is taken in from the port P2. In reverse mode, the start signal START is output from the port P2 and the data signal DATA is received from the port P1.

Immediately after the data transfer device of this embodiment is powered on, both ports P1 and P2 of the master device 10 are at high impedance. Also, the switch SW7 of each slave device 10-1, 10-2, . . . , 20-N is OFF. Therefore, ports P3 and P4 of slave devices 10-1, 10-2, . SW7 is turned ON by this determination.

Next, when the master device 10 is set to the forward mode, the port P1 is set to low impedance, so the port P3 of the slave device 20-1 in the first stage is changed to low impedance determination. Port P4 remains determined to be high impedance. Therefore, the input/output switching circuits SW1 and SW2 are switched to the contact a, the input port IN of the temperature sensor 21 is connected to the port P3, and the output port OUT is connected to the port P4. At this time, the signal flows as shown in FIG. 1, and the operation waveforms thereof are shown in FIG.

Next, when the start signal START is output from the port P1 of the master device 10, the start signal START is detected by the start signal detection circuit 212 in the temperature sensor 21 of the first-stage slave device 20-1. As a result, the switch SW7 is turned off, and temperature measurement starts at time t2 (=ta). When the temperature measurement ends at time t3, the measured data signal DATA1 is output from the output port OUT to the port P4 via the contact a of the switch SW2 of the input/output switching circuit 22. FIG. This data signal DATA1 is directly taken into the port P2 of the master device 10 via the switches SW7 of the slave devices 20-2, .

The start signal START input to the port P3 is also input to the delay circuit 25, but the delay time of the delay circuit 25 must be set longer than the normal pulse width time (t1 to t2) of the start signal START. For example, when the start signal detection circuit 212 completes the detection of the start signal START, the switch SW7 is turned off, so the start signal START input to the port P3 does not pass through to the port P4.

At this time, in the second-stage slave device 20-1, the port P4 of the first-stage slave device 20-1 has a low impedance because the switch SW2 is connected to the contact a. The port P3 of the slave device 20-2 is changed to low impedance determination. Further, the port P4 of the slave device 20-2 in the second stage is still judged to be high impedance.

In the slave device 20-1 at the first stage, when the output of the data signal DATA1 from the temperature sensor 21 is completed, a new start signal START is subsequently generated by the temperature sensor 21 and output via the switch SW2. Input from port P4 to port P3 of slave device 20-2 in the second stage. This second-stage slave device 20-2 also operates in the same manner as the first-stage slave device 20-1, and the data signal DATA2 measured by the temperature sensor 21 is output from the port P4. . . , and taken into the port P2 of the master device 10 as it is via the ON switch SW7 of the 20-N. Further, following the data signal DATA2, a new start signal START signal is generated and output from the port P4 to the third-stage slave device 20-3.

. . , 20-N in the third stage to the N-th stage to sequentially generate data signals DATA3, . are input to the port P2 of the master device 10, N temperature measurement data signals DATA1, . . . DATAN is sequentially taken into the master device 10 . A start signal START that is output from the slave device 20-N at the final stage and is input to the port P2 of the master device 10 is ignored by the master device 10. FIG.

From the above, if the slave devices 20-1, 20-2, .

On the other hand, when the master device 10 is set to the reverse mode after power-on, the port P1 is set to high impedance and the port P2 is set to low impedance. At this time, the signal flows as shown in FIG. 9, and the operation waveform diagram thereof is shown in FIG. At this time, the port P4 of the slave device 20-N of the Nth stage is changed to the low impedance determination. Port P3 remains determined to be high impedance. Therefore, the input/output switching circuits SW1 and SW2 are switched to the contact b, the input port IN of the temperature sensor 21 is connected to the port P4, and the output port OUT is connected to the port P3.

Next, when the start signal START is output from the port P2 of the master device 10 at time t21, the start signal START is detected by the start signal detection circuit 212 in the temperature sensor 21 of the N-th slave device 20-N. As a result, the switch SW7 is turned off, and temperature measurement starts at time t22 (=ta). When the temperature measurement ends at time t23, the measured data signal DATAN is output from the output port OUT to the port P3 via the contact b of the switch SW1 of the input/output switching circuit 22. FIG. This data signal DATAN is directly taken into the port P1 of the master device 10 via the ON switches SW7 of the slave devices 20-N-1, . . . , 20-1.

The start signal START input to the port P4 is also input to the delay circuit 26, but the delay time of the delay circuit 26 should be set longer than the normal pulse width time (t21 to t22) of the start signal START. For example, when the start signal detection circuit 212 completes the detection of the start signal START, the switch SW7 is turned off, so the start signal START input to the port P4 does not pass through to the port P3.

At this time, in the N-1th stage slave device 20-N-1, the port P3 of the N-th slave device 20-N is connected to the contact b of the switch SW1. port P4 of slave device 20-N-1 is changed to low impedance determination. Further, the port P3 of the slave device 20-N-1 of the N-1th stage remains judged to be high impedance.

In the N-th slave device 20-N, when the output of the data signal DATA1 from the temperature sensor 21 is completed, a new start signal START is subsequently output from the temperature sensor 21, and sent from the port P3 via the switch SW1. , to the port P4 of the slave device 20-N-1 at the N-1th stage. This N−1th stage slave device 20-N−1 also operates in the same manner as the Nth stage slave device 20-N, and the data signal DATAN-1 measured by the temperature sensor 21 is output from the port P3, , 20-1 through the ON switch SW7 of the slave device 20-N-2, . . . Further, following the data signal DATAN-1, a new start signal START is generated and output from the port P3 to the slave device 20-N-2 at the N-2th stage.

A similar operation is repeated from the N-2 stage to the first stage slave devices 20-N-2, . , DATA1 is generated and input to the port P1 of the master device 10, N temperature measurements measured by the slave devices 20-N, 20-N-1, . Data signals DATAN, . The master device 10 ignores the start signal START that is output from the slave device 20-1 in the first stage and is input to the port P1 of the master device 10. FIG.

From the above, if the slave devices 20-1, 20-2, .

As described above, when the master device 10 is set to the normal mode, the temperature data signals DATA1, DATA2, . , DATAN are sequentially taken into the port P2 of the master device 10; Also, if the master device 10 is set to the reverse order mode, the temperature data signals DATAN, DATAN-1, . DATA1 is sequentially taken into port P1 of master device 10 .

Therefore, when it is necessary to quickly capture the data signals measured by the slave devices in the first to middle stages, the master device 10 can be set to forward mode, and the data signals measured by the slave devices in the last to middle stages can be read. If early capture is required, the master device 10 can be set to reverse order mode. From the above, even when slave devices are connected in hundreds to thousands of stages, there is an advantage that the waiting time until acquiring a data signal measured in a desired stage can be reduced.

10: Master device 20, 20-1, . : start signal detection circuit 22: input/output switching circuit 23, 24: impedance determination circuit 25, 26: delay circuit

Claims (3)

Between the first and second ports of a master device having a first port and a second port, one for outputting a start signal and the other for inputting a data signal, a third port for inputting and outputting a data signal and a third port for inputting a data signal are provided. The third port and the fourth port of a slave device having four ports are daisy-chained over N stages (N is a positive integer equal to or greater than 2), and the third port of the first stage slave device is connected to the master device. connecting to the first port, connecting the fourth port of the N-th slave device to the second port of the master device;
When the third port has a low impedance and the fourth port has a high impedance, the slave device keeps the data signal to be input to the third port until a start signal to be input to the third port is detected. 4 port as it is, and when the start signal input to the 3rd port is detected, the communication between the 3rd port and the 4th port is interrupted, and a desired data signal is generated to be sent from the 4th port. while outputting, continuously generating a new start signal and outputting it from the fourth port;
When the third port has a high impedance and the fourth port has a low impedance, the slave device keeps the data signal to be input to the fourth port until the start signal to be input to the fourth port is detected. 3 port as it is, and when the start signal input to the 4th port is detected, the communication between the 3rd port and the 4th port is interrupted, and a desired data signal is generated to be sent from the 3rd port. outputting and continuously generating a new start signal and outputting it from the third port;
A data transfer method characterized by: a master device comprising a first port and a second port, one for outputting a start signal and the other for inputting a data signal; a third port and a fourth port for inputting and outputting a data signal; N (N is a positive integer equal to or greater than 2) slave devices daisy-chained between the 1st port and the 2nd port via the 3rd port and the 4th port. and
The slave device is
When the third port has low impedance and the fourth port has high impedance, the data signal input to the third port is passed through the fourth port as it is until the start signal input to the third port is detected. and when a start signal input to the third port is detected, the connection between the third port and the fourth port is cut off, and a desired data signal is generated and output from the fourth port while continuously generating a new start signal and outputting it from the fourth port;
When the third port has high impedance and the fourth port has low impedance, the data signal input to the fourth port is passed through the third port as it is until the start signal input to the fourth port is detected. and when a start signal input to the fourth port is detected, the connection between the third port and the fourth port is cut off, and a desired data signal is generated and output from the third port, and continuously generating a new start signal and outputting it from the third port;
A data transfer device characterized by: 3. The data transfer apparatus according to claim 2, wherein said slave device
a first impedance determination circuit that determines whether the impedance of the third port is high or low;
a second impedance determination circuit that determines whether the impedance of the fourth port is high or low;
It has an input port and an output port, and when the start signal is input to the input port, after detecting it, a data signal is generated and output from the output port, and then a new start signal is generated and output from the output port. a data signal generation circuit for output;
When the third port is low impedance and the fourth port is high impedance, the third port is connected to the input port and the fourth port is connected to the output port, and the third port is high impedance and the when the fourth port is low impedance, connecting the fourth port to the input port and connecting the third port to the output port; when both the third port and the fourth port are high impedance, the third port; and an input/output switching circuit that cuts off connection of the fourth port to the input port and the output port;
a first delay circuit connected to the third port and having a delay time longer than the pulse width of the start signal;
a second delay circuit connected to the fourth port and having a delay time longer than the pulse width of the start signal;
It is connected between the first delay circuit and the second delay circuit, is turned off when the first and second impedance determination circuits perform impedance determination operation after power-on, and the first and second impedance determination circuits are turned off. a seventh switch that turns ON when completes the impedance determination operation and turns OFF when the start signal is detected;
A data transfer device comprising:

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