JP7230341B2 - PLL circuit - Google Patents

Description

The present invention relates to a PLL (Phase Locked Loop) circuit.

A PLL circuit mainly includes a reference signal generator, a phase comparator, a loop filter, and a VCO (Voltage Controlled Oscillator), and feedback-controls the output frequency of the VCO. Patent document 1 is mentioned as a document related to this application. According to the technique described in Patent Document 1, it is possible to change the load driving capability of the drive circuit, and to reduce the clock skew after the semiconductor chip is formed.

JP-A-8-335670

In recent years, however, the power supply voltage has become low, and it has become difficult to generate a control voltage for the VCO using a general varicap diode. Desired .

It is desired that the loop filter of the PLL circuit has a variable loop band so as to meet legal requirements and adjust performance such as spurious response according to various situations.

An object of the present disclosure is to provide a PLL circuit that can change the loop band of a loop filter while suppressing the circuit scale as much as possible even if the operating power supply voltage becomes low.

The invention according to claim 1 compares the phases of a VCO (Voltage Controlled Oscillator) whose output signal is a signal having a frequency corresponding to a control voltage, and a reference signal generated by a reference signal generator and a frequency-divided signal of the output signal of the VCO. and a phase comparator for outputting the frequency error of the output signal of the VCO as a pulse signal from the output stage, and a loop filter for cutting the high frequency band of the pulse signal and inputting it to the VCO as a control voltage. The output stage of the phase comparator has an output current variable function, and the loop filter has a loop band variable function. The switching unit switches the loop band at the same time as switching the output current of the output stage using one transistor switch interposed between the output stage and the loop filter. Since the phase comparator outputs the frequency error of the VCO output signal as a pulse signal, the frequency error can be accurately detected even if a low power supply voltage is used. At least one transistor switch among a plurality of transistors between the output stage and the loop filter is controlled to switch the output current of the output stage and simultaneously switch the loop band. The loop band of the loop filter can be made variable while suppressing it.
The loop filter is composed of a low-pass filter with a plurality of parallel resistors and parallel capacitors, and is configured by connecting a common connection point between the plurality of parallel resistors and parallel capacitors to the input of the control voltage of the VCO. The switching unit is configured to switch current paths of the plurality of parallel resistors at the same time as switching the plurality of output currents of the output stage. switch so that the voltage amplitude on the low-frequency side of is controlled to be constant.

FIG. 2 is an electrical block diagram showing the output stage and loop filter of the phase comparator in the first embodiment; Electrical configuration diagram of a PLL circuit Equivalent circuit diagram showing the output stage of the phase comparator and the pre-stage circuit of the loop filter Signal voltage waveform before loop filter input and spectrum characteristic diagram after loop filter output Comparative example 1 I/O signal waveform of RC filter Signal voltage waveform before RC filter input and spectrum characteristic diagram after RC filter output (comparative example 1) Comparative example 2 An electrical configuration diagram showing the output stage and loop filter of the phase comparator in the second embodiment. Explanatory diagram of changes in the lock frequency of the PLL circuit and changes in various settings over time in the third embodiment. Electrical configuration diagram of a millimeter-wave radar system in the fourth embodiment Explanatory diagram of changes in the lock frequency of the PLL circuit with time and changes in various settings

Several embodiments of the PLL circuit will be described below with reference to the drawings. In each of the embodiments described below, the same or similar reference numerals are assigned to configurations that perform the same or similar operations, and description thereof will be omitted as necessary. In the following embodiments, the same or similar configurations are described by attaching the same reference numerals to the tens digit and the ones digit of the reference numerals.

(First embodiment)
1 to 8 show explanatory diagrams of the first embodiment. FIG. 2 shows an electrical block diagram of the PLL circuit 1. As shown in FIG. The PLL circuit 1 includes a voltage controlled oscillator (hereinafter referred to as a VCO) 2, a frequency divider 3, an MMD (Multi Modulus Divider) 4, a phase comparator 5, a loop filter 6, a decimal point calculation logic section 7, and a switching section. , and operates by inputting a reference signal Reference Clock generated by an external reference signal generator (not shown) to the phase comparator 5 . The logic circuit 8 constitutes a control subject, and if necessary, has a memory as a non-transitional substantive recording medium.

The VCO 2 is configured to output a signal having a frequency corresponding to (for example, proportional to) the control voltage input through the loop filter 6, for example. This VCO 2 is composed of, for example, an LC resonance type oscillation circuit. A frequency divider 3 divides an output signal of a frequency of about 40 GHz from the VCO 2, for example, converts the frequency to a frequency band of several GHz, and outputs the signal to the MMD 4. FIG. The decimal point calculation logic unit 7 is a frequency division ratio setting module for determining the frequency division ratio of the MMD 4, and changes the externally applied modulation signal according to the required operating frequency to give the value to the MMD 4, that is, the division ratio. Change the circumference ratio and output to MMD4.

MMD 4 is a multi-modulus divider for re-dividing the output obtained from VCO 2 via frequency divider 3, and re-divides the output signal of frequency divider 3 according to the frequency division ratio given from decimal point operation logic unit 7. It is frequency-divided and output to the phase comparator 5 . The phase comparator 5 compares the phases of the reference signal Reference Clock and the output of the MMD 4 and detects a signal corresponding to the phase difference, and detects the frequency error of the output signal of the VCO 2 as a pulse signal. The loop filter 6 cuts the high frequency band of the detected pulse signal to perform low-pass filter processing, and outputs it as a control voltage to the VCO 2 .

FIG. 1 shows the configuration of the output stage 5a of the phase comparator 5 and the configuration of the loop filter 6 together. The phase comparator 5 and loop filter 6 operate based on a low power supply voltage of about 1.1V, for example, applied between the two power supply lines. The preceding stage (not shown in FIG. 1) of the phase comparator 5 compares the phase of the reference signal ReferenceClock and the output of the MMD 4, thereby detecting the frequency error of the output signal of the VCO 2 from the magnitude of the pulse width of the pulse signal. do. In order to cope with this low power supply voltage, the inventors have found that the phase comparator detects the frequency error of the VCO output signal as the duty of the pulse signal, and the loop filter cuts the high frequency range of this pulse signal to convert it to a DC voltage. A configuration is adopted in which the voltage is converted and output as the control voltage of the VCO. At this time, the phase comparator outputs a pulse signal having a pulse width corresponding to the frequency error. Therefore, the VCO can change the output frequency by inputting a control voltage corresponding to the frequency error via the loop filter. Since the frequency error is detected based on the pulse width of the pulse signal, the frequency error can be accurately detected even if a low power supply voltage is used.

The output stage 5a of the phase comparator 5 includes a first-stage inverter 11, a plurality of subsequent second-stage inverters 12a-12d, and enable switches 13a-13d. The loop filter 6 includes resistors (corresponding to parallel resistors) Ra to Rd and capacitors (corresponding to parallel capacitors) Ca to Cd.

In the first stage inverter 11, the source and drain of the P-channel MOS transistor Mp1 and the drain and source of the N-channel MOS transistor Mn1 are connected in series between the two power supply lines, and these gates are connected to each other. are connected in common and their inputs are connected in parallel with each other. This first-stage inverter 11 inputs the pulse signal detected at the preceding stage of the phase comparator 5 and shapes the waveform.

A plurality of inverters 12a to 12d in the second stage are connected in parallel with their inputs positioned after the output stage 5a of the phase comparator 5. FIG. These second-stage inverters 12a to 12d are composed of P-channel MOS transistors (hereinafter referred to as PMOS transistors) Mpa to Mpd and N-channel MOS transistors (hereinafter referred to as NMOS transistors) Mna. ~Mnd.

These second-stage inverters 12a-12d are configured by connecting the source-drain regions of PMOS transistors Mpa-Mpd and the drain-source regions of NMOS transistors Mna-Mnd in series between two power supply lines. ing. All the gates of the PMOS transistors Mpa-Mpd and the NMOS transistors Mna-Mnd of the plurality of second-stage inverters 12a-12d are commonly connected. Enable switches 13a-13d are interposed between the drains of the PMOS transistors Mpa-Mpd and the NMOS transistors Mna-Mnd, respectively.

The enable switches 13a to 13d are selection switches provided to enable/disable one or more of the plurality of second stage inverters 12a to 12d. It includes channel type MOS transistors (hereinafter referred to as PMOS transistors) Mepa to Mepd and N channel type MOS transistors (referred to as NMOS transistors) Mena to Mend. These PMOS/NMOS transistors Mepa to Mepd and Mena to Mend constitute transistor switches.

Enable signals EN1 to EN4 from the logic circuit 8 are input to the NOT gates Ga to Gd and the gates of the NMOS transistors Mena to Mend. Enable signals EN1 to EN4 are input from the logic circuit 8 via Ga to Gd. Here, an example is given in which the logic circuit 8 controls the number of control bits of the enable signals EN1 to EN4 to four.

The source/drain of the PMOS transistor Mepa and the NMOS transistor Mena forming the enable switches 13a to 13d is interposed between the drains of the PMOS transistor Mpa and the NMOS transistor Mna forming the inverters 12a to 12d between the two power supply lines. configured as follows. The drains of the PMOS transistor Mepa and the NMOS transistor Mena are connected in common and connected to one end of the resistors Rd to Ra in the latter stage.

Therefore, for example, when the enable signal EN1 becomes "H", the PMOS transistor Mepa is turned on and the NMOS transistor Mena is turned on. Conversely, when the enable signal EN1 becomes "L", the PMOS transistor Mepa is turned off. At the same time, the NMOS transistor Mena is turned off. Even if the other enable signals EN2 to EN4 are H/L, the same operation is performed.

Therefore, the logic circuit 8 switches the enable signals EN1 to EN4 to H/L to select one or a plurality of outputs of the plurality of second-stage inverters 12a to 12d, and selects the output of the selected inverter 12a. 12d can be output to the resistors Ra to Rd, respectively.

These second-stage inverters 12a to 12d are configured to have different current driving capabilities. The plurality of inverters 12a to 12d adjust the sizes of the respective PMOS/NMOS transistors Mpa to Mpd and Mna to Mnd in proportion to the current drive capability, so that when enabled by the enable switches 13a to 13d, respectively. , “×1” times, “×2” times, “×4” times, and “×8” times the predetermined reference current (see FIG. 1), that is, 2 n times (n is 0, . . . ). , k−1, k; k is a predetermined number (k=3 in this embodiment)) and is configured to output currents to the resistors Ra to Rd.

The PMOS transistors Mepa to Mepd and the NMOS transistors Mena to Mend of the enable switches 13a to 13d are also configured to have different current driving capacities. Proportionally adjusted so that when enabled by enable switches 13a-13d, 'x1', 'x2', 'x4', 'x8' times the predetermined reference current. (see description in FIG. 1), that is, 2 n times (n is 0, ..., k-1, k; k is a predetermined natural number (k = 3 in this embodiment)) current configured to output to

The current driving capabilities of the plurality of inverters 12a to 12d and the enable switches 13a to 13d in the second stage correspond to 2 to the 0th power, 2 to the 1st power, 2 to the 2nd power, and 2 to the 3rd power. However, the present invention is not limited to this, and the plurality of inverters 12a to 12d and the enable switches 13a to 13d in the second stage are configured to have a current drive capability corresponding to 2 to the fourth power or more. can be

The plurality of resistors Ra to Rd are connected in parallel with each other, and one terminal thereof is connected to the common connection points Na to Nd of the PMOS transistors Mepa to Mepd and the NMOS transistors Mena to Mend of the enable switches 13a to 13d, respectively, The other terminals are commonly connected at a common connection point Nin.

These multiple resistors Ra to Rd have resistance values of "8×R", "4×R", "2×R", and "1×R" with the reference resistance value as R, that is, 2 to the mth power (m are set to k, k−1, . . . , 0).

A plurality of parallel capacitors Ca to Cd are connected in parallel between this common connection point Nin and the ground, and switches SWa to SWd are configured in the conduction paths of the respective capacitors Ca to Cd. The switches SWa to SWd can be turned on/off by a logic circuit 8. FIG. Thereby, the connections of the capacitors Ca to Cd can be switched, and the loop band of the loop filter 6 can be switched.

A common connection point Nin between the plurality of resistors Ra to Rd and the plurality of capacitors Ca to Cd is connected to the input terminal of the control voltage of the VCO2, and the VCO2 uses the output voltage of the loop filter 6 as the control voltage. signal is the output signal.

FIG. 3 shows an equivalent circuit to facilitate understanding of the connection relationship between the second stage inverters 12a to 12d and the resistors Ra to Rd. As shown in FIG. 3, the inverter 11 in the first stage has a current driving capability of "×8" of a predetermined reference current, and the inverters 12a to 12d in the second stage are located in the latter stage. connected in parallel. These second-stage inverters 12a to 12d have ratios of "x1", "x2", "x4", and "x8" of a predetermined reference current, that is, 2 to the nth power (where n is 0, . . . ). , k−1, k).

That is, the phase comparator 5 has an output current variable function in the output stage 5a that outputs the pulse signal. In addition, corresponding to these, the second-stage inverters 12a to 12d each have a ratio of resistance values "x8", "x4", "x2", and "x1" with the reference resistance value as R. It is connected in series with resistors Ra to Rd having a resistance value, ie, a ratio of 2 to the mth power (where m is k, k-1, . . . , 0).

Therefore, when the logic circuit 8 inputs the enable signals EN1 to EN4 to the respective enable switches 13a to 13d, the output stage 5a can select the second stage inverters 12a to 12d to switch the output current. At the same time, the energization paths of the plurality of parallel resistors Ra to Rd can also be switched. At this time, regardless of how the enable signals EN1 to EN4 are input to the respective enable switches 13a to 13d, (output currents of the second stage inverters 12a to 12d)×(resistance values of the resistors Ra to Rd)= The voltage can be kept constant, and as a result, in principle, the voltage amplitude on the low frequency side can be controlled to be constant.

Substantially, when the current driving capabilities of the inverters 12a-12d differ, the transistor sizes of the MOS transistors Mpa-Mpd and Mna-Mnd also change, and the MOS transistors forming the inverters 12a-12d are proportional to the transistor sizes. The output impedances (so-called on-resistances) when the transistors Mpa-Mpd and Mna-Mnd are turned on change with each other.

For this reason, for example, when the output impedance of the MOS transistors Mpa-Mpd and Mna-Mnd is 1/k (for example, 1/10) of the resistors Ra-Rd constituting the loop filter 6, the input of the loop filter 6 The voltage amplitude will drop at the ends. Therefore, for each input path of the current output by the inverters 12a-12d to the resistors Ra-Rd, the voltage amplitude is kept constant by taking into account the output impedance of the MOS transistors Mpa-Mpd and Mna-Mnd constituting the inverters 12a-12d. It is desirable to control Moreover, it is desirable that the resistance values of the plurality of parallel resistors Ra to Rd are set based on the output impedances of the MOS transistors Mpa to Mpd and Mna to Mnd.

The action and operation of the above configuration will be described with reference to FIGS. 4 and 5. FIG. FIG. 4 shows the signal voltage waveform before the input to the loop filter 6 on the upper side, and the spectrum characteristics after the output of the loop filter 6 on the lower side. The solid line indicates the characteristics when the cutoff frequency fc is set to a relatively narrow band fc1, and the dashed line indicates the characteristics when the cutoff frequency fc is set to a relatively wide band fc2.

As shown in FIG. 4, since the phase comparator 5 of the PLL circuit 1 detects the frequency error of the output signal as a pulse width, its output is a rectangular wave in principle. Here, the logic circuit 8 selects the current path from the output of the inverters 12a to 12d to the resistors Ra to Rd according to the enable signals EN1 to EN4, thereby selecting the resistors Ra to Rd forming the loop filter 6. FIG. The output voltage is smoothed because the loop filter 6 filters its input voltage. At this time, the carrier of the pulse signal leaks, and the frequency component of the pulse signal remains and becomes spurious.

However, no matter how high or low the cutoff frequency fc of the loop filter 6 is set by the logic circuit 8, the circuit configuration shown in FIG. unit drive capability can be made uniform. Therefore, the input voltage waveform to the loop filter 6 can be made equal in both narrow band characteristics and wide band characteristics. As shown in the spectrum characteristic in the lower part of FIG. 4, even if the cutoff frequency fc is increased from fc1 to fc2 to widen the band, the spurious due to the rectangular wave can be suppressed from Y dB to Z dB (where Z dB>Y dB), and the frequency Degradation of characteristics can be suppressed to a minimum.

(Comparative example 1)
FIGS. 5-7 show one configuration of the comparative example and its corresponding characteristics.
As shown in FIG. 5, the output stage 5aa of the phase comparator 5 is configured by connecting a plurality of stages of inverters 11a and 11b in cascade, and the loop filter 6aa includes a plurality of parallel resistors Ra to Rd and a plurality of parallel capacitors Ca. to Cd can be selected by switches SWaa to SWda and SWa to SWd, respectively.

In general, this type of loop filter 6aa is often configured by adding switches SWa to SWd that enable the values of resistors Ra to Rd and capacitors Ca to Cd to be changed in order to adjust the time constant. If a circuit configuration with an output stage 5aa and a loop filter 6aa as shown in FIG. 5 is adopted, then from the output stage 5aa of the phase comparator 5, as shown in FIG. By outputting the pulse signal, the loop filter 6aa performs low-pass filtering to cut high frequency components. At this time, when the phase comparator 5 outputs a pulse signal with a large duty ratio, the pulse signal is smoothed to increase the low frequency component (DC component), and conversely, a pulse signal with a small duty ratio is output. Then, the low frequency component (DC component) becomes smaller by smoothing the pulse signal.

FIG. 7 shows the input voltage waveforms when the time constant of the loop filter 6aa is large or small, that is, narrow band or wide band, in the upper part, and the spectrum characteristics of the output in the lower part corresponding to FIG. is shown.

As shown in FIG. 7, by adjusting the time constant of the loop filter 6aa, the cutoff frequency fc can be adjusted to a relatively narrow cutoff frequency fc1 or a relatively wide cutoff frequency fc2.
However, even if the loop filter 6aa cuts the harmonic components by the combination of the resistors Ra to Rd and the capacitors Ca to Cd, it is confirmed that the spurious +X dB becomes large especially when the wideband cutoff frequency fc2 is applied. It is That is, when the time constant of the loop filter 6aa is small and the cutoff frequency fc2 is high, the slew rate is high, so the carrier leak spurious of the pulse signal is increased and the degree of suppression of the filter is also reduced. As a result, the spurious tends to get worse. See spurious Y [dB]<X [dB] in FIG.
In contrast, when configured as shown in FIG. 1 of the present embodiment, spurious +Y [dB] of narrowband characteristics shown in FIG. Even if fc is widened, spurious deterioration can be reduced.

(Comparative example 2)
FIG. 8 shows the second configuration of the comparative example. In order to solve the first problem of the comparative example, the configuration shown in FIG. The configuration of the loop filter 6ab for selective adjustment according to EN1 to EN4 is shown.

The logic circuit 8 controls the ON/OFF of the enable switches 13a to 13d by the enable signals EN1 to EN4 to enable the outputs of the inverters 12a to 12d, or to enable the output stage 5a of the phase comparator 5. Switch the output to a high impedance state (Hi-Z).
In the comparative example 2 shown in FIG. 8, the logic circuit 8 selects one of the inverters 12a to 12d with the current drive capabilities "x1", "x2", "x4", and "x8" by the enable switches 13a to 13d. When one or more are selected, resistors Rd to Ra with resistance values "1 x R", "2 x R", "4 x R", and "8 x R" are selected by switches SWdb to SWab to input VCO2. can be output as a control voltage to

In particular, when the logic circuit 8 selects the inverter 12a with the current drivability “×1” as enabled by the enable switch 13a, the resistor Rd with the resistance value “1×R” is selected by the switch SWdb and controlled to the input of the VCO2. Consider outputting as a voltage. Conversely, when the logic circuit 8 selects the inverter 12d with the current drivability "x8" as enabled by the enable switch 13d, it selects the resistor Ra with the resistance value "8xR" and controls it to the input of the VCO2. Consider outputting as a voltage.

In this case, the current drive capability of the output stage 5a of the phase comparator 5 is set according to the conditions when the resistance Ra of the loop filter 6ab is large and the capacitance of the capacitor Ca is large. If Rd is selected to be small and the capacity of the capacitor Cd is small, there is a concern that the current will be excessively driven and the spurious noise will be aggravated.

In the second comparative example, the enable switches 13a to 13d of the output stage 5a of the phase comparator 5 and the switches SWab to SWdb for switching the resistors Ra to Rd of the loop filter 6ab are separately provided. , these switches 13a to 13d and SWab to SWdb are connected in series. Therefore, at least two or more of the switches 13a to 13d and SWab to SWdb are connected in series. 13d, it is desired to secure a sufficiently large size of SWab to SWdb. It should be noted that increasing the size of these switches 13a-13d and SWab-SWdb leads to an increase in element area, which leads to an increase in circuit scale.

On the other hand, according to this embodiment, there exists an effect as shown below.
<Summary of conceptual configuration and effects of the present embodiment>
According to this embodiment, the phase comparator 5 has an output current variable function in the output stage 5a that outputs the pulse signal, the loop filter 6 has a loop band variable function, and the output stage of the phase comparator 5 One transistor switch (one of Mepa to Mepd and Mena to Mend constituting 13a to 13d) interposed between 5a and loop filter 6 is used to switch the output current of output stage 5a of phase comparator 5. It is configured to switch the loop band at the same time. According to the configuration of this embodiment, the inverters 12a to 12d can be switched using one transistor switch. function can be achieved. Moreover, the loop band of the loop filter 6 can be made variable while suppressing the circuit scale as much as possible without increasing the size of the transistor switch.

In particular, by adjusting the enable signals EN1 to EN4, the logic circuit 8 can variably adjust the time constant and cutoff frequency fc of the loop filter 6, and at the same time optimize the current driving capability of the output stage 5a of the phase comparator 5. value can be variably adjusted. Therefore, these parameters can be adjusted according to the intended use.

Further, the logic circuit 8 is configured to switch between the plurality of output currents of the output stage 5a of the phase comparator 5 and at the same time switch the conduction paths of the plurality of parallel resistors Ra to Rd. , the voltage amplitude on the low-frequency side of the loop filter 6 is controlled to be constant when current is output to the parallel resistors Ra to Rd. Thereby, spurious can be reduced as much as possible.

Spurious can be further reduced if the resistance values of the plurality of parallel resistors Ra to Rd are set based on the output impedance when the MOS transistors Mpa to Mpd and Mna to Mnd are turned on.

The plurality of parallel resistors Ra to Rd are each set to a resistance value of a ratio of 2 to the mth power (where m is k, . . . , 1, 0). Since the currents are each set to a current value with a ratio of 2 to the nth power (where n is 0, . . . , k-1, k), spurious can be minimized.

(Second embodiment)
FIG. 9 shows an additional explanatory diagram of the second embodiment. FIG. 9 shows the configuration of the output stage 205 a of the phase comparator 205 and the loop filter 206 . In the first embodiment, an example is shown in which the resistance values of the resistors Ra to Rd and the output currents of the inverters 12a to 12d are weighted and set by so-called binary weights. It is not always necessary to weight them, and they may be evenly divided.

As shown in FIG. 9, the plurality of parallel resistors Ra to Rd are set to the same ratio of "×4", and the output currents of the output stage 5a are set to the same ratio of "×4". is set to a current value of Since other configurations are the same as those of the above-described embodiment, description thereof is omitted. In this embodiment, (output currents of inverters 12a to 12d of output stage 5a)×(resistance values of resistors Ra to Rd)=voltage can be kept constant. As a result, the same effects as those of the above-described embodiment can be obtained.

(Third embodiment)
FIG. 10 shows an additional explanatory diagram of the second embodiment. In this embodiment, a practical example will be described. The hardware configuration of the PLL circuit 1 will be described using the configurations of FIGS. 1 and 2 described in the first embodiment.

When the output frequency of the VCO 2 is stably held, the PLL circuit 1 uses the output signal to perform frequency feedback control with high accuracy, so it is important to keep the loop band of the loop filter 6 held. However, if the loop band of the loop filter 6 is set to, for example, a narrow-band predetermined frequency fc1, the PLL circuit 1 There is a risk that the phase-locking speed of will be slower than necessary.

Therefore, when the PLL circuit 1 changes its lock frequency stepwise from the first frequency f1 to the second frequency f2, in order to improve the phase locking speed of the PLL circuit 1, as shown in FIG. It is desirable to widen the loop bandwidth of

10, when changing the frequency of the output signal of the PLL circuit 1 from the first frequency f1 to the second frequency f2 in steps, the logic circuit 8 outputs the enable signals EN1 to EN4. or by switching and controlling the switches SWa to SWd of the capacitors Ca to Cd to set the loop band of the loop filter 6 to a frequency fc2 that is wider than the predetermined frequency fc1, thereby accelerating the phase lock speed. .

In particular, in this phase lock period, when spurious radiation must be suppressed due to legal limit requirements (see limit in FIG. 10), the configurations described in the first and second embodiments can be adopted. Spurious radiation can be particularly effectively suppressed. In other words, by adjusting the current drive capability of the inverters 12a-12d, it becomes possible to simultaneously select the energization paths of the resistors Ra-Rd, thereby significantly suppressing spurious emission.

Further, when the frequency of the output signal of the PLL circuit 1 converges to the constant frequency f2 at the time T3, the loop band of the loop filter 6 is returned to the predetermined narrow band frequency fc1 during the subsequent allowance time T3-T2. It is good to do so. The leeway time T3 to T2 is set in consideration of the influence of the lock of the PLL circuit 1 being shaken again due to the filter constant change. Then, even after the frequency is returned to the frequency f2, the phase lock control processing of the PLL circuit 1 can be continuously performed with high accuracy.

As described above, according to the present embodiment, when the frequency of the output signal of the VCO2 is stably held, the logic circuit 8 switches the loop band so as to hold it at the predetermined frequency fc1, and changes the frequency of the output signal of the VCO to is switched stepwise, the loop band is switched so as to expand from the predetermined frequency fc1. Therefore, even when the frequency of the output signal of the PLL circuit 1 is changed stepwise from the first frequency f1 to the second frequency f2, the phase locking speed can be accelerated. Moreover, when the frequency is stably held, the phase lock processing of the PLL circuit 1 can be performed with high accuracy.

(Fourth embodiment)
11 and 12 show explanatory diagrams of the third embodiment. In this embodiment, a form applied to a millimeter wave radar system 31 is shown. FIG. 11 schematically shows the configuration of the millimeter wave radar system 31. As shown in FIG.

The millimeter-wave radar system 31 includes a one-chip transmitter/receiver IC 32 , a transmitting antenna 33 , a receiving antenna 34 , a controller 35 and a reference oscillation circuit 36 . The transceiver-mounted IC 32 and the controller 35 may be configured as one chip or may be configured separately. A controller 35 and a reference oscillation circuit 36 based on a crystal oscillator are connected to the transceiver-equipped IC 32 . The reference oscillation circuit 36 generates a reference clock with a certain reference frequency, and outputs this reference clock to the modulation/demodulation signal generation section 37 inside the transceiver-equipped IC 32 .

The transceiver-mounted IC 32 includes a modulation/demodulation signal generator 37 , a transmitter 38 , a receiver 39 , and a circuit control register 40 . The controller 35 first writes a frequency command such as the frequency fsta and parameters such as the amplification degree of the intermediate frequency amplifier 49 to the circuit control register 40, thereby performing command processing and circuit control processing for the transceiver-equipped IC 32. . The transceiver-mounted IC 32 is composed of a semiconductor integrated circuit device.

The modulation/demodulation signal generation unit 37 includes a ramp wave generator 41 as a control command output unit and a PLL circuit 301 . The ramp wave generator 41 generates, for example, a command signal (initial frequency fsta→final frequency fsto) for gradually increasing/decreasing the frequency in time according to the frequency command input to the circuit control register 40. output to

When the reference clock of the reference oscillation circuit 36 is input, the modulation/demodulation signal generator 37 gradually increases/decreases according to the FCM (Fast-Chirp Modulation) modulation method, and outputs it as a high-precision local signal. The frequency of this local signal is adjusted to Fmod/N (N is the multiplication number by N multipliers 43 and 47, etc., which will be described later), and is output to the transmitting section 38 and the receiving section 39. FIG. Here, the modulation/demodulation signal generator 37 gradually increases/decreases according to a predetermined modulation method to generate a local signal of frequency Fmod/N, but the local signal of frequency Fmod may also be generated. The form is not limited.

The transmission unit 38 includes an N multiplier 43 that multiplies the local signal by N, a phase shifter 44 that phase-shifts the signal output from the N multiplier 43, and an amplifier 45 that amplifies the output of the phase shifter 44. , output the amplified signal of the amplifier 45 . Since the N multiplier 43 multiplies the output of the modulation/demodulation signal generator 37 by N, the frequency of the output signal of the N multiplier 43 becomes the modulation frequency Fmod. be done. Therefore, the frequency of the transmission signal from the transmitter 38 is the modulation frequency Fmod.

A transmission signal from the transmission unit 38 is output as a radar transmission wave to the outside through the transmission antenna 33 . Phase shifter 44 is provided to change the phase of the signal output from N multiplier 43 . Although schematically shown in FIG. 11, the transmitting antenna 33 is composed of a plurality of antenna elements such as a planar antenna using a patch antenna. Also, the phase shifter 44 is connected to each of the plurality of antenna elements forming the transmitting antenna 33, for example, and changes the phase corresponding to each antenna element. This allows the transmission direction to be adjusted by beamforming technology.

As shown in FIG. 11, the radar transmission wave output from the transmission antenna 33 is reflected by the object T to generate a reflected signal. This reflected signal is input to the receiving antenna 34 . The receiving antenna 34 is also composed of, for example, a planar antenna such as a patch antenna, and receives radar waves. The antenna elements of the transmitting antenna 33 and the receiving antenna 34 are arranged in parallel so that the distance between adjacent antenna elements is equal, although not shown.

On the other hand, the receiving section 39 comprises a low noise amplifier 46 , an N multiplier 47 , a mixer 48 , an intermediate frequency amplifier 49 and an A/D converter 50 . The receiving unit 39 receives signals through the receiving antenna 34 . Low-noise amplifier 46 amplifies the received signal with a predetermined degree of amplification and outputs this amplified signal to mixer 48 . The N multiplier 47 multiplies the signal output from the modulation/demodulation signal generator 37 by N and outputs the result to the mixer 48 .

Mixer 48 is configured as a frequency converter, mixes the output signal of low noise amplifier 46 and the modulated signal output from N multiplier 47 , and outputs this mixed and frequency-converted signal to intermediate frequency amplifier 49 . The intermediate frequency amplifier 49 is configured by, for example, a variable amplifier, amplifies the signal by the amplification factor set in the circuit control register 40 , and outputs the amplified signal to the A/D converter 50 . The A/D converter 50 digitally converts the amplified analog signal and outputs it to the controller 35 . The controller 35 is composed of, for example, a microcomputer (none of which is shown) having a CPU, ROM, RAM, etc., and acquires digital data converted by the receiver 39 .

By adopting such a configuration, the millimeter wave radar system 31 is mounted so as to be able to transmit radar waves, for example, in front of the vehicle, transmits and receives radar waves in the millimeter wave (eg, 80 GHz band: 76.5 GHz) band, and controls Information about the object T is calculated by the device 35 performing signal processing based on the digital data acquired from the receiving unit 39 . This object T is, for example, another vehicle such as a preceding vehicle, or a roadside object on the road. The information about the object T is, for example, information based on distance, relative speed, direction, and the like.

In such a millimeter wave radar system 31, the PLL circuit 301 has the same configuration as the PLL circuit 1 shown in FIG. is configured to be controlled by inputting the contents of the control register of

The PLL circuit 301 receives a command signal from the ramp wave generator 41, and outputs an output signal whose frequency gradually decreases in response to the command signal, as shown from timing to T11 in FIG. At this time, the PLL circuit 301 gradually decreases the frequency of the output signal of the VCO2 from the initial frequency fsta to the final frequency fsto. After that, the PLL circuit 301 returns to the initial frequency fsta in a stepwise manner according to the command signal input from the ramp wave generator 41 and outputs a signal as shown at timings T11 to T12 in FIG.

In this case, as shown in FIG. 12, the logic circuit 308 switches the loop band of the loop filter 6 so as to maintain the predetermined frequency fc1 when the frequency of the output signal of the VCO2 is gradually decreased, and the frequency of the output signal of the VCO2 is changed to the final frequency. When the frequency fsto is first returned to the frequency fsta, it is desirable to switch the loop band to a frequency fc2 that is wider than the predetermined frequency fc1. Then, as in the previous embodiment, the phase lock speed can be accelerated when returning from the final frequency fsto to the initial frequency fsta.

In particular, in this phase lock period, when spurious radiation must be suppressed due to legal limit requirements (see limit in FIG. 12), the configurations described in the first and second embodiments can be adopted. Spurious radiation can be particularly effectively suppressed. In other words, by adjusting the current drive capability of the inverters 12a-12d, it becomes possible to simultaneously select the energization paths of the resistors Ra-Rd, thereby significantly suppressing spurious emission.

Further, when the output frequency of the PLL circuit 301 first converges to the frequency fsta at the time T13, the loop band of the loop filter 6 is returned to the predetermined narrow band frequency fc1 during the subsequent allowance time T13-T12. good. The leeway time T13 to T12 is set in consideration of the influence of the lock of the PLL circuit 301 being shaken again due to the filter constant change. Then, even after the frequency is first returned to fsta, the phase lock control processing of the PLL circuit 301 can be performed with high accuracy. Other effects are the same as those of the first to third embodiments, so description thereof will be omitted.

(Other embodiments)
The present disclosure is not limited to the embodiments described above, and can be implemented in various modifications, and can be applied to various embodiments without departing from the scope of the present disclosure. For example, the following modifications or extensions are possible.

Although the case where the PLL circuit 301 outputs a gradually decreasing signal by the FCM modulation method is exemplified, it is the same when outputting a gradually increasing signal according to the employed modulation method. The modulation method is not limited as long as it is a method that outputs .

The configurations and functions of the multiple embodiments described above may be combined. A mode in which part of the above embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, all conceivable aspects can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the language in the claims.

Although the present disclosure has been described in accordance with the embodiments described above, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of this disclosure.

In the drawings, 1, 301 is a PLL circuit, 2 is a VCO, 5 is a phase comparator, 5a is an output stage, 6 is a loop filter, 8, 308 is a logic circuit (switching section), 12a to 12d are inverters, and Ra to Rd. is a resistance (parallel resistance), Mpa to Mpd, Mna to Mnd are MOS transistors of the output stage 5a, fsta is the initial frequency, and fsto is the final frequency.

Claims (6)

a VCO (Voltage Controlled Oscillator) (2) that outputs a signal having a frequency corresponding to the control voltage;
a phase comparator (5) for comparing the phases of the reference signal generated by the reference signal generator and the frequency-divided signal of the output signal of the VCO and outputting the frequency error of the output signal of the VCO as a pulse signal from the output stage (5a); ,
a loop filter (6) for cutting a high frequency band of the pulse signal and inputting it to the VCO as the control voltage,
The output stage of the phase comparator has an output current variable function, and the loop filter has a loop band variable function,
a plurality of transistors provided between the output stage and the loop filter, and controlling at least one transistor switch among the plurality of transistors interposed between the output stage and the loop filter to control the output; A switching unit (8) that switches the output current of the stage and switches the loop band at the same time,
The loop filter is composed of a low-pass filter composed of a plurality of parallel resistors and a parallel capacitor, and a common connection point (Nin) between the plurality of parallel resistors and the parallel capacitor is connected to the control voltage of the VCO. configured by connecting to the input,
The switching unit is configured to switch current paths of the plurality of parallel resistors at the same time as switching the plurality of output currents of the output stage, and switches the output current of the output stage to output the current to the plurality of parallel resistors. A PLL circuit that switches so as to control the voltage amplitude on the low-pass side of the loop filter to be constant . The output stage of the phase comparator is configured using inverters (12a-12d) using MOS transistors (Mpa-Mpd, Mna-Mnd),
2. The PLL circuit according to claim 1 , wherein the resistance values of said plurality of parallel resistors are set based on the output impedance when said MOS transistor is turned on. Each of the plurality of parallel resistors is set to a resistance value of a ratio of m power of 2 (where m is k, . . . 2, 1, 0: k is a predetermined natural number), and correspondingly, 3. The PLL circuit according to claim 1 , wherein the output currents of said output stages are each set to a current value of a ratio of 2 n (where n is 0, . . . , k-1, k). 3. The PLL circuit according to claim 1, wherein the plurality of parallel resistors are set to have resistance values of the same ratio, and the output currents of the output stage are set to current values of the same ratio. When the frequency of the output signal of the VCO is stably held, the switching section switches the loop band so as to hold it at a predetermined frequency (fc1), and when the frequency of the output signal of the VCO is switched stepwise, the 2. A PLL circuit according to claim 1, wherein said loop band is switched to be wider than said predetermined frequency. The VCO gradually increases or decreases the frequency of its output signal from the initial frequency (fsta) to the final frequency (fsto) and then returns to the initial frequency to output a signal with a frequency according to the FCM modulation method. sometimes,
When the frequency of the output signal of the VCO is gradually increased or decreased, the switching unit switches so as to maintain the loop band at a predetermined frequency (fc1), and changes the frequency of the output signal of the VCO from the final frequency to the initial frequency. 2. A PLL circuit according to claim 1, wherein said loop band is switched so as to expand said loop band from said predetermined frequency when returning.

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