JP7200203B2 - ERROR DETECTION DEVICE AND ERROR DETECTION METHOD - Google Patents

Description

The present invention decodes a PAM4 signal by a four-level pulse amplitude modulation system (PAM4 system) in which the amplitude is divided into four types for each symbol into a binary signal (NRZ signal), and detects an error based on the level measurement result of the decoded signal. It relates to an error detection device and an error detection method for detecting

For example, as disclosed in Patent Document 1 below, an error rate measurement device outputs a test signal of a known pattern including fixed data in a state where a device under test (DUT: Device Under Test) is transitioned to a signal pattern loopback state. Conventionally, as a device for measuring a bit error rate by comparing a signal under test transmitted to a device under test and received back from the device under test in accordance with the transmission of the test signal with a reference signal as a reference on a bit-by-bit basis. Are known.

JP 2007-274474 A

By the way, in Ethernet (registered trademark), which is the mainstream of wired network technology, for example, in 400G Ethernet (registered trademark), a Stressed Input Test is specified for a C2M (chip 2 module) interface. For the Stressed Input Test, a scrambled idle pattern with RS-FEC (Reed-Solomon Forward Error Correction) encoding is defined in addition to a pseudo-random pattern such as PRBS13Q.

In the scrambled idle pattern with RS-FEC encoding, since error correction is performed by FEC, the error correction effect by FEC can be evaluated by checking the number of FEC symbol errors (conversely, if bit errors are It is difficult to correctly evaluate the effect of error correction by FEC only by checking).

Especially in 200G and 400G Ethernet (registered trademark), since error correction by FEC is a prerequisite, it is important to evaluate the effect of FEC using a scrambled idle pattern with RS-FEC encoding.

On the other hand, 400G Ethernet (registered trademark) is a multi-lane interface, allows skew between lanes, and uses alignment markers to remove the skew. However, since bit strings are recombined when skew is removed, the bit string for error measurement may be different from the bit string output for error measurement. Bit strings are also rearranged in a gearbox when changing the number of lanes. Therefore, the bit string for error measurement is different from the bit string output for error measurement.

On the other hand, when using a pseudo-random pattern such as PRBS, the same pattern is used for all lanes, so this operation is not a problem. Even if the output bit string (output pattern of the pattern generator) is directly set in the error detector, it is not always possible to measure the error. Moreover, since there are many combinations of bit strings after recombination, it is extremely difficult to manually set the error measurement pattern in the error detector. As an example of such a phenomenon, FIG. 5 shows a measurement system of a stressed input test in which a 400G Ethernet (registered trademark) optical module (QSFP-DD LR4 optical module) is used as a device to be measured.

In the measurement system of FIG. 5, a device under test (DUT) W is equipped with a gearbox Wa that converts the transmission rate and the number of transmission channels. If there is, there is no guarantee that the pattern output by the MSB of the pattern generator 21 will return to the MSB of the error detector 22 .

In the case of the measurement system of FIG. 5, considering that the outputs of the two-lane pattern generators 21 among the outputs of the eight pattern generators 21 are maximized in the PAM4ASIC of the gearbox Wa of the device under test W, 1 Since a lane has two channels, MSB and LSB, four channels are maxed. Therefore, the combination of channels input to the error detector 22 is a permutation of choosing 2 out of 4, so ₄ P ₂ =4! /(4-2)! = 12 ways. In other words, there are 12 types of data input to one lane of the error detector 22, and it is very difficult for the user to manually search for 12 types of reference patterns.

Further, the details of combinations of patterns input to the error detector 22 under the influence of skew will be described with reference to FIGS. 6 to 9. FIG.

6 to 9, two pattern generators 21 (21a, 21b) and two error detectors 22 (22a, 22b) are provided, and the device under test (DUT) W is 2:1 MUX (W1 ∼ W3), and a 1:2 DEMUX (W4 to W6) are provided inside, and patterns of 2 lanes (lanes 0 to 3) are generated from the pattern generators 21a and 21b via the device under test (DUT) W to the error detector 22a. , 22b will be described as an example.

6 to 9, the pattern generator 21a generates a bit string of 0→0.1→0.2→0.3 as a pattern of MSB: FEC lane 0, and 2→2.1→2.2→ 2. 3 bit strings are generated as LSB:FEC lane 2 patterns, and these patterns are input to the 2:1 MUX (W1) of the device under test W;

Also, the pattern generator 21b generates a bit string of 1→1.1→1.2→1.3 as a pattern of MSB:FEC lane 1, and a bit string of 3→3.1→3.2→3.3. are generated as LSB:FEC lane 3 patterns, and these patterns are input to the 2:1 MUX (W2) of the device under test W.

The 2:1 MUX (W1) is a bit string 2→0→2.1→0.1→ obtained by alternately MUXing the FEC lane 2 pattern bit and the FEC lane 0 pattern bit from the leading bit of FEC lane 2. Input 2.2→0.2→2.3→0.3 to 2:1 MUX (W3). The 2:1 MUX (W2) is a bit string 3→1→3.1→1.1→ obtained by alternately MUXing the pattern bits of FEC lane 3 and the pattern bits of FEC lane 1 from the leading bit of FEC lane 3. Input 3.2→1.2→3.3→1.3 to 2:1 MUX (W3).

Subsequently, the 2:1 MUX (W3) generates a PAM4 signal using the bit string multiplexed by the 2:1 MUX (W2) as the MSB and the bit string multiplexed by the 2:1 MUX (W1) as the LSB. A bit string obtained by alternately MUXing the bits from W2) and the bits from the 2:1 MUX (W1) is returned by an optical fiber and input to the 1:2 DEMUX (W4). The 1:2 DEMUX (W4) demuxes the bit string from the 2:1 MUX (W3) into odd-numbered (LSB) bits and even-numbered (MSB) bits, and 1:2 DEMUXes the odd-numbered (LSB) bit string. (W6), and the even-numbered (MSB) bit string is input to 1:2 DEMUX (W5).

Then, the 1:2 DEMUX (W5) demuxes the bit string from the 1:2 DEMUX (W4) into even-numbered bits and odd-numbered bits. As a result, even-numbered bits are input to the error detector 22a as MSB: FEC lane 0, and odd-numbered bits are input as LSB: FEC lane 2. FIG. Also, the 1:2 DEMUX (W6) demuxes the bit string from the 1:2 DEMUX (W4) into even-numbered bits and odd-numbered bits. As a result, even-numbered bits are input to the error detector 22b as MSB: FEC lane 1, and odd-numbered bits are input as LSB: FEC lane 3. FIG.

Here, FIG. 6 shows an example of skew-free pattern combinations when patterns are input from the pattern generators 21a and 21b to the error detectors 22a and 22b via the object W to be measured. In the example of FIG. 6, the bit strings input to the error detectors 22a and 22b are not exchanged.

FIG. 7 shows the case where the pattern input from the pattern generator 21a to the object W to be measured has a skew when the patterns are input from the pattern generators 21a and 21b to the error detectors 22a and 22b via the object W to be measured. 1 shows an example of a combination of patterns of . In the example of FIG. 7, a 1-bit skew (x) occurs at the head of FEC lane 0 of the MSB of the pattern generator 21a. In this case, as in FIG. 6, the bit strings input to the error detectors 22a and 22b are not interchanged.

FIG. 8 shows an example of a combination of patterns when patterns are skewed in the object W to be measured when patterns are input from the pattern generators 21a and 21b to the error detectors 22a and 22b via the object W to be measured. showing. In the example of FIG. 8, a 1-bit skew (x) occurs at the head of the pattern input from 2:1 MUX (W1) to 2:1 MUX (W3). In this case, the MSB and LSB of the bit string input to the error detector 22a are interchanged.

FIG. 9 shows another combination of patterns when patterns are skewed in the object W to be measured when patterns are input from the pattern generators 21a and 21b to the error detectors 22a and 22b via the object W to be measured. An example is shown. In the example of FIG. 9, a 1-bit skew (x) occurs at the beginning of the pattern input from the 2:1 MUX (W3) to the 1:2 DEMUX (W4). In this case, the MSB and LSB of the bit strings input to the error detectors 22a and 22b are interchanged.

As described above, the bit string for error measurement by the error detectors 22a and 22b becomes a bit string different from the bit string output for error measurement depending on the skew occurrence location (including the amount of skew). However, there is a problem that the error correction effect cannot be evaluated.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an error detection apparatus and an error detection method capable of evaluating the error correction effect of RS-FEC.

In order to achieve the above object, an error detection device according to claim 1 of the present invention decodes a PAM4 pattern pre-record in which the FEC lane is Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding. a pre-record decoder 3;
a PAM4 decoder 4 for separating the PAM4 pattern into a most significant bit channel and a least significant bit channel;
a Gray code decoder 5 for decoding a PAM4 pattern Gray code whose precode is decoded by the precode decoder;
an alignment marker detection unit 6 for detecting alignment markers included in the scrambled idle pattern decoded by the gray code decoder and detecting bit shifts between the detected alignment markers;
an error measurement pattern generator 7 for generating a scrambled idle pattern corresponding to the alignment marker detected by the alignment marker detector in each channel as a reference pattern for error measurement;
a skew circuit 8 for adding bit deviation between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a Bit MUX unit 9 that bit-muxes the reference pattern to which the bit shift between the alignment markers is added in the skew circuit;
a Gray code encoder 10 that performs Gray code encoding on the reference pattern Bit MUXed by the Bit MUX unit;
a first deskew circuit 11 that removes bit shifts between alignment markers detected by the alignment marker detection unit with respect to the reference pattern encoded in Gray code by the Gray code encoder;
a second deskew circuit 12 for removing bit shifts between alignment markers detected by the alignment marker detection unit from input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and an error detection unit 13 for performing symbol error measurement.

The error detection device according to claim 2 of the present invention includes a precode decoder 3 for decoding a precode of a PAM4 pattern in which the FEC lane is not Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding;
a PAM4 decoder 4 for separating the PAM4 pattern into a most significant bit channel and a least significant bit channel;
a Gray code decoder 5 for decoding a PAM4 pattern Gray code whose precode is decoded by the precode decoder;
an alignment marker detection unit 6 for detecting alignment markers included in the scrambled idle pattern decoded by the gray code decoder and detecting bit shifts between the detected alignment markers;
an error measurement pattern generator 7 for generating a scrambled idle pattern corresponding to the alignment marker detected by the alignment marker detector in each channel as a reference pattern for error measurement;
a skew circuit 8 for adding bit deviation between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a Gray code encoder 10 that performs Gray code encoding on the reference pattern;
a first deskew circuit 11 that removes bit shifts between alignment markers detected by the alignment marker detection unit with respect to the reference pattern encoded in Gray code by the Gray code encoder;
a second deskew circuit 12 for removing bit shifts between alignment markers detected by the alignment marker detection unit from input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and an error detection unit 13 for performing symbol error measurement.

In the error detection method according to claim 3 of the present invention, the step of decoding a pre-record of a PAM4 pattern in which the FEC lane is Bit-MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding in a pre-record decoder 3. When,
separating the PAM4 pattern into a most significant bit channel and a least significant bit channel in a PAM4 decoder 4;
a step of decoding, by a Gray code decoder 5, the Gray code of the PAM4 pattern, the precode of which is decoded by the precode decoder;
a step of detecting an alignment marker included in the scrambled idle pattern decoded by the Gray code decoder and detecting a bit shift between the detected alignment markers by an alignment marker detector 6;
a step of generating a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detection unit as a reference pattern for error measurement in each channel by the error measurement pattern generation unit 7;
a step of adding the bit deviation between the alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit, using a skew circuit 8;
a step of Bit MUXing the reference pattern to which the bit shift between the alignment markers is added by the skew circuit in the Bit MUX unit 9;
a step of performing Gray code encoding with a Gray code encoder 10 on the reference pattern Bit MUXed by the Bit MUX unit;
a step of removing, by a first deskew circuit 11, a bit shift between alignment markers detected by the alignment marker detection unit with respect to the reference pattern encoded in Gray code by the Gray code encoder;
a step of removing, by a second deskew circuit 12, bit deviations between alignment markers detected by the alignment marker detector from the input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and a step of performing symbol error measurement in the error detection unit 13 .

In the error detection method according to claim 4 of the present invention, the pre-record decoder 3 decodes a PAM4 pattern pre-record in which the FEC lane is not Bit-MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding. a step;
separating the PAM4 pattern into a most significant bit channel and a least significant bit channel in a PAM4 decoder 4;
a step of decoding, by a Gray code decoder 5, the Gray code of the PAM4 pattern, the precode of which is decoded by the precode decoder;
a step of detecting an alignment marker included in the scrambled idle pattern decoded by the Gray code decoder and detecting a bit shift between the detected alignment markers by an alignment marker detector 6;
a step of generating a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detection unit as a reference pattern for error measurement in each channel by the error measurement pattern generation unit 7;
a step of adding the bit deviation between the alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit, using a skew circuit 8;
a step of using a Gray code encoder 10 to encode a reference pattern to which a bit shift between alignment markers has been added by the skew circuit;
a step of removing, by a first deskew circuit 11, a bit shift between alignment markers detected by the alignment marker detection unit with respect to the reference pattern encoded in Gray code by the Gray code encoder;
a step of removing, by a second deskew circuit 12, bit deviations between alignment markers detected by the alignment marker detector from the input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and a step of performing symbol error measurement in the error detection unit 13 .

According to the present invention, a pattern can be specified by detecting an alignment marker, and a reference pattern for error measurement can be automatically generated. Error measurement can be performed without the user setting a reference pattern, and bit errors can be evaluated correctly. It is possible to evaluate the error correction effect by RS-FEC, which cannot be done.

1 is a block configuration diagram of a first embodiment of an error detection device according to the present invention; FIG. FIG. 4 is a block configuration diagram of a second embodiment of an error detection device according to the present invention; Fig. 3 is a flow chart of an error detection method according to the present invention; 4A and 4B are diagrams showing display examples of detection results of alignment markers; FIG. FIG. 2 is a diagram showing a measurement system for a stressed input test of a 400G Ethernet (registered trademark) optical module as a device under test; FIG. 10 is a diagram showing an example of skew-free pattern combinations when patterns are input from the pattern generator to the error detector via the device under test; FIG. 10 is a diagram showing an example of a combination of patterns when the pattern input from the pattern generator to the device under test has a skew when the pattern is input from the pattern generator to the error detector via the device under test; FIG. 10 is a diagram showing an example of a combination of patterns when patterns are skewed in the device under test when patterns are input from the pattern generator to the error detector through the device under test; FIG. 10 is a diagram showing another example of a combination of patterns when patterns are skewed in the device under test when the patterns are input from the pattern generator to the error detector through the device under test;

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated in detail, referring attached drawings.

The present invention decodes a PAM4 signal by a four-level pulse amplitude modulation system (PAM4 system) in which the amplitude is divided into four types for each symbol into a binary signal (NRZ signal), and detects an error based on the level measurement result of the decoded signal. In particular, an alignment marker included in an RS-FEC Scramble Idle pattern as an error measurement pattern is detected, and a lane bit error indicated by the detected alignment marker, FEC A function to measure the symbol error is realized.

As shown in FIG. 1, the error detection device 1A of the first embodiment is adopted when the FEC lane is a bit-muxed input in realizing the above functions. Code decoder 3, PAM4 decoder 4, Gray code decoder 5, alignment marker detector 6, error measurement pattern generator 7, skew circuit 8, Bit MUX unit 9, Gray code encoder 10, first deskew circuit 11, second Deskew circuit 12 and error detection unit 13 are provided.

The bit-muxed pattern input to the error detection device 1A includes bit strings of patterns by two types of FEC lanes in one FEC lane, and even-numbered bit strings and odd-numbered bit strings in one FEC lane. Lane information is different.

Further, as shown in FIG. 2, the error detection device 1B of the second embodiment is adopted when the FEC lane is an input that is not bit-muxed in realizing the above functions. , precode decoder 3, PAM4 decoder 4, Gray code decoder 5, alignment marker detector 6, error measurement pattern generator 7, skew circuit 8, Gray code encoder 10, first deskew circuit 11, second deskew circuit 12 and an error detection unit 13 .

In the error detection device 1A shown in FIG. 1 and the error detection device 1B shown in FIG. 2, the same numbers are assigned to the same or equivalently functioning components.

The pattern generator 2 generates a known measurement pattern, specifically a PAM4 pattern based on a scrambled idle pattern with RS-FEC encoding. The PAM4 pattern is composed of two channels, the most significant bit channel (hereinafter referred to as MSB CH) and the least significant bit channel (hereinafter referred to as LSB CH), and one FEC lane is assigned to each channel. The pattern generators 2 are provided in the number corresponding to the transmission speed and bit rate between the device under test W, and when the pattern generators 2 are composed of a plurality of units, each pattern generator 2 is different for each channel. Generate a PAM4 pattern to be the pattern.

It should be noted that the device under test W can also generate a PAM4 pattern by itself using the scrambled idle pattern with RS-FEC encoding described above.

In transmission using the PAM4 pattern, precoding is used as an encoding method for removing burst errors. A precoding encoder that performs precoding is PAM4 A process for converting the pattern into a prerecorded symbol P(j) is performed.

Note that j in the above formulas (1) and (2) is an integer of 1 or more. Also, P(j) is the j-th prerecorded symbol. Also, G(j) is the j-th Gray code symbol, which is obtained by converting the four PAM4 symbols 0, 1, 2, 3 of the PAM4 pattern to 0, 1, 3, 2, respectively.

The precoding decoder 3 decodes the PAM4 pattern precoding from the device under test W using the scrambled idle pattern with RS-FEC encoding.

More specifically, the precoding decoder 3 converts a precoding symbol P(j) into a Gray code G(j) by G(j+1)=(P(j+1)+P(j)) mod 4 (3). ), G(1)=P(1) . . .

Note that j in the above formulas (3) and (4) is an integer of 1 or more. Also, P(j) is the jth precoded symbol and G(j) is the jth Gray code symbol.

For example, if a 1-bit error is added only to the MSB of the precoded PAM4 symbol, a 2-bit error occurs in the MSB of the decoded Gray code. On the other hand, when an n-bit (n≧2) burst error is added only to the MSB of the precoded PAM4 symbol, a 2-bit error occurs in the MSB of the gray code after decoding. Thus, precoding is a very effective encoding method for removing burst errors added to MSBs.

The PAM4 decoder 4 separates the PAM4 pattern pre-decoded by the pre-coding decoder 3 into MSB CH and LSB CH.

The Gray code decoder 5 decodes the Gray code of the PAM4 pattern pre-decoded by the pre-code decoder 3 .

The alignment marker detector 6 detects an alignment marker pattern included in the scrambled idle pattern obtained by the gray code decoding of the PAM4 pattern by the gray code decoder 5 . Specifically, when the FEC lane is not Bit-MUXed, one alignment marker is detected per channel, and when the FEC lane is Bit-MUXed, two alignment markers are detected per channel.

When the FEC lane is not bit-muxed, the alignment marker detection unit 6, upon detecting an alignment marker pattern, synchronizes with the detected alignment marker pattern, detects a bit shift between the two alignment markers, and detects the bit shift between the two alignment markers. 8, notify the first deskew circuit 11 and the second deskew circuit 12;

In addition, when the FEC lane is Bit MUXed, the alignment marker detection unit 6, upon detecting an alignment marker pattern, synchronizes with the detected alignment marker pattern, detects a bit deviation between the four alignment markers, and notifies that fact. The skew circuit 8, the first deskew circuit 11, and the second deskew circuit 12 are notified.

The alignment marker pattern is a pattern that is included in the scrambled idle pattern as a pattern for lane identification, appears at a predetermined cycle, and can be detected by a well-known procedure in accordance with the standard.

The error measurement pattern generator 7 generates a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detector 6 as a reference pattern for error measurement in each channel.

To explain further, when the FEC lane is not Bit MUXed, the error measurement pattern generator 7 generates the above-described reference pattern for two channels. On the other hand, when the FEC lane is Bit MUXed, the above reference pattern is generated for four channels.

The skew circuit 8 adds the bit deviation between the alignment markers notified from the alignment marker detector 6 to the reference pattern generated by the error measurement pattern generator 7 .

To explain further, the skew circuit 8 adds two channels of bit deviation between the alignment markers when the FEC lane is not bit-muxed. On the other hand, when the FEC lane is Bit MUXed, four channels of bit deviation are added between the alignment markers.

The Bit MUX unit 9 Bit MUXes the reference pattern generated by the error measurement pattern generator 7 in the error detection device 1A of FIG.

The Gray code encoder 10 performs Gray code encoding on the reference pattern to which a bit shift between alignment markers is added by the skew circuit 8 in the error detection device 1A of FIG. .

Note that the Gray code encoder 10 of the error detection device 1B of FIG. 2 encodes the reference pattern to which the bit shift between the alignment markers is added by the skew circuit 8 into Gray code.

The first deskew circuit 11 removes the bit deviation between the alignment markers notified from the alignment marker detection unit 6 for the reference pattern encoded in Gray code by the Gray code encoder 10 .

The second deskew circuit 12 removes the bit shift between the alignment markers notified from the alignment marker detector 6 from the input data separated into the MSB CH and LSB CH by the PAM4 decoder 4 .

The error detection unit 13 compares the reference pattern from which the bit deviation between the alignment markers has been removed by the first deskew circuit 11 and the input data from which the bit deviation between the alignment markers has been eliminated by the second deskew circuit 12 . , bit error measurement, and FEC symbol error measurement.

Next, an error detection method by the error detection apparatuses 1A and 1B described above will be described with reference to FIG.

First, the prerecord decoder 3 generates a PAM4 pattern (a known pattern by a scrambled idle pattern with RS-FEC encoding) input from the pattern generator 2 via the device under test W, or a PAM4 pattern generated by the device under test W itself. A pattern (a known pattern based on a scrambled idle pattern with RS-FEC encoding) is pre-decoded (ST1).

Next, the PAM4 decoder 4 separates the PAM4 pattern pre-decoded by the pre-code decoder 3 into MSB CH and LSB CH (ST2).

Also, the Gray code decoder 5 decodes the Gray code of the PAM4 pattern whose precode was decoded by the precode decoder 3 (ST3).

Next, the alignment marker detection unit 6 detects the alignment marker pattern included in the scrambled idle pattern in the PAM4 pattern whose Gray code has been decoded by the Gray code decoder 5 according to a well-known procedure in accordance with the standard. Synchronization is established with the aligned alignment marker pattern (ST4).

Then, the alignment marker detector 6 detects a bit shift between the alignment markers, and notifies the skew circuit 8 and each of the deskew circuits 11 and 12 to that effect (ST5). That is, when the FEC lane is not bit-muxed, the alignment marker detection unit 6 detects a bit shift between the two alignment markers and notifies the skew circuit 8, the first deskew circuit 11, and the second deskew circuit 12. . On the other hand, if the FEC lane is Bit MUXed, bit deviations between the four alignment markers are detected and notified to the skew circuit 8, the first deskew circuit 11, and the second deskew circuit 12. FIG.

Next, the error measurement pattern generator 7 generates a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detector 6 as a reference pattern for error measurement in each channel (ST6). That is, the error measurement pattern generator 7 generates a reference pattern for 2CH when the FEC lane is not Bit-MUXed, and generates a reference pattern for 4CH when the FEC lane is Bit-MUXed.

Next, the skew circuit 8 adds the bit shift between the alignment markers notified from the alignment marker detector 6 to the reference pattern (ST7). That is, the skew circuit 8 adds 2CH of bit deviation between the alignment markers when the FEC lane is not Bit MUXed, and adds 4CH of bit deviation between the alignment markers when the FEC lane is Bit MUXed.

Then, if the FEC lane is bit-muxed, the bit-mux unit 9 bit-muxes the reference pattern to which the bit shift between the alignment markers is added in the skew circuit 8 (ST8).

Next, the Gray code encoder 10 performs Gray code encoding on the reference pattern (ST9). That is, when the FEC lane is not Bit MUXed, the Gray code encoder 10 performs Gray code encoding on the reference pattern to which the bit shift between the alignment markers is added. On the other hand, when the FEC lane is Bit MUXed, Gray code encoding is performed on the reference pattern to which a bit shift between alignment markers is added and which is Bit MUXed.

Next, the first deskew circuit 11 removes the bit shift between the alignment markers notified from the alignment marker detection unit 6 for the reference pattern that has been Gray code encoded by the Gray code encoder 10 . Also, the second deskew circuit 12 removes the bit shift between the alignment markers notified from the alignment marker detector 6 from the input data separated into the MSB CH and LSB CH by the PAM4 decoder 4 . That is, the bit deviation between the notified alignment markers is removed from the input data and the reference pattern (ST10).

The error detector 13 then compares the input data from the second deskew circuit 12 with the reference pattern from the first deskew circuit 11, and performs bit error measurement and FEC symbol error measurement.

By the way, although not particularly shown in FIGS. 1 and 2, the error detection devices 1A and 1B may be provided with a display unit to display the detection results of the alignment markers on the display unit. Specifically, as shown in FIGS. 4A and 4B, the presence or absence of detection of MSB and LSB alignment markers (MSB Alignment Maker Loss, LSB Alignment Maker Loss) (in the case of Bit MUX, an odd bit: odd bit, even bit: even bit), the marker number (lane number: Marker map) of the detected MSB and LSB alignment marker (if Bit MUX is performed, odd bit: odd bit, even bit: even bit) ) and the amount of skew (Relative Lane Skew [UI]) are displayed on the display screen 14 of the display unit.

Thus, according to the present embodiment, by detecting the alignment marker of the RS-FEC scrambled idle pattern as the error measurement pattern, the error measurement pattern is automatically detected and the FEC symbol error is measured. can be done. That is, even if a pattern different from the error measurement pattern on the output side is input, the error can be measured by specifying the pattern by detecting the alignment marker, and the error correction effect by RS-FEC, which cannot be correctly evaluated by bit errors, can be evaluated. be able to. In systems where the bit string output for error measurement (the output pattern of the pattern generator) is not directly input to the error detection unit, the reference pattern for error measurement is automatically generated, eliminating the need for the user to set the reference pattern. error measurements can be made.

Although the best mode of the error detection device and error detection method according to the present invention has been described above, the present invention is not limited by the description and drawings according to this mode. In other words, it goes without saying that other forms, embodiments, operation techniques, etc. made by persons skilled in the art based on this form are all included in the scope of the present invention.

1A, 1B error detector 2 pattern generator 3 prerecord decoder 4 PAM4 decoder 5 gray code decoder 6 alignment marker detector 7 error measurement pattern generator 8 skew circuit 9 Bit MUX section 10 gray code encoder 11 first deskew circuit 12 second deskew circuit 13 error detector 14 display screen 21 (21a, 21b) pattern generator 22 (22a, 22b) error detector W device under test (DUT)
Wa Gearbox W1-W3 2:1MUX
W4 to W6 1:2 DEMUX

Claims (4)

A pre-record decoder (3) that decodes a pre-record of a PAM4 pattern in which the FEC lane is Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding;
a PAM4 decoder (4) for separating the PAM4 pattern into a most significant bit channel and a least significant bit channel;
a Gray code decoder (5) for decoding a PAM4 pattern Gray code whose precode has been decoded by the precode decoder;
an alignment marker detection unit (6) for detecting alignment markers included in the scrambled idle pattern decoded by the gray code decoder and detecting bit shifts between the detected alignment markers;
an error measurement pattern generator (7) for generating a scrambled idle pattern corresponding to the alignment marker detected by the alignment marker detector in each channel as a reference pattern for error measurement;
a skew circuit (8) for adding a bit shift between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a Bit MUX unit (9) for Bit MUXing the reference pattern to which the bit shift between the alignment markers is added in the skew circuit;
a Gray code encoder (10) that performs Gray code encoding on the reference pattern Bit MUXed by the Bit MUX unit;
a first deskew circuit (11) for removing bit shifts between alignment markers detected by the alignment marker detection unit with respect to a reference pattern encoded in Gray code by the Gray code encoder;
a second deskew circuit (12) for removing bit shifts between alignment markers detected by the alignment marker detector from input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and an error detection unit (13) for performing symbol error measurement. A pre-record decoder (3) that decodes a pre-record of a PAM4 pattern in which the FEC lane is not Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding;
a PAM4 decoder (4) for separating the PAM4 pattern into a most significant bit channel and a least significant bit channel;
a Gray code decoder (5) for decoding a PAM4 pattern Gray code whose precode has been decoded by the precode decoder;
an alignment marker detection unit (6) for detecting alignment markers included in the scrambled idle pattern decoded by the gray code decoder and detecting bit shifts between the detected alignment markers;
an error measurement pattern generator (7) for generating a scrambled idle pattern corresponding to the alignment marker detected by the alignment marker detector in each channel as a reference pattern for error measurement;
a skew circuit (8) for adding a bit shift between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a Gray code encoder (10) that performs Gray code encoding on the reference pattern;
a first deskew circuit (11) for removing bit shifts between alignment markers detected by the alignment marker detection unit with respect to a reference pattern encoded in Gray code by the Gray code encoder;
a second deskew circuit (12) for removing bit shifts between alignment markers detected by the alignment marker detector from input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder;
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and an error detection unit (13) for performing symbol error measurement. A step of decoding a pre-record of a PAM4 pattern in which the FEC lane is Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding by a pre-record decoder (3);
separating said PAM4 pattern into a most significant bit channel and a least significant bit channel in a PAM4 decoder (4);
a step of decoding, with a Gray code decoder (5), the Gray code of the PAM4 pattern whose precode has been decoded by the precode decoder;
a step of detecting an alignment marker included in the scrambled idle pattern decoded by the gray code decoder and detecting a bit shift between the detected alignment markers by an alignment marker detector (6);
a step of generating a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detection unit as a reference pattern for error measurement in each channel by an error measurement pattern generation unit (7);
a step of adding, by a skew circuit (8), a bit shift between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a step of Bit MUXing the reference pattern to which a bit shift between alignment markers is added by the skew circuit in a Bit MUX unit (9);
a step of using a Gray code encoder (10) to perform Gray code encoding on the reference pattern Bit MUXed by the Bit MUX unit;
a step of removing, by a first deskew circuit (11), a bit shift between alignment markers detected by the alignment marker detection unit with respect to a reference pattern encoded in Gray code by the Gray code encoder;
A step of removing, by a second deskew circuit (12), bit deviations between alignment markers detected by the alignment marker detector from the input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder. When,
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and C. performing symbol error measurement in an error detector (13). A step of decoding a pre-record of a PAM4 pattern in which the FEC lane is not Bit MUXed as a known pattern by a scrambled idle pattern with RS-FEC encoding by a pre-record decoder (3);
separating said PAM4 pattern into a most significant bit channel and a least significant bit channel in a PAM4 decoder (4);
a step of decoding, with a Gray code decoder (5), the Gray code of the PAM4 pattern whose precode has been decoded by the precode decoder;
a step of detecting an alignment marker included in the scrambled idle pattern decoded by the gray code decoder and detecting a bit shift between the detected alignment markers by an alignment marker detector (6);
a step of generating a scramble idle pattern corresponding to the alignment marker detected by the alignment marker detection unit as a reference pattern for error measurement in each channel by an error measurement pattern generation unit (7);
a step of adding, by a skew circuit (8), a bit shift between alignment markers detected by the alignment marker detection unit to the reference pattern generated by the error measurement pattern generation unit;
a step of using a Gray code encoder (10) to encode a reference pattern to which a bit shift between alignment markers has been added by the skew circuit;
a step of removing, by a first deskew circuit (11), a bit shift between alignment markers detected by the alignment marker detection unit with respect to a reference pattern encoded in Gray code by the Gray code encoder;
A step of removing, by a second deskew circuit (12), bit deviations between alignment markers detected by the alignment marker detector from the input data separated into the most significant bit channel and the least significant bit channel by the PAM4 decoder. When,
Bit error measurement by comparing a reference pattern from which bit deviation between alignment markers has been removed by the first deskew circuit and input data from which bit deviation between alignment markers has been eliminated by the second deskew circuit, and performing FEC and C. performing symbol error measurement in an error detector (13).

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