JP7195243B2 - semiconductor equipment - Google Patents

Description

More particularly, the present disclosure relates to equalizer circuits that compensate for attenuated frequency components of differential input signals.

2. Description of the Related Art In recent years, information communication technology has become faster, and a high-speed serial interface, which is faster than a parallel interface, is widely used as a connection interface between information communication devices and inside the device.

In such a high-speed serial interface, when a differential signal for transmitting data passes through a transmission path, the signal is degraded due to the influence of the external environment such as connectors, cables, and board substrates. In particular, inter-symbol interference (ISI) occurs due to the effects of jitter due to the attenuation characteristics of transmission paths, which hinders high-speed transmission. In order to correct this ISI, an equalizer circuit is usually used in the circuit on the receiving side that receives the differential signal.

As a conventional equalizer circuit, a configuration is disclosed in which a differential input signal is converted to a predetermined level and a predetermined frequency characteristic is obtained (Patent Document 1).

JP 2013-90026 A

On the other hand, in recent years, with the increasing number of cases where the function of transmitting the data is installed in vehicles, the possibility of testing the adjustment function of the equalizer circuit is also increasing.

As an adjustment function of the equalizer circuit, it is conceivable to test the resistance value (adjustment amount).

The present disclosure is intended to solve the above problems, and provides a semiconductor device capable of testing the adjustment function of an equalizer circuit while suppressing an increase in area. Other problems and novel features will become apparent from the description of the specification and drawings.

According to one embodiment, a semiconductor device includes an equalizer circuit that corrects attenuated frequency components of a differential input signal input via a transmission line. The equalizer circuit includes a first equalizer unit including a plurality of first switches capable of adjusting resistance values in multiple steps for differential input signals, and adjusting the resistance values in multiple steps for differential input signals. a second equalizer unit including a plurality of second switches, a comparator, a path switching section, and a determination circuit. A comparator compares the differential output signal of the first equalizer unit and the differential output signal of the second equalizer unit. The path switching section switches between the first path for connecting the output of the first equalizer unit and the output of the second equalizer unit during normal operation, and the output of the first equalizer unit and the output of the second equalizer unit during testing. Switching the second path to connect with the comparator to compare with each other. A decision circuit detects a failure based on the comparison result of the comparator.

According to one embodiment, the semiconductor device can test the adjustment function of the equalizer circuit while suppressing an increase in area.

1 is a diagram for explaining the configuration of a semiconductor device based on Embodiment 1; FIG. 3 is a diagram illustrating the configuration of the semiconductor device during normal operation according to the first embodiment; FIG. 4 is a diagram illustrating the configuration of the semiconductor device during test operation according to the first embodiment; FIG. FIG. 10 is a diagram for explaining the result of test operation of the semiconductor device according to the first embodiment; FIG. 10 is a diagram illustrating a flow during test operation of the semiconductor device according to the first embodiment; FIG. 10 is a diagram illustrating the configuration of a semiconductor device based on Embodiment 2; FIG. 10 is a diagram for explaining the result of test operation of the semiconductor device according to the second embodiment; FIG. 10 is a diagram illustrating results of another test operation of the semiconductor device according to the second embodiment; FIG. 10 is a diagram illustrating a flow during test operation of the semiconductor device according to the second embodiment; FIG. 11 is a diagram illustrating a subroutine flow describing individual detection processing according to the second embodiment;

This embodiment will be described in detail with reference to the drawings. In addition, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated.

<Embodiment 1>
FIG. 1 is a diagram illustrating the configuration of a semiconductor device based on Embodiment 1. FIG.

1, the semiconductor device according to the first embodiment includes amplifiers AP1, AP2, equalizer circuits EQA, EQB, a controller 10, a comparator CP, a resistance element RA, and a path switching circuit 20. .

The controller 10 includes a switch control controller 12 , a decision circuit 13 and a register 14 .

The switch controller 12 switches the path of the path switching circuit 20 between normal operation and test operation. Register 14 stores the output from comparator CP. The determination circuit 13 determines abnormality based on the information registered in the register 14 .

The switch control controller 12 controls the switches of the equalizer circuits EQA and EQB for various tests according to instructions from the determination circuit 13 .

The resistance element RA is provided to pull up one input node of the comparator CP.

The equalizer circuits EQA and EQB based on the first embodiment have the same configuration, and are adjusted using both the equalizer circuits EQA and EQB during normal operation. The equalizer circuits EQA and EQB are connected to the comparator CP so as to compare the output signals with each other during the test operation.

Amplifier AP1 includes P-channel MOS transistors PT1 and PT2, resistance elements R1 and R2, and a current source I1.

Current source I1 is connected to node N0.

P-channel MOS transistor PT1 is connected between nodes N0 and N1, and receives differential input signal POS at its gate.

P-channel MOS transistor PT2 is connected between nodes N0 and N2, and receives differential input signal NEG at its gate.

Resistance element R1 is connected between node N1 and ground voltage GND.

Resistance element R2 is connected between node N2 and ground voltage GND.

P-channel MOS transistor PT2 and resistance element R2 are connected in series between node N0 and ground voltage GND in parallel with P-channel MOS transistor PT1 and resistance element R1. The differential input signal POS and the differential input signal NEG have a complementary relationship.

The amplifier AP1 receives the differential input signals POS and NEG, amplifies them to a predetermined voltage level, and outputs them to the equalizer circuits EQA and EQB.

The equalizer circuits EQA and EQB correct the frequency characteristics according to the resistance values of the resistive elements according to the inputs of the differential input signals POS and NEG.

In this example, a 4-bit adjustment function is provided as the resistance value of the resistance element.

Specifically, it is possible to adjust the resistance value of the resistance element in 16 stages.

Equalizer circuit EQA includes current sources IA, IB, capacitor CA, adjustment switch SWA, P-channel MOS transistors XA, YA, and resistance elements R5, R6.

Current source IA is connected to node NA0. P-channel MOS transistor XA is connected between nodes NA0 and NA2, and has its gate connected to output node N1 of amplifier AP1.

Current source IB is connected to node NA1. P-channel MOS transistor YA is connected between nodes NA1 and NA3, and has its gate connected to output node N2 of amplifier AP1.

Capacitor CA is connected between node NA0 and node NA1.

Adjustment switch SWA is connected between node NA0 and node NA1.

The adjustment switch SWA includes resistive elements RA1-RA4 and switches ST1-ST4. As an example, the switch controller 12 controls conduction/non-conduction of the switches ST1 to ST4.

Resistance element RA1 and switch ST1 are connected in series between node NA0 and node NA1. Resistance element RA2 and switch ST2 are connected in series between node NA0 and node NA1. Resistance element RA3 and switch ST3 are connected in series between node NA0 and node NA1. Resistance element RA4 and switch ST4 are connected in series between node NA0 and node NA1.

In this example, the switch controller 12 controls the switches ST1 to ST4 based on a 4-bit selection signal. Specifically, the switch ST1 conducts when the first bit of the selection signal is at "H" level. When the second bit of the selection signal is at "H" level, switch ST2 is turned on. When the 3rd bit of the selection signal is at "H" level, the switch ST3 is turned on. When the 4th bit of the selection signal is at "H" level, the switch ST4 is turned on.

The resistance value of resistance element RA1 is set to be twice the resistance value of resistance element RA2. The resistance value of the resistance element RA2 is set to twice the resistance value of the resistance element RA3. The resistance element RA3 is set to twice the resistance value of the resistance element RA4.

It is possible to adjust the resistance value of the combined resistance of the resistance elements RA1-RA4 based on the combination of the conductive states of the switches ST1-ST4. This example shows a case where the resistance value can be adjusted in 16 steps based on a 4-bit selection signal.

Equalizer circuit EQB includes current sources IC, ID, capacitor CB, adjustment switch SWB, P-channel MOS transistors XB, YB, and resistance elements R7, R8.

The adjustment switch SWB includes resistance elements RB1-RB4 and switches ST5-ST8.

Current source IC is connected to node NB0. P-channel MOS transistor XB is connected between nodes NB0 and NB2, and has its gate connected to output node N1 of amplifier AP1.

Current source ID is connected to node NB1. P-channel MOS transistor YB is connected between nodes NB1 and NB3, and has its gate connected to output node N2 of amplifier AP1.

Capacitor CB is connected between nodes NB0 and NB1.

Adjustment switch SWB is connected between node NB0 and node NB1.

The adjustment switch SWB includes resistance elements RB1-RB4 and switches ST5-ST8. As an example, the switch controller 12 controls conduction/non-conduction of the switches ST5 to ST8.

Resistance element RB1 and switch ST5 are connected in series between node NB0 and node NB1. Resistance element RB2 and switch ST6 are connected in series between node NB0 and node NB1. Resistance element RB3 and switch ST7 are connected in series between node NB0 and node B1. Resistance element RB4 and switch ST8 are connected in series between node NB0 and node B1.

In this example, the switch controller 12 controls the switches ST5-ST8 based on a 4-bit selection signal. Specifically, the switch ST5 conducts when the first bit of the selection signal is at "H" level. If the second bit of the selection signal is at "H" level, switch ST6 is turned on. When the 3rd bit of the selection signal is at "H" level, the switch ST7 is turned on. When the 4th bit of the selection signal is at "H" level, the switch ST8 is turned on.

The resistance value of the resistance element RB1 is set to twice the resistance value of the resistance element RB2. The resistance value of the resistance element RB2 is set to twice the resistance value of the resistance element RB3. The resistance value of the resistance element RB3 is set to twice the resistance value of the resistance element RB4.

It is possible to adjust the resistance value of the combined resistance of the resistance elements RB1-RB4 based on the combination of the switches ST5-ST8. This example shows a case where the resistance value can be adjusted in 16 stages based on a 4-bit selection signal.

Amplifier AP2 includes P-channel MOS transistors PT3 and PT4, resistance elements R3 and R4, and a current source I2.

P-channel MOS transistor PT3 and resistance element R3 are connected in series between current source I2 and ground voltage GND.

P-channel MOS transistor PT4 and resistance element R4 are connected in series between current source I2 and ground voltage GND in parallel with P-channel MOS transistor PT3 and resistance element R3.

The gate of P-channel MOS transistor PT3 is connected to equalizer circuits EQA and EQB via path switching circuit 20. FIG.

The gate of P-channel MOS transistor PT4 is connected to equalizer circuits EQA and EQB via path switching circuit 20. FIG.

The path switching circuit 20 switches connections between the equalizer circuits EQA and EQB, the amplifier AP2 and the comparator CP.

Specifically, the path switching circuit 20 connects the amplifier AP2 and the equalizer circuits EQA and EQB during normal operation. Specifically, the gate of P-channel MOS transistor PT3 is connected to output node NA2 of equalizer circuit EQA. Further, the gate of P-channel MOS transistor PT4 is connected to output node NA3 of equalizer circuit EQA.

The gate of P-channel MOS transistor PT3 is connected to output node NB2 of equalizer circuit EQB. Further, the gate of P-channel MOS transistor PT4 is connected to output node NB3 of equalizer circuit EQB.

The path switching circuit 20 connects the equalizer circuits EQA and EQB and the comparator CP during the test operation. Specifically, one and the other input nodes of the comparator CP are connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively.

The amplifier AP2 receives the input of the output signal after frequency characteristic correction by the equalizer circuits EQA and EQB, amplifies it to a predetermined voltage level, and outputs it.

FIG. 2 is a diagram illustrating the configuration of the semiconductor device during normal operation according to the first embodiment.

Referring to FIG. 2, switch controller 12 controls path switching circuit 20 to switch the signal path.

Specifically, the path switching circuit 20 connects the amplifier AP2 and the equalizer circuits EQA and EQB. Specifically, the gate of P-channel MOS transistor PT3 is connected to output node NA2 of equalizer circuit EQA. Further, the gate of P-channel MOS transistor PT4 is connected to output node NA3 of equalizer circuit EQA.

The gate of P-channel MOS transistor PT3 is connected to output node NB2 of equalizer circuit EQB. Further, the gate of P-channel MOS transistor PT4 is connected to output node NB3 of equalizer circuit EQB.

FIG. 3 is a diagram illustrating the configuration of the semiconductor device during test operation according to the first embodiment.

Referring to FIG. 3, switch controller 12 controls path switching circuit 20 to switch the signal path.

Specifically, the path switching circuit 20 connects the equalizer circuits EQA and EQB and the comparator CP. Specifically, one and the other input nodes of the comparator CP are connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively.

The comparator CP is connected to output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result.

In this example, the presence or absence of abnormality in the adjustment function is determined by comparing the output signals based on the adjustment function of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB.

For example, when the voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB, it outputs "H" level as the determination signal.

On the other hand, when the voltage of output node NA3 of equalizer circuit EQA is lower than the voltage of output node NB3 of equalizer circuit EQB, it outputs "L" level as a determination signal.

In this example, a pull-up resistor RA is connected to one input node of the comparator CP.

If the output signals based on the adjustment functions of the adjustment switches SWA and SWB are at the same voltage level, the pull-up resistor RA causes the voltage at the output node NA3 of the equalizer circuit EQA to be higher than the voltage at the output node NB3 of the equalizer circuit EQB. get higher

Therefore, the determination signal of "H" level is output to the register 14. FIG.

If the output signals based on the adjustment functions of the adjustment switches SWA and SWB are not at the same voltage level and the voltage at the output node NA3 of the equalizer circuit EQA is lower than the voltage at the output node NB3 of the equalizer circuit EQB, the determination signal is "L". Output the level to the register 14 .

By performing this operation in order with respect to the adjustment switches SWA and SWB, it is possible to determine whether there is an abnormality in the adjustment function.

4A and 4B are diagrams for explaining the results of the test operation of the semiconductor device according to the first embodiment. FIG.

Referring to FIG. 4, four patterns of tests T1 to T4 are shown.

First, the case where the equalizer circuits EQA and EQB are operating normally will be described.

Specifically, in test T1, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 0V.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above.

As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above.

As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 0V and 7.5V, respectively. The voltage of the output node NA3 of the equalizer circuit EQA is lower than the voltage of the output node NB3 of the equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "L" level as the determination signal based on the comparison result.

Next, the case where equalizer circuit EQA has an "H" level stuck fault will be described. A "H" level stuck failure refers to a state in which the switch of the adjusting switch SWA fails and is always conducting.

In test T1, all the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

The voltage of the output node NA3 of the equalizer circuit EQA in that case is set to 7.5V because of the "H" level stuck failure. The voltage of the output node NB3 of the equalizer circuit EQB is set to 0V. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above. As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

On the other hand, the voltage of the output node NA3 of the equalizer circuit EQA is set to 7.5V because it has an "H" level stuck fault. The voltage of the output node NB3 of the equalizer circuit EQB is set to 7.5V. In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above. As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

Therefore, the test results of the adjustment switches of the equalizer circuits EQA and EQB in the normal state differ from the test results of the adjustment switches of the equalizer circuit EQA having the "H" level stuck failure. Thereby, it is determined that at least one of the equalizer circuits EQA and EQB is abnormal.

Next, the case where equalizer circuit EQB has an "L" level stuck fault will be described. A "L" level stuck fault refers to a state in which the switch of the adjustment switch SWB is faulty and is always in a non-conducting state.

In test T1, all the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuit EQA are set to 0V. The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a determination signal based on the comparison result. In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above. As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In this case, the voltage of output node NA3 of equalizer circuit EQA is set to 7.5V. Also, the equalizer circuit EQB is set to 0V because it has an "L" level stuck fault. The voltage of the output node NB3 of the equalizer circuit EQB is set to 0V.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

In that case, the voltage of the output node NA3 of the equalizer circuit EQA is set to 0V. In addition, the voltage of output node NB3 of equalizer circuit EQB is set to 0V because it has an "L" level stuck failure. In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above. As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

Therefore, the test result of the adjustment switch of the equalizer circuits EQA and EQB in the normal state differs from the test result of the adjustment switch of the equalizer circuit EQB having the "L" level stuck failure. Thereby, it is determined that at least one of the equalizer circuits EQA and EQB is abnormal.

FIG. 5 is a diagram illustrating the flow during test operation of the semiconductor device according to the first embodiment.

Referring to FIG. 5, the semiconductor device switches to the path with comparator CP (step S2).
Specifically, the determination circuit 13 instructs the switch controller 12 during the test operation. The switch control controller 12 instructs the path switching circuit 20 to connect the equalizer circuits EQA and EQB and the comparator CP. One and the other input nodes of comparator CP are connected to output nodes NA3 and NB3 of equalizer circuits EQA and EQB, respectively.

Next, the semiconductor device sets the switch (step S4).

Specifically, the determination circuit 13 instructs the switch controller 12 during the test operation. The switch control controller 12 sets the adjustment switches SWA and SWB. First, all the adjustment switches SWA and SWB are set to OFF.

Next, the semiconductor device registers the comparison result (step S6).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

In this example, the register 14 registers the determination signal corresponding to each switch combination of the adjustment switches SWA and SWB.

Next, the semiconductor device determines whether or not all combinations have been checked (step S8). The determination circuit 13 determines whether or not all switch combinations have been instructed to the switch controller 12 .

In step S8, when the semiconductor device determines that all combinations have been checked (YES in step S8), it executes determination processing based on the result (step S10). When determining that all switch combinations have been instructed to the switch controller 12 , the determination circuit 13 executes determination processing based on the information registered in the register 14 .

Then, the semiconductor device ends the processing (END).

On the other hand, if the semiconductor device determines in step S8 that all the combinations have not been ticked, it returns to step S4 and sets the switch.

If the determination circuit 13 determines that all switch combinations have not been instructed to the switch controller 12 , the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 sets the switch combination of the adjustment switches SWA and SWB. Then, the above processing is repeated.

Through this processing, the determination circuit 13 determines that at least one of the equalizer circuits EQA and EQB is abnormal.

Also, by providing the equalizer circuits EQA and EQB in parallel, they can be used as one equalizer circuit EQA and EQB during normal operation, and can be compared with each other during test operation to determine abnormality. Therefore, it is possible to greatly reduce the circuit area without providing a replica circuit for test operation.

<Embodiment 2>
FIG. 6 is a diagram illustrating the configuration of a semiconductor device according to Embodiment 2. FIG.

Referring to FIG. 6, the semiconductor device according to the second embodiment differs from the configuration of the semiconductor device according to the first embodiment in that a switching circuit SWD for pull-up resistor RA is further provided.

Since other configurations are the same as those described in the first embodiment, detailed description thereof will not be repeated.

The switching circuit SWD can switch the connection relationship of the pull-up resistor RA. Specifically, the connection relationship between the pull-up resistor RA and the input node of the comparator CP is switched.

In the first embodiment described above, in the case of an "L" level stuck failure in the equalizer circuit EQB, the output result is the same as in the case of an "H" level stuck failure in the equalizer circuit EQA. It was not possible to determine which one was the fault.

However, it is possible to determine which of the equalizer circuits EQA and EQB has failed by switching using the switching circuit SWD.

Further, although it was not possible to determine which portion of the adjustment function is defective, the semiconductor device according to the second embodiment can further determine which portion of the adjustment function is defective. .

FIG. 7 is a diagram for explaining the result of test operation of the semiconductor device according to the second embodiment.

A case of executing four patterns of tests T1 to T4 is shown.

A case where equalizer circuits EQA and EQB are operating normally will be described with reference to FIG. In this example, the case where the pull-up resistor RA is connected to the other side of the input node of the comparator CP will be described.

Specifically, in test T1, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 0V.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above.

As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above.

As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 0V and 7.5V, respectively. The voltage of the output node NA3 of the equalizer circuit EQA is lower than the voltage of the output node NB3 of the equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "L" level as the determination signal based on the comparison result.

Next, the case where equalizer circuit EQA has an "H" level stuck fault will be described. A "H" level stuck failure refers to a state in which the switch of the adjusting switch SWA fails and is always conducting.

A "H" level stuck failure refers to a state in which the switch of the adjusting switch SWA fails and is always conducting.

In test T1, all the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

The voltage of the output node NA3 of the equalizer circuit EQA in that case is set to 7.5V because of the "H" level stuck failure. The voltage of the output node NB3 of the equalizer circuit EQB is set to 0V. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the pull-up resistor RA makes the voltage at the output node B3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above. As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

On the other hand, the voltage of the output node NA3 of the equalizer circuit EQA is set to 7.5V because it has an "H" level stuck fault. The voltage of the output node NB3 of the equalizer circuit EQB is set to 7.5V. In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above. As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

Therefore, the test results of the adjustment switches of the equalizer circuits EQA and EQB in the normal state differ from the test results of the adjustment switches of the equalizer circuit EQA having the "H" level stuck failure. Thereby, it is determined that at least one of the equalizer circuits EQA and EQB is abnormal.

A case where equalizer circuit EQB has an "L" level stuck fault will be described with reference to FIG. A "L" level stuck fault refers to a state in which the switch of the adjustment switch SWB is faulty and is always in a non-conducting state.

In test T1, all the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned off.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuit EQA are set to 0V. The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above. As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

In test T2, all of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on.

In this case, the voltage of output node NA3 of equalizer circuit EQA is set to 7.5V. Equalizer circuit EQB has an "L" level stuck failure, so that the voltage of output node NB3 is set to 0V.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T3, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned on, and all switches SWB are turned off.

In this case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 7.5V and 0V, respectively. The voltage of output node NA3 of equalizer circuit EQA is higher than the voltage of output node NB3 of equalizer circuit EQB.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result. In this case, the register 14 registers "H" level as the determination signal based on the comparison result.

In test T4, the adjustment switches SWA of the equalizer circuits EQA and EQB are turned off, and all switches SWB are turned on.

In that case, the voltage of the output node NA3 of the equalizer circuit EQA is set to 0V. In addition, the voltage of output node NB3 of equalizer circuit EQB is set to 0V because it has an "L" level stuck failure. In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above. As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

Therefore, the test result of the adjustment switch of the equalizer circuits EQA and EQB in the normal state differs from the test result of the adjustment switch of the equalizer circuit EQB having the "L" level stuck failure. Thereby, it is determined that at least one of the equalizer circuits EQA and EQB is abnormal.

In the above-described first embodiment, the case where the "L" level stack failure of the equalizer circuit EQB results in the same output result as the "H" level stack failure of the equalizer circuit EQA has been described. , when abnormality is determined in the test T1 by switching using the switching circuit SWD, it is possible to determine as an "H" level stuck failure of the equalizer circuit EQA. Further, when an abnormality is determined in the test T2 by switching using the switching circuit SWD, it can be determined as an "L" level stuck failure of the equalizer circuit EQB.

It is possible to determine which of the equalizer circuits EQA and EQB has a failure and whether it is an "H" level failure or an "L" level failure.

Next, an individual bit determination method will be described.

FIG. 8 is a diagram for explaining the result of another test operation of the semiconductor device according to the second embodiment.

A case where the equalizer circuits EQA and EQB are operating normally will be described with reference to FIG. In this example, the case where the pull-up resistor RA is connected to the other side of the input node of the comparator CP will be described.

In this example, one bit is tested.

Specifically, one bit is tested.

In the test TA1, the switch corresponding to one bit of the adjustment switches SWA, SWB of the equalizer circuits EQA, EQB is turned on. In this example, switches ST2 and ST6 corresponding to the second bit are turned on.

In that case, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 1V.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above.

As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In the test TA2, the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB are turned on. In this example, the switches ST2 and ST6 corresponding to the second bit are turned on.

The difference from the previous point is that the connection destination of the pull-up resistor RA is connected to the output node side of the equalizer circuit EQB.

In this case, the pull-up resistor RA makes the voltage at the output node NB3 of the equalizer circuit EQB higher than the voltage at the output node NA3 of the equalizer circuit EQA, as described above.

As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

Therefore, when the same bit is tested by turning on the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB, the voltage of the node to which the pull-up resistor RA is connected increases if the operation is normal. The determination signal based on the comparison result is switched between "H" level and "L" level.

Next, the case where the second bit of the equalizer circuit EQA has an "L" level stuck fault will be described. A "L" level stuck fault refers to a state in which the adjustment switch SWA is always non-conducting due to a fault in the switch.

In the test TA1, the switch corresponding to one bit of the adjustment switches SWA, SWB of the equalizer circuits EQA, EQB is turned on. In this example, switches ST2 and ST6 corresponding to the second bit are turned on.

Since the 2nd bit of the adjustment switch SWA has a stuck failure of "L" level, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 0V and 1V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, as described above, the voltage at the output node NB3 of the equalizer circuit EQB is higher than the voltage at the output node NA3 of the equalizer circuit EQA.

As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

In the test TA2, the switch corresponding to one bit of the adjustment switches SWA, SWB of the equalizer circuits EQA, EQB is turned on. In this example, switches ST2 and ST6 corresponding to the second bit are turned on.

In this case, as described above, the voltage at the output node NB3 of the equalizer circuit EQB is higher than the voltage at the output node NA3 of the equalizer circuit EQA.

As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

Therefore, when testing the same bit by turning on the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB, if there is an "L" level stuck fault, the connection destination of the pull-up resistor RA is determined. is switched, the decision signal based on the comparison result remains the same and is not replaced.

By doing this one by one for each bit, it is possible to determine which bit has an "L" level stuck fault.

A case where the second bit of equalizer circuit EQA has an "H" level stuck fault will be described with reference to FIG. 8B. "H" level stuck failure refers to a state in which the switch of the adjustment switch SWA fails and is always conductive.

Here, all of the adjustment switches SWA of the equalizer circuit EQA on the faulty side are turned off. The adjustment switches SWB of the equalizer circuit EQB on the normal side are turned on one by one.

In test TB1, all switches of the adjustment switches SWA of the equalizer circuit EQA are turned off. The switch ST5 of the adjustment switch SWB of the equalizer circuit EQB is turned on.

Since the 2nd bit of the adjustment switch SWA has a stuck failure of "H" level, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 1V and 0.5V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, as described above, the voltage at the output node NA3 of the equalizer circuit EQA becomes higher than the voltage at the output node NB3 of the equalizer circuit EQB.

As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test TB2, all switches of the adjustment switches SWA of the equalizer circuit EQA are turned off. The switch ST6 of the adjustment switch SWB of the equalizer circuit EQB is turned on.

Since the 2nd bit of the adjustment switch SWA has a stuck failure of "H" level, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 1V and 1V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the pull-up resistor RA makes the voltage at the output node NA3 of the equalizer circuit EQA higher than the voltage at the output node NB3 of the equalizer circuit EQB, as described above. As a result, the register 14 registers "H" level as the determination signal based on the comparison result.

In test TB3, all switches of the adjustment switches SWA of the equalizer circuit EQA are turned off. The switch ST7 of the adjustment switch SWB of the equalizer circuit EQB is turned on.

Since the 2nd bit of the adjustment switch SWA has a stuck failure of "H" level, the voltages of the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB are set to 1V and 2V, respectively.

The comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs to the register 14 a decision signal based on the comparison result.

In this case, the voltage of the output node NB3 of the equalizer circuit EQB becomes higher than the voltage of the output node NA3 of the equalizer circuit EQA. As a result, the register 14 registers "L" level as the determination signal based on the comparison result.

At this point, it is determined that the determination signal of the comparison result has been switched. That is, it is determined that the previous bit has an "H" level stuck fault.

FIG. 9 is a diagram illustrating the flow during test operation of the semiconductor device according to the second embodiment.

Referring to FIG. 9, the semiconductor device switches to the path with comparator CP (step S2).
Specifically, the determination circuit 13 instructs the switch controller 12 during the test operation. The switch control controller 12 instructs the path switching circuit 20 to connect the equalizer circuits EQA and EQB and the comparator CP. One and the other input nodes of comparator CP are connected to output nodes NA3 and NB3 of equalizer circuits EQA and EQB, respectively.

Next, the semiconductor device sets the connection of the pull-up resistor (step S3).

Specifically, the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 instructs the switching circuit SWD to switch the connection between the pull-up resistor RA and the equalizer circuits EQA and EQB. The switching circuit SWD connects the output node NA3 of the equalizer circuit EQA and the pull-up resistor RA.

Next, the semiconductor device sets the switch (step S4).

Specifically, the determination circuit 13 instructs the switch controller 12 during the test operation. The switch controller 12 sets the adjustment switches SWA and SWB in the same manner as described in the first embodiment. First, all the adjustment switches SWA and SWB are set to OFF.

Next, the semiconductor device registers the comparison result (step S6).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

In this example, the register 14 registers the determination signal corresponding to each switch combination of the adjustment switches SWA and SWB.

Next, the semiconductor device determines whether or not all combinations have been checked (step S8). The determination circuit 13 determines whether or not all switch combinations have been instructed to the switch controller 12 .

If the semiconductor device determines in step S8 that all the combinations have not been ticked (NO in step S8), it returns to step S4 and sets the switch. If the determination circuit 13 determines that all switch combinations have not been instructed to the switch controller 12 , the determination circuit 13 instructs the switch controller 12 . Then, the switch controller 12 sets the switch combination of the adjusting switches SWA and SWB. Then, the above processing is repeated.

On the other hand, when the semiconductor device determines in step S8 that all combinations have been checked (YES in step S8), it executes determination processing based on the result (step S10). Specifically, when determining that all switch combinations have been instructed to the switch controller 12 , the determination circuit 13 executes determination processing based on the information registered in the register 14 . It is determined that at least one of the equalizer circuits EQA and EQB is abnormal according to the determination signal based on the comparison result registered in the register 14 .

At step S12, the semiconductor device determines whether or not there is an abnormality (step S12). If it is determined in step S12 that at least one of the equalizer circuits EQA and EQB is normal (NO in step S12), the semiconductor device ends the process (end).

On the other hand, when it is determined in step S12 that at least one of the equalizer circuits EQA and EQB is abnormal (YES in step S12), the semiconductor device executes a process of identifying the abnormal equalizer circuit.

The semiconductor device switches the connection of the pull-up resistor (step S13).

Specifically, the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 instructs the switching circuit SWD to switch the connection between the pull-up resistor RA and the equalizer circuits EQA and EQB. The switching circuit SWD connects the output node NB3 of the equalizer circuit EQB and the pull-up resistor RA.

Next, the semiconductor device sets the switch (step S14).

Specifically, the determination circuit 13 instructs the switch control controller 12 during the test operation. The switch controller 12 sets the adjustment switches SWA and SWB in the same manner as described in the first embodiment. First, all the adjustment switches SWA and SWB are set to OFF.

Next, the semiconductor device registers the comparison result (step S16).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

In this example, the register 14 registers the determination signal corresponding to each switch combination of the adjustment switches SWA and SWB.

Next, the semiconductor device determines whether or not all combinations have been checked (step S18). The determination circuit 13 determines whether or not all switch combinations have been instructed to the switch controller 12 .

If the semiconductor device determines in step S18 that all the combinations have not been ticked (NO in step S18), it returns to step S14 and sets the switch. If the determination circuit 13 determines that all switch combinations have not been instructed to the switch controller 12 , the determination circuit 13 instructs the switch controller 12 . Then, the switch controller 12 sets the switch combination of the adjusting switches SWA and SWB. Then, the above processing is repeated.

On the other hand, when the semiconductor device determines in step S18 that all combinations have been checked (YES in step S18), it executes determination processing based on the result (step S20). Specifically, when determining that all switch combinations have been instructed to the switch controller 12 , the determination circuit 13 executes determination processing based on the information registered in the register 14 . According to the determination signal based on the comparison result registered in the register 14, it is determined which of the equalizer circuits EQA and EQB is abnormal, and whether it is an "H" level stack abnormality or an "L" level stack abnormality.

Next, in step S22, the semiconductor device performs a process of individually detecting which bit has an abnormality with respect to the specified abnormality (step S24). Processing for individually detecting anomalies will be described later.

Then, the semiconductor device ends the processing (END).

FIG. 10 is a diagram illustrating a subroutine flow describing individual detection processing according to the second embodiment.

Referring to FIG. 10, the semiconductor device determines whether or not there is an "H" level stuck failure (step S30). Specifically, determination circuit 13 determines which of "H" level and "L" level of equalizer circuits EQA and EQB is abnormal based on the above determination result.

When the semiconductor device determines that the equalizer circuit EQA or EQB is stuck at "H" level, the process proceeds to step S32. On the other hand, when the semiconductor device determines that the equalizer circuit EQA or EQB is stuck at "L" level, the process proceeds to step S50.

The semiconductor device turns on the same bit switches of the equalizer circuits EQA and EQB (step S50).

Specifically, the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 turns on the switch corresponding to one bit of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB. In this example, the switches ST1 and ST5 corresponding to the 1st bit are turned on.

Next, the semiconductor device registers the comparison result (step S52).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

Next, the semiconductor device sets the connection of the pull-up resistor (step S54).

Specifically, the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 instructs the switching circuit SWD to switch the connection between the pull-up resistor RA and the equalizer circuits EQA and EQB. The switching circuit SWD connects the output node NB3 of the equalizer circuit EQB and the pull-up resistor RB when the output node NA3 of the equalizer circuit EQA and the pull-up resistor RA are connected.

Next, the semiconductor device registers the comparison result (step S56).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

Next, the semiconductor device determines whether or not the comparison results have been changed (step S60). The determination circuit 13 determines whether or not the comparison results have changed based on the information registered in the register 14 .

If the semiconductor device determines in step S60 that the comparison result has been changed (YES in step S60), it determines that the bit is normal, and proceeds to step S64.

At step S64, the semiconductor device turns on the next same bit switch of the equalizer circuits EQA and EQB (step S64).

Specifically, the determination circuit 13 instructs the switch controller 12 . The switch control controller 12 turns on the switch corresponding to one bit of the adjustment switches SWA and SWB of the equalizer circuits EQA and EQB. In this example, switches ST2 and ST6 corresponding to the second bit are turned on.

Next, the semiconductor device registers the comparison result (step S56).

Subsequent processing is the same as described above, and detailed description thereof will not be repeated.

When the semiconductor device determines in step S60 that the comparison results have not been changed (NO in step S60), it executes determination processing (step S62).

Specifically, based on the information registered in the register 14, the decision circuit 13 decides that there is an "L" level stuck fault with respect to bits for which there is no comparison result.

Then, the processing ends (return).

On the other hand, if the semiconductor device determines in step S30 that there is an "H" level stuck failure (YES in step S30), it switches off the failed equalizer circuit (step S32). The determination circuit 13 instructs the switch control controller 12 . The switch control controller 12, for example, turns off all the switches of the adjustment switches SWA of the equalizer circuit EQA on the failed side.

Next, the semiconductor device turns on one switch of the equalizer circuit on the normal side (step S34). The determination circuit 13 instructs the switch control controller 12 . The switch control controller 12, for example, turns on one of the adjustment switches SWB of the equalizer circuit EQB on the normal side. The switch ST5 of the adjustment switch SWB of the equalizer circuit EQB is turned on.

Next, the semiconductor device registers the comparison result (step S36).

Specifically, the comparator CP is connected to the output nodes NA3 and NB3 of the equalizer circuits EQA and EQB, respectively, compares the voltage difference between the output nodes, and outputs a determination signal based on the comparison result to the register 14 . A register 14 registers a determination signal based on the comparison result.

Next, the semiconductor device determines whether or not the comparison results have been changed (step S38). The determination circuit 13 determines whether or not the comparison results have changed based on the information registered in the register 14 .

If the semiconductor device determines in step S38 that the comparison results have not changed (NO in step S38), then it turns on the next switch of the equalizer circuit on the normal side (step S42). The determination circuit 13 instructs the switch control controller 12 . The switch control controller 12 turns on the switch ST6 of the adjustment switch SWB of the equalizer circuit EQB in this example.

Next, the semiconductor device registers the comparison result (step S36).

Subsequent processing is the same as described above, and detailed description thereof will not be repeated.

If the semiconductor device determines in step S38 that the comparison results have been changed (YES in step S38), it performs determination processing (step S40).

Specifically, based on the information registered in the register 14, the determination circuit 13 determines that there is an "H" level stuck fault in the bit immediately preceding the bit whose comparison result is changed.

Then, the processing ends (return).

By this processing, it is possible to determine which of the equalizer circuits EQA and EQB is abnormal, and to determine which bit is "H" level stuck or "L" level stuck.

Although the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the embodiments and can be variously modified without departing from the gist thereof.

10 controller, 12 switch control controller, 13 determination circuit, 14 register, 20 path switching circuit.

Claims (4)

Equipped with an equalizer circuit that corrects attenuated frequency components of a differential input signal input via a transmission line,
The equalizer circuit is
a first equalizer unit including a plurality of first switches capable of adjusting resistance values in a plurality of stages with respect to the differential input signal;
a second equalizer unit including a plurality of second switches capable of adjusting resistance values in a plurality of steps with respect to the differential input signal;
a comparator that compares the differential output signal of the first equalizer unit and the differential output signal of the second equalizer unit;
a first path for connecting the output of the first equalizer unit and the output of the second equalizer unit during normal operation, and connecting the output of the first equalizer unit and the output of the second equalizer unit together during testing a path switching unit for switching a second path for connecting to the comparator for comparison;
and a determination circuit that detects a failure based on the comparison result of the comparator. 2. The semiconductor device according to claim 1, wherein said equalizer circuit further includes a pull-up resistance element corresponding to one input node of said comparator. 3. The semiconductor device according to claim 2, wherein said equalizer circuit further includes a switch for switching electrical connection between one and the other input node of said comparator and said pull-up resistance element. 2. The semiconductor device according to claim 1, wherein said determination circuit controls conduction/non-conduction of said plurality of first switches and said plurality of second switches to detect a stuck failure of said first or second equalizer unit.

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