JP7187930B2 - Velocity estimation circuit, optical transmitter, optical receiver and velocity estimation method - Google Patents

Description

The present invention relates to a speed estimation circuit and speed estimation method, and more particularly to a speed estimation circuit and speed estimation method for estimating the speed of data from data.

2. Description of the Related Art Optical transceivers are known that realize optical fiber transmission using a light-emitting element such as a laser diode, a light-receiving element such as a photodiode, and an associated electrical circuit. In general optical transceivers, parameters that define the operation of electric circuits are often set based on the transmission speed of data to be transmitted and received (data speed). Data rate information may be obtained from the recovered clock in the optical transceiver. In relation to the present invention, Patent Document 1 describes a clock switching circuit that includes a frequency divider that divides a clock signal extracted from an optical signal.

JP 2011-176590 A

However, there are cases where information on the transmission speed cannot be obtained in the optical transceiver. For example, an optical transceiver without a clock recovery circuit cannot obtain information on the transmission speed. Therefore, in such an optical transceiver, it is not always possible to appropriately set the parameters of the electrical circuits of the optical transmitter and optical receiver included in the optical transceiver. If the information on the transmission speed cannot be obtained from the clock signal, it is possible to set the electric circuit to match the highest possible data speed. The noise-to-noise ratio can deteriorate. Therefore, there is a demand for a technique for obtaining information on the data transmission speed even when the information on the transmission speed cannot be obtained from the clock signal.

(Purpose of Invention)
SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of estimating the data transmission speed.

The speed estimating circuit of the present invention includes a frequency dividing circuit that outputs frequency-divided data obtained by frequency-dividing input data, and one of the number of rises and the number of times of fall of a code included in the frequency-divided data within a predetermined period. and an arithmetic circuit for obtaining an estimated speed, which is the estimated speed of the data, based on the distribution of .

The speed estimation method of the present invention outputs frequency-divided data obtained by frequency-dividing input data. to obtain an estimated velocity, which is the estimated velocity of the data.

The present invention makes it possible to estimate the transmission rate of data.

2 is a block diagram showing a configuration example of a speed estimation circuit 100 according to the first embodiment; FIG. 2 is a block diagram showing a configuration example of a frequency dividing circuit 101; FIG. 3 is a diagram showing an example of data waveforms in the frequency dividing circuit 101. FIG. 3 is a block diagram showing another configuration example of the frequency dividing circuit 101; FIG. It is a figure explaining the number of rises of NRZ data. FIG. 3 is a diagram for explaining the distribution of 10 Gbit/s and 25 Gbit/s NRZ data and the number of rises of clocks; FIG. 10 is a diagram showing an example of measurement results of the distribution of the number of rising edges of divided 25 Gbit/s NRZ data; FIG. 10 is a diagram showing an example of measurement results of the distribution of the number of rising edges of frequency-divided 10 Gbit/s NRZ data; 2 is a block diagram showing a configuration example of an optical transceiver 10 according to a second embodiment; FIG. 4 is a flow chart showing an example of a speed estimation procedure of a speed estimation circuit 40; FIG. 13 is a diagram showing an example of the distribution of the number of rises of data before frequency division in the third embodiment; FIG. 11 is a diagram showing a measurement example of the distribution of the number of rises of data after frequency division in the third embodiment; FIG. 12 is a block diagram showing a configuration example of a speed estimation circuit 200 applicable to the third embodiment; FIG. 4 is a flow chart showing an example of a speed estimation procedure of a speed estimation circuit 200;

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a speed estimation circuit 100 according to the first embodiment of the present invention. A speed estimating circuit 100 includes a frequency dividing circuit 101 and an arithmetic circuit 102 . A frequency dividing circuit 101 outputs frequency-divided data obtained by frequency-dividing input data. Arithmetic circuit 102 obtains an estimated speed, which is the estimated data speed, based on the distribution of the rising numbers of codes included in the frequency-divided data within a predetermined period. Since the distribution of the number of rising edges of the frequency-divided data within a predetermined period depends on the data transmission speed, the speed estimating circuit 100 having such a configuration can estimate the data speed based on the distribution.

The operation of the speed estimating circuit 100 will be further described with reference to FIGS. 2 to 8. FIG. FIG. 2 is a block diagram showing a configuration example of the frequency dividing circuit 101. As shown in FIG. The frequency dividing circuit 101 includes frequency dividers 1011 , 1012 , and 1013 . Frequency dividers 1011-1013 are connected in series. Both of these frequency dividers have a division ratio of 2, which halves the speed of the input data. That is, when data DAT_0 with a speed of a [bits/second] is input to frequency divider 1011, frequency divider 1011 outputs data DAT_1 of a/2 [bits/second]. a is a positive integer. Similarly, frequency divider 1012 outputs a/4 [bit/second] data DAT_2, and frequency divider 1013 outputs a/8 [bit/second] data DAT_3. In this way, the frequency dividing circuit 101 divides the frequency of the input data DAT_0 by 8 and outputs data DAT_3 of 1/8 speed.

FIG. 3 is a diagram showing waveform examples of data DAT_0 to DAT_3 in the frequency dividing circuit 101. As shown in FIG. Data DAT_0 is an NRZ (Non Return to Zero) code. Each of the frequency dividers 1011 to 1013 divides the input data by detecting the rising edge of the input data and inverting the sign of the output data. Data DAT_0 input to frequency dividing circuit 101 having such a configuration is frequency-divided to 1/8 speed by frequency dividers 1011 to 1013 to obtain data DAT_3.

FIG. 4 is a block diagram showing another configuration example of the frequency dividing circuit 101. As shown in FIG. The frequency dividing circuit 101 includes n frequency dividers 1011-101n with a frequency dividing ratio of two. n is a natural number. Frequency dividers 1011-101n are connected in series. As a result, data DAT_n having a speed of 1/ ²ⁿ of data DAT_0 is obtained. Note that the frequency dividing ratio of the frequency dividing circuit is not limited to two. By combining frequency dividers 1011 to 101n having different frequency division ratios, the frequency divider circuit 101 having an arbitrary frequency division ratio may be configured.

The frequency dividing circuit 101 described with reference to FIGS. 2 to 4 divides the input data DAT_0. At this time, the number of rising edges included in data DAT_0 within a predetermined period also decreases according to the division ratio. For example, as shown in FIG. 3, in the data DAT_n divided n times by the 2-divider, the number of rising edges of the data within a predetermined period is approximately 1/2 ⁿ of the data DAT_0. Therefore, by counting the number of rising edges of the data obtained by dividing the frequency of the data DAT_0, the number of rising edges included in the data DAT_0 within a predetermined period can be estimated by a low-speed circuit. Unless otherwise specified, the number of rising edges included in data within a certain period is simply referred to as "the number of rising edges".

A procedure for estimating the speed of data from the number of rises of data will be described below. FIG. 5 is a diagram for explaining the number of rising edges of NRZ data DAT_0 at a bit/second speed. In the NRZ data DAT_0 of a bit/second, the number of rising edges N0 per second becomes maximum when the bit pattern of the data is "101010...", where N0=a/2. Since the clock has a rising edge for each bit of data, the maximum number of rising edges of the NRZ data is 1/2 the number of rising edges of the data clock. N0 fluctuates depending on the mark rate and bit pattern of data DAT_0, but in the case of random patterns, the distribution when the number of rises N0 is repeatedly measured is almost constant.

FIG. 6 is a diagram illustrating an example of the distribution of the number of rises of 10 Gbit/s and 25 Gbit/s NRZ data and clocks. The horizontal axis is the number of data or clock rises per unit time (that is, frequency), and the vertical axis is the frequency of the rises. It should be noted that the vertical and horizontal axes in FIG. 6 exemplify the magnitude relationship of the values, and do not strictly indicate the difference or ratio of the values.

At each data rate, the number of rising edges of the data is lower than the clock, and if the data is in a random pattern, the number of rising edges is spread out. For example, at 10 Gbit/s, the number of rising edges of the clock coincides with the clock frequency and is at 10 GHz (10 ⁹ times/second). However, in the case of NRZ random data, the number of rises of data is distributed at frequencies lower than 10 GHz. Similarly, the number of rising edges of NRZ random data at 25 Gbit/s is also distributed in frequencies below 25 GHz.

Arithmetic circuit 102 included in speed estimating circuit 100 counts the number of rising edges of data divided by frequency dividing circuit 101 . The number of rising edges of the divided data decreases according to the division ratio. Therefore, the operation speed of the arithmetic circuit 102 when counting the number of rising edges of the frequency-divided data may be lower than the data speed before frequency division. Therefore, the arithmetic circuit 102 can count the number of rises of the frequency-divided data using a relatively low-speed circuit, and estimate the distribution of the number of rises of the data before frequency division based on the count result. Further, arithmetic circuit 102 can estimate the data rate before frequency division based on the count result, as described below.

First, the calculation of the frequency dividing ratio when the arithmetic circuit 102 counts the number of rising edges of the frequency-divided data will be described. Let a [bit/second] be the data rate before frequency division, and R be the frequency division ratio. Also, if the speed at which the arithmetic circuit 102 can count the number of rises of the frequency-divided data is k [times/second], the number of rises per second of the data at speed a [bits/second] is a/2 at maximum. Therefore, the following relationship holds.

(a/2)×(1/R)≦M (1)
Here, if a = 25 G [bits/second], k = 10000 [times/second], and R = 2 ⁿ (n is the number of stages of the frequency divider with a frequency division ratio of 2),
25×10 ⁹ ×(1/2 ⁿ )≦10000 (2)
from which it follows that n≧22. That is, by using a frequency dividing circuit in which 22 stages of frequency dividers having a frequency dividing ratio of 2 are connected in series, the arithmetic circuit 102 can reduce the number of rises of the divided 25 Gbit/sec data at a speed of 10,000 times per second or less. can be counted. Note that the frequency division ratio of the frequency division circuit 101 in equation (2) is 2 ²² =4,194,304, and the 25 Gbit/second data is divided into about 6000 bits/second. In the case of NRZ data, as described with reference to FIG. 5, the maximum number of rising edges of data of about 6000 bits/second is 1/2, which is about 3000 times/second. When the number of rises is measured repeatedly, in the case of a random pattern, the number of rises per second is distributed between 0 and 3000 times, and the frequency peaks around 1500 times near the center.

7 and 8 are diagrams showing examples of measurement results of the distribution of rising numbers of data divided by the frequency dividing circuit 101. FIG. FIG. 7 shows an example of the distribution of the number of rises counted when the number of rises of 25 Gbit/s data divided by a frequency divider with a frequency division ratio of ²²² is measured every 10 milliseconds. Histogram. Since the measurement period is 10 milliseconds, the number of rises is 1/100 of the number of rises in one second. Therefore, the number of rises measured during 10 milliseconds is distributed between 0 and 30 times. The horizontal axis in FIG. 7 indicates the number of counts per 10 milliseconds, and the vertical axis indicates the frequency of the counts. In FIG. 7, the frequency C1 in the section (class) where the number of counts is 13 to 16 times every 10 milliseconds is the highest. Assuming that the number of counts in this section is 15, it can be estimated that the number of rises per second is about 1500, which is 100 times that number. Calculating back from the number of rises, the divided data rate can be estimated to be about 6000 bits/sec. By multiplying this by the frequency ^dividing ratio of the frequency dividing circuit 101, the data rate before frequency division can be estimated to be approximately 25.1 Gbit/second.

FIG. 8 is a histogram showing an example of distribution when the number of rising edges of 10 Gbit/s data is measured every 10 milliseconds as in FIG. Dividing 10 Gbit/s data by a divide ratio of ²²² divides down to about 2400 bits/s by the same calculation as for 25 Gbit/s. Therefore, in the case of NRZ data, the maximum number of rises of data after frequency division is about 1200 times/second. When the number of rises is measured every 10 milliseconds, the distribution of the number of rises is distributed between 0 and 12 times. In FIG. 8, the frequency C2 is the highest in the section where the number of counts is 5 to 8 times. Assuming that the number of counts in this section is 7, the number of rises per second is estimated to be about 700. From this it can be estimated that the divided data rate is 2800 bits/second. Therefore, by multiplying this by the frequency dividing ratio of the frequency dividing circuit 101, it can be estimated that the data rate before frequency division is about 11.7 ^Gbits /second.

Since the interval (1-4, 5-8, 9-12, etc.) shown by the horizontal axis in FIGS. 7 and 8 has a width, the estimated value of the data rate also includes an error depending on this width. have However, in many cases, the data rate before frequency division used in a communication system is a default value that is separated to some extent. For example, even if the estimated speeds are about 25.1 Gbit/s and about 11.7 Gbit/s as described above, arithmetic circuit 102 determines that the actual data speeds are 25 Gbit/s and 10 Gbit/s, respectively. can be judged. Therefore, if the speed at which the optical transceiver to which the speed estimation circuit 100 is applied is used is a default value (for example, 25 Gbit/s and 10 Gbit/s), the accuracy of the estimated speed is The accuracy may be such that it can be determined whether or not they are close.

If we measure the number of rises every 10 milliseconds, we get a distribution based on 100 measurements every second. As the number of measurements to obtain one distribution increases, the data rate can be estimated more accurately, but the time required to obtain the distribution also increases. 7 and 8, the narrower the number of rises, the more accurately the distribution can be expressed. However, in order to accurately grasp the frequency distribution of each section, it is necessary to increase the number of measurements of the number of rises. Furthermore, in order to accurately estimate the data rate in a short measurement period, it is preferable that the arithmetic circuit 102 has a high counting capability. Therefore, the number of measurements may be determined in consideration of the time allowed for speed estimation, the accuracy of the estimated speed, and the counting speed of arithmetic circuit 102 .

In FIGS. 7 and 8, the data rate was estimated from the number of rising edges in the section with the highest frequency. However, the number of rises used to estimate the data rate may be determined from values based on the entire distribution (eg, median or mean number of rises). Also, in this embodiment, the data rate is estimated by counting the number of rising times. However, it is also clear that the same effect can be obtained by counting the number of trailing edges.

The speed estimating circuit 100 of the first embodiment can estimate the data speed based on the distribution of rising numbers of the frequency-divided data. Since the frequency-divided data is slower than the data before frequency division, even if the data before frequency division is high-speed, the data speed can be estimated by configuring the arithmetic circuit 102 with a low-speed circuit. For example, even if the data rate is 10 Gbit/s or more, by appropriately setting the frequency dividing ratio of the frequency dividing circuit 101, the arithmetic circuit 102 that counts the number of rises can be used as a CPU (central processing unit) and its peripheral circuits. It can be configured with a low-speed circuit composed of Further, the calculation procedure can also be realized by having the CPU execute a program. As a result, even if information about the data frequency is not directly available in the optical transceiver, the data signal processing circuit can be controlled based on the estimated data rate, and the operation of the optical transceiver can be further optimized.

(Second embodiment)
FIG. 9 is a block diagram showing a configuration example of the optical transceiver 10 according to the second embodiment of the present invention. The optical transceiver 10 includes amplifiers 11 and 12 , signal processing circuits 13 and 14 , a light emitting element 15 , a light receiving element 16 and a velocity estimation circuit 40 . The amplifier 11 amplifies the input transmission data and outputs it to the signal processing circuit 13 . The signal processing circuit 13 is a driving circuit for the light emitting element 15, and processes transmission data based on the speed of the transmission data so that the light emitting element 15 is properly driven. The light emitting element 15 is driven by transmission data to transmit an optical signal. The light emitting element 15 is, for example, a laser diode.

The light receiving element 16 converts the received optical signal into an electrical signal. The light receiving element 16 is, for example, a photodiode. The signal processing circuit 14 amplifies the electrical signal (photocurrent) output by the light receiving element and outputs reception data. The signal processing circuit 14 is, for example, a TIA (Trans-Impedance amplifier). The amplifier 12 amplifies received data output from the signal processing circuit 14 .

The speed estimating circuit 40 includes frequency dividing circuits 21 and 22 and an arithmetic circuit 30 . The frequency dividing circuits 21 and 22 have the same function as the frequency dividing circuit 101 of the speed estimation circuit 100 of the first embodiment. That is, the frequency dividing circuit 21 frequency-divides the transmission data output from the amplifier 11 and outputs the result to the arithmetic circuit 30 . The frequency dividing circuit 22 frequency-divides the reception data output from the signal processing circuit 14 and outputs the result to the arithmetic circuit 30 . The arithmetic circuit 30 includes an estimation circuit 31 and a control circuit 32 . The estimation circuit 31 estimates the respective speeds of the transmission data and the reception data according to the procedure described in the first embodiment. The control circuit 32 generates control signals for controlling the signal processing circuits 13 and 14 based on the respective estimated velocities, and outputs the control signals to the signal processing circuits 13 and 14 . For example, the control circuit 32 generates a control signal that sets the parameters of the signal processing circuit 13 so that the light emitting element 15 is preferably driven at the estimated transmission data rate. The control circuit 32 also generates a control signal that sets the parameters of the signal processing circuit 14 so that the signal processing circuit 14 preferably amplifies the electrical signal from the light emitting element 15 at the estimated rate of received data. A parameter set in the signal processing circuits 13 and 14 is, for example, the bandwidth of the signal to be processed, but is not limited to this.

FIG. 10 is a flow chart showing an example of the speed estimation procedure of the speed estimation circuit 40. As shown in FIG. The speed estimation circuit 40 frequency-divides the transmission data and the reception data to generate frequency-divided data (step S101 in FIG. 10). Equation (1) of the first embodiment can be used to determine the division ratio. Also, the frequency dividing ratio may be set in the frequency dividing circuits 21 and 22 by an external device of the optical transceiver 10 or by the user. Next, the distribution of rising numbers of each frequency-divided data is measured (step S102), and the data speed (speed of transmission data and reception data) is estimated based on the measured distribution (step S103). The data rate estimation procedure of the first embodiment can be used for the procedures of steps S102 and S103. After that, the speed estimation circuit 40 controls the signal processing circuits 13 and 14 based on the estimated speeds of the transmission data and the reception data (step S104).

The optical transceiver 10 having such a configuration can estimate the respective speeds of the transmitted data and the received data from the transmitted data and the received data. Therefore, even if information about the speed of the transmission data and the reception data cannot be obtained from another source, the signal processing circuits 13 and 14 can be operated under more favorable conditions according to the respective speeds of the transmission data and the reception data.

The estimation circuit 31 also counts the number of rises of the frequency-divided transmission data and reception data, and estimates the respective speeds of the transmission data and reception data based on the distribution thereof. Therefore, the estimating circuit 31 can be composed of a circuit that is slower than the transmission data and the reception data. Therefore, the estimating circuit 31 can be composed of a low-speed circuit such as a CPU and its peripheral circuits.

(Third embodiment)
As a third embodiment, a case where the distribution of the number of rises of data is characterized will be described. Some data encoding methods increase or decrease the occurrence probability of a specific bit pattern. Therefore, the frequency of the number of rises may have a characteristic shape depending on the encoding method. FIG. 11 is a diagram showing an example in which a second peak appears in the distribution of the number of rises of data before frequency division. The positions and shapes of the peaks in FIG. 11 are examples for distinguishing from random data, and differ depending on the distribution of the bit pattern of the data.

FIG. 12 is a diagram showing a measurement example of the distribution of the number of rises after frequency division of the data shown in FIG. The vertical and horizontal scales are arbitrary. When the distribution of the number of rises of the data after frequency division is measured according to the procedure of the first embodiment, the frequency peaks (C3 and C4) appears. Therefore, by detecting the specific shape of the distribution of the number of rises in the arithmetic circuit 102, it may be possible to estimate not only the data speed but also the code.

The difference in the distribution of the number of rising edges depending on the data encoding method will be described using the 4B5B code as an example. For example, if 16-bit data with a bit pattern of "0111 0000 0111 0000" is 4B5B encoded, 20-bit encoded data of "01111 11110 01111 11110" is obtained. Since there is no limit to the number of consecutive "0"s and "1"s in random data, there are cases where there is no leading edge (bit pattern "01") for a long period of time. On the other hand, the maximum number of consecutive “0”s and “1”s in 4B5B encoded data is 8 bits. In the above example, the number of consecutive "1"s is eight. Therefore, any consecutive 16 bits extracted from a 4B5B code will contain at least one leading edge (bit pattern "01"). As a result, the number of rising edges of the 4B5B code is statistically greater than the number of rising edges of the random data. Therefore, when the number of rises is counted in the output of the frequency divider, the 4B5B-encoded data is compared to the random data in sections where the number of rises is low (for example, sections "0" and "1-4" in FIG. 7). ) becomes smaller. Therefore, random data can be distinguished from data such as 4B5B encoded data that has an upper limit on the number of continuations of the same bit, based on the characteristic of the frequency of the interval in which the number of rises is small. By measuring or calculating in advance the characteristics of the shape of such distributions for various encoding systems and comparing them with the measured distributions, it is possible to estimate the encoding system in addition to the data speed.

FIG. 13 is a block diagram showing a configuration example of a speed estimation circuit 200 applicable to the third embodiment. The speed estimating circuit 200 differs from the speed estimating circuit 100 of the first embodiment in that it further includes a storage unit 103 . The storage unit 103 is, for example, a fixed magnetic disk device or a semiconductor memory, but is not limited to these. The storage unit 103 stores information (distribution information) on the distribution of the number of rises of the frequency-divided data. The distribution information is, for example, information in which the shape of distribution (for example, information on a plurality of frequency peaks) is associated with data characteristics (for example, speed before frequency division, frequency division ratio, and code format). Arithmetic circuit 102 compares the measured data of the distribution of the number of rises of the frequency-divided data with the distribution information stored in storage unit 103 . Then, if the distribution information contains a distribution shape that matches the actually measured data, the arithmetic circuit 102 outputs the feature of the data corresponding to the distribution shape as an estimation result.

Also, the speed estimation circuit 40 of the optical transceiver 10 of the second embodiment may further include the storage unit 103 . In this case, the control circuit 32 controls the signal processing circuits 13 and 14 based on the respective characteristics of the transmission data and reception data. As a result, the signal processing circuits 13 and 14 can be controlled in consideration of not only the respective speeds of the transmission data and the reception data but also the characteristics such as the code format.

FIG. 14 is a flow chart showing an example of the speed estimation procedure of the speed estimation circuit 40. As shown in FIG. The speed estimation circuit 200 stores data distribution information in advance (step S201 in FIG. 14). Then, the data is frequency-divided to generate frequency-divided data (step S202). Next, the distribution of rising numbers of the frequency-divided data is measured (step S203). Then, the data characteristics are estimated based on the measured distribution and the stored distribution information (step S204). Note that the speed estimation circuit 200 may control a signal processing circuit that processes data based on the estimated characteristics (step S205).

The speed estimation circuit 200 of the third embodiment compares the measured distribution with the stored distribution information to estimate the characteristics of the data in addition to the effect of the speed estimation circuit 100 of the first embodiment. can do.

Although the embodiments of the present invention can be described in the following supplementary remarks, they are not limited thereto.

(Appendix 1)
a frequency dividing circuit for outputting frequency-divided data obtained by frequency-dividing input data;
an arithmetic circuit for obtaining an estimated speed, which is the speed of the data, based on the distribution of either the number of rises or the number of falls of the code contained in the frequency-divided data within a predetermined period;
A speed estimation circuit comprising:

(Appendix 2)
The speed estimating circuit according to appendix 1, wherein the data consists of NRZ (non-return-to-zero) codes.

(Appendix 3)
3. The speed estimation circuit according to appendix 1 or 2, wherein the arithmetic circuit obtains the estimated speed from the shape of the distribution.

(Appendix 4)
4. Any one of Appendices 1 to 3, wherein the arithmetic circuit obtains the estimated speed based on the range of the number of rising times or the number of falling times at which the frequency in the distribution peaks, and the frequency dividing ratio of the frequency dividing circuit. The speed estimation circuit described in .

(Appendix 5)
5. The speed estimation circuit according to any one of Appendices 1 to 4, wherein the arithmetic circuit estimates the characteristics of the data from the shape of the distribution.

(Appendix 6)
6. The speed estimation circuit according to appendix 5, wherein the arithmetic circuit estimates the characteristics of the data based on distribution information in which the shape of the distribution and the characteristics of the data are associated.

(Appendix 7)
The arithmetic circuit is
an estimation circuit for obtaining the estimated speed; and a control circuit for outputting a control signal for processing the data based on the estimated speed.
7. A speed estimation circuit according to any one of Appendices 1 to 6.

(Appendix 8)
a speed estimating circuit described in Supplementary Note 7;
a first signal processing circuit that processes the data based on the control signal;
a light emitting element driven by the output of the first signal processing circuit;
An optical transmitter comprising:

(Appendix 9)
a speed estimating circuit described in Supplementary Note 7;
a light receiving element;
a second signal processing circuit that processes the light receiving signal output from the light receiving element based on the control signal and outputs the result of the processing as the data;
An optical receiver with

(Appendix 10)
An optical transceiver comprising the optical transmitter according to appendix 8 and the optical receiver according to appendix 9.

(Appendix 11)
Output the divided data obtained by dividing the input data,
obtaining an estimated speed, which is the estimated speed of the data, based on the distribution of either the number of rising times or the number of falling times of the code contained in the frequency-divided data within a predetermined period;
Velocity estimation method.

(Appendix 12)
12. The velocity estimation method according to appendix 11, wherein the data is composed of non-return-to-zero (NRZ) codes.

(Appendix 13)
13. The speed estimation method according to appendix 11 or 12, wherein the estimated speed is obtained from the shape of the distribution.

(Appendix 14)
14. Any one of Appendices 11 to 13, wherein the estimated speed is obtained based on the range of the number of rising times or the number of falling times at which the frequency in the distribution peaks, and a frequency division ratio between the data and the frequency-divided data. velocity estimation method described in

(Appendix 15)
15. A velocity estimation method according to any one of appendices 11 to 14, wherein the characteristic of the data is estimated from the shape of the distribution.

(Appendix 16)
16. The speed estimation method according to appendix 15, wherein the characteristics of the data are estimated based on distribution information in which the shape of the distribution and the characteristics of the data are associated.

(Appendix 17)
17. The speed estimation method according to any one of appendices 11 to 16, further comprising outputting a control signal for processing the data based on the estimated speed.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

Also, the configurations described in each embodiment are not necessarily mutually exclusive. The actions and effects of the present invention may be realized by a configuration in which all or part of the above-described embodiments are combined.

The functions described in each of the above embodiments may be realized by the speed estimating circuits 40, 100, 200 or the CPU provided in the optical transceiver 10 executing a program. The program is recorded on a fixed, non-transitory recording medium. A semiconductor memory or a fixed magnetic disk device is used as the recording medium, but is not limited to these. The CPU is a computer provided in the speed estimation circuits 40, 100, 200 or the optical transceiver 10, for example. The CPU may be provided outside of these.

REFERENCE SIGNS LIST 10 optical transceiver 11-12 amplifier 13-14 signal processing circuit 15 light emitting element 16 light receiving element 21-22 frequency dividing circuit 30 arithmetic circuit 31 estimating circuit 32 control circuit 40, 100, 200 speed estimating circuit 101 frequency dividing circuit 102 arithmetic circuit 103 storage unit 1011-101n frequency divider

Claims (10)

a frequency dividing circuit for outputting frequency-divided data obtained by frequency-dividing input data;
an arithmetic circuit for obtaining an estimated speed, which is the speed of the data estimated based on the shape of the distribution of either the number of rises or the number of falls of the code contained in the frequency-divided data within a predetermined period;
A speed estimation circuit comprising: 2. The arithmetic circuit according to claim 1 , wherein the arithmetic circuit obtains the estimated speed based on the range of the number of times of rise or the number of times of fall at which the frequency in the distribution reaches a peak, and the frequency dividing ratio of the frequency dividing circuit. Speed estimation circuit. a frequency dividing circuit for outputting frequency-divided data obtained by frequency-dividing input data;
a range of the number of rising times or the number of falling times at which the frequency in the distribution of either the number of rising times or the number of falling times of the code contained in the frequency-divided data within a predetermined period peaks, and the division of the frequency dividing circuit; an arithmetic circuit for obtaining an estimated speed, which is the estimated speed of the data , based on the circumference ratio ;
A speed estimation circuit comprising: a frequency dividing circuit for outputting frequency-divided data obtained by frequency-dividing input data;
Based on the distribution of either the number of rise times or the number of fall times of the code contained in the frequency-divided data within a predetermined period, an estimated speed, which is the estimated speed of the data, is obtained , and the data is obtained from the shape of the distribution. an arithmetic circuit for estimating the characteristics of
A speed estimation circuit comprising: 5. The speed estimation circuit according to claim 4 , wherein said arithmetic circuit estimates the characteristics of said data based on distribution information in which the shape of said distribution and characteristics of said data are associated with each other. 6. The speed estimation circuit according to claim 3 , wherein said arithmetic circuit obtains said estimated speed from the shape of said distribution. 7. The speed estimating circuit according to claim 1 , wherein said data is composed of NRZ (non-return-to-zero) code. a first signal processing circuit;
a light emitting element driven by the output of the first signal processing circuit;
a speed estimating circuit comprising a frequency dividing circuit and an arithmetic circuit;
with
The frequency dividing circuit outputs frequency-divided data obtained by frequency-dividing input data,
The arithmetic circuit is
an estimation circuit that obtains an estimated speed, which is the speed of the data, based on the distribution of either the number of rising times or the number of falling times of the code contained in the frequency-divided data within a predetermined period;
a control circuit that outputs to the first signal processing circuit a control signal for setting a parameter for driving the light emitting element at the estimated speed to the first signal processing circuit;
optical transmitter . a frequency dividing circuit for outputting frequency-divided data obtained by frequency-dividing input data;
an estimation circuit for obtaining an estimated speed, which is the estimated speed of the data, based on the distribution of either the number of rises or the number of falls of the code contained in the frequency-divided data within a predetermined period; an arithmetic circuit comprising : a control circuit that outputs a control signal for processing the data based on
a speed estimation circuit comprising
a light receiving element;
a second signal processing circuit that processes the light receiving signal output from the light receiving element based on the control signal and outputs the result of the processing as the data;
An optical receiver with Output the divided data obtained by dividing the input data,
obtaining an estimated speed, which is the estimated speed of the data, based on the shape of the distribution of either the number of rising times or the number of falling times of the code contained in the frequency-divided data within a predetermined period;
Velocity estimation method.

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