JP7181824B2 - Display device - Google Patents

Description

The present invention relates to display devices.

Patent Document 1 describes a protection circuit provided in a liquid crystal display device. The liquid crystal display device described in Patent Document 1 includes pads for external connection, internal circuits such as a vertical scanning circuit and a horizontal scanning circuit, and protection provided at the input stage of the internal circuit in the peripheral portion of the insulating substrate. and a circuit. The protection circuit has a plurality of diode-connected transistors. The protection circuit releases static electricity applied from the outside to a power supply line or the like, thereby suppressing static electricity flowing in the internal circuit.

JP-A-6-51346

Protection circuits provided in display devices are required to have improved resistance to static electricity.

An object of the present invention is to provide a display device capable of improving resistance to static electricity.

A display device of one embodiment of the present invention includes a substrate, a plurality of terminals provided in a peripheral region of the substrate, and an internal circuit provided in the peripheral region of the substrate and connected to the terminals through signal lines. and a protection circuit provided between the internal circuit and the terminal, the protection circuit including a first transistor connected to a first power supply line and the signal line, and a gate of the first transistor. a first gate line connected to the signal line at one end and the other end; a second transistor connected to the second power supply line and the signal line; and a second gate line having the other end connected to the second power supply line.

FIG. 1 is a perspective view showing the display device according to the first embodiment. FIG. 2 is a plan view schematically showing the array substrate. FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. FIG. 4 is a circuit diagram showing the pixel arrangement of the display area. FIG. 5 is a circuit diagram showing a protection circuit according to the first embodiment. FIG. 6 is a plan view schematically showing the protection circuit. 7 is a cross-sectional view taken along line VII-VII' of FIG. 6. FIG. FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. FIG. 9 is a plan view showing a connection configuration between a plurality of terminals and a protection circuit of the display device according to the second embodiment. 10 is a cross-sectional view taken along the line XX' of FIG. 9. FIG. FIG. 11 is a plan view showing terminal connection wiring. FIG. 12 is a circuit diagram showing a protection circuit according to the first modified example. FIG. 13 is a circuit diagram showing a protection circuit according to a second modification.

A form (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art will naturally include within the scope of the present invention any appropriate modifications that can be easily conceived while maintaining the gist of the invention. In addition, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual embodiment, but this is only an example, and the interpretation of the present invention is not intended. It is not limited. In addition, in this specification and each figure, the same reference numerals may be given to the same elements as those described above with respect to the existing figures, and detailed description thereof may be omitted as appropriate.

(First embodiment)
FIG. 1 is a perspective view showing the display device according to the first embodiment. As shown in FIG. 1, the display device 1 includes an array substrate SUB1, a counter substrate SUB2, a first polarizing plate PL1, a second polarizing plate PL2, and an illumination device IL. In the third direction Dz, the illumination device IL, the first polarizing plate PL1, the array substrate SUB1, the counter substrate SUB2, and the second polarizing plate PL2 are laminated in this order.

In this embodiment, the first direction Dx is a direction along the long side of the array substrate SUB1. The second direction Dy is a direction crossing (or orthogonal to) the first direction Dx. The second direction Dy is not limited to this, and may intersect the first direction Dx at an angle other than 90°. A plane defined by the first direction Dx and the second direction Dy is parallel to the surface of the array substrate SUB1. A third direction Dz orthogonal to the first direction Dx and the second direction Dy is the thickness direction of the array substrate SUB1.

The array substrate SUB1 is a drive circuit board for driving a plurality of pixels PX. The array substrate SUB1 has a first insulating substrate 10 as a base. The array substrate SUB1 has switching elements Tr provided on the first insulating substrate 10, and various wirings such as scanning lines GL and pixel signal lines SL (see FIG. 4). The counter substrate SUB2 is provided facing the array substrate SUB1 and has a second insulating substrate 20 as a base. The first insulating substrate 10 and the second insulating substrate 20 are made of a translucent material such as a glass substrate or a resin substrate. The counter substrate SUB2 has a color filter CF, a light shielding layer BM (see FIG. 4), etc. provided on the second insulating substrate 20 .

The length of the array substrate SUB1 in the second direction Dy is longer than the length of the counter substrate SUB2 in the second direction Dy. As shown in FIG. 1, the first insulating substrate 10 has a projecting portion 10A. The protruding portion 10A is a portion that protrudes outward from the second insulating substrate 20 in plan view.

A driver IC (Integrated Circuit) 110 and a wiring board 101 are provided on the projecting portion 10A. The driver IC 110 includes a control circuit and the like for controlling the display of the display device 1 . The driver IC 110 is COG (Chip on Grass) mounted on the first insulating substrate 10 . The driver IC 110 may be mounted on the wiring board 101 by COF (Chip On Film) using ACF, for example (hereinafter referred to as "COF mounting"). The arrangement of the driver IC 110 is not limited to this, and may be provided on a control board or flexible board outside the module, for example.

The wiring board 101 is configured by, for example, a flexible printed circuit (FPC). The wiring substrate 101 is connected to a plurality of terminals of the first insulating substrate 10 by FOG (Film On Glass) using, for example, an anisotropic conductive film (ACF: Anisotropic Conductive Film) (hereinafter referred to as “FOG mounting”). ). Thereby, each wiring of the first insulating substrate 10 and each wiring of the wiring substrate 101 are electrically connected.

The array substrate SUB1 faces the illumination device IL, and the counter substrate SUB2 is positioned on the display surface side. The illumination device IL irradiates light toward the array substrate SUB1. For example, a sidelight type backlight or a direct type backlight can be applied to the illumination device IL. Although various forms are applicable as the illumination device IL, the detailed structure thereof will not be described.

An optical element including the first polarizing plate PL1 is arranged on the outer surface of the first insulating substrate 10 or on the surface facing the illumination device IL. An optical element including the second polarizing plate PL2 is arranged on the outer surface of the second insulating substrate 20 or the observation position side surface. The first polarizing axis of the first polarizing plate PL1 and the second polarizing axis of the second polarizing plate PL2 are in a crossed Nicol positional relationship on the XY plane, for example. Note that the optical element including the first polarizing plate PL1 and the second polarizing plate PL2 may include other optical functional elements such as retardation plates.

FIG. 2 is a plan view schematically showing the array substrate. As shown in FIG. 2, in the display device 1, a peripheral area BE is provided outside the display area DA. Although the display area DA is formed in a rectangular shape, the outer shape of the display area DA is not limited. For example, the display area DA may have a substantially rectangular shape with curved corners, may have a notch, or may be formed in another polygonal shape. , the display area DA may be formed in other shapes such as a circular shape or an elliptical shape.

The display area DA is an area for displaying an image, and is an area overlapping with a plurality of pixels PX. The peripheral area BE indicates an area inside the outer periphery of the array substrate SUB1 and outside the display area DA. Note that the peripheral area BE may be frame-shaped surrounding the display area DA, in which case the peripheral area BE can be said to be a frame area.

The peripheral area BE is located between the edge of the first insulating substrate 10 and the display area DA. An area in the peripheral area BE where the driver IC 110 and the wiring board 101 are provided is called a partial peripheral area sBE. The partial peripheral area sBE is an area between one side of the display area DA and the edge 10s of the first insulating substrate 10, and the projecting portion 10A is a portion of the partial peripheral area sBE along the edge 10s. .

Various wirings such as a plurality of terminals T1, a protection circuit 3, an internal circuit 4, a signal line connection wiring 51, a signal output wiring 52, and a signal line 53 are provided in the partial peripheral region sBE of the first insulating substrate 10. FIG. A gate driver 18 is provided in a region extending along the second direction Dy in the peripheral region BE of the first insulating substrate 10 . Although two gate drivers 18 are provided across the display area DA, only one of them may be provided.

A plurality of signal output wirings 52 connect the driver IC 110 and the signal line connection wirings 51 . A plurality of signal output wirings 52 are provided inclined with respect to the second direction Dy, and output signals supplied from the driver IC 110 to the signal line connection wirings 51 .

The signal line connection wiring 51 connects the signal output wiring 52 and a plurality of pixel signal lines SL (see FIG. 4) provided in the display area DA. In the example shown in FIG. 2 , the signal line connection wiring 51 is provided in a region overlapping the second insulating substrate 20 of the opposing substrate SUB2, and the signal output wiring 52 is provided in a region not overlapping the second insulating substrate 20 . Although not shown, a signal line connection circuit such as a multiplexer is provided between the signal line connection wiring 51 and the pixel signal line SL.

A signal line 53 is a wiring for supplying various control signals to the gate driver 18 . The signal line 53 supplies the gate driver 18 with signals such as a clock signal, a power supply voltage, and a gate driving signal (scanning signal) for driving the switching element Tr. The gate driver 18 scans a plurality of scanning lines GL (see FIG. 4) provided in the display area DA based on the control signal.

Internal circuit 4 is connected to driver IC 110 via signal line 53 . The internal circuit 4 is a circuit that performs signal processing on various control signals supplied from the driver IC 110 and outputs signals to the gate driver 18 . The internal circuit 4 has a plurality of thin film transistors, and various forms are applicable.

A plurality of terminals T<b>1 are provided between the driver IC 110 and the internal circuit 4 , and are provided in the projecting portion 10</b>A, that is, in a region that does not overlap the second insulating substrate 20 . The multiple terminals T1 are connected to various wirings such as the signal line 53 . In other words, the internal circuit 4 is connected to the multiple terminals T1 via the signal lines 53 . The plurality of terminals T1 are, for example, inspection terminals used when inspecting the pixel signal lines SL, the scanning lines GL, the signal line connection wirings 51, the signal lines 53, and the like.

The protection circuit 3 is provided between the multiple terminals T1 and the internal circuit 4 . The protection circuit 3 is a circuit that suppresses static electricity applied from the outside, for example, static electricity applied to a plurality of terminals T<b>1 , from flowing to the internal circuit 4 .

FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. FIG. 3 shows a cross-sectional view along line III-III' of FIG. As shown in FIG. 3, the counter substrate SUB2 is arranged to face the surface of the array substrate SUB1 in a direction perpendicular to it. The liquid crystal layer LC is provided between the array substrate SUB1 and the counter substrate SUB2.

The array substrate SUB1 has a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a fifth insulating film 15, a It includes a pixel signal line SL, a pixel electrode PE, a common electrode DE, a first alignment film AL1, and the like.

In this specification, the direction from the first insulating substrate 10 to the second insulating substrate 20 in the direction perpendicular to the first insulating substrate 10 is referred to as "upper" or simply "upper". Also, the direction from the second insulating substrate 20 to the first insulating substrate 10 is referred to as "lower side" or simply "lower side." Also, “planar view” refers to the case when viewed from a direction perpendicular to the first insulating substrate 10 .

A first insulating film 11 is provided on the first insulating substrate 10 . A second insulating film 12 is provided on the first insulating film 11 . A third insulating film 13 is provided on the second insulating film 12 . A signal line SL is provided on the third insulating film 13 . The fourth insulating film 14 is provided on the third insulating film 13 and covers the signal line SL. Although not shown in FIG. 3, the scanning lines GL are provided on the second insulating film 12 .

A common electrode DE is provided on the fourth insulating film 14 . The common electrode DE is provided continuously over the display area DA. However, it is not limited to this, and the common electrode DE may be provided with a slit and divided into a plurality of parts. The common electrode DE is covered with the fifth insulating film 15 .

The pixel electrode PE is provided on the fifth insulating film 15 and faces the common electrode DE with the fifth insulating film 15 interposed therebetween. The pixel electrode PE and the common electrode DE are made of a translucent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrode PE and the fifth insulating film 15 are covered with the first alignment film AL1.

The first insulating film 11, the second insulating film 12, the third insulating film 13, and the fifth insulating film 15 are made of, for example, a translucent inorganic material such as silicon oxide or silicon nitride. The fourth insulating film 14 is made of a translucent resin material and has a greater film thickness than other insulating films made of an inorganic material.

The counter substrate SUB2 includes, on the side of the second insulating substrate 20 facing the array substrate SUB1, a light shielding layer BM, color filters CFR, CFG, CFB, an overcoat layer OC, a second alignment film AL2, and the like. The counter substrate SUB2 has a conductive layer 21 on the opposite side of the second insulating substrate 20 to the array substrate SUB1.

In the display area DA, the light blocking layer BM is located on the side of the second insulating substrate 20 facing the array substrate SUB1. The light shielding layer BM defines openings facing the pixel electrodes PE. The pixel electrode PE is partitioned for each opening of the pixel PX. The light shielding layer BM is made of a black resin material or a light shielding metal material.

Each of the color filters CFR, CFG, and CFB is located on the side of the second insulating substrate 20 facing the array substrate SUB1, and their ends overlap the light shielding layer BM. In one example, the color filters CFR, CFG, and CFB are made of resin materials colored red, green, and blue, respectively.

An overcoat layer OC covers the color filters CFR, CFG, and CFB. The overcoat layer OC is made of a translucent resin material. The second alignment film AL2 covers the overcoat layer OC. The first alignment film AL1 and the second alignment film AL2 are made of, for example, a material exhibiting horizontal alignment.

A conductive layer 21 is provided on the second insulating substrate 20 . The conductive layer 21 is, for example, a translucent conductive material such as ITO. Static electricity applied from the outside and static electricity charged on the second polarizing plate PL2 flow through the conductive layer 21 . The display device 1 can remove static electricity in a short time, and can reduce static electricity applied to the liquid crystal layer LC, which is the display layer. Thereby, the display device 1 can improve the ESD resistance.

The array substrate SUB1 and the counter substrate SUB2 are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. The liquid crystal layer LC is enclosed between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LC is composed of a negative liquid crystal material with negative dielectric anisotropy or a positive liquid crystal material with positive dielectric anisotropy.

For example, when the liquid crystal layer LC is a negative liquid crystal material and no voltage is applied to the liquid crystal layer LC, the long axis of the liquid crystal molecule LM is in the first direction Dx in the XY plane. is initially oriented in the direction along On the other hand, when a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrode PE and the detection electrode DE, the liquid crystal molecules LM are affected by the electric field and their alignment state is changed to Change. In the ON state, the incident linearly polarized light changes its polarization state according to the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LC.

FIG. 4 is a circuit diagram showing the pixel arrangement of the display area. On the array substrate SUB1, the switching elements Tr of each sub-pixel SPX, the pixel signal lines SL, the scanning lines GL, etc. shown in FIG. 4 are formed. The pixel signal line SL extends in the second direction Dy. The pixel signal line SL is a wiring for supplying a pixel signal to each pixel electrode PE (see FIG. 3). The scanning line GL extends in the first direction Dx. The scanning line GL is wiring for supplying a driving signal (scanning signal) for driving each switching element Tr.

A pixel PX includes a plurality of sub-pixels SPX. Each sub-pixel SPX has a capacitance of a switching element Tr and a liquid crystal layer LC. The switching element Tr is composed of a thin film transistor, and in this example, is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. A fifth insulating film 15 is provided between the pixel electrode PE and the common electrode DE shown in FIG. 3 to form the storage capacitor Cs shown in FIG.

In the color filters CFR, CFG, and CFB shown in FIG. 3, for example, three color regions of red (R), green (G), and blue (B) are arranged periodically. Each sub-pixel SPX is associated with a set of three color areas of R, G, and B. FIG. A pixel PX is formed by using a set of sub-pixels SPX corresponding to the three color regions. Note that the color filter may include color areas of four or more colors. In this case, the pixel PX may include four or more sub-pixels SPX.

Next, a detailed configuration of the protection circuit 3 will be described. FIG. 5 is a circuit diagram showing a protection circuit according to the first embodiment. As shown in FIG. 5, the protection circuit 3 includes a plurality of first transistors Tr1, a plurality of second transistors Tr2, a first power supply line 31, a second power supply line 32, a source line 33, and a drain line 34. , a first gate line 35 and a second gate line 36 .

The first power supply line 31 is connected to the first power supply 111 and supplied with the first power supply voltage VDD. The first power supply line 31 is a wiring that supplies the first power supply voltage VDD to the plurality of first transistors Tr1. The second power supply line 32 is connected to the second power supply 112 and supplied with the second power supply voltage VSS. The second power supply line 32 is a wiring that supplies the second power supply voltage VSS to the plurality of second transistors Tr2. The first power supply voltage VDD is a voltage signal having a higher potential than the second power supply voltage VSS. The first power supply voltage VDD has a higher potential than the signal supplied from the signal line 53 and the second power supply voltage VSS has a lower potential than the signal supplied from the signal line 53 .

The first power supply 111 and the second power supply 112 may be power supply circuits built in the driver IC 110 or may be external power supply circuits via the wiring substrate 101 .

The plurality of first transistors Tr1 and the plurality of second transistors Tr2 are composed of n-channel MOS TFTs. Sources of the plurality of first transistors Tr1 are connected to a common source line 33 . One end 33s of the source line 33 is connected to the first power supply line 31 via the connection wiring 37a, and the other end 33t of the source line 33 is connected to the first power supply line 31 via the connection wiring 37b. Also, the drains of the plurality of first transistors Tr1 are connected to a common signal line 53 . Thereby, the plurality of first transistors Tr1 are connected to the first power supply line 31 and the signal line 53, respectively. In this manner, the plurality of first transistors Tr1 are connected in parallel between the first power supply line 31 and the signal line 53 to form the first transistor group TG1.

The first gate line 35 is connected to gates of the plurality of first transistors Tr1. One end 35s of the first gate line 35 is connected to the signal line 53 via the connection portion 53a, and the other end 35t of the first gate line 35 is connected to the signal line 53 via the connection portion 53b. As a result, the gates and drains of the plurality of first transistors Tr1 are short-circuited, and the plurality of first transistors Tr1 have a so-called diode-connected configuration.

Sources of the plurality of second transistors Tr2 are connected to a common signal line 53 . That is, the signal line 53 is connected to the drain of the first transistor Tr1 and the source of the second transistor Tr2. Also, the drains of the plurality of second transistors Tr2 are connected to a common drain line 34 . One end 34s of the drain line 34 is connected to the second power supply line 32 via the connection wiring 38a, and the other end 34t of the drain line 34 is connected to the second power supply line 32 via the connection wiring 38b. Thereby, the plurality of second transistors Tr2 are connected to the second power line 32 and the signal line 53, respectively. In this manner, the plurality of second transistors Tr2 are connected in parallel between the second power supply line 32 and the signal line 53 to form the second transistor group TG2.

The second gate line 36 is connected to gates of the plurality of second transistors Tr2. One end 36s of the second gate line 36 is connected to the drain line 34 via the connection portion 34a, and the other end 36t of the second gate line 36 is connected to the drain line 34 via the connection portion 34b. As a result, the gates and drains of the plurality of second transistors Tr2 are short-circuited, and the plurality of second transistors Tr2 have a so-called diode-connected configuration.

A resistor R1 and capacitors C3 and C4 are formed between the plurality of first transistors Tr1. Similarly, resistors R2 and capacitors C1 and C2 are formed between the plurality of second transistors Tr2. Resistances R1 and R2 are resistance components of the first gate line 35 and the second gate line 36, respectively. A capacitance C1 is a parasitic capacitance formed between the second gate line 36 and the drain line 34 . A capacitance C2 is a parasitic capacitance formed between the second gate line 36 and the signal line 53 . A capacitance C3 is a parasitic capacitance formed between the first gate line 35 and the source line 33 . A capacitance C4 is a parasitic capacitance formed between the first gate line 35 and the signal line 53 .

With the configuration as described above, in the first transistor group TG1 and the second transistor group TG2, the plurality of first transistors Tr1 and the plurality of second transistors Tr2 are connected in parallel along the common signal line 53, respectively. In other words, the first transistor group TG1 and the second transistor group TG2 are connected in series via the common signal line 53 between the first power line 31 and the second power line 32 .

When static electricity having a positive potential is applied from the terminal T1 to the signal line 53, the multiple first transistors Tr1 are turned on and the multiple second transistors Tr2 are turned off. As a result, static electricity flows from the signal line 53 to the first power supply line 31 via the plurality of first transistors Tr1.

When static electricity having a negative potential is applied from the terminal T1 to the signal line 53, the multiple first transistors Tr1 are turned off and the multiple second transistors Tr2 are turned on. As a result, static electricity flows from the signal line 53 to the second power supply line 32 via the plurality of second transistors Tr2. Thereby, the protection circuit 3 can suppress static electricity from flowing to the internal circuit 4 .

In this embodiment, one end 35 s and the other end 35 t of the first gate line 35 are connected to the signal line 53 , and one end 36 s and the other end 36 t of the second gate line 36 are connected to the drain line 34 . Thus, when static electricity is applied, the potential changes from both the one end 35s and the other end 35t of the first gate line 35 . Alternatively, the potential changes from both the one end 36s and the other end 36t of the second gate line 36 .

Therefore, compared to the configuration in which only one end 35s of the first gate line 35 is connected to the signal line 53 and only one end 36s of the second gate line 36 is connected to the drain line 34, the plurality of first transistors Tr1 and the plurality of can reduce the ON time constant of the second transistor Tr2. That is, it is possible to suppress the difference in rise time between the first transistor Tr1 located near the terminal T1 and the first transistor Tr1 located far from the terminal T1. Similarly, it is possible to suppress the difference in rise time between the second transistor Tr2 located near the terminal T1 and the second transistor Tr2 located far from the terminal T1. Thereby, the protection circuit 3 can quickly release the static electricity applied to the signal line 53 to the first power line 31 or the second power line 32 .

In this embodiment, one end 33 s and the other end 33 t of the source line 33 are connected to the first power line 31 , and one end 34 s and the other end 34 t of the drain line 34 are connected to the second power line 32 . Accordingly, when static electricity is applied, static electricity flows from the one end 33s and the other end 33t of the source line 33 to the first power supply line 31 via the plurality of first transistors Tr1. Similarly, static electricity flows from one end 34s and the other end 34t of the drain line 34 to the second power supply line 32 via the plurality of second transistors Tr2.

Therefore, compared to the configuration in which only one end 33 s of the source line 33 is connected to the first power line 31 and only one end 34 s of the drain line 34 is connected to the second power line 32 , static electricity is It is possible to increase the number of routes for escape to the second power supply line 32 . Thereby, the protection circuit 3 can quickly release the static electricity applied to the signal line 53 to the first power line 31 or the second power line 32 .

As described above, the display device 1 is provided with the protection circuit 3 between the terminal T1 and the internal circuit 4. Therefore, even if static electricity is applied from the terminal T1 to the signal line 53, the static electricity will not be generated in the internal circuit 4. flow can be suppressed. Therefore, the display device 1 can improve resistance to static electricity.

Next, a specific configuration example of the protection circuit 3 will be described. FIG. 6 is a plan view schematically showing the protection circuit. In FIG. 6, each wiring is hatched in order to make the drawing easier to see. As shown in FIG. 6, the second power line 32, the first power line 31, the drain line 34, the second gate line 36, the signal line 53, the first gate line 35 and the source line 33 are arranged in the first direction Dx. procrastinate. The second power line 32, the first power line 31, the drain line 34, the second gate line 36, the signal line 53, the first gate line 35, and the source line 33 are arranged in this order in the second direction Dy. be.

The first gate line 35 is arranged between the signal line 53 and the source line 33 in the second direction Dy. The first gate line 35 has a first partial gate line 35a and a second partial gate line 35b. The first partial gate line 35a and the second partial gate line 35b each extend in the first direction Dx and are arranged adjacent to each other in the second direction Dy. The first partial gate line 35a and the second partial gate line 35b are connected at one end 35s and the other end 35t.

Connection portions 53a and 53b of the signal line 53 are provided so as to protrude from the signal line 53 in the second direction Dy, and are connected to one end 35s and the other end 35t of the first gate line 35 via contact holes.

One end 33s and the other end 33t of the source line 33 are connected to connection wirings 37a and 37b through contact holes, respectively. The connection wirings 37a and 37b extend in the second direction Dy, are provided to cross the signal line 53 in plan view, and are connected to the first power supply line 31 through contact holes.

The second gate line 36 is arranged between the signal line 53 and the drain line 34 in the second direction Dy. The second gate line 36 has a first partial gate line 36a and a second partial gate line 36b. The first partial gate line 36a and the second partial gate line 36b each extend in the first direction Dx and are arranged adjacent to each other in the second direction Dy. The first partial gate line 36a and the second partial gate line 36b are connected at one end 36s and the other end 36t.

Connection portions 34a and 34b of the drain line 34 are provided so as to protrude from the drain line 34 in the second direction Dy, and are connected to one end 36s and the other end 36t of the second gate line 36 via contact holes.

One end 34s and the other end 34t of the drain line 34 are connected to connection wirings 38a and 38b through contact holes, respectively. The connection wirings 38a and 38b extend in the second direction Dy, are provided to cross the first power supply line 31 in plan view, and are connected to the second power supply line 32 through contact holes.

The multiple first transistors Tr1 each have a first semiconductor layer 39a. The plurality of first semiconductor layers 39a are arranged in regions overlapping the first gate lines 35, respectively. The plurality of first transistors Tr1 has a double gate structure in which two first partial gate lines 35a and second partial gate lines 35b are provided to overlap the first semiconductor layer 39a. In addition, the first semiconductor layers 39a are spaced apart with an interval SP in the first direction Dx.

Each of the plurality of second transistors Tr2 has a second semiconductor layer 39b. The plurality of second semiconductor layers 39b are arranged in regions overlapping the second gate lines 36, respectively. The plurality of second transistors Tr2 also have a double gate structure like the first transistor Tr1. In addition, the second semiconductor layers 39b are spaced apart with an interval SP in the first direction Dx.

The first semiconductor layer 39a and the second semiconductor layer 39b are formed of a common semiconductor layer 39. As shown in FIG. The semiconductor layer 39 (first semiconductor layer 39a and second semiconductor layer 39b) is provided continuously across the first gate line 35 and the second gate line 36 in the second direction Dy. One end side of the semiconductor layer 39 is connected to the source line 33 via a contact hole. A central portion of the semiconductor layer 39 in the second direction Dy is connected to the signal line 53 via a contact hole. The other end side of the semiconductor layer 39 is connected to the drain line 34 via a contact hole. In the following description, the first semiconductor layer 39a and the second semiconductor layer 39b are simply referred to as the semiconductor layer 39 when there is no need to distinguish between them.

7 is a cross-sectional view taken along line VII-VII' of FIG. 6. FIG. As shown in FIG. 7, the semiconductor layer 39 is provided on the first insulating film 11 . Polysilicon, for example, can be used for the semiconductor layer 39 . More preferably, the semiconductor layer 39 is Low Temperature Polycrystalline Silicone (LTPS). However, the material is not limited to this, and the semiconductor layer 39 may be made of other materials such as amorphous silicon and oxide semiconductor.

The semiconductor layer 39 includes a channel region 39s, a low concentration impurity region 39t and a high concentration impurity region 39u. The channel region 39s is, for example, a non-doped intrinsic semiconductor or a low impurity region, and has lower conductivity than the low concentration impurity region 39t and the high concentration impurity region 39u. The channel regions 39s are provided in regions overlapping the first gate line 35 and the second gate line 36, respectively.

The high-concentration impurity region 39u is provided in a region connected to the source line 33, the signal line 53, and the drain line 34, that is, a region overlapping the bottom surface of the contact hole penetrating the second insulating film 12 and the third insulating film 13. . Low concentration impurity region 39t is provided between channel region 39s and high concentration impurity region 39u.

A light shielding layer 55 is provided between the semiconductor layer 39 and the first insulating substrate 10 . The light shielding layer 55 is provided at least in a region overlapping with the channel region 39s. The light shielding layer 55 is made of, for example, a metal material and has a lower light transmittance than the first insulating substrate 10 . As a result, light leakage of the first transistor Tr1 and the second transistor Tr2 can be suppressed.

The second insulating film 12 is provided on the first insulating film 11 to cover the semiconductor layer 39 . The first gate line 35, the second gate line 36 and the connection wiring 38a are provided on the second insulating film 12 in the same layer. Although not shown in FIG. 7, the connection wirings 37a, 37b and 38b are also provided in the same layer as the first gate line 35, the second gate line 36 and the connection wiring 38a.

The first gate line 35, the second gate line 36, and the connection wirings 37a, 37b, 38b, and 38a are provided in the same layer as the scanning lines GL provided in the display area DA, and are made of the same material. The first gate line 35, the second gate line 36 and the connection wirings 37a, 37b, 38b, 38a can be made of, for example, metal materials such as molybdenum (Mo) and tungsten (W), or alloy materials thereof.

The third insulating film 13 is provided on the second insulating film 12 to cover the first gate lines 35, the second gate lines 36, the connection wirings 38a, and the like. The source line 33 , the signal line 53 , the drain line 34 , the first power line 31 and the second power line 32 are provided on the third insulating film 13 in the same layer. A portion of the first power supply line 31 is provided in a region overlapping with the connection wiring 38a.

The source lines 33, the signal lines 53, the drain lines 34, the first power lines 31, and the second power lines 32 are provided in the same layer as the pixel signal lines SL provided in the display area DA, and are made of the same material. The source line 33, the signal line 53, the drain line 34, the first power line 31 and the second power line 32 can be made of a low resistance metal material such as aluminum (Al). That is, the sheet resistance of the first gate line 35, the second gate line 36 and the connection wirings 37a, 37b, 38b, 38a is higher than the sheet resistance of 32.

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. Although FIG. 8 shows the cross-sectional configuration of a plurality of first transistors Tr1, the description of FIG. 8 can also be applied to the second transistor Tr2.

As shown in FIG. 8, the semiconductor layers 39 are arranged with intervals SP in the first direction Dx. The second insulating film 12 covers the plurality of semiconductor layers 39 and is provided on the first insulating film 11 at intervals SP between adjacent semiconductor layers 39 . Since the semiconductor layer 39, which is the heat-generating part of the first transistor Tr1, is divided into a plurality of parts, the area capable of dissipating heat can be increased compared to the case where the plurality of semiconductor layers 39 are formed as one continuous semiconductor layer. . The second transistor Tr2 also has a cross-sectional configuration similar to that of FIG. 8, and the semiconductor layer 39 is divided into a plurality of parts with intervals SP.

Therefore, the protection circuit 3 can suppress heat generation in the first transistor group TG1 and the second transistor group TG2 as a whole. As a result, the resistance to static electricity of the protection circuit 3 itself can be improved.

As described above, the display device 1 of this embodiment has the substrate (first insulating substrate 10), the plurality of terminals T1, the internal circuit 4, and the protection circuit 3. A plurality of terminals T1 are provided in the peripheral area BE of the first insulating substrate 10 . The internal circuit 4 is provided in the peripheral area BE of the first insulating substrate 10 and is connected to the terminal T1 via the signal line 53 . The protection circuit 3 is provided between the internal circuit 4 and the terminal T1. The protection circuit 3 includes a first power supply line 31, a second power supply line 32, a plurality of first transistors Tr1, a first gate line 35, a plurality of second transistors Tr2, and a second gate line 36. have. A first power supply voltage VDD is supplied to the first power supply line 31 . The second power supply line 32 is supplied with the second power supply voltage VSS. Each of the plurality of first transistors Tr1 is connected to the first power line 31 and the signal line 53 . The first gate line 35 is connected to the gates of the plurality of first transistors Tr1 and has one end 35s and the other end 35t connected to the signal line 53 . Each of the multiple second transistors Tr2 is connected to the second power supply line 32 and the signal line 53 . The second gate line 36 is connected to gates of the plurality of second transistors Tr<b>2 and has one end 36 s and the other end 36 t connected to the second power supply line 32 .

According to this, the potential changes from both the one end 35s and the other end 35t of the first gate line 35 when static electricity is applied. Alternatively, the potential changes from both the one end 36s and the other end 36t of the second gate line 36 . Therefore, it is possible to reduce the ON time constants of the plurality of first transistors Tr1 and the plurality of second transistors Tr2. Thereby, the protection circuit 3 can quickly release the static electricity applied to the signal line 53 to the first power line 31 or the second power line 32 . Therefore, the display device 1 can improve resistance to static electricity.

Note that the configuration of the protection circuit 3 is not limited to the example described above, and can be changed as appropriate. For example, although the protection circuit 3 has a configuration in which a plurality of first transistors Tr1 and a plurality of second transistors Tr2 are provided on one signal line 53, a plurality of signal lines 53 may be provided. In this case, the protection circuit 3 is provided with a plurality of first transistors Tr1 and a plurality of second transistors Tr2 for each of the plurality of signal lines 53 . Also, although the protection circuit 3 is provided on the input side of the gate driver 18, it is not limited to this. The protection circuit 3 may be provided between the terminals T1 and the image signal lines SL.

Also, the configurations of the first transistor Tr1 and the second transistor Tr2 are not limited to the configurations shown in FIGS. For example, the first transistor Tr1 and the second transistor Tr2 may have a bottom gate structure in which the first gate line 35 and the second gate line 36 are provided under the semiconductor layer 39 .

Moreover, although the display device 1 is a liquid crystal display device, it is not limited to this. The protection circuit 3 can also be applied to display devices such as an organic EL display device, an electrophoretic display device, and a micro LED display device, for example.

(Second embodiment)
FIG. 9 is a plan view showing a connection configuration between a plurality of terminals and a protection circuit of the display device according to the second embodiment. As shown in FIG. 9, the plurality of terminals T1-1, T1-2, T1-3, T1-4, T1-5, T1-6 are staggered. Terminals T1-1, T1-3, and T1-5 are arranged in the first direction Dx. Terminals T1-2, T1-4, and T1-6 are arranged in the first direction Dx. The terminals T1-1, T1-3, T1-5 and the terminals T1-2, T1-4, T1-6 are arranged so as to be adjacent to each other in the second direction Dy and at different positions in the first direction Dx. be done.

A plurality of terminals T1-1, T1-2, T1-3, T1-4, T1-5, and T1-6 are provided with terminal connection wirings TCN-1, TCN-2, TCN-3, TCN-4, and TCN, respectively. -5 and TCN-6 are connected. The terminal connection wirings TCN-1, TCN-2, TCN-3 intersect with the plurality of signal lines 53-1, 53-2, 53-3, the first power line 31 and the second power line 32 to form the second extends in direction Dy. Terminal connection wirings TCN-1, TCN-2, and TCN-3 are connected to, for example, image signal lines SL provided in the display area DA.

In the following description, when the terminals T1-1, T1-2, T1-3, T1-4, T1-5, and T1-6 do not need to be distinguished and described, they are simply referred to as terminals T1. . When the terminal connection wirings TCN-1, TCN-2, TCN-3, TCN-4, TCN-5, and TCN-6 need not be distinguished and explained, they are simply referred to as terminal connection wirings TCN. The signal lines 53-1, 53-2, and 53-3 are simply referred to as signal lines 53 when there is no need to distinguish between them.

Terminal connection wirings TCN-4, TCN-5 and TCN-6 are connected to a plurality of signal lines 53-1, 53-2 and 53-3, respectively. Each of the plurality of signal lines 53-1, 53-2, 53-3 has a first partial signal line 53c and a second partial signal line 53d. The first partial signal line 53c is connected to the terminal T1 via the terminal connection wiring TCN. The second partial signal line 53 d is connected to the protection circuit 3 . The first partial signal line 53c and the second partial signal line 53d are provided apart from each other in the first direction Dx. The relay wiring 54 connects the first partial signal line 53c and the second partial signal line 53d.

10 is a cross-sectional view taken along the line XX' of FIG. 9. FIG. As shown in FIG. 10 , a plurality of terminal connection wirings TCN and relay wirings 54 are provided on the second insulating film 12 . That is, the plurality of terminal connection wirings TCN and relay wirings 54 are provided in the same layer as the first gate lines 35, the second gate lines 36, etc. (see FIG. 7), and the first gate lines 35, the second gate lines 36, etc. made of the same material as

A first partial signal line 53 c and a second partial signal line 53 d of the signal line 53 are provided on the third insulating film 13 . The first partial signal line 53c and the second partial signal line 53d are connected to the relay wiring 54 through contact holes provided in the third insulating film 13, respectively. Also, the first partial signal line 53c is connected to the terminal connection wiring TCN-6 through a contact hole provided in the third insulating film 13. As shown in FIG.

As described above, the signal line 53 is made of a low resistance metal material such as aluminum (Al). The terminal connection wiring TCN and the relay wiring 54 are made of a metal material such as molybdenum (Mo) or tungsten (W). That is, the relay wiring 54 is provided in a layer different from that of the signal line 53 and has a sheet resistance greater than that of the signal line 53 .

Thus, the plurality of terminals T1 and the protection circuit 3 are connected via the plurality of signal lines 53 (the first partial signal line 53c and the second partial signal line 53d) and the relay wiring . Thereby, the resistance from the plurality of terminals T1 to the protection circuit 3 can be increased compared to the case where the plurality of terminals T1 to the protection circuit 3 are connected without the relay wiring 54 intervening. As a result, the static electricity applied to the multiple terminals T1 is thermally converted in the path from the multiple terminals T1 to the protection circuit 3 . Therefore, in the present embodiment, static electricity flowing through the protection circuit 3 and the internal circuit 4 can be suppressed.

Further, as shown in FIG. 9, each of the terminal connection wirings TCN-3, TCN-4, TCN-5, and TCN-6 has a meandering portion TCNa. The meandering portion TCNa is provided in a region between the second power supply lines 32 adjacent in the second direction Dy and the plurality of terminals T1.

FIG. 11 is a plan view showing terminal connection wiring. As shown in FIG. 11 , the meandering portion TCNa has a plurality of straight portions 61 and a plurality of curved portions 62 . The plurality of linear portions 61 extend in the first direction Dx and are arranged in the second direction Dy. The curved portion 62 connects the ends of the straight portions 61 adjacent in the second direction Dy. The curved portion 62 alternately connects one end side and the other end side of the straight portion 61 . In this manner, the meandering portion TCNa is formed in a meandering shape, and the terminal connection wiring TCN connects the terminal T1 and the signal line 53 . Moreover, the meandering portion TCNa has a sheet resistance greater than that of the signal line 53 .

As a result, the wiring length from the terminal T1 to the signal line 53 becomes longer and the resistance increases, compared to the case where the terminal T1 and the signal line 53 are connected by a straight line without the meandering portion TCNa. As a result, the static electricity applied to the multiple terminals T1 is thermally converted at the meandering portion TCNa between the multiple terminals T1 and the signal line 53 . Therefore, in the present embodiment, static electricity flowing through the protection circuit 3 and the internal circuit 4 can be suppressed.

The configuration of the plurality of signal lines 53, the plurality of terminals T1, and the terminal connection wiring TCN is merely an example. For example, the plurality of signal lines 53 may be separated into three or more portions, and the relay wiring 54 may be provided between the portions. The number of signal lines 53 connected to the protection circuit 3 may be two or less, or four or more. The multiple terminals T1 are not limited to the staggered arrangement, and may be arranged in the first direction Dx, for example.

(First modification)
FIG. 12 is a circuit diagram showing a protection circuit according to the first modified example. In the protection circuit 3A of the first modified example shown in FIG. 12, the other end 35t of the first gate line 35 is not connected to the signal line 53, and the second The other end 36 t of the gate line 36 is disconnected from the drain line 34 .

Also in the first modification, one end 33 s and the other end 33 t of the source line 33 are connected to the first power line 31 , and one end 34 s and the other end 34 t of the drain line 34 are connected to the second power line 32 . Therefore, when static electricity is applied to the terminal T1, the number of paths for releasing the static electricity to the first power line 31 and the second power line 32 can be increased. Thereby, the protection circuit 3A can quickly release the static electricity applied to the signal line 53 to the first power line 31 or the second power line 32 .

(Second modification)
FIG. 13 is a circuit diagram showing a protection circuit according to a second modification. In the protection circuit 3B of the second modification shown in FIG. 13, compared with the first embodiment shown in FIG. is disconnected from the first power supply line 31 . One end 34 s of the drain line 34 is connected to the second power line 32 , and the other end 34 t of the drain line 34 is not connected to the second power line 32 .

Also in the second modification, one end 35 s and the other end 35 t of the first gate line 35 are connected to the signal line 53 , and one end 36 s and the other end 36 t of the second gate line 36 are connected to the drain line 34 . Thereby, the ON time constants of the plurality of first transistors Tr1 and the plurality of second transistors Tr2 can be reduced. Therefore, the protection circuit 3B can quickly release static electricity applied to the signal line 53 to the first power line 31 or the second power line 32 . In addition, since the protection circuit 3B can reduce the number of wirings compared to the first embodiment, the circuit scale can be suppressed.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The content disclosed in the embodiment is merely an example, and various modifications can be made without departing from the scope of the present invention. Appropriate changes that do not deviate from the gist of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, replacements, and modifications of the components can be made without departing from the scope of each embodiment and each modification described above.

1 display device 3, 3A, 3B protective circuit 4 internal circuit 10 first insulating substrate 20 second insulating substrate 31 first power supply line 32 second power supply line 33 source line 34 drain line 35 first gate line 36 second gate line 39 Semiconductor layer 39a First semiconductor layer 39b Second semiconductor layer 51 Signal line connection wiring 52 Signal output wiring 53 Signal line 54 Relay wiring 55 Light shielding layer 101 Wiring board 110 Driver IC
111 First power supply 112 Second power supply BE Peripheral area DA Display area SUB1 Array substrate SUB2 Counter substrate T1 Terminal TCN Terminal connection wiring TCNa Snaking portion Tr1 First transistor Tr2 Second transistor

Claims (10)

a substrate;
a plurality of terminals provided in a peripheral region of the substrate;
an internal circuit provided in a peripheral region of the substrate and connected to the terminal via a signal line;
a protection circuit provided between the internal circuit and the terminal;
The protection circuit is
a first transistor connected to the first power supply line and the signal line;
a first gate line connected to the gate of the first transistor and having one end and the other end connected to the signal line;
a second transistor connected to the second power supply line and the signal line;
a second gate line connected to the gate of the second transistor and having one end and the other end connected to the second power supply line. a source line connected to the sources of the plurality of first transistors;
The display device according to claim 1, wherein one end and the other end of the source line are connected to the first power line. having a drain line connected to the drains of the plurality of second transistors;
3. The display device according to claim 1, wherein one end and the other end of said drain line are connected to said second power line. The display device according to any one of claims 1 to 3, wherein the signal line is connected to the drains of the plurality of first transistors and the sources of the plurality of second transistors. each of the plurality of first transistors has a first semiconductor layer;
the first gate line extends in a first direction;
5. The plurality of first semiconductor layers according to any one of claims 1 to 4, wherein the plurality of first semiconductor layers are provided in a region overlapping with the first gate line and are spaced apart from each other in the first direction. Display device as described. each of the plurality of second transistors has a second semiconductor layer;
the second gate line extends in the first direction;
6. The display device according to claim 5, wherein the plurality of second semiconductor layers are provided in a region overlapping with the second gate line, and are spaced apart from each other in the first direction. 7. The first semiconductor layer and the second semiconductor layer are continuously provided across the first gate line and the second gate line in a second direction crossing the first direction. Display device as described. a plurality of signal lines;
a relay wiring that is provided in a layer different from that of the signal line, has a sheet resistance greater than that of the signal line, and connects the plurality of signal lines;
8. The display device according to any one of claims 1 to 7, wherein the terminal and the protection circuit are connected via a plurality of the signal lines and the relay wiring. 9. The display device according to claim 8, wherein the relay wiring is provided in the same layer as the first gate line and the second gate line. 10. The display device according to any one of claims 1 to 9, further comprising a terminal connection wiring that is formed in a meandering shape and connects the terminal and the signal line.

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