JP7176289B2 - Communication device - Google Patents

Description

The present invention relates to communication devices.

For example, an in-vehicle communication system employs a master-slave communication system through networks such as CAN and LIN (see, for example, Patent Document 1). This patent document 1 proposes a decoding method in so-called CXPI (Clock Extension Peripheral Interface) communication. In this type of CXPI communication technology, both the master node and the slave node decode data based on measuring the time width when the signal flowing through the bus line becomes low level (L) from the PWM waveform.

JP 2014-30124 A

When the technology described in Patent Document 1 is employed, data can be decoded by detecting edges of signals flowing through the bus line. At this time, if disturbance noise is input to the bus line, chattering occurs in the bus line, and even if the time width of the low signal is measured, it cannot be measured correctly. This measurement time width is used for sampling in the next period. Therefore, if the communication device learns the time width incorrectly, erroneous sampling may occur in subsequent cycles. That is, there is a possibility that a logical value "0" is decoded instead of being decoded as a logical value "1".

SUMMARY OF THE INVENTION It is an object of the present invention to provide a communication apparatus capable of establishing communication while reducing the risk of decoding errors even if disturbance noise is input to a bus line.

The invention according to claim 1 includes a first measuring section, a first storage section, a setting section, and a decoding section. The first measuring unit measures the duration of the other level from the timing when one of the binary levels flowing in the bus line changes to the other level. The first storage unit stores the measured value of the first measurement unit. The setting unit sets a sampling point for sampling the signal on the bus line at a decoding threshold obtained by adding a margin time to the value stored in the first storage unit. The decoding circuit determines that the code is the first code if the decoding threshold is less than or equal to the measured value of the first measuring unit based on the sampling operation, and determines that the code is the first code if the decoding threshold is greater than the measured value of the first measuring unit. is the second code. The first storage unit has a mechanism for storing when the decoding circuit determines that the measured value of the first measurement unit is the second code. Then , the stored value is repeatedly updated and set based on the comparison between the previous stored value stored in the first storage unit and the current measured value measured by the first measurement unit . Since the stored value is repeatedly updated and set based on the comparison between the previous stored value stored in the first storage unit and the current measured value measured by the first measurement unit, the magnitude of these measured values Sampling points can be appropriately updated and set accordingly. Therefore, even if disturbance noise is input to the bus line, it is possible to reduce the possibility of erroneous decoding.

1 is a block diagram showing a schematic configuration of a communication system according to a first embodiment; FIG. Explanatory diagram of signals transmitted to bus lines Block diagram showing schematic configuration of master node and slave node Configuration diagram of frames transmitted and received between the signal processing unit and the transceiver Operation explanatory diagram of the encoding circuit in the slave node Block diagram of decoding circuit Flowchart for explaining the processing contents of the row width write control unit and bit garbled detection arithmetic circuit Operation explanatory diagram of bit garbled detection arithmetic circuit Timing chart that explains the processing contents in chronological order Explanatory diagram of a comparative example Block configuration diagram of a decoding circuit according to the second embodiment Flowchart for explaining processing contents by the margin write control unit

Several embodiments of the communication device will be described below with reference to the drawings. In each embodiment, substantially the same or similar parts are denoted by the same reference numerals, and the description thereof is omitted as necessary, and the description of each embodiment will focus on the characteristic parts.

(First embodiment)
FIG. 1 schematically shows an electrical block diagram of a communication system Sy. A plurality of communication nodes 1 to 4 are mounted in the vehicle, and these communication nodes 1 to 4 are connected to a bus line 5 to construct a communication system Sy. One of these communication nodes 1-4 operates as a master node 1, and the other communication nodes 2-4 operate as slave nodes 2-4. Therefore, in FIG. 1, communication node 1 is designated as master node 1, and communication nodes 2 to 4 are designated as slave nodes.

These communication nodes 1 to 4 are composed of an electronic control unit (ECU (Electronic Control Unit)) for executing vehicle body system applications, or various sensors or various switches for detecting the state of the vehicle. be. For example, body system ECUs include various ECUs such as a body wiper ECU, a slide door ECU, and a mirror ECU. Various sensors or switches include a rain sensor, a wiper switch, a light switch, and the like.

A bus line 5 is a communication line for constructing an in-vehicle network, and these communication nodes 1 to 4 can communicate data with each other through the bus line 5. FIG. FIG. 2 shows binary level transmission signal waveforms transmitted and received through the bus line 5 between the communication nodes 1-4. The binary level flowing through the bus line 5 has an edge (for example, a falling edge) positioned at a boundary defining a bit and changing from one level to the other. A PWM signal that changes in level (for example, from low level "L" to high level "H") is used, and logic "1"/logic "0" is expressed using PWM signals with different duty ratios. In the following description, it is assumed that logic "0" is dominant and logic "1" is recessive. In the following description, "one level" is assumed to be high level "H" and "the other level" is assumed to be low level "L", but this may be reversed.

Dominant is defined to have a long low level "L" period and a short high level "H" period, and recessive has a short low level "L" period and a long high level "H" period. Specifically, the low level "L" period of the dominant PWM signal is defined to be longer than the low level "L" period of the recessive PWM signal by 6% or more. In the bus line 5, when the recessive and the dominant collide, the dominant has priority. At this time, the communication nodes (for example, 2 to 4) on the receiving side can accurately receive the dominant/recessive by appropriately setting the sampling point SP.

In this bus line 5, a period in which the recessive continues for more than the allowable bit (11 bits or more in this embodiment) is called an IFS (Inter Frame Space), and a state in which IFS is detected is an idle state. In this communication system Sy, when the bus line 5 is in an idle state, each of the communication nodes 1 to 4 is stipulated to be able to transmit data. For example, 3) stops the transmission process, and only the communication node (eg, 2) that wins the arbitration continues the transmission process. That is, this communication system Sy employs so-called CSMA/CA access control.

A frame used for transmission/reception among a plurality of communication nodes 1 to 4 includes a header for designating data to be permitted to be transmitted and a variable-length response for transmitting the data designated by the header. The header has a data identifier, and the outcome of bus arbitration is determined according to the value of this identifier. On the other hand, the response contains original data, and in addition to this data, contains size information indicating the size of the data, parity code for checking the presence or absence of errors, and the like.

The master node 1 supplies the other communication nodes 2 to 4 with a recessive signal having a logical 1L width based on the PWM signal described above to the bus line 5 as a clock. The slave nodes 2 to 4 execute communication synchronous with the clock supplied via the bus line 5 .

FIG. 3 schematically shows block configurations of the master node 1 and the slave node 2. As shown in FIG. Since the master node 1 and the slave nodes 2 to 4 have almost the same configuration, the same reference numerals are given to the same parts for explanation. Also, since the slave nodes 2 to 4 have the same configuration, only the configuration of the slave node 2 will be described below, and the description of the configurations of the other slave nodes 3 to 4 will be omitted.

As shown in FIG. 3, the master node 1 and the slave node 2 are equipped with a signal processor 11 and a transceiver 12 . The transceiver 12 includes a digital processing unit 16 including an arbitration circuit 13, an encoding circuit 14, and a decoding circuit 15, a transmission buffer 17, a reception buffer 18, an oscillation circuit 23, and a timing control circuit 24. The decoding circuit 15 is a block that functions as a decoding section.

The signal processing unit 11 is mainly composed of a microcomputer having a CPU 19, a memory 20 as a non-transitional substantive recording medium, and an I/O 21, and a communication unit 22 based on a UART (Universal Asynchronous Receiver Transmitter) that realizes serial communication. It has The memory 20 is composed of volatile memory such as RAM and non-volatile memory such as ROM and EEPROM.

The oscillation circuit 23 generates a clock signal using, for example, a CR oscillation circuit, and supplies the clock signal to the timing control circuit 24 .

The timing control circuit 24 controls the timing required for the operation of the digital processing section 16 . The timing control circuit 24 is a circuit that generates a timing signal synchronized with the internal clock of the oscillation circuit 23 by dividing the clock generated by the oscillation circuit 23. For example, a plurality of inverters are connected in a ring. It is configured using a ring oscillator (not shown) configured by As this timing signal, a signal with a significantly higher frequency than the frequency (baud rate) of each bit representing communication data is generated. The timing control circuit 24 of the master node 1 supplies an internal clock set to approximately the same speed (about ±1%) as the bit rate of the communication unit 22 .

FIG. 4 shows the structure of frames transmitted and received between the signal processing unit 11 and the transceiver 12. As shown in FIG. As shown in FIG. 4, the signal processing unit 11 has a total of 10 bits composed of a start bit Sta indicating the start of data, a stop bit Sto indicating the end of data, and 8-bit data between them. block data is sent and received as one unit. The 8-bit data is set so that the head is LSB and the end is MSB. The header constituting the aforementioned frame is composed of one block data, 7 bits of the 8-bit data are used as an identifier, and the remaining 1 bit is used as a parity bit. A response is composed of one or a plurality of block data, and size information is recorded in the first block data to be transmitted.

The signal processing unit 11 outputs transmission data TXD in NRZ code to the encoding circuit 14 of the transceiver 12 . The encoding circuit 14 encodes the transmission data TXD supplied from the signal processing unit 11 into transmission data TX of a PWM signal, and outputs the transmission data TX to the bus line 5 through the transmission buffer 17 .

More specifically, the encoding circuit 14 performs different processing for the master node 1 and the slave node 2 . The encoding circuit 14 of the master node 1 has a low level "L" for a short time (that is, a duty ratio is small) so that it becomes recessive when the transmission data TXD supplied from the signal processing unit 11 becomes logic "1". Generate a PWM signal. The encoding circuit 14 of the master node 1 generates a PWM signal of low level "L" for a long time (that is, with a large duty ratio) so as to be dominant when the transmission data TXD is logic "0". Then, the encoding circuit 14 outputs it to the bus line 5 through the transmission buffer 17 as transmission data TX.

When there is no transmission data TXD supplied from the signal processing unit 11, the encoding circuit 14 of the master node 1 has a low level "L" for a short time (that is, duty ratio ) is output to the bus line 5 as transmission data TX. That is, the master node 1 outputs recessive to the bus line 5 when there is no data to be transmitted.

On the other hand, in the slave node 2, when the communication unit 22 of the signal processing unit 11 sets the transmission data TXD to logic "0", as shown in FIG. is output to the encoding circuit 14 . Further, the communication unit 22 of the signal processing unit 11 outputs a high level “H” to the encoding circuit 14 during the entire 1-bit period when the transmission data TXD is set to logic “1”.

When the transmission data TXD supplied from the signal processing unit 11 is logic "1" and the transmission data TXD is high level "H" during one bit period, the encoding circuit 14 of the slave node 2 converts the bus line 5 is maintained at the high level "H". As a result, the signal level of bus line 5 depends on the output of master node 1 .

Conversely, the encoding circuit 14 of the slave node 2 detects that the transmission data TXD supplied from the signal processing unit 11 is logic "0" and that the transmission data TXD is low level "L" during one bit period. , the transmission data TX is set to low level "L" from the timing when the falling edge of the bus line 5 is detected, and then the duration of the dominant low level "L" is measured. ” as transmission data TX.

Then, when the slave node 2 superimposes the transmission data TX on the bus line 5 to which the master node 1 outputs recessive, recessive is output to the bus line 5 when the transmission data TX is logic "1". A dominant is output to the bus line 5 when it is logic "0".

For example, as shown in FIG. 5, the master node 1 continues to output recessive as a clock to the bus line 5 while it is in the normal idle state. While the master node 1 is in an idle state by continuously outputting recessive, the slave node 2 can output a dominant to the bus line 5 by outputting a dominant.

Further, as shown in FIG. 3, in the master node 1 and the slave node 2, the decoding circuit 15 of the transceiver 12 converts the reception data RX of the PWM signal acquired from the bus line 5 through the reception buffer 18 into the reception data RXD in NRZ code. , and input to the communication unit 22 of the signal processing unit 11 .

At this time, the decoding circuit 15 measures the duration of the low level "L" (corresponding to the other voltage level) starting from the falling timing of the reception data RX, and the duration of this low level "L" corresponds to the sampling point SP. When the decoding threshold Tth of the sampling point SP is equal to or less than the duration of the low level "L", it is determined as logic "1" (corresponding to the first code), and the decoding threshold Tth of the sampling point SP is determined as If it is longer than the duration of the low level "L", it is determined as logic "0" (corresponding to the second code) and decoded. This sampling point SP indicates the sampling timing corresponding to the decoding threshold Tth.

The decoding circuit 15 then outputs the decoding result to the signal processing section 11 . The arbitration circuit 13 compares the transmission data TXD and the reception data RXD bit by bit, and stops supplying the transmission data TXD to the encoding circuit 14 when the signal levels do not match. is configured to be in receive mode. The signal processing unit 11 executes various processes assigned to its own communication node (eg, 2) based on information obtained from other communication nodes (eg, 3).

FIG. 6 shows a configuration example of the decoding circuit 15. As shown in FIG. The decoding circuit 15 includes a first memory 25 as a first storage section, a second memory 26 as a margin time storage section, a low width write control section 27 as a level duration update section and an initialization section, and an adder. 28, a margin write control unit 29 as a margin time calculator and a margin time update unit, a comparator 30 as a setting unit, a bit timer 31 as a second measuring unit, a level timer 32 as a first measuring unit, and edge detection. Along with the unit 33 and comparators 34 and 35, it includes an garbled bit detection arithmetic circuit 36 as a garbled bit detector, and an arithmetic result register 37. FIG. A comparator 35 is a block that functions as an initialization section.

The first memory 25 is a memory that stores the duration of the recessive low level “L” (hereinafter referred to as logic 1L width), and is rewritten by the low width write controller 27 . Each time a logic "1" is decoded, the first memory 25 is sequentially updated with a logic 1L width.

The second memory 26 stores margin time TB×MJ (%) defined based on the difference between the duration of low level "L" in the dominant (hereinafter referred to as logic 0L width) and the logic 1L width. The margin write control unit 29 controls rewriting. The margin MJ (%) is a predetermined value of 6% or less that is predefined based on the difference between the logic 0L width and the logic 1L width, and is a margin ratio provided to prevent erroneous sampling. In the second memory 26, margin time TB×MJ (%) is sequentially updated bit by bit.

The adder 28 adds the stored value REG_L of the first memory 25 and the stored value REG_TB of the second memory 26 to calculate the decoding threshold Tth, and outputs it to the comparator 30 . The edge detector 33 detects falling edges and rising edges of the received data RX and outputs them to the level timer 32 . Also, the edge detector 33 outputs the detected falling edge of the received data RX to the bit timer 31 . In this embodiment, the "falling edge" is called a periodic edge PE because it occurs in each 1-bit period of the received data RX. The "rising edge" is called a data edge DE because the timing changes according to the recessive/dominant of the received data RX.

The bit timer 31 measures the time TB between two consecutive period edges PE in the received data RX, and outputs this time TB to the margin write controller 29. The margin write controller 29 controls this time The margin time TB×MJ (%) calculated by multiplying TB by the margin MJ (%) is stored in the second memory 26 .

On the other hand, the level timer 32 measures the time TL from the period edge PE of the received data RX to the next data edge DE, and outputs the measured time TL to the comparators 30 and 34 and the row width write controller 27. do. After receiving the time TL measured by the level timer 32 and the decoding threshold Tth of the adder 28, the comparator 30 compares the received data RXD at a predetermined timing until the arrival of the next periodic edge PE. to output

The decoding threshold Tth of the sampling point SP is set to the time TL+TB×MJ (%) obtained by adding the margin time TB×MJ (%) to the time TL from the period edge PE to the next data edge DE. At this time, when the measured value TL of the level timer 32 is equal to or less than the decoding threshold value Tth of the sampling point SP, the comparator 30 determines logic "1" for decoding, and when it exceeds the decoding threshold value Tth of the sampling point SP, the comparator 30 determines logic "0". ', decodes and outputs received data RXD.

The garbled bit detection arithmetic circuit 36 always performs arithmetic processing for detecting whether or not the stored value REG_L of the first memory 25 has garbled bits, and stores the result of this arithmetic operation in the arithmetic result register 37 . Therefore, for example, every time the stored value REG_L of the first memory 25 is updated, the calculation result of the garbled bit detection calculation circuit 36 is updated in the calculation result register 37 .

The row width write controller 27 is configured to store, delete, or update the logical 1L width in the first memory 25 . The row width write control unit 27 executes the processing shown in FIG. 7 each time the measured value TL is input from the level timer 32 . In FIG. 7, the row width write controller 27 determines whether or not the logical 1L width has been stored in the first memory 25 (S11), and if not stored, sets the counter CNT to 0 to clear it. (S12). This counter CNT is built in the row width write control unit 27 and counts the number of consecutive dominants (logic "0"). If the logical 1L width is not stored in the first memory 25, the measured value TL output from the level timer 32 is stored as the logical 1L width in the first memory 25 for initialization (S13), and write control is performed. finish.

When the row width write control unit 27 determines in S11 that the logic 1L width is stored in the first memory 25 (S11: YES), it determines whether the value of the logic 1L width is garbled. The determination result of the comparator 35 is referred to (S14), and if garbled bits have occurred, the measured value TL supplied from the level timer 32 is again stored in the first memory 25 as a logic 1L width in S12 and S13. . This allows the previous logical 1L width REG_L stored in the first memory 25 to be initialized.

When the row width write control unit 27 determines that the logic 1L width is correctly stored, it determines NO in S14. Thereafter, the low width write control unit 27 determines whether or not the received data RXD output by the comparator 30 is logic "1" (S15). Execute the process.

The row width write control unit 27 clears the counter CNT (S16), and the comparator 34 compares the value REG_L stored in the first memory 25 (hereinafter referred to as the previous logical 1L width REG_L as necessary) with the current value REG_L. is compared with the measured value TL of the logical 1L width (S17). When the previous logic 1L width REG_L is larger than the current logic 1L width measurement value TL (YES in S17), the row width write control unit 27 calculates the previous logic 1L width REG_L-1LSB (S18), The calculated logic 1L width is updated as the stored value REG_L of the first memory 25 (S19), and the process ends.

When the result of the comparison in S17 is NO, the low width write control unit 27 determines whether or not the previous logic 1L width REG_L is the same as the current logic 1L width measurement value TL. (S20). When the row width write control unit 27 determines that the previous logical 1L width REG_L is the same as the measured value TL (S20: YES), the measured value TL of the level timer 32 (=previous logical 1L width REG_L) is set to the first value. The stored value REG_L in the memory 25 is updated (S21, S19) and the process ends.

Further, when the previous logic 1L width REG_L is smaller than the current logic 1L width measurement value TL as a result of the comparison in S17 and S20 (NO in S20), the row width write control unit 27 The load control unit 27 calculates the previous logic 1L width REG_L+1LSB (S22), updates it as the stored value REG_L of the first memory 25 (S19), and terminates. In this S22, the stored value REG_L of the first memory 25 may be updated to the same value as the measured value TL of the level timer 32 (=previous logic 1L width REG_L).

When the low width write control unit 27 determines in S15 that the received data RXD output by the comparator 30 is logic "0" (S15: NO), the low width write control unit 27 increments the counter CNT (S23). It is determined whether or not the value of CNT is less than a preset upper limit value (eg, 10) (S24). This upper limit value is determined because logic "0" does not continue for 10 bits or more. (S25), end.

Thereafter, the row width write control unit 27 repeats the processing shown in FIG. 7 many times, thereby repeatedly updating the logical 1L width REG_L stored in the first memory 25. At this time, , even if the logic 1L width REG_L changes, it will change only by ±1LSB. Therefore, even if it is affected by chattering noise, logic "0"/logic "1" can be determined using sampling points SP that have changed slightly, and the risk of erroneous sampling can be eliminated. Moreover, the logic 1L width TL can be relatively learned by about ±1LSB compared to the previous logic 1L width REG_L, and can be learned without erroneous sampling.

<Processing Contents of Bit Garbage Detection Arithmetic Circuit 36>
The content of the garbled bit detection processing executed by the garbled bit detection arithmetic circuit 36 will be described below with reference to FIG. The low width write control unit 27 updates the logic 1L width to the first memory 25 on condition that the edge detection unit 33 has detected the period edge PE of the received data RX (timings t0, t10, t20 in FIG. 8). .

The garbled bit detection arithmetic circuit 36 always calculates the number of 1s by referring to the 2-bit data in the first memory 25 (timings t1, t11, t21 in FIG. 8). The calculation result register 37 stores the calculation result by the garbled bit detection calculation circuit 36 at the timing immediately after the period edge PE is generated (timings t1 and t11 in FIG. 8).

The comparator 35 compares and collates the calculation result calculated by the garbled bit detection calculation circuit 36 and the calculation result stored in the calculation result register 37 . If these calculation results match, the comparator 35 outputs data indicating that no garbled bits have occurred to the low-width write controller 27. If they do not match, the comparator 35 outputs garbled bits. is output to the row width write control unit 27 .

At this time, it is assumed that the data stored in the first memory 25 is changed due to some influence at timing t12 in FIG. When the data stored in the first memory 25 changes, the garbled bit detection arithmetic circuit 36 performs parity arithmetic processing immediately after the change. However, since this calculation result is stored in the calculation result register 37 immediately after the generation timing t20 of the next periodic edge PE, it is not stored in the calculation result register 37 at timings t12 and t13. Therefore, even if the comparator 35 compares and collates these operation results, the operation results do not match. (refer to timing t13 onward in FIG. 8). As a result, the garbled bit detection process can be reliably executed.

<Technical significance>
Further, the technical significance will be explained with reference to FIGS. 9 and 10. FIG. FIG. 9 is an explanatory diagram of a comparative example for explaining the effect of the configuration of this embodiment. The sampling point SP is set at a timing obtained by adding the margin time TB×MJ (%) (=predetermined time Ta) to the time TL from the period edge PE to the data edge DE.

At this time, as shown in the period T1, if the measured value TL is determined normally, the decoding threshold value Tth (=(measured value TL of the level timer 32)+(bit timer 31) is detected from the period edge PE of the bus line 5. The signal on the bus line 5 is sampled with the timing at which the measured value TB)×MJ (%)) has passed as the sampling point SP. During the period T1 in FIG. 9, when the signal on the bus line 5 is sampled at the sampling point SP, it becomes high level "H". Therefore, the reception data RXD becomes recessive.

However, as shown during period T2 in FIG. 9, when external noise such as chattering occurs in bus line 5, edge detector 33 detects falling/rising edges based on error Δ. During the period T2, the margin time TB×MJ (%) is calculated by multiplying the measured value TB of the bit timer 31 measured during the previous period T1 by the margin ratio MJ (%). MJ (%) (=predetermined time Ta) has a normal magnitude. During the period T2, the bit timer 31 calculates the time TB between two periodic edges PE based on the error Δ, and the level timer 32 calculates the interval TL between the periodic edge PE and the data edge DE based on the error Δ. Therefore, both the time TB and the interval TL are calculated to be short according to the influence of this error Δ.

For this reason, when the shortened time error based on the influence of this error Δ is set to "G", the sampling point SP in the subsequent period T3 is determined from the falling timing of the bus line 5 to the decoding threshold Tth (={(level timer 32's Measured value TL)-G}+(Measured value TB of bit timer 31)×MJ (%)) becomes sampling point SP corresponding to. For this reason, if the shortened time error G is large, the sampling point SP does not come to an appropriate timing, and although it is originally logic "1" (recessive), it is determined to be logic "0" (dominant). I will put it away.

On the other hand, according to the present embodiment, external noise such as chattering occurs in the bus line 5 as shown in period T11 in FIG. Even if this is done, the storage value REG_L of logical 1L width in the first memory 25 is reduced by 1LSB only by performing the processing of S16 to S18 shown in FIG. When the stored value REG_L of logical 1L width is updated, the adder 28 updates the decoding threshold Tth in the subsequent period T12 (see period T12 in FIG. 10).

As shown in the period T12 in FIG. 10, the sampling point SP is set at the decoding threshold Tth (=(measurement value TL of level timer 32)-1LSB+(measurement value TB of bit timer 31) from the fall timing of the signal on bus line 5. xMJ (%)) is the sampling point SP. Therefore, the sampling point SP can be appropriately updated according to the magnitude of the previous logic 1L width REG_L and the current measurement value TL by the level timer 32 . As a result, even if disturbance noise is input to the bus line 5, it is possible to reduce the possibility of erroneous decoding.

In the configuration of this embodiment, the decoding threshold Tth is changed by ±1 LSB, but this sampling point SP does not differ greatly from the time of the sampling point SP in the previous period T11 (period T12 in FIG. 10). reference). Therefore, it is possible to eliminate the possibility that the sampling point SP will immediately change in the direction of losing all of the margin time TB×MJ (%).

<Summary of this embodiment, effect>
As described above, according to the present embodiment, the row width write control unit 27 controls the first logical width REG_L measured by the level timer 32 based on the comparison between the previous logical 1L width REG_L and the current measured value TL. By updating the logic 1L width REG_L stored in the memory 25, the decoding threshold Tth of the sampling point SP is updated. The sampling point SP is appropriately updated and set according to the magnitude of the previous logical 1L width REG_L and the current measurement value TL by the level timer 32 . Therefore, even if disturbance noise is input to the bus line 5, it is possible to reduce the possibility of erroneous decoding.

Further, the row width write control unit 27 repeats the updating process of the logic 1L width REG_L many times, thereby gradually updating the logic 1L width REG_L stored in the first memory 25. At this time, Even if the logic 1L width REG_L changes, it will only change by ±1LSB. Therefore, even if the signal flowing through the bus line 5 is affected by chattering noise, logic "0"/logic "1" will be determined at the slightly updated sampling point SP, resulting in erroneous sampling. It is possible to eliminate the risk of Moreover, the logic 1L width TL can be learned relatively within ±1LSB as compared with the previous logic 1L width REG_L, and can be learned to the extent that erroneous sampling does not occur.

Since the garbled bit detection arithmetic circuit 36 for detecting garbled bits in the value stored in the first memory 25 is provided, even if there is an error in the previous logic 1L width REG_L stored in the first memory 25, the error is detected. can.

Further, when garbled bits are detected by the garbled bit detection arithmetic circuit 36, the low width write controller 27 initializes and stores in the first memory 25 the measured value TL of the duration of the low level "L" of the bus line 5. Therefore, even if an error occurs in the logical 1L width stored in the first memory 25, the stored logical 1L width can be initialized.

(Second embodiment)
11 to 12 show additional explanatory diagrams of the second embodiment. FIG. 11 shows another configuration example of the decoding circuit 15 as a decoding circuit 115. As shown in FIG. This decoding circuit 115 includes a comparator 40 in addition to the components of the decoding circuit 15 described in the first embodiment.

The comparator 40 is a block that outputs the comparison result between the measured value TB of the bit timer 31 and the margin time TB×MJ (%) stored in the second memory 26 to the margin write controller 29 . The margin write controller 29 writes the margin time TB×MJ (%) into the second memory 26 based on the measured value TB of the bit timer 31 and the comparison result of the comparator 40 . Since other configurations are the same as those of the first embodiment, description thereof is omitted. Hereinafter, the margin time TB.times.MJ (%) written in the second memory 26 will be referred to as "previous margin time REG_TB" as required.

The margin write control unit 29 executes the processing shown in FIG. 12 each time the measured value TB is input from the bit timer 31 . In FIG. 12, the margin write control unit 29 determines whether or not the previous margin time REG_TB is stored in the second memory 26 (S21), and if not stored (S21: NO), the bit timer Measured value TB input from 31 is multiplied by margin MJ (%), and this margin time TB×MJ (%) is stored in second memory 26 for initialization (S22).

If the margin write control unit 29 determines that the previous margin time REG_TB is stored, it determines YES in S21. After that, the margin write control unit 29 multiplies the current measurement value TB by the margin MJ (%) to calculate the current margin time TB×MJ%, and outputs it to the comparator 40 . The comparator 40 compares the previous margin time REG_TB stored in the second memory 26 with the current margin time TB×MJ (%) (S23), and sends the comparison result to the margin write control unit 29. Output.

When the previous margin time REG_TB is greater than the current margin time TB×MJ (%) (YES in S23), the margin write control unit 29 calculates the previous margin time REG_TB−1LSB, , the margin time REG_TB is updated (S24, S25) and the process ends. That is, the margin write control unit 29 subtracts the time of the clock signal corresponding to 1 LSB from the margin time REG_TB, and writes the result into the second memory 26 .

Further, when the comparison result of the comparator 40 is input and the result of S23 is NO, the margin write control unit 29 determines whether or not the previous margin time REG_TB is the same as the current margin time TB×MJ (%). is determined (S26). When these values are the same (YES in S26), the margin write control unit 29 stores the current margin time TB×MJ (%) (=previous margin time REG_TB) as the margin time REG_TB in the second memory 26. Update (S27, S25) and end.

Furthermore, as a result of comparison in S23 and S26, when the previous margin time REG_TB is smaller than the current margin time TB×MJ (%) (NO in both S23 and S26), the margin write control unit 29 The margin time REG_TB+1LSB is calculated, and the margin time REG_TB is updated in the second memory 26 (S28, S25). That is, the margin write control unit 29 adds the time of the clock signal corresponding to 1 LSB to the margin time REG_TB and controls writing to the second memory 26 . In this S28, the margin write control unit 29 sets the same value as the margin time TB×MJ (%) (=previous margin time REG_TB) derived from the measured value TB of the bit timer 31 as the margin time REG_TB in the second memory. You can update to 26.

As in the first embodiment, a second garbled bit detection circuit (not shown) for the stored content of the second memory 26 is newly provided, and this second garbled bit detection circuit Bit corruption in the margin time REG_TB may be detected. In this case, when the second garbled bit detection circuit refers to the second memory 26 and determines that garbled bits have occurred, the margin time TB×MJ (%) newly calculated by the margin write control unit 29 is It is preferable to newly store it in the second memory 26 . Such processing shown in FIG. 12 is repeated.

As described above, according to the present embodiment, the margin write control unit 29 combines the previous margin time REG_TB stored in the second memory 26 with the current margin time calculated by the margin write control unit 29. Based on the comparison with TB×MJ, the margin time TB×MJ (%) is repeatedly updated. Therefore, the margin time TB×MJ (%) can also be repeatedly updated, and the margin time TB×MJ (%) can be learned repeatedly.

(Other embodiments)
The present invention is not limited to the above-described embodiments, and can be modified or expanded, for example, as follows.
In the above-described embodiment, an error detection technique using a parity check is used, but error detection can also be performed using a CRC (Cyclic Redundancy Check) code, or an ECC (Error Correction Code) code or the like can be used for error correction. It is also possible to correct errors using techniques that In the above-described embodiment, the first code is logic "1" and the second code is logic "0", but these may be reversed.

In the above-described embodiment, the logic 1L width is used for determination, but instead of this, the logic "1" high "H" time width may be used for determination. That is, in the above-described embodiment, the duration of the low level "L" is measured from the timing when one high level "H" changes to the other low level "L", and this measured value and the decoding threshold value Tth of the sampling point SP are measured. However, instead of this, from the timing when one low level "L" changes to the other high level "H", the other high level It can also be applied to a communication device that measures the duration of level "H" and compares this measured value with the decoding threshold value Tth of the sampling point SP to determine logic "1"/logic "0".

In the above-described second embodiment, the form of learning the margin time TB×MJ (%) is shown, but the period TB of the clock of the bus line 5 is also repeatedly updated in the second memory 26 or the like as a learning object. You can make it work. That is, the margin write control unit 29 inputs the measured value TB from the bit timer 31 to measure the clock cycle TB, and repeatedly updates the clock cycle TB of the bus line 5 in the second memory 26. It may be configured to function as In this case, the period TB can be repeatedly updated.
In the above-described embodiment, an up-counter or a down-counter may be used as the clock to measure the duration of the low level "L". When a down counter is used, it is preferable to reset the previous initial value when the periodic edge PE is detected, and to count down the low level "L".

The configurations and functions of the multiple embodiments described above may be combined. A mode in which part of the above embodiment is omitted as long as the problem can be solved can also be regarded as an embodiment. In addition, all conceivable aspects can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the language in the claims.

Although the present disclosure has been described in accordance with the embodiments described above, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of this disclosure.

In the drawing, 5 is a bus line, 15 and 115 are decoding circuits (decoding units), 25 is a first memory (first storage unit), 26 is a second memory (margin time storage unit), and 27 is a row width write. 29 is a margin write control unit (margin time calculation unit, margin time update unit, period update unit); 30 is a comparator (setting unit); 31 is a bit timer; (second measuring unit), 32 is a level timer (first measuring unit), 35 is a comparator (initializing unit), and 36 is an erroneous bit detection arithmetic circuit (erroneous bit detection unit).

Claims (7)

a first measuring unit (32) for measuring the duration of the other level from the timing when one of the binary levels flowing on the bus line (5) changes to the other level;
a first storage unit (25) that stores the measured value of the first measurement unit;
a setting unit (30) for setting a sampling point (SP) for sampling the signal on the bus line at a decoding threshold value (Tth) obtained by adding a margin time (TB×MJ) to the stored value (REG_L) of the first storage unit; ,
If the decoding threshold is less than or equal to the measured value (TL) of the first measuring unit based on the sampling operation, it is determined that the code is the first code, and the decoding threshold is greater than the measured value of the first measuring unit. a decoding circuit (15, 115) that determines that it is the second code when
The first storage unit has a mechanism for storing when the measured value (TL) of the first measurement unit is determined to be the second code by the decoding circuit,
repeatedly updating and setting the stored value (REG_L) based on a comparison between the previous stored value (REG_L) stored in the first storage unit and the current measured value (TL) measured by the first measurement unit Communication device. a second measuring unit (31) for measuring a period (TB) of a binary level periodic edge (PE) flowing on the bus line;
A margin time calculation unit (a margin time calculation unit ( 29) and
a margin time storage unit (26) for storing the margin time;
repeating the margin time based on comparing the previous margin time (REG_TB) stored in the margin time storage unit and the current margin time (TB×MJ) calculated by the margin time calculation unit; The communication device according to claim 1, further comprising: an updating margin time updater (29). a second measuring unit (31) for measuring a period (TB) of a binary level periodic edge (PE) flowing on the bus line;
2. The communication device according to claim 1 , further comprising a period updating section (29) that updates the period measured by the second measuring section. 3. The communication device according to claim 2 , further comprising a period updating section (29 ) for updating the period measured by the second measuring section. 5. The communication device according to any one of claims 1 to 4 , further comprising a second level duration update section (27) that updates the stored value (REG_L) of the first storage section. 6. The communication device according to any one of claims 1 to 5 , further comprising an garbled bit detection section (36) for detecting garbled bits in the value stored in the first storage section. When the garbled bit detection unit detects the garbled bit, the measured value of the previous measurement time of the other level of the first storage unit is initialized, and the measured value of the continuation time of the other level of the bus line is initialized. 7. The communication device according to claim 6 , further comprising an initialization unit (35, 27, S14, S13) for storing in the first storage unit.

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