JP7161509B2 - gate drive circuit - Google Patents

Description

The present invention relates to gate drive circuits for driving power switches such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field effect transistors).

With the demand for energy saving in recent years, photovoltaic power generation and wind power generation are becoming important in terms of energy supply. A gate drive circuit is used to drive the high power switch used in such power equipment.
Such high-power switches need to be turned on/off at high speed (nsec level accuracy). In other words, the switching frequency of electric power equipment tends to be higher due to demands for weight reduction, space saving, low cost, and the like. Power switches used under such conditions must also switch fast.
Semiconductors such as IGBTs, SiC-MOSFETs, and GaN are used for power switches. Semiconductors such as these IGBTs have a large input capacitance at their drive terminals (gate terminals). The gating circuitry of high power power switches is generally capacitive, and the higher the power capacity, the higher the capacitance.

Therefore, a large current flows at the beginning of driving the power switch. Therefore, a high-speed switch that drives such a power switch must be capable of switching large currents at high speed. Due to the recent demand for energy saving, there is a demand for further weight reduction of the apparatus and further speedup. As a result, drive circuits for high-speed switching of power switches are increasingly required to have the ability to instantaneously supply a large current.
On the other hand, the control circuit of the power equipment cannot supply such a large current directly to the high power switch. Therefore, between the control circuit and the high-power switch, a gate drive circuit that performs current amplification and voltage amplification at high speed is usually required. SUMMARY OF THE INVENTION The present invention is a switch circuit used in such a gate drive circuit, and an object thereof is to provide a gate drive circuit capable of realizing faster switching.

Prior Patent Technique For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 03-286619), which will be described later, discloses a gate driving circuit for driving a semiconductor having an insulated gate. In particular, a configuration is disclosed in which a reverse blocking switch is provided in the middle of wiring for supplying charges from a power source to a gate, and an inductance element is provided between the reverse blocking switch and the gate. This configuration is said to enable high-speed switching by causing resonance between the gate capacitance and the inductance of the inductance element.

Patent Document 2 (Japanese Laid-Open Patent Publication No. 04-176209), which will be described later, discloses a configuration in which charges are supplied via a diode to turn on a MOS (metal-oxide-semiconductor) transistor. As a result, a MOSFET (metal-oxide-semiconductor field-effect transistor) that has been turned ON once continues to be turned ON, thereby enabling high-speed switching.

Patent Document 3 (Japanese Patent Application Laid-Open No. 2017-17995), which will be described later, discloses a wireless power supply device including a high-frequency circuit using MISFETs (Metal Insulator Semiconductor Field Transistors) and a resonance circuit connected to the high-frequency circuit. there is It is said that the resonant circuit enables high-speed switching and provides a wireless power supply device with excellent performance.

JP-A-03-286619 JP-A-04-176209 JP 2017-17995 A

A circuit configuration as shown in FIG. 10 is used to amplify a signal from the control circuit at high speed. As shown in FIG. 10, the switch circuit 10 is configured by providing a high side switch 11 on the positive side of the power supply and a low side switch 12 on the negative side of the power supply. An input terminal 13 for inputting a control signal from a control circuit (not shown) is connected to the high side switch 11 and the low side switch 12 . This constitutes a circuit that drives the high-side switch 11 and the low-side switch 12 with a control signal (or called an "ON/OFF signal") from the control circuit.

In FIG. 10, the output terminal 14 is further connected to the high side switch 11 and the low side switch 12 and outputs an output signal for driving the IGBT 15 . A P-AMP 16 for power amplification is provided between the output terminal 14 and the IGBT 15 (see FIG. 10).

However, if the control signal from the control circuit is directly connected to the high side switch 11 and the low side switch 12, each switch (high side switch 11 and low side switch 12) may be turned on at the same time.

The reason for this is that the control signal from the control circuit, as shown in FIG. This is because During this period, the voltage of the control signal is an input voltage (referred to as an ON operation voltage) that causes both the high-side switch 11 and the low-side switch 12 to turn ON. As a result, both switches are simultaneously turned ON during this period.

FIG. 11 is a graph showing ON/OFF states of the high-side switch 11 and the low-side switch 12 when the control signal changes. In the graph of FIG. 11, the horizontal axis indicates the passage of time, and the vertical axis indicates each signal.
For example, if the threshold voltage at which the high-side switch 11 is switched ON/OFF is VHg, and the threshold voltage of the low-side switch 12 is VLg, the period when the output voltage of the control circuit changes from VLg to (Vdc−VHg) is It will be in the ON operation state. That is, since both the high-side switch 11 and the low-side switch 12 are in the ON state during the period of time t1 to t2 shown in FIG. 11, a through current is generated from Vdc to Vee.

Method Using Level Shift Circuit One method of preventing such through current is to use a level shift circuit. An example of a circuit using level shifting circuitry is shown in FIG. 12A. The level shift circuit is a circuit that shifts the DC level of the signal of the high-side switch 11 in the direction of increasing the constant voltage. By using such a level shift circuit, it is possible to eliminate the time zone in which both switches are simultaneously turned on as shown in FIG.
12A differs from the diagram of FIG. 10 in that a level shift circuit 20 is provided. That is, the switch circuit 10a of FIG. 12A differs from the switch circuit 10 of FIG. 10 in that the level shift circuit 20 is provided. Note that FIG. 12A shows a control circuit 21 that applies a control signal to the input terminal 13 .

FIG. 12B depicts a time chart showing how the level shift circuit 20 performs level shifting. In the time chart of FIG. 12B, the horizontal axis indicates the passage of time, and the vertical axis indicates the output signal of the level shift circuit 20 applied to the high side switch 11 and the control circuit 21 applied to the low side switch 12. and the state of the output signal (control signal) of each are exemplified.
As shown in FIG. 12B, in this example, the output signal (control signal) of the control circuit 21 is a 10Vp-p signal that swings from the GND level to 10V. On the other hand, the output signal of the level shift circuit 21 is a 10Vp-p signal that swings in the range from the positive side voltage (Vdc) to Vdc-10V as a result of shifting the voltage by the shift voltage. As a result of level shifting in this manner, the high-side switch 11 is turned off at an earlier timing, and turned on later.

As a result, as shown in FIG. 12B, the low-side switch 12 is turned on after a predetermined dead time has elapsed since the high-side switch 11 was turned off. Conversely, the high side switch 11 enters the ON state after a predetermined dead time has passed since the low side switch 12 was turned OFF.
As described above, in the example shown in FIG. 12, the level shift circuit is used to shift the ON/OFF timing of the high-side switch 11, so that a dead time is provided in which both switches are in the OFF state. be able to. Therefore, it is possible to prevent a through current from occurring.

Method Using Dead Time As another method for preventing through current, there is a method in which a dead time is provided in advance in the control signal itself. Explanatory diagrams of how to create this dead time are shown in FIGS. 13A and 13B.
FIG. 13A is a circuit diagram when this method is adopted. Unlike the switch circuit 10 of FIG. 10, the switch circuit 10b shown in FIG. 13A has two types of input terminals. That is, as shown in FIG. 13A, the switch circuit 10b has two types of input terminals 13a for control signals to be supplied to the internal high-side switch 11 and input terminals 13b for control signals to be supplied to the low-side switch 12. input terminal.
The control circuit 21a performs two types of control, an ON/OFF signal for the high side switch 11 (high side switch control signal IN1) and an ON/OFF signal for the low side switch 12 (low side switch control signal IN2). A signal is output and supplied to each switch to drive both switches.

By providing a dead time in advance between the high-side switch control signal IN1 and the low-side switch control signal IN2, the period during which each switch is ON is longer than the period during which it is OFF. set a little shorter. As a result, it is possible to eliminate the time zone in which both switches are simultaneously turned on. A time chart illustrating such timing is shown in FIG. 13B.
FIG. 13B depicts a time chart showing the state of each signal when the control circuit 21 outputs two types of control signals with dead time. In the time chart of FIG. 13B, the horizontal axis indicates the passage of time, and the high-side switch control signal IN1 and the low-side switch control signal IN2 are shown side by side in the vertical direction.
As shown in FIG. 13B, in this example, the control circuit 21a changes the high-side switch control signal IN1 to a value at which the high-side switch 11 is turned off, and after a predetermined dead time has passed, this time The low-side switch control signal IN2 is changed to a value at which the low-side switch 12 is turned on.

Further, the control circuit 21a changes the low-side switch control signal IN2 to a value at which the low-side switch 12 is turned off, and after a predetermined dead time elapses, the control circuit 21a changes the high-side switch control signal IN1 to the high-side switch. It is changed to a value that causes the switch 11 to turn ON.
The control circuit 21a outputs the high-side switch control signal IN1 and the low-side switch control signal IN2 so that the high-side switch 11 and the low-side switch 12 are alternately turned on with a predetermined dead time in between. controlled and output.

As a result, through current flowing through the high-side switch 11 and the low-side switch 12 can be prevented.
Although any of these methods can prevent the through current, the complexity of the circuit and the increase in circuit cost cannot be avoided. SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate drive circuit having a faster switch circuit while using a simpler circuit and suppressing an increase in cost. With the goal.

(1) In order to solve the above problems, the present invention provides a gate drive circuit for driving a semiconductor switch based on a control signal, comprising: an input terminal for inputting the control signal; a switch, a low-side switch connected to a negative power supply, a first differentiating circuit connected to the input terminal and the positive power supply, differentiating the control signal and supplying it to the high-side switch, the input a second differentiating circuit connected to a terminal and the negative side power supply for differentiating the control signal and supplying it to the low side switch; an output terminal for outputting a signal for driving the semiconductor switch; and the high side switch. and the output terminal and connected between a first impedance circuit having an impedance of 0 ohms or more; and a second impedance circuit having an impedance.

(2) Further, the present invention is the gate drive circuit according to (1), wherein the high-side switch includes a pnp-type transistor, the low-side switch includes an npn-type transistor, and the first differentiating circuit includes , the differentiated control signal is supplied to the base of the pnp-type transistor, the second differentiating circuit supplies the differentiated control signal to the base of the npn-type transistor, the first impedance circuit supplies the pnp-type It is connected between the collector terminal of a transistor and the output terminal, and the second impedance circuit is connected between the collector terminal of the npn-type transistor and the output terminal. It is a gate drive circuit.

(3) The present invention also provides the gate drive circuit according to (1) or (2), wherein the collector terminal of either the collector terminal of the pnp-type transistor or the collector terminal of the npn-type transistor is provided. and a zener diode connected between the output terminal and the gate drive circuit.

(4) Further, the present invention is the gate drive circuit according to any one of (1) to (3), wherein the gate drive circuit is connected between the input terminal of the high side switch and the plus side power supply. a semiconductor switch, wherein the semiconductor switch is turned on by a predetermined inhibition signal, connects the input terminal of the high side switch to the plus side power supply, and applies a High voltage to the output terminal regardless of the control signal. It is a gate drive circuit that can prohibit output.

(5) The present invention also provides a gate drive circuit for driving a plurality of semiconductor switches in parallel based on a control signal, comprising: an input terminal for inputting the control signal; and a high side switch connected to a plus side power supply. , a low-side switch connected to a negative side power supply, the input terminal, a first differentiating circuit connected to the positive side power supply, differentiating the control signal and supplying it to the high-side switch, and the input terminal. , a second differentiating circuit connected to the negative side power supply, differentiating the control signal and supplying it to the low side switch; an output terminal for outputting a signal for driving the semiconductor switch; the high side switch; a first impedance circuit connected between the output terminal and having an impedance of 0 ohms or more; and a first impedance circuit connected between the low-side switch and the output terminal and having an impedance of 0 ohms or more. and a second impedance circuit having a gate drive circuit.

According to the present invention, a switch circuit capable of preventing through current with a simpler configuration is realized. Therefore, by using the switch circuit, it is possible to provide a gate drive circuit with a simpler configuration while preventing through current.

2 is a circuit diagram of a switch circuit using a differentiating circuit in Embodiment 1. FIG. FIG. 3 is an explanatory diagram showing an example of a differentiating circuit in Embodiment 1; 2 is a circuit diagram of a specific circuit example of the differentiating circuit of FIG. 1; FIG. 5 is a time chart showing how a signal in a switch circuit using a differentiating circuit in Embodiment 1; 4 is a graph obtained by calculating the input voltage of the high-side switch using Equation (1). FIG. 4 is a circuit diagram of a switch circuit in which a high side switch and a low side switch are configured using bipolar transistors; FIG. 4 is a circuit diagram of a switch circuit using voltage regulator diodes; FIG. 4 is a circuit diagram of a switch circuit in which a P-channel MOSFET is provided between the input terminal of a high-side switch and Vdc; It is a circuit diagram of a concrete gate drive circuit using a switch circuit. It is a circuit diagram of a concrete gate drive circuit using a switch circuit. 1 is a circuit diagram including a conventional switch circuit; FIG. It is a graph when a control signal changes. It is a switch circuit diagram using a conventional level shift circuit. 5 is a time chart showing how level shifting is performed by a conventional level shift circuit; It is a switch circuit diagram using a control signal provided with a conventional dead time. 5 is a time chart showing how a switch circuit using a control signal with a conventional dead time operates;

Preferred embodiments of the present invention will be described below with reference to the drawings.
1. Embodiment 1
This embodiment is a switch circuit used in a gate drive circuit for driving a power switch such as an IGBT or a MOSFET. FIG. 1 shows a circuit diagram of a gate drive circuit comprising a switch circuit 110. As shown in FIG. This gate drive circuit is a gate drive circuit that drives the gate of the IGBT 15 . Here, the IGBT 15 corresponds to a preferred example of the semiconductor switch in the claims. Also, the gate drive circuit may include other circuits with the switch circuit 110 as a main component. For example, P-AMP 16 may be included (see FIG. 1), but may not be included depending on the application. The switch circuit 110 according to the first embodiment is characterized in that differentiating circuits 120 and 121 are connected to the input terminals of the high-side switch 111 and the low-side switch 112 . These differentiation circuits 120 and 121 are similar to the case where the above-described level shift circuit (which shifts the voltage in the positive direction) is inserted on the input side of the high-side switch 111 during the period when the input signal (control signal) rises. produce the effect of Also, in the time period when the input signal falls, the same effect as when a level shift circuit (which shifts the voltage in the negative direction) is inserted on the input side of the low-side switch 112 is produced.

Here, the differentiating circuits 120 and 121 are assumed to be the circuit networks shown in the differentiating circuits 1 to 3 in FIG. 2 or a circuit network in which these circuit networks are connected in parallel. The differentiating circuit 1 in FIG. 2 is a circuit with only a capacitor C, and the differentiating circuit 2 in FIG. 2 is a parallel circuit with a capacitor C and a resistor R. The differentiating circuit 3 of FIG. 2 is a direct circuit of the resistor Ra and the capacitor C and a parallel circuit of the resistor Rb.
Here, if a parallel circuit of a capacitor C and a resistor R (differentiating circuit 2 in FIG. 2), for example, is employed as the differentiating circuits 120 and 121, FIG. 1 described above can be expressed as shown in FIG. 3A.
Note that the impedances Z1 and Z2 in FIG. 1 are omitted and not shown in FIG. 3A. 3A, the differentiating circuit 120 is composed of a parallel circuit of a capacitor C1 and a resistor R1, and a resistor Rg is shown as an input resistor of the high-side switch 111. FIG. 3A, the differentiating circuit 121 is composed of a parallel circuit of the capacitor C2 and the resistor R2, and the resistor Rg is shown as the input resistor of the low-side switch 112. FIG. Also shown in FIG. 3A is a control circuit 131 that outputs a control signal, and the control circuit 131 supplies the control signal to the input terminal 113 .
The gate drive circuit in FIG. 3A mainly includes the switch circuit 110, but the P-AMP 16 may or may not be included in the gate drive circuit.
The differentiating circuit 120 corresponds to a preferred example of the first differentiating circuit in the claims. The differentiating circuit 121 corresponds to a preferred example of the second differentiating circuit in the claims. This also applies to FIGS. 3A, 5, 6, etc., which will be described later.

In FIG. 3A, consider the case where the control signal rises from the Vee potential to the Vdc potential. Let k (V/sec) be the absolute value of the slope of the voltage rise of the control signal at this time.
Also, let t=0 be the time when the control signal starts going from the Vee potential to the Vdc potential. As long as the control signal is in the rising process, the input terminal voltage vhg of the high-side switch 111 and the input terminal voltage vlg of the low-side switch 112 are represented by the following equations (1) and (2), respectively.

From this equation (1), the input terminal voltage of the high-side switch 111 becomes the value of the first term of equation (1) at t=0. It can be seen that even if the voltage of the control signal rises with Vee as the starting point, the starting point of the input voltage of the high-side switch 111 starts from the voltage indicated by the first term in Equation (1). That is, by providing the differentiating circuit 120, it is possible to obtain the same effect as providing a voltage shift circuit, and to prevent a period in which both the high-side switch 111 and the low-side switch 112 are in the ON state.
This is because the differentiating circuit 120 is connected to the plus side power supply Vdc. Since the control signal is differentiated with reference to the plus side power supply Vdc, the voltage shown in the first term of the equation (1) is started.

ただし、

ここで、例として、時定数τ１ ＝ ２００ｎｓｅｃ、図３ＡのＲ１ ＝ ２７ｋΩ、Ｒｇ ＝ ２．２ｋΩ、Ｃ１ ＝ １００ｐＦ、Ｖｄｃ ＝ １５Ｖ、 また、Ｖｅｅ ＝ －１０Ｖとし、制御信号の電圧の上昇率がｋ ＝ ３Ｖ／ｎｓｅｃとする。これらの値を用いて、ハイサイドスイッチ１１１の入力電圧を、式（１）を用いて算出すると、図４のグラフが描かれる。図４のグラフは、横軸が時間であり、縦軸がハイサイドスイッチ１１１の駆動電圧を示す。この図４のグラフからわかるように、式（１）の第１項（図４中、「シフト電圧（第１項）」で表される）は、あたかも、電圧シフト回路があるかのようにハイサイドスイッチ１１１の制御信号の電圧をかさ上げする。 On the other hand, the formula (2) for the input terminal voltage of the low-side switch 112 does not have such a term, and there is no initial voltage generation when the voltage of the control signal rises with Vee as the starting point.
This is because the differentiating circuit 121 is connected to the negative power supply Vee. Since the control signal is differentiated with respect to the negative power supply Vee, the voltage shown in the first term of equation (1) is not generated.
In this manner, the same effect as when the voltage shift circuit is inserted only in the high-side switch 111 can be obtained. That is, an effect similar to that of the circuit shown in FIG. 12 can be obtained.

however,

Here, as an example, let the time constant τ1 = 200 nsec, R1 = 27 kΩ, Rg = 2.2 kΩ, C1 = 100 pF, Vdc = 15 V, Vee = -10 V, and the control signal voltage rise rate is k = 3V/nsec. Using these values and calculating the input voltage of the high-side switch 111 using equation (1), the graph of FIG. 4 is drawn. In the graph of FIG. 4 , the horizontal axis represents time, and the vertical axis represents the drive voltage of the high-side switch 111 . As can be seen from the graph of FIG. 4, the first term of equation (1) (represented by "shift voltage (first term)" in FIG. 4) is as if there is a voltage shift circuit. The voltage of the control signal for the high-side switch 111 is increased.

この場合は、ローサイドスイッチ１１２の入力電圧に電圧シフトに相当する電圧が発生し、ハイサイドスイッチ１１１の入力電圧には、電圧シフトは発生しない。 Now consider the opposite case, ie, the control signal going from Vdc to Vee in FIG. 3A.
In FIG. 3A, consider the case where the control signal goes from Vdc to Vee. Considering the moment when the control signal starts going from Vdc to Vee as t=0, the study will be limited to the time period during which the control signal is falling. Then, the voltages of the input terminals of the high-side switch 111 and the low-side switch 112 are expressed by the following equations (4) and (5).

In this case, a voltage corresponding to the voltage shift occurs in the input voltage of the low-side switch 112 and no voltage shift occurs in the input voltage of the high-side switch 111 .

A time chart showing how the control signal by the differentiating circuit changes is shown in FIG. 3B. In FIG. 3B, the horizontal axis represents time, and the vertical axis represents the control signal, the signal at the input terminal of the high-side switch 111, and the signal at the input terminal of the low-side switch 112, in this order. That is, how the control signal is changed by the differentiating circuit is depicted.
In FIG. 3B, the control signal rises from Vee to Vdc in a predetermined rise time (tr) and changes from Vdc to Vee in a predetermined fall time (tf) (see FIG. 3B). where tr=Vdc/k and tf=Vdc/k.

In FIG. 3B, the lower part is the signal of the input terminal of the low-side switch 112, and when compared with the control signal in the upper part by passing through the differentiation circuit, overshoot appears at the rise of the signal, and undershoot appears at the fall of the signal. It is shown. The portion in which the value of this signal exceeds Vsh (threshold value) is the ON operation period of the low-side switch 112 .
3B shows the signal at the input terminal of the high-side switch 111. By passing through the differentiation circuit, similarly to the low-side switch 112, overshoot appears at the rise of the signal, and at the fall of the signal, Undershoot is shown. A portion from Vdc to Vsh (threshold value) of this signal is the OFF operation period of the high-side switch 111 . The period from Vsh (threshold) to GND is the ON operation period of the high-side switch 111 . These are shown in FIG. 3B.

Note that the signal at the input terminal of the high-side switch 111 in the middle stage of FIG. 3B is boosted by the shift voltage indicated by the first term of Equation (1). Due to this shift voltage, the waveform of the signal at the input terminal of the high-side switch 111 falls below Vsh at the time of fall, delaying the timing at which the high-side switch 111 transitions to ON operation. In addition, due to this shift voltage (first term of equation (1)), the waveform of the signal at the input terminal of the high-side switch 111 exceeds Vsh early at the time of rising, and the high-side switch 111 shifts to the OFF operation. The timing to do so has been advanced. As a result, a dead time is formed between the signal appearing at the input terminal of the low-side switch 112, a dead time is formed between the signal at the input terminal of the high-side switch 111 and the signal at the input terminal of the low-side switch 112, It is possible to prevent the high-side switch 111 and the low-side switch 112 from turning ON at the same time.

Note that the output signal of the high-side switch 111 is connected to the output terminal 114 via the impedance z1 (see FIG. 1). Also, the output signal of the low-side switch 112 is connected to the output terminal 114 via the impedance z2 (see FIG. 1). The impedance circuits z1 and z2 may have predetermined resistance values or the like, but may be omitted. That is, one or both of the impedance circuits z1 and z2 may be 0 ohms (that is, direct connection). However, it is preferable to insert an impedance circuit with a small value in order to stabilize the output and smoothly switch between the high-side switch 111 and the low-side switch 112 .
The impedance circuit z1 corresponds to a preferred example of the first impedance circuit in the claims. Also, the impedance circuit z2 corresponds to a preferred example of the second impedance circuit in the claims.

As described above, according to the circuit configuration of FIG. 3 (FIG. 1), when the control signal swings from Vee to Vdc, the control signal rises (rises from Vee to Vdc) and falls (falls from Vdc to Vee). ), it is possible to prevent occurrence of a period in which both the high-side switch 111 and the low-side switch 112 are in the ON state at the same time.

2. Embodiment 2 Example Using Bipolar Transistors FIG. 5 is a circuit block diagram of a gate drive circuit including a switch circuit 110 in which a pnp transistor is used for the high-side switch 111a and an npn transistor is used for the low-side switch 112a. It is shown. In FIG. 5 as well, the gate drive circuit has the switch circuit 110 as its main component, but may include other components. For example, the gate drive circuit may or may not include the P-AMP16.
Even when so-called bipolar transistors are used, substantially the same effects as those of the circuits shown in FIGS. 1 to 3 can be obtained. Various advantages are obtained by using a transistor instead of a MOSFET for each switch of the high-side switch 111a.

In the following, equations relating to the second embodiment using transistors for the high-side switch 111a and the low-side switch 112a are added. Let VBE be the base-emitter voltage when each transistor is turned on. When the transistor shifts from the OFF operation state to the ON operation state, the base voltage is calculated just before the ON operation, and after the ON operation, the base-emitter voltage is limited to about 0.7V. Also, when the transistor shifts from the ON operation state to the OFF operation state, it is assumed that the impedance between the base and the emitter is high impedance with respect to the resistance value of the resistor Rg immediately after the control signal starts to change. do.

制御信号が、ＶｄｃからＶｅｅへ下降する場合の式は、次の式（８）、式（９）に示されている。ただし、式（８）の場合、トランジスタのベース－エミッタ間が導通すると、ベース－エミッタ間電圧は約０．７Ｖにクランプされる。

ここで、ハイサイドスイッチ１１１やローサイドスイッチ１１２を、バイポーラトランジスタの代わりにＭＯＳＦＥＴを用いる場合は、ＯＦＦ動作の状態からＯＮ動作の状態に移行するとき、ＭＯＳＦＥＴのゲートの閾値電圧以上をゲート－ソース間に印加する必要がある。この閾値以上の電圧をゲート－ソース間に印加することによって、ＭＯＳＦＥＴはＯＮ動作して電流を流す。ドレイン－ソース間に流し得る電流はゲート－ソース間電圧にほとんど関係なく、ゲート－ソース間電圧が閾値を超えると電流を流すことができる。 When the control signal rises from Vee to Vdc, the input signal of each switch is represented by Equation (6), which represents the input signal of the high-side switch 111a, and Equation (7), which represents the input signal of the low-side switch 112a. is.
However, in the case of equation (7), the base-emitter voltage is clamped at about 0.7V when the base-emitter conducts.

Expressions when the control signal drops from Vdc to Vee are shown in the following expressions (8) and (9). However, in the case of equation (8), the base-emitter voltage is clamped to approximately 0.7V when the transistor's base-emitter conducts.

Here, if MOSFETs are used instead of bipolar transistors for the high-side switch 111 and the low-side switch 112, when the OFF operation state is shifted to the ON operation state, the threshold voltage of the gate of the MOSFET or more is applied between the gate and the source. must be applied to By applying a voltage higher than this threshold between the gate and the source, the MOSFET is turned on and current flows. The current that can flow between the drain and the source is almost independent of the voltage between the gate and the source, and the current can flow when the voltage between the gate and the source exceeds the threshold.

On the other hand, when the transistor exceeds the base-emitter voltage of about 0.6 V, the base current flows and the collector current flows, but the current is limited to hFE times the base current. Therefore, if the base current Ib is limited, even if the pnp transistor of the high-side switch 111a and the npn transistor of the low-side switch 112a are turned on at the same time and become conductive, the flowing current (collector current) is IC=hFE×Ib. , and damage can sometimes be avoided for an extremely short period of time. On the other hand, when the high-side switch 111 and the low-side switch 112 are configured using MOSFETs, the drain current is limited only by the ON resistance, so there is a possibility that the current becomes large. A situation in which both the low-side switch 112 and the low-side switch 112 are turned on at the same time cannot be allowed.

Furthermore, in the case of MOSFET, there is a maximum rated voltage between the gate and source, and a voltage exceeding this maximum rated voltage cannot be applied. necessary. On the other hand, in the case of a transistor, since the voltage between the base and the emitter is about 0.6 V during ON operation, there is a feature that such a voltage regulator diode for protection is not required.

As described above, there are different points to be noted depending on whether the high-side switch 111 and the low-side switch 112 use bipolar transistors or MOSFETs.

3. Embodiment 3: Example Using a Constant-Voltage Diode FIG. 6 is a block diagram showing a case where a constant-voltage diode D1 is inserted in the output circuit of the switch circuit 110a. In a gate drive circuit that drives a power switch (IGBT 15, etc.), diversity is required for the output of the switch circuit described in this embodiment and the gate drive circuit using the switch circuit. The gate drive circuit in FIG. 6 has the switch circuit 110a as a main component, but may include other components. For example, the gate drive circuitry may or may not include the P-AMP16.
For example, the output may require a swing width from Vdc to Vee, or the voltage range must be limited such as from Vdc to GND. In such a case, as shown in FIG. 6, by inserting a diode D1 between the transistors forming the high-side switch 111a and the low-side switch 112a and the output terminal 114, the swing width of the output voltage is adjusted. be able to.

For example, if you want to obtain an output in the range of Vdc to GND, make the Zener voltage of D1 equal to Vee, and connect as shown in FIG. good.
Conversely, when it is desired to obtain an output that swings between Vee and GND, the output should be obtained from the collector of the npn transistor that constitutes the low-side switch 112 .

In particular, the zener diode D1 used in the circuit shown in FIG. It can be charged up to the voltage of D1. Therefore, even at the moment when the switch is reversed, the high-side switch is turned ON, and the low-side switch 112 is turned OFF, the charge stored in the equivalent capacitance is maintained. As a result, according to this embodiment, it is not necessary to charge the parallel equivalent capacitance of the zener diode D1 at the moment when the high-side and low-side switches are switched, and it is possible to output a stable output voltage instantaneously. There are also benefits.

4. Embodiment 4
FIG. 7 is a circuit block diagram of a gate drive circuit when a P-channel MOSFET 140 (hereinafter referred to as Q1) is inserted between the input terminal of the high-side switch 111 and Vdc. The source terminal of Q1 is connected to Vdc and the drain terminal is connected to the input terminal of high side switch 111 . The gate drive circuit in FIG. 7 may include the switch circuit 110b as a main component and other components. For example, the gate drive circuit may or may not include a buffer or an inverter circuit using a MOSFET or the like, which is connected between the output terminal 114 and the IGBT 15 to be driven.
The switch circuit 110b included in this gate drive circuit has an inhibition signal input terminal 141 for inputting the inhibition signal IN2. This inhibition signal input terminal 141 is connected to the gate terminal of Q1 through a voltage dividing circuit of resistors R10 and R11.
When the inhibition signal IN2 is High, when a Low signal is input to the control signal IN1, the output terminal 114 outputs High in response to the signal. When a High signal is input to the control signal IN1, the output terminal 114 outputs Low in response to that signal.

On the other hand, when the inhibition signal IN2 is Low, the output terminal 114 is Low regardless of the value of the control signal IN1. Depending on the drive state of the IGBT 15 to be driven, the output terminal 114 may have to be forcibly held Low even when the control signal IN1 is operating normally. , Q1 are provided so that the inhibit signal can be input.
By the way, in such a case, it is conceivable to forcibly set the output terminal 114 to Low by an external circuit. As a result, the high-side switch 111 of this circuit is overloaded more than necessary, which is not preferable.
A method of inserting, for example, a predetermined logic circuit in the input terminal 113 and forcibly holding the control signal itself at High is also conceivable. However, it is considered that the logic circuit and the time delay of the logic circuit are excessively generated, and the desired result is not brought about.

Normally, such a prohibited operation is performed when there is an abnormality in the state of the IGBT 15, and it is necessary to reduce the delay time as much as possible. Therefore, the circuit shown in FIG. 7 in which such a delay operation does not occur can easily construct a configuration capable of receiving the inhibit signal. Furthermore, according to the circuit shown in FIG. 7, the configuration that can receive the prohibition signal can be configured more simply.

5. Specific embodiment of the present invention
5.1 Specific Embodiment 1
A specific example of a circuit diagram of the gate drive circuit 200 is shown in FIG. The gate drive circuit shown in FIG. 8 includes the switch circuit 110c as a main component, and other circuits are not shown. However, P-AMP may also be included, for example, as in FIGS. 1, 3A and 5 previously described. A control signal is input to the input terminal 113 . The control signal swings from +15V on the positive supply to -10V on the negative supply. Also, the control signal is a rectangular wave with a frequency of about 10 kHz.
The input terminal 113 is connected to two differentiating circuits 120, 121 as in FIG. 3A. The output signal of the differentiating circuit 120 is supplied to the base terminal of a high-side switch 111 (for example, a pnp transistor) (hereinafter referred to as Q1). The output signal of the differentiating circuit 121 is supplied to the base terminal of the low-side switch 112 (for example, an npn transistor) (hereinafter referred to as Q2) (see FIG. 8).

A series circuit of a voltage regulator diode D1 and a resistor R5 is connected between the collector terminal of Q1 and the collector terminal of Q2, and the output signal of the switch circuit 110c is output from both ends of the series circuit. . These two kinds of output signals are outputted from an output terminal 114b through an inverter composed of a P-channel MOSFET (referred to as Q3) and an N-channel MOSFET (referred to as Q4). Therefore, the output terminal 114b is the substantial output terminal of the switch circuit 110c. The output terminal 114b is connected to the gate terminal of the IGBT 15 to be driven.

Now, when the control signal changes from -10V to +15V, the voltage at the base terminal of Q1 generates a voltage corresponding to the voltage of the shift circuit shown in the first term of the above equation (1). rises to +15V in proportion to the rise in the voltage of . At this time, a voltage calculated by the equation (1) appears at the base terminal of Q1. In this way, the state of the ON operation is changed to the state of the OFF operation at the very initial time when the control voltage changes from -10V to +15V.
On the other hand, Q2 shifts from the OFF state to the ON state when the control signal shifts from -10V to +15V. When the control signal changes from +15 V to -10 V, the voltage at the base terminal of Q2 generates a voltage corresponding to the voltage of the shift circuit due to the action of the differentiating circuit 121 composed of C2 and R2. Due to this generated voltage, the potential of the base terminal drops very early in the fall of the control signal, and Q2 turns off.

Next, Q1 shifts from the OFF state to the ON state as the voltage of the control signal shifts from +15V to −10V. When the voltage of the control signal is -10 V, the output transistor Q4 in FIG. 8 is turned ON and Q3 is turned OFF. Therefore, the output voltage of the output terminal 114b of the gate drive circuit 200 becomes LOW, and the gate drive circuit 200 extracts the charge between the gate and source of the IGBT 15 via R9 and Q4. As a result, the IGBT is turned off. The gate terminal of the IGBT 15 becomes approximately -10V and is sufficiently kept off. As for the voltage between the gate and the source of Q3, it is possible to apply a proper voltage while securing the withstand voltage by the function of the constant voltage diode D1.

When the control voltage reaches +15V, Q3 turns ON and Q4 turns OFF. At this time, the gate drive circuit 200 causes current to flow between the gate and source of the IGBT 15 via R8 and Q3. The output voltage of the output terminal 114b becomes HIGH, and the gate voltage of the IGBT 15 is approximately +15V. As a result, the IGBT 15 is turned ON. The gate voltage is maintained at +15V to hold the ON state. As with Q3, the voltage between the gate and the source of Q4 can be properly applied to the gate terminal of Q4 while ensuring the withstand voltage due to the action of the zener diode D1. Thus, the gate drive circuit 200 shown in FIG. 8 can drive the IGBT 15 that switches a large amount of power. Since the polarities of the control signal and the output signal also match, the circuit can be configured very efficiently.

5.2 Specific Embodiment 2
A circuit diagram of a concrete embodiment 2 is shown in FIG. FIG. 9 shows the gate drive circuit 200b. The gate drive circuit 200b includes a switch circuit 110d composed of R1 to R7, C1, C2, D1, Q1, Q2, etc. in FIG. The switch circuit 110d is a preferred example of the switch circuit having the configuration shown in FIG. 5 (and claim 3 of the scope of claims).
9, the switch circuit 110e consisting of R11 to R15, R20, C11, C12, C20, D11, Q11, Q12, etc. has the configuration shown in FIG. 6 (and claim 4 of the scope of claims). It is a preferred example of a switch circuit. Q3, Q4, Q14, R6-R9, and R16-R19 correspond to a preferred example of the internal circuit configuration of the P-AMP (power amplifier) 16 in FIG.

となる。ＩＧＢＴ１５がＯＮ動作の状態からＯＦＦ動作の状態に移行する時間はこの時定数に影響を受ける。τが大きければ移行時間は長くなり、τが短ければ移行時間は短くなる。
なお、図９に示す例では、Ｒ９とＲ１９とがＩＧＢＴ１５のゲート端子に対して並列に接続されている例を示し、かかる並列接続によって、上記（１０）式のように時定数が算出されているが、この２個の抵抗は直列に接続されていてもよい。
例えば、図９において、ＩＧＢＴ１５のゲート端子に接続している側のＲ９の端子の接続先を、ＩＧＢＴ１５のゲート端子から、Ｒ１９とＱ１４のドレイン端子の接続点に変更してもよい。
このような回路接続とすることによって、通常動作時の（ＩＧＢＴ１５の）ＯＦＦ動作の時定数は、Ｒ１９に基づく時定数となる。また、禁止信号を受信している際の時定数は。Ｒ９に基づく時定数とすることができる。但し、Ｒ９の抵抗値は、Ｒ１９の抵抗値より十分に大きいものとする。 A control signal, which is a rectangular wave of about 10 kHz, is input to the input terminal 113 as normal operation, and the Soft-off-in terminal 142 is in a High state during normal operation. In this state, when the input terminal 113 is High, Q3 is turned on and the output terminal 114 outputs High. When the input terminal 113 is Low, both Q4 and Q14 are turned ON, and the output terminal is connected to the potential of -10V via R9 and R19 and becomes Low. At this time, the gate charge of the IGBT 15 is discharged by the parallel resistance value of R9 and R19. Its discharge time constant is

becomes. The time for the IGBT 15 to shift from the ON state to the OFF state is affected by this time constant. A large τ results in a long transition time, and a small τ results in a short transition time.
Note that the example shown in FIG. 9 shows an example in which R9 and R19 are connected in parallel to the gate terminal of the IGBT 15, and the parallel connection allows the time constant to be calculated as in the above equation (10). However, the two resistors may be connected in series.
For example, in FIG. 9, the connection destination of the terminal of R9 connected to the gate terminal of IGBT15 may be changed from the gate terminal of IGBT15 to the connection point of the drain terminals of R19 and Q14.
By such circuit connection, the time constant of the OFF operation (of the IGBT 15) during normal operation becomes the time constant based on R19. Also, what is the time constant when receiving the inhibit signal? It can be a time constant based on R9. However, it is assumed that the resistance value of R9 is sufficiently larger than the resistance value of R19.

It is necessary to appropriately select the transition time for the IGBT 15 to transition from the ON operation state to the OFF operation state. If the transition time is too long, the switching loss increases, and if the transition time is too short, the switching loss decreases. A voltage surge occurs. In addition, since this voltage surge increases in proportion to the collector current, the optimum switching loss can be selected according to the collector current by changing the transition time according to the collector current. Further, if the IGBT 15 is turned off during a normal transition time during a short circuit, a surge voltage exceeding the withstand voltage between the collector and the emitter of the IGBT 15 is applied, leading to destruction of the IGBT 15 .
In this embodiment, the Soft-off-in terminal 142 is set to Low when short-circuited, so that Q11 can always be maintained in the OFF state. In this state, the time constant for extracting the gate charge from the IGBT 15 can be expressed as τ=Cge×R9. As a result, the time constant τ becomes longer, the time required for the IGBT 15 to shift from the ON operation state to the OFF operation state becomes longer, and the voltage surge is reduced. As a result, breakage of the IGBT 15 can be avoided.

6. Effects and Others As described above, the switch circuit and the gate drive circuit using the same according to the present embodiment have the following effects.
A differentiating circuit was provided at the input portion of the switch circuit, and the control signal passed through this differentiating circuit was supplied to the switch circuit (high side switch, low side switch). As a result, it is possible to obtain the same effect as the voltage shift of the control signal. Therefore, it is possible to provide a switch circuit that can prevent through current with a simple configuration. Furthermore, the switch circuit can be used to provide a gate drive circuit with a simple configuration.
Also, as the switch circuits (high side switch, low side switch), bipolar transistors (pnp type, npn type) may be used instead of MOSFETs. In that case, since the voltage between the base and the emitter is clamped at about 0.6 V, there is no need to provide a constant voltage diode or the like for protection unlike the MOSFET, so that the configuration can be made simpler.

Furthermore, although the switch circuit can obtain the same effect as the voltage shift of the control signal, the use of the differentiating circuit shortens the time required to switch the gate voltage of the semiconductor switch with respect to the input signal. can be done. Therefore, if this switch circuit is applied to drive a plurality of semiconductor switches in parallel, variations in ON/OFF timings of the plurality of semiconductor switches can be effectively suppressed.

Further, adjustment such as narrowing the range of the output voltage by that voltage can be performed by using a constant voltage diode or the like between the switch circuit (high side switch, low side switch) and the output terminal. This also allows the swing range of the output voltage to be adjusted.
Further, the gate drive circuit may be forcibly stopped depending on the driving state of the IGBT or the like to be driven. By providing a switch that connects the input terminal on the side of the high side switch to Vdc based on the inhibition signal, the gate drive circuit can be forcibly stopped easily with a simple configuration. As a switch for connection, an example of a P-channel MOSFET has been described above, but any switch may be used as long as it is operated by an inhibit signal.
Further, in the above-described embodiments, the time constant for extracting the electric charge from the IGBT to be driven can be lengthened. As a result, it is possible to reduce the surge voltage due to the parasitic inductance, thereby preventing damage to the IGBT.
If this time constant is too long, the switching loss will increase, but if it is too short, a voltage surge will occur as described above. Since this voltage surge increases in proportion to the collector current, the switching loss can be selected according to the collector current by adjusting the time constant according to the collector current.

Further, the embodiment described above is an example of means for realizing the present invention, and should be appropriately modified or changed according to the configuration of the apparatus to which the present invention is applied and various conditions, and the present invention is the present embodiment. It is not limited to the aspect of For example, in the above-described embodiments, IGBTs were mainly described as power semiconductor switches to be driven, but other power semiconductor switches can also be applied. Also, the various differentiating circuits described above are only suitable examples, and other circuits having similar functions may be used.

10, 10a, 10b, 110, 110a, 110b, 110c switch circuit 110d, 110e switch circuit 11, 111 high side switch 12, 112 low side switch 13, 113 input terminal 14, 114 output terminal 15 IGBT
16P-AMP
20 shift circuit 21, 131 control circuit 120, 121 differentiation circuit 141 inhibition signal input terminal 142 Softoff-in terminal 200, 200b gate drive circuit

Claims (6)

A gate drive circuit that drives a semiconductor switch based on a control signal,
an input terminal for inputting the control signal;
a high-side switch connected to the positive power supply; and
a low-side switch connected to the negative power supply; and
a first differentiating circuit connected to the input terminal and the positive side power supply, differentiating the control signal and supplying the result to the input terminal of the high-side switch;
a second differentiating circuit connected to the input terminal and the negative side power supply, differentiating the control signal and supplying it to the input terminal of the low-side switch;
an output terminal for outputting a signal for driving the semiconductor switch;
a first impedance circuit connected between the high-side switch and the output terminal and having an impedance of a predetermined value ;
a second impedance circuit connected between the low-side switch and the output terminal and having an impedance of a predetermined value ;
A gate drive circuit comprising: A gate drive circuit that drives a semiconductor switch based on a control signal,
an input terminal for inputting the control signal;
a high-side switch connected to the positive power supply; and
a low-side switch connected to the negative power supply; and
a first differentiating circuit connected to the input terminal and the positive side power supply, differentiating the control signal and supplying the result to the input terminal of the high-side switch;
a second differentiating circuit connected to the input terminal and the negative side power supply, differentiating the control signal and supplying it to the input terminal of the low-side switch;
an output terminal connected to the high-side switch and the low-side switch and outputting a signal for driving the semiconductor switch;
A gate drive circuit comprising: The gate drive circuit of claim 1, comprising:
The high-side switch includes a pnp transistor,
the low-side switch comprises an npn transistor;
the first differentiating circuit supplies the differentiated control signal to the base of the pnp transistor;
The second differentiating circuit supplies the differentiated control signal to the base of the npn transistor,
the first impedance circuit is connected between the collector terminal of the pnp transistor and the output terminal;
The gate drive circuit, wherein the second impedance circuit is connected between the collector terminal of the npn transistor and the output terminal. 4. The gate drive circuit of claim 3 , wherein
a zener diode connected between the collector terminal of either the collector terminal of the pnp-type transistor or the collector terminal of the npn-type transistor and the output terminal;
A gate drive circuit comprising: The gate drive circuit according to any one of claims 1 to 4 ,
a semiconductor switch for switching a predetermined inhibition signal, having one end connected to the input terminal of the high side switch and the other end connected to the plus side power supply;
a prohibition signal input terminal connected to a control terminal for controlling on/off of a semiconductor switch for switching the prohibition signal and receiving the prohibition signal;
and a semiconductor switch for switching the prohibition signal is turned on by inputting a predetermined prohibition signal input from the prohibition signal input terminal to the control terminal, and the input terminal of the high side switch is switched to the plus terminal. connected to the side power supply,
When the semiconductor switch for switching the prohibition signal is turned on by inputting the predetermined prohibition signal to the control terminal of the semiconductor switch for switching the prohibition signal, regardless of the control signal, the A gate drive circuit that can prohibit the output of a high level voltage to an output terminal. The gate drive circuit according to any one of claims 1 to 4 ,
a P-channel MOSFET whose drain terminal is connected to the input terminal of the high-side switch and whose source terminal is connected to the plus side power supply;
an inhibition signal input terminal connected to the gate terminal of the P-channel MOSFET for inputting a predetermined inhibition signal;
The P-channel MOSFET is turned on by inputting a predetermined inhibition signal input from the inhibition signal input terminal to the gate terminal of the P-channel MOSFET, and the input terminal of the high side switch is connected to the positive side power supply and connect with
When the P-channel MOSFET is turned on by inputting the predetermined prohibition signal to the gate terminal of the P-channel MOSFET, outputting a high level voltage to the output terminal is prohibited regardless of the control signal . A gate drive circuit that can

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