JP7160956B2 - 分岐命令のタイプに基づく先行分岐予測の選択的実行 - Google Patents

分岐命令のタイプに基づく先行分岐予測の選択的実行 Download PDF

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JP7160956B2
JP7160956B2 JP2020570692A JP2020570692A JP7160956B2 JP 7160956 B2 JP7160956 B2 JP 7160956B2 JP 2020570692 A JP2020570692 A JP 2020570692A JP 2020570692 A JP2020570692 A JP 2020570692A JP 7160956 B2 JP7160956 B2 JP 7160956B2
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branch
block
instruction
instructions
prediction
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JP2021527892A (ja
JPWO2019245846A5 (https=
JP2021527892A5 (https=
Inventor
エバース マリウス
シャガラジャン アパルナ
ティー． ベンカタチャー アショク
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2020570692A 2018-06-18 2019-06-13 分岐命令のタイプに基づく先行分岐予測の選択的実行 Active JP7160956B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/011,010 US10732979B2 (en) 2018-06-18 2018-06-18 Selectively performing ahead branch prediction based on types of branch instructions
US16/011,010 2018-06-18
PCT/US2019/036967 WO2019245846A1 (en) 2018-06-18 2019-06-13 Selectively performing ahead branch prediction based on types of branch instructions

Publications (4)

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JP2021527892A JP2021527892A (ja) 2021-10-14
JPWO2019245846A5 JPWO2019245846A5 (https=) 2022-06-21
JP2021527892A5 JP2021527892A5 (https=) 2022-06-21
JP7160956B2 true JP7160956B2 (ja) 2022-10-25

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JP2020570692A Active JP7160956B2 (ja) 2018-06-18 2019-06-13 分岐命令のタイプに基づく先行分岐予測の選択的実行

Country Status (6)

Country Link
US (2) US10732979B2 (https=)
EP (1) EP3807758A4 (https=)
JP (1) JP7160956B2 (https=)
KR (2) KR20230110649A (https=)
CN (1) CN112368677B (https=)
WO (1) WO2019245846A1 (https=)

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US11086629B2 (en) * 2018-11-09 2021-08-10 Arm Limited Misprediction of predicted taken branches in a data processing apparatus
US10922082B2 (en) * 2019-03-05 2021-02-16 Arm Limited Branch predictor
US11269642B2 (en) * 2019-09-20 2022-03-08 Microsoft Technology Licensing, Llc Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor
US11138014B2 (en) * 2020-01-29 2021-10-05 Arm Limited Branch predictor
US11403103B2 (en) * 2020-04-14 2022-08-02 Shanghai Zhaoxin Semiconductor Co., Ltd. Microprocessor with multi-step ahead branch predictor and having a fetch-target queue between the branch predictor and instruction cache
US12153927B2 (en) 2020-06-01 2024-11-26 Advanced Micro Devices, Inc. Merged branch target buffer entries
US20220129763A1 (en) * 2020-10-23 2022-04-28 Intel Corporation High confidence multiple branch offset predictor
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
CN116737240B (zh) * 2022-03-02 2024-08-06 腾讯科技（深圳）有限公司 分支预测方法、装置、处理器、介质及设备
KR102781288B1 (ko) * 2022-05-11 2025-03-14 서울시립대학교 산학협력단 명령어를 처리하는 방법 및 이를 위한 프로세서 모듈
CN115934171B (zh) * 2023-01-16 2023-05-16 北京微核芯科技有限公司 为多指令调度分支预测器的方法及装置
US12578965B2 (en) 2023-07-25 2026-03-17 Apple Inc. Biased indirect control transfer prediction
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction

Citations (1)

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JP2019526873A (ja) 2016-08-30 2019-09-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 分岐ターゲットバッファの圧縮

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US5574928A (en) * 1993-10-29 1996-11-12 Advanced Micro Devices, Inc. Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
US5903772A (en) * 1993-10-29 1999-05-11 Advanced Micro Devices, Inc. Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
US5903750A (en) 1996-11-20 1999-05-11 Institute For The Development Of Emerging Architectures, L.L.P. Dynamic branch prediction for branch instructions with multiple targets
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6385719B1 (en) * 1999-06-30 2002-05-07 International Business Machines Corporation Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor
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US7254693B2 (en) 2004-12-02 2007-08-07 International Business Machines Corporation Selectively prohibiting speculative execution of conditional branch type based on instruction bit
US7844806B2 (en) * 2008-01-31 2010-11-30 Applied Micro Circuits Corporation Global history branch prediction updating responsive to taken branches
US7979675B2 (en) * 2009-02-12 2011-07-12 Via Technologies, Inc. Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution
US8578139B2 (en) 2010-08-05 2013-11-05 Arm Limited Checkpointing long latency instruction as fake branch in branch prediction mechanism
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JP2019526873A (ja) 2016-08-30 2019-09-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 分岐ターゲットバッファの圧縮

Also Published As

Publication number Publication date
JP2021527892A (ja) 2021-10-14
US11416256B2 (en) 2022-08-16
KR20230110649A (ko) 2023-07-24
KR102554799B1 (ko) 2023-07-13
CN112368677A (zh) 2021-02-12
EP3807758A4 (en) 2022-02-23
US10732979B2 (en) 2020-08-04
KR20210011060A (ko) 2021-01-29
US20190384612A1 (en) 2019-12-19
CN112368677B (zh) 2022-07-15
US20210034370A1 (en) 2021-02-04
WO2019245846A1 (en) 2019-12-26
EP3807758A1 (en) 2021-04-21

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