JP7153856B2 - FAILURE DETECTION CIRCUIT AND FAILURE DETECTION METHOD - Google Patents

Description

The present disclosure relates to fault detection circuits and fault detection methods.

A circuit using a resistance ladder composed of a plurality of resistors is known as a circuit for fault detection based on a plurality of signals from a plurality of circuits. For example, Patent Document 1 discloses a configuration in which a signal line from an overvoltage protection circuit and a signal line from an overcurrent protection circuit are connected to different connection points of a resistance ladder.

JP-A-11-101837

However, in the configuration of Patent Document 1, there is a problem that it is not possible to detect simultaneous failures in a plurality of circuits.

An object of the present disclosure is to provide a fault detection circuit or a fault detection method capable of individually detecting faults in a plurality of circuits.

A fault detection circuit according to one aspect of the present disclosure is connected to either a plurality of resistors connected in series with each other and a connection point of the plurality of resistors between a DC power supply and a reference potential point, An output terminal from which the voltage at the connection point is output is connected in parallel with one of the plurality of resistors, each is connected with one of a plurality of circuits, and a failure detection signal from the connected circuit a plurality of switch elements that are switched on and off, and the resistance values of the plurality of resistors are set such that the voltages are different values in a plurality of combinations of on and off of the plurality of switch elements. .

The present disclosure can provide a fault detection circuit or fault detection method capable of individually detecting faults in multiple circuits.

FIG. 1 is a diagram showing the configuration of a failure detection circuit according to an embodiment. FIG. 2 is a diagram illustrating an example of states of switch elements and output voltages in the failure detection circuit according to the embodiment. FIG. 3 is a diagram showing a configuration of a modification of the fault detection circuit according to the embodiment; FIG. 4 is a diagram illustrating an example of the state of a switch element and an output voltage in a modification of the failure detection circuit according to the embodiment;

A fault detection circuit according to one aspect of the present disclosure is connected to either a plurality of resistors connected in series with each other and a connection point of the plurality of resistors between a DC power supply and a reference potential point, An output terminal from which the voltage at the connection point is output is connected in parallel with one of the plurality of resistors, each is connected with one of a plurality of circuits, and a failure detection signal from the connected circuit a plurality of switch elements that are switched on and off, and the resistance values of the plurality of resistors are set such that the voltages are different values in a plurality of combinations of on and off of the plurality of switch elements. .

According to this, different voltages are output to the output terminal according to the combination of failure detection signals from a plurality of circuits. Therefore, failures in a plurality of circuits can be individually detected based on this voltage.

For example, the plurality of resistors may include a plurality of first resistors to which one of the plurality of switch elements is connected in parallel, and a first resistor connected between the plurality of first resistors and the DC power supply. 2 resistors, and the output terminal may be connected to a connection point between the plurality of first resistors and the second resistors.

For example, the plurality of resistors are connected between a plurality of first resistors to which any one of the plurality of switch elements is connected in parallel and between the plurality of first resistors and the reference potential point and a second resistor, and the output terminal may be connected to a connection point between the plurality of first resistors and the second resistor.

A fault detection method according to one aspect of the present disclosure is a fault detection method using a fault detection circuit, wherein the fault detection circuit includes a plurality of serially connected terminals between a DC power supply and a reference potential point. a resistor, an output terminal connected to one of the connection points of the plurality of resistors and outputting a voltage at the connection point, and one of the plurality of resistors connected in parallel to each of the plurality of a plurality of switch elements each connected to one of the circuits and switched between on and off by a failure detection signal from the connected circuit, wherein a plurality of combinations of on and off of the plurality of switch elements, are set so that the resistance values of the plurality of resistors are different values, and the failure detection method determines whether a failure or abnormality has occurred in each of the plurality of circuits based on the voltage of the output terminal. determine whether or not

According to this, different voltages are output to the output terminal according to the combination of failure detection signals from a plurality of circuits. Therefore, failures in a plurality of circuits can be individually detected based on this voltage.

In addition, these general or specific aspects may be realized by a system, method, integrated circuit, computer program, or a recording medium such as a computer-readable CD-ROM. and any combination of recording media.

Hereinafter, embodiments will be specifically described with reference to the drawings. It should be noted that each of the embodiments described below is a specific example of the present invention. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are examples and are not intended to limit the present invention. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in independent claims representing the highest concept will be described as arbitrary constituent elements.

First, the configuration of the failure detection system according to this embodiment will be described. FIG. 1 is a diagram showing the configuration of a failure detection system according to this embodiment. This fault detection system detects faults or anomalies in the circuits 11A-11D. The fault detection system includes a fault detection circuit 10, a plurality of circuits 11A-11D, and a microcomputer 12. FIG.

The plurality of circuits 11A to 11D detect whether a failure or abnormality has occurred in their own circuits, and output failure detection signals S1 to S4 indicating whether or not a failure or abnormality has occurred in their own circuits. For example, the fault detection signals S1 to S4 are normally low level, and become high level when a fault or abnormality occurs. Note that the relationship between the presence or absence of a failure or abnormality in the failure detection signals S1 to S4 and the logic value may be reversed. Further, the relationship between the presence or absence of a failure or abnormality and the logic value may differ among the plurality of failure detection signals S1 to S4. Also, the functions of the circuits 11A to 11D are not particularly limited, but are, for example, overvoltage protection circuits or overcurrent protection circuits. Also, the circuits 11A-11D may detect other circuits (not shown) in the system or failures or anomalies of the system instead of detecting their own failures or anomalies.

The failure detection circuit 10 is a circuit used for failure or abnormality detection, and includes a resistance ladder 20, a plurality of switch elements SW1 to SW4, and an output terminal 21. FIG.

Resistor ladder 20 includes a plurality of resistors R0 to R4 connected in series between a DC power supply that outputs power supply voltage VCC and a reference potential point (GND).

Each of the plurality of switch elements SW1-SW4 is connected in parallel with one of the plurality of resistors R1-R4. Specifically, the switch element SW1 is connected in parallel with the resistor R1, the switch element SW2 is connected in parallel with the resistor R2, the switch element SW3 is connected in parallel with the resistor R3, and the switch element SW4 is connected in parallel with the resistor R2. It is connected in parallel with R4.

The plurality of switch elements SW1 to SW4 are each connected to one of the plurality of circuits 11A to 11D, and are switched on and off by failure detection signals S1 to S4 from the connected circuits 11A to 11D. Specifically, the switch element SW1 is connected to the circuit 11A, and is switched on and off by the failure detection signal S1 from the circuit 11A. The switch element SW2 is connected to the circuit 11B, and is switched on and off by the failure detection signal S2 from the circuit 11B. The switch element SW3 is connected to the circuit 11C and is switched on and off by the failure detection signal S3 from the circuit 11C. The switch element SW4 is connected to the circuit 11D, and is switched on and off by the failure detection signal S4 from the circuit 11D.

The output terminal 21 is connected to a connection point N1 between the resistors R0 and R1, and outputs a voltage VS at the connection point N1. That is, the plurality of resistors R0 to R4 includes a plurality of first resistors R1 to R4 to which one of the plurality of switch elements SW1 to SW4 is connected in parallel, a plurality of first resistors R1 to R, and a DC power supply. and a second resistor R0 connected between. The output terminal 21 is connected to a connection point N1 between the plurality of first resistors R1 to R4 and the second resistor R0. Also, the output terminal 21 is connected to the input port of the microcomputer 12 .

The microcomputer 12 is a control unit that detects whether or not each of the plurality of circuits 11A to 11D is faulty based on the voltage VS of the output terminal 21. FIG. For example, the microcomputer 12 includes a processor and memory, and implements the above functions by executing programs stored in the memory.

For example, the circuits 11A-11D and the microcomputer 12 are separate integrated circuits, and the fault detection circuit 10 is a discrete circuit. This configuration is only an example, and the failure detection circuit 10 may be an integrated circuit, or two or more of the failure detection circuit 10, the plurality of circuits 11A to 11D, and the microcomputer 12 are formed as a single integrated circuit. may

Here, the resistance values r0 to r4 of the plurality of resistors R0 to R4 are set so that the voltage VS has different values in a plurality of combinations of on and off of the plurality of switch elements SW1 to SW4. Further, the microcomputer 12 grasps in advance the relationship between the plurality of combinations of ON and OFF of the plurality of switch elements SW1 to SW4 and the voltage VS. The microcomputer 12 uses the voltage VS and this relationship to determine whether a failure or abnormality has occurred in each of the plurality of circuits 11A to 11D, and performs processing according to the determination result.

FIG. 2 is a diagram showing the relationship between a plurality of combinations of on and off of the plurality of switch elements SW1 to SW4 and the voltage VS. FIG. 2 shows numerical examples of the voltage VS when the power supply voltage VCC=5 V, the resistance value r0=5 kΩ, the resistance value r1=2 kΩ, the resistance value r2=3 kΩ, the resistance value r3=4 kΩ, and the resistance value r4=8 kΩ. show.

As shown in FIG. 2, by appropriately setting the resistance values r0 to r4, the voltage VS has different values in a plurality of combinations of on and off of the plurality of switch elements SW1 to SW4. For example, the resistance values r1-r4 of the resistors R1-R4 are set to at least different values. Also, the resistance value r0 of the resistor R0 can be set to any value, and may be, for example, the same value as any one of the resistance values r1 to r4 of the resistors R1 to R4. It should be noted that the numerical example of the voltage VS shown in FIG. 2 and the values of the resistance values r0 to r4 are merely examples, and the present invention is not limited to these.

As described above, based on the voltage VS of the output terminal 21, the microcomputer 12 can individually detect failures or abnormalities in the plurality of circuits 11A to 11D. In this way, failures or abnormalities in a plurality of circuits 11A to 11D can be detected based on a single voltage VS, so there is no need to provide a plurality of signal lines between the microcomputer 12 and the failure detection circuit 10, and the configuration can be simplified. Can be simplified.

Note that FIG. 1 shows an example in which the voltage VS at the connection point N1 between the resistors R0 and R1 is input to the microcomputer 12. may be input to the microcomputer 12. In other words, the output terminal 21 may be connected to any one of the connection points N1 to N4 of the plurality of resistors R0 to R4 and output the voltage VS at the connection point. Further, when the output terminal 21 is connected to any one of the connection points N2 to N4, a resistor whose switch element is not connected in parallel is further connected in series between the connection point and the reference potential point (GND). preferably. The resistor may be connected in series at any position between the connection point and the reference potential point (GND). For example, when the output terminal 21 is connected to the connection point N3, the resistors that are not connected in parallel with the switch element are between the connection point N3 and the resistor R3, between the connection point N4 and the resistor R4 and the reference It is connected in series anywhere between the potential points.

Further, when the output terminal 21 is connected to one of the connection points N2 to N4, the resistor R0 may be connected in series at any position between the connection point and the DC power supply (VCC). . For example, when the output terminal 21 is connected to the connection point N3, the resistor R0 may be connected in series between the DC power supply and the resistor R1 as shown in FIG. N2, or may be connected in series between resistor R2 and node N3.

Even in the above case, by appropriately setting the values of the resistors, the voltage VS of the output terminal 21 can be set to different values in a plurality of combinations of on and off of the switch elements SW1 to SW4. .

Modifications of the failure detection circuit 10 of the present embodiment will be described below. FIG. 3 is a diagram showing the configuration of a failure detection circuit 10A according to a modification of the present embodiment. The failure detection circuit 10A shown in FIG. 3 differs from the failure detection circuit 10 shown in FIG. 1 in that the resistor ladder 20A includes a resistor R5 instead of the resistor R0. Also, the output terminal 21 is connected to a connection point N5 between the resistors R4 and R5. That is, the plurality of resistors R1 to R5 included in the resistor ladder 20A includes a plurality of first resistors R1 to R4 to which any of the plurality of switch elements SW1 to SW4 are connected in parallel, and a plurality of first resistors R1 to R4. It includes a second resistor R5 connected between R1-R4 and a reference potential point. The output terminal 21 is connected to a connection point N5 between the plurality of first resistors R1 to R4 and the second resistor R5.

FIG. 4 is a diagram showing the relationship between a plurality of combinations of on and off of the plurality of switch elements SW1 to SW4 and the voltage VS in the failure detection circuit 10A shown in FIG. FIG. 4 shows numerical examples of the voltage VS when the power supply voltage VCC=5 V, the resistance value r1=2 kΩ, the resistance value r2=3 kΩ, the resistance value r3=4 kΩ, the resistance value r4=8 kΩ, and the resistance value r5=5 kΩ. show.

As shown in FIG. 4, by appropriately setting the resistance values r1 to r5, the voltage VS has different values in a plurality of combinations of on and off of the plurality of switch elements SW1 to SW4. For example, the resistance values r1-r4 of the resistors R1-R4 are set to at least different values. Also, the resistance value r5 of the resistor R5 can be set to any value, and may be the same value as any one of the resistance values r1 to r4 of the resistors R1 to R4, for example. It should be noted that the numerical example of the voltage VS shown in FIG. 4 and the values of the resistance values r1 to r5 are merely examples, and the present invention is not limited to these.

As described above, based on the voltage VS of the output terminal 21, the microcomputer 12 can individually detect failures or abnormalities in the plurality of circuits 11A to 11D. In this way, failures or abnormalities in a plurality of circuits 11A to 11D can be detected based on a single voltage VS, so there is no need to provide a plurality of signal lines between the microcomputer 12 and the failure detection circuit 10, and the configuration can be simplified. Can be simplified.

Although the failure detection system and the failure detection circuit according to the present embodiment have been described above, the present disclosure is not limited to this embodiment.

For example, in FIGS. 1 and 3, the case of detecting failures in the four circuits 11A to 11D is connected as an example, but the number of failure detection target circuits may be plural. In this case, a set of a switch element and a resistor connected in parallel may be provided for each circuit.

Also, in the above description, the switch elements SW1 to SW4 are NPN transistors, but the switch elements SW1 to SW4 may be PNP transistors. Also, NPN transistors and PNP transistors may be mixed. Moreover, the switch elements SW1 to SW4 are not limited to bipolar transistors, and may be other types of transistors such as MOS transistors.

The present disclosure may also be implemented as a failure detection method using a failure detection circuit, etc., which is executed by a failure detection system.

Although the failure detection circuit and the failure detection system according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications that a person skilled in the art can think of are applied to this embodiment, and a form constructed by combining the components of different embodiments is also within the scope of one or more aspects may be included within

The present disclosure can be applied to fault detection circuits, fault detection systems, and the like.

10, 10A Failure detection circuit 11A, 11B, 11C, 11D Circuit 12 Microcomputer 20, 20A Resistor ladder 21 Output terminal R0, R1, R2, R3, R4, R5 Resistor S1, S2, S3, S4 Failure detection signal SW1, SW2 , SW3, SW4 switch elements

Claims (4)

a plurality of resistors connected in series between the DC power supply and the reference potential point;
an output terminal connected to one of the connection points of the plurality of resistors and outputting a voltage at the connection point;
a plurality of switch elements each connected in parallel to one of the plurality of resistors, each connected to one of a plurality of circuits, and switched on and off by a failure detection signal from the connected circuit;
The failure detection circuit, wherein resistance values of the plurality of resistors are set such that the voltages have different values in a plurality of combinations of on and off of the plurality of switch elements. The plurality of resistors include a plurality of first resistors to which one of the plurality of switch elements is connected in parallel, and a second resistor connected between the plurality of first resistors and the DC power supply. and
2. The fault detection circuit according to claim 1, wherein said output terminal is connected to a connection point between said plurality of first resistors and said second resistors. The plurality of resistors include: a plurality of first resistors to which one of the plurality of switch elements is connected in parallel; and a second resistor connected between the plurality of first resistors and the reference potential point. a resistor and
2. The fault detection circuit according to claim 1, wherein said output terminal is connected to a connection point between said plurality of first resistors and said second resistors. A failure detection method using a failure detection circuit,
The failure detection circuit is
a plurality of resistors connected in series between the DC power supply and the reference potential point;
an output terminal connected to one of the connection points of the plurality of resistors and outputting a voltage at the connection point;
a plurality of switch elements each connected in parallel to any one of the plurality of resistors, each connected to any one of the plurality of circuits, and switched on and off by a failure detection signal from the connected circuit; ,
resistance values of the plurality of resistors are set so that the voltages are different values in a plurality of combinations of on and off of the plurality of switch elements;
The failure detection method includes:
A failure detection method for determining whether or not a failure or abnormality has occurred in each of the plurality of circuits based on the voltage of the output terminal.

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