JP7141046B2 - Nitride semiconductor transistor device - Google Patents

Description

The present invention relates to a nitride semiconductor transistor device, and more particularly to a field effect nitride semiconductor transistor, in which a conductive channel under a gate electrode is substantially turned off when no voltage is applied to the gate electrode. The present invention relates to a nitride semiconductor transistor device that realizes normally-off.

Semiconductors made of nitride semiconductors such as GaN, AlN, InN, or mixed crystals thereof have a wide bandgap and high carrier mobility of conduction electrons, so they are suitable for high-voltage and high-power electronic devices. is. In particular, field-effect transistors (FETs) made of nitride semiconductors, one form of which is high electron mobility using conduction electrons induced at semiconductor heterojunction interfaces such as AlGaN/GaN as conduction channels. A high electron mobility transistor (HEMT) is capable of operating at high voltage, large current, and low on-resistance, and is used as a high-output power amplifier and a high-power switching element.

However, a normal nitride semiconductor FET is a so-called normally-on state in which a conductive channel under a gate electrode is in an ON state when no voltage is applied to the gate electrode. As a switching element used in devices such as power supplies, the switch opens when the control voltage applied to the gate electrode is lost due to a malfunction or failure, leading to the destruction of the entire device. unfavorable from a sexual point of view.

For this reason, several techniques have been developed to make nitride semiconductor FETs normally off. As one technique, a method is known in which a normally-off operation is realized by inserting a p-type nitride semiconductor layer directly under the gate of an FET to form a pn junction gate electrode (see Non-Patent Document 1). In this technology, the operating range of the gate electrode is limited by the flat band voltage determined by the bandgap of the semiconductor. Therefore, if the threshold is a positive voltage, the value stays at 2 V or less, and although a positive threshold of 3 V or more is desired for a normal power supply device, a sufficient threshold cannot be obtained. In addition, since the positive voltage that can be applied to the gate voltage is limited by the ON voltage of the pn junction, the operating voltage amplitude of the gate becomes small, and the current that can flow through the conductive channel in the ON state of the FET is limited.

As another method for realizing normally-off, a method of inserting an insulating film directly under the gate of an FET to form a metal-insulator-semiconductor (MIS) junction type gate electrode is known ( See Non-Patent Document 2). In this method, since the insulator exists under the gate metal, leakage current flowing through the gate electrode can be suppressed to a low level, and a large positive gate voltage can be applied. Therefore, even when the threshold voltage is set to a large positive value, the operating voltage amplitude of the gate can be sufficiently large compared to the case of using a pn junction for the gate electrode.

FIG. 6 shows a cross-sectional structure of a main portion of a GaN FET having a conventional MIS-type gate electrode. Silicon carbide (SiC), silicon (Si), sapphire, GaN, or the like is used as the material of the substrate 1001 . A buffer layer 1002, a GaN layer 1003, and an AlGaN layer 1004 formed by epitaxial growth are sequentially laminated on the substrate 1001. As shown in FIG. A portion of the AlGaN layer 1004 in the gate electrode formation portion is removed by recess etching. A gate electrode 1007 is formed in the recess etching portion 1006 with an insulating film 1005 interposed therebetween. Further forming a source electrode 1008 and a drain electrode 1009 completes the main part of the GaN HEMT. Materials for the insulating film 1005 include, for example, aluminum oxide, silicon oxide, silicon nitride, or other conventionally known gate insulator materials. A conductive channel 1010 is formed by conduction electrons induced on the GaN layer 1003 side of the interface between the GaN layer 1003 and the AlGaN layer 1004 having a bandgap larger than that of the GaN layer 1003 . By changing the conduction electron density in the conductive channel 1010 immediately below the gate electrode 1007 with the voltage applied to the gate electrode 1007, transistor operation is obtained. This conventional FET uses a conductive channel formed at the AlGaN/GaN semiconductor hetero-interface, and is a type of FET called a so-called HEMT.

FIG. 7 shows a cross-sectional structure of a main portion of another conventional GaN FET having an MIS-type gate electrode. Silicon carbide (SiC), silicon (Si), sapphire, GaN, or the like is used as the material of the substrate 1101, as in the conventional example shown in FIG. A buffer layer 1102, a GaN layer 1103, and an AlGaN layer 1104 are sequentially stacked on a substrate 1101 by epitaxial growth. As the material of the insulating film 1105, for example, aluminum oxide, silicon oxide, silicon nitride, or other conventionally known gate insulating materials are used. A difference of this conventional example from the conventional example shown in FIG. The source electrode 1108 and the gate electrode 1107 and the drain electrode 1109 and the gate electrode 1107 are electrically connected by a conductive channel 1110 formed at the AlGaN/GaN interface, and the conductive channel 1111 immediately below the gate electrode is insulated. It is formed by conduction electrons induced at the interface between film 1105 and GaN layer 1103 . By changing the density of the conduction electrons with the voltage applied to the gate electrode 1107, a transistor operation can be obtained.

Y. Umemoto et al. , IEEE Transactions on Electron Devices, Volume 54, Number 12, December 2007, p. 3393. M. Kanamura et al. , IEEE Electron Device Letters, Volume 31, Number 3, March 2010, p. 189. Bongmook Lee, et al, International Electron Device Meeting, 2010, p. 484.

In the conventional example shown in FIG. 6, the purpose of forming the recess etching portion 1006 in the gate electrode portion is to make the threshold voltage of the FET a positive value to make it normally off. Nitride semiconductors used in conventional electronic devices have a hexagonal crystal structure, and a layer grown in the c-axis direction is usually used for ease of epitaxial growth. In this case, large polarization is generated in the AlGaN layer 1004 along the direction perpendicular to the plane (c-axis direction) in the substrate direction due to piezoelectric polarization and spontaneous polarization.

8A and 8B show band diagrams of the semiconductor layer under the gate electrode. This band diagram is for the case where no voltage is applied to the gate. FIG. 8(b) shows a case where the thickness of the AlGaN layer 1004 is made thinner than in the structure of FIG. 8(a). 8(a) and 8(b), due to the polarization (P) 1202 present in the AlGaN layer 1004, the energy value of the conduction band bottom 1201 decreases with increasing distance from the gate electrode. Therefore, as shown in FIG. 8A, when the AlGaN layer 1004 is thick, the ground quantum level formed in the triangular potential well at the contact interface between the AlGaN layer 1004 and the GaN layer 1003 is Fermi Situated below the level 1203 (labeled “EF” in the figure), conduction electrons are induced in the quantum well to form a conducting channel 1010 . In order to make the conduction electrons induced in the conduction channel substantially zero with no gate voltage applied and normally off, the thickness of the AlGaN layer 1004 must be reduced as shown in FIG. 8(b).

As described in Non-Patent Document 2, for example, when the AlN mixed crystal ratio of the AlGaN layer 1004, that is, when x is 20% when the chemical composition is expressed as Al _x Ga _1-x N, the lower portion of the gate electrode 1007 The thickness of the AlGaN layer 1004 should be about 2 nanometers. As x increases, the AlGaN layer 1004 needs to be thinner. On the other hand, in FIG. 6, in the regions between the source electrode 1008 and the gate electrode 1007, and between the drain electrode 1009 and the gate electrode 1007, the AlGaN layer 1004 has a thickness of about 10 nanometers or more, and a sufficient amount of Conduction electrons should be induced into the conducting channel 1010 at the AlGaN/GaN interface to lower the resistance in this region. Therefore, as shown in FIG. 6, it is necessary to grow a thick AlGaN layer 1004 in advance and to thin the AlGaN layer by recess-etching only the portion where the gate electrode is to be formed. However, the threshold voltage varies depending on the thickness of the AlGaN layer remaining after etching. When a large number of transistors are collectively formed in one step, it is difficult to suppress in-plane variations in the amount of etching.

The conventional example shown in FIG. 6 has another problem. Generally, at the interface between a nitride semiconductor and an insulator, a large number of trap levels exist within a range of several hundred millielectron volts from the bottom of the conduction band of the nitride semiconductor. In FIG. 8C, when the AlGaN layer 1004 is made sufficiently thin and the transistor is normally off, a positive gate voltage 1205 (indicated by “V” in the figure) is applied to the gate electrode 1007 to turn the conduction electrons into conduction. In the band diagram showing the state induced in the channel 1010, since the trap level 1204 exists at the interface between the insulating film 1005 and the AlGaN layer 1004, when a positive gate voltage 1205 is applied, the Fermi level 1203 is trapped. Pinned by the level 1204 , the induction of conduction electrons into the conducting channel 1010 by a positive gate voltage 1205 is inhibited. As a result, the on-resistance does not decrease, the on-current does not increase, and the performance as a switch significantly deteriorates.

On the other hand, in the conventional example shown in FIG. 7, recess etching portion 1106 penetrates AlGaN layer 1104 and reaches GaN layer 1103, unlike the case of FIG. Therefore, the influence of the polarization of the AlGaN layer 1004 can be avoided, and the problem of controlling the thickness of the AlGaN layer after etching is eliminated. However, the mobility of conduction electrons in the conductive channel 1111 formed at the interface between the insulating film 1105 and the GaN layer 1103 is several times smaller than the mobility of conduction electrons at the AlGaN/GaN interface. As a result, compared with the so-called HEMT shown in FIG. Also in this conventional example, similarly to the conventional example shown in FIG. However, there is a problem that the current does not decrease and the on-current does not increase, resulting in deterioration of performance as a switch.

As another prior art, Non-Patent Document 3 describes a method of realizing normally-off operation by using a structure in which a charge storage electrode is provided under a gate electrode of a nitride semiconductor FET. A nitride semiconductor FET capable of being normally off by the method includes a first nitride semiconductor layer provided on a substrate and a first nitride semiconductor layer provided on the first nitride semiconductor layer. A second nitride semiconductor layer having a large bandgap, a gate insulating film (hereinafter referred to as a first insulating film) provided thereon, and a charge storage layer provided on the first insulating film It has a gate electrode, and a control gate electrode is provided on the charge storage gate electrode via a block insulating film. A source electrode and a drain electrode are provided on the second nitride semiconductor layer with the charge storage gate electrode interposed therebetween in the plane direction. By injecting electrons from the second nitride semiconductor layer into the charge storage gate electrode and accumulating negative charges in the charge storage gate electrode, the space between the source electrode and the drain electrode can be normally off. . In operation, the voltage applied to the controlling gate electrode controls the current that flows between the source and drain electrodes through the conducting channel.

However, in the conventional structure as described above, the injection of electrons from the second nitride semiconductor layer to the charge storage gate electrode is actually hindered, and a sufficient amount of electrons are stored in the charge storage gate electrode. However, it was found that it was not practical. This is for the following reasons. In order to inject electrons into the charge storage gate electrode, a positive voltage is applied to the control gate electrode, and the charge storage gate electrode is forward biased with respect to the second nitride semiconductor layer by electrostatic capacitive coupling. Therefore, it is necessary to tunnel the conduction electrons in the second nitride semiconductor layer to the charge storage gate electrode. However, the Fermi level is fixed by the trap level existing at the interface between the second nitride semiconductor layer and the first insulating film, and the forward bias voltage is not transmitted to the second nitride semiconductor layer. Electrons necessary for injection are not induced in the second nitride semiconductor layer. In addition, it has been pointed out that device reliability is affected by the application of a high electric field to the first insulating film during electron injection, that the threshold retention time is short, and that uniformity of the threshold is difficult. ing.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a normally-off nitride semiconductor transistor device capable of solving the above-described problems in the conventional nitride semiconductor FET.

In order to solve the above problems, a nitride semiconductor transistor device according to the present invention comprises a substrate, an electrically inactive element isolation region provided on the substrate, and a nitride semiconductor layer provided on the substrate. a first insulating film provided on the nitride semiconductor layer; a charge storage gate electrode provided on at least the first insulating film; and a first charge storage gate electrode provided on the charge storage gate electrode. 2, a first gate electrode provided on the second insulating film, and a source electrode and a drain provided on the nitride semiconductor layer with the charge storage gate electrode interposed in the plane direction. an electrode, a third insulating film provided on the charge storage gate electrode, and a second gate electrode provided on the third insulating film.

The nitride semiconductor layer preferably includes a first nitride semiconductor layer provided on the substrate and at least a portion of the first nitride semiconductor layer provided on the first nitride semiconductor layer. a second nitride semiconductor layer containing at least a nitride semiconductor having a bandgap larger than that of the nitride semiconductor of the second nitride semiconductor layer.

It is preferable that a third insulating film exists on the charge storage gate electrode provided on the element isolation region, and a second gate electrode is provided on the third insulating film on the element isolation region.

In the nitride semiconductor transistor device of the present invention, a current is passed between the second gate electrode and the charge storage gate electrode to store charges in the charge storage gate electrode, thereby increasing the potential of the charge storage gate electrode. change.

When a current is passed between the second gate electrode and the charge accumulating gate electrode to accumulate charges in the charge accumulating gate electrode, a voltage is applied to the first gate electrode to facilitate control of the charge injection amount. can be set to

In the nitride semiconductor transistor device of the present invention, it is preferable that the electric capacity between the first gate electrode and the charge storage gate electrode is larger than the electric capacity between the second gate electrode and the charge storage gate electrode.

The electric capacitance between the first gate electrode and the charge storage gate electrode is the same as the electric capacitance between the second gate electrode and the charge storage gate electrode and the electric capacitance between the source and the charge storage gate electrode. greater than the sum of the electric capacitance between the drain and the charge storage gate electrode, or the electric capacitance between the first gate electrode and the charge storage gate electrode and the electric capacitance between the second gate electrode and the charge storage gate electrode It is preferable that the total capacitance is larger than the sum of the electric capacitance between the source and the charge storage gate electrode and the electric capacitance between the drain and the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, by applying a voltage lower than that of the source and drain electrodes and the first gate electrode to the second gate electrode, a voltage is applied between the second gate electrode and the charge storage gate electrode. It is preferable to pass a current, thereby changing the charge in the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, when sealed in a package, external pins are connected to the first gate electrode, the drain electrode, and the source electrode, respectively, and the external pins are not connected to the second gate electrode. may be the same potential as that of the first gate electrode.

The nitride semiconductor transistor device of the present invention is characterized in that the transistor is off when the voltage of the first gate electrode is 0V or lower.

In the nitride semiconductor transistor device of the present invention, the first gate electrode and the second gate electrode may be insulated.

In the nitride semiconductor transistor device of the present invention, the electric capacity formed by the first gate electrode and the charge storage gate electrode is larger than the electric capacity formed by the charge storage gate electrode and the nitride semiconductor layer. is preferred.

In the nitride semiconductor transistor device of the present invention, the area of the first gate electrode is preferably larger than the area of the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, the overlapping region of the first gate electrode and the charge storage gate electrode preferably protrudes from the charge storage gate electrode toward the drain electrode.

In a preferred embodiment of the nitride semiconductor transistor device of the present invention, the first nitride semiconductor layer is made of GaN, and the second nitride semiconductor layer is made of Al _x Ga _1-x N (0<x≦1). consists of Since the conductive channel induced at the interface between GaN and _{AlxGa1 -xN} has high electron mobility, a normally-off nitride semiconductor transistor device having excellent switch characteristics such as on-resistance and on-current can be obtained.

In another preferred form of the nitride semiconductor transistor device of the present invention, at least the bottom layer of the first insulating film is composed of aluminum oxide. Since aluminum oxide is less likely to generate an interface state at the interface with the nitride semiconductor layer, the positive voltage applied to the first gate electrode is increased to increase the voltage between the first nitride semiconductor layer and the second nitride semiconductor layer. When increasing the current flowing through the conductive channel induced at the interface of the second nitride semiconductor layer and the first insulating film, the on-resistance, A normally-off nitride semiconductor transistor device having excellent switch characteristics such as ON current can be obtained.

According to the present invention, since the second gate electrode is provided on the charge storage gate electrode through the third insulating film, electrons are transferred from the second gate electrode through the third insulating film. The electrons can be injected into the storage gate electrode, and the injection of electrons is performed independently of the first insulating film. Injection of electrons from the semiconductor layer to the charge storage gate electrode is hindered, the desired amount of negative charge cannot be stored in the charge storage gate electrode, and the first insulating film is damaged during charge injection. It is possible to obtain a practical normally-off nitride semiconductor transistor device by solving the problems due to the structure of (1). Note that when the nitride semiconductor layer is composed of the first nitride semiconductor layer and the second nitride semiconductor layer, the thickness of the second nitride semiconductor layer is increased so that the thickness of the first gate electrode is reduced. When the current flowing through the conductive channel is increased by increasing the positive voltage applied to , the influence of the interface level existing between the second nitride semiconductor layer and the first insulating film is reduced. A normally-off nitride semiconductor transistor device having excellent switch characteristics such as on-resistance and on-current can be obtained.

According to the present invention, it is possible to obtain a normally-off nitride semiconductor transistor device which is excellent in switching characteristics such as on-resistance and on-current, and which has little variation in characteristics.

FIG. 1 is a plan view showing a normally-off nitride semiconductor transistor device according to an embodiment of the present invention, and cross-sectional views showing the A-A' and B-B' cross sections thereof, respectively. FIG. 2 is an equivalent circuit diagram showing inter-node capacitances of the transistor device shown in FIG. (a) shows the case when a channel is formed in the channel region included in the active region, and (b) shows the case where the transistor device is turned off and there are substantially no electrons in the channel region. there is FIG. 3 is a plan view showing a device in which a plurality of normally-off nitride semiconductor transistors are connected in parallel according to an embodiment of the present invention, and cross-sectional views showing the a-a' and b-b' cross sections thereof, respectively. FIG. 4 is a plan view showing a normally-off nitride semiconductor transistor device according to another embodiment of the present invention. FIG. 5 is a plan view showing a normally-off nitride semiconductor transistor device according to another embodiment of the present invention, and cross-sectional views showing sections A-A' and B-B' thereof, respectively. FIG. 6 is a plan view and a cross-sectional view of a conventional FET. FIG. 7 is a sectional view of another conventional FET. FIG. 8(a) is a diagram showing a band diagram of a conventional FET. FIG. 8(b) is a diagram showing a band diagram of a conventional FET. FIG. 8(c) is a diagram showing a band diagram of a conventional FET.

FIG. 1 shows a plan view of an FET according to an embodiment of the present invention and its cross-sectional views taken along lines A-A' and B-B'. The plan view and cross-sectional view are slightly different in scale. A buffer layer 102 , a GaN layer 103 and an AlGaN layer 104 are sequentially laminated on a substrate 101 . Silicon carbide (SiC), silicon (Si), sapphire, GaN, or the like is used as the material of the substrate 101 .

Next, as shown in the plan view and cross-sectional view, an isolation region 114 is formed by electrically inactivating the AlGaN layer 104, the GaN layer 103 and the buffer layer 102 by ion implantation. Here, a region not subjected to inactivation treatment is called an active region. A method of removing the AlGaN layer 104 in the isolation region and the underlying GaN layer 103 or buffer layer 102 may be used. Next, a field insulating film 105 is formed. After that, the field insulating film 105 is removed only in the portion of the channel region 106 which will be the channel portion of the FET, and the first insulating film 110 is formed. Thereafter, a charge storage gate electrode 111 is formed from a metal or conductive semiconductor layer. At this time, the charge storage gate electrode 111 exists at least on the first insulating film 110 on the channel region 106, and may also exist on the element isolation region. Here, the charge storage gate electrode 111 may be formed of a plurality of materials that are electrically connected so as to have substantially the same potential. Subsequently, a block insulating film 112 is formed thereon. The block insulating film 112 is an insulating film that can substantially block the flow of electrons, and is composed of a silicon oxide film, a silicon nitride film, an alumina film, a zirconium oxide film, a hafnium oxide film, or a laminated film thereof. The thickness is preferably about 40 nm in terms of SiO2 film. After that, the block insulating film 112 is partially removed on the field insulating film 105 and above the charge storage gate electrode 111 to form the charge injection region 113. In the region 113, on the charge storage gate electrode 111, A tunnel insulating film 115 is formed on the block insulating film 112 except for the region 113 . The tunnel insulating film 115 is an insulating film through which tunnel electrons can flow, and is made of, for example, a silicon oxide film and has a thickness of, for example, 20 nm or less. After that, a first gate electrode 116 and a second gate electrode 117 are formed from a metal or conductive semiconductor layer. The first gate electrode 116 is formed above the main portion of the charge storage gate electrode 111 including above the channel region 106 , and the second gate electrode 117 is formed in the charge injection region 113 to cover the charge storage gate electrode 111 . It is formed in contact with the tunnel insulating film 115 on the upward projecting portion of the element isolation region 114 . After forming an insulating film 118 so as to cover these gate electrodes 116 and 117, the insulating films 105, 110, 112, 115 and 118 of the source formation region 107 and the drain formation region 108 are removed, and metal or metal nitride or the like is deposited. A source electrode 109 and a drain electrode 210 are formed of a conductive material or a laminated film thereof. At this time, the source electrode 109 and the drain electrode 210 may be in contact only with the AlGaN layer 104 or may also be in contact with the GaN layer 103 .
If it can be ensured that the current in the region where the first gate electrode 116 and the charge storage gate electrode 111 overlap during operation is sufficiently small, the step of not forming the block insulating film 112 (thus removing only the region of the charge injection layer is eliminated). unnecessary), the first gate electrode 116 and the charge storage gate electrode 111 may be overlapped with only the tunnel insulating film 115 interposed therebetween.

In the manufacturing process described above, the source electrode 109 and the drain electrode 210 are formed immediately after the field insulating film 105 is formed, and the first insulating film 110 to the first gate electrode 116 and the second gate electrode 117 are formed. I don't mind.

By applying a negative voltage to the second gate electrode 117 with respect to the charge storage gate electrode 111 , electrons are transferred to the second gate electrode 117 via the tunnel insulating film 115 between them in the charge injection region 113 . , is injected into the charge storage gate electrode 111 . The threshold voltage of this FET seen from the first gate electrode 116 changes depending on the charge amount of the charge storage gate electrode 111 . A so-called normally-off FET is realized by controlling the number of electrons injected from the second gate electrode 117 to the charge storage gate electrode 111 so as to obtain a desired positive voltage.

In the regions between the source electrode 109 and the charge storage gate electrode 111 and between the drain electrode 210 and the charge storage gate electrode 111, the thickness of the AlGaN layer 104 is about 10 nanometers or more, and a sufficient amount of conduction electrons is generated. is induced in the conductive channel at the AlGaN/GaN interface to lower the resistance in that region. The AlN mixed crystal ratio of the AlGaN layer 104, ie, the value of x when the chemical formula is expressed as _{AlxGa1 -xN} , is appropriately adjusted so that AlGaN, which has a lattice constant different from that of GaN, does not undergo significant lattice relaxation. Usually x is adjusted between 0.1 and 0.4. The charge storage gate electrode 111 is surrounded by a first insulating film 110, a block insulating film 112 and a tunnel insulating film 115, and is electrically floating. Therefore, when sealed in a package, only the source electrode 109, the drain electrode 210, the first gate electrode 116, and the second gate electrode 117 are connected to external pins. Alternatively, the second gate electrode 117 may be floating and sealed without being connected to an external pin. Four or three electrodes are connected to the external pins.

As the charge storage gate electrode 111, impurity-doped polycrystalline silicon can be used in addition to the metal layer. In that case, impurities such as phosphorus, arsenic, and boron are used.

FIG. 2 shows the inter-node capacitance of the FET shown in FIG. When the first gate electrode 116 is formed through the block insulating film 112 and the tunnel insulating film 115, if the area thereof is sufficiently large, a capacitor 120 formed by the charge storage gate electrode 111 and the first gate electrode 116 can be formed. is larger than the capacitance 121 formed by the second gate electrode 117 and the charge storage gate electrode 111 and the capacitance 119 formed between the charge storage gate electrode 111 and the source and the drain, and the first gate electrode 116 and the charge storage gate electrode 111 can be relatively strengthened. At this time, the overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 may be on the element isolation region 114, but by extending from the channel region 106 to the drain side in the active region, a field plate is formed. can also be expected to play the role of
(a) shows the case where a channel is formed in the channel region 106, and (b) shows the case where the FET is turned off and there are substantially no electrons in the channel region 106. FIG. A capacitor 120 is formed between the first gate electrode 116 and the charge storage gate electrode 111 , and a capacitor 121 is formed between the second gate electrode 117 and the charge storage gate electrode 111 . On the other hand, the capacitance 119 formed between the charge storage gate electrode 111 and the source and the drain is the same as the charge storage gate electrode 111 and the source when the channel is formed in the channel region 106 (FIG. 1A). - formed between regions 122 where inter-drain charge is accumulating; On the other hand, when no channel is formed in the channel region 106 (FIG. (b)), GaN is depleted and a capacitance 123 is formed between the charge storage gate electrode 111 and the source and drain. 123 is extremely small compared to capacitance 119 .

By fixing the voltages of the first gate electrode 116, the source electrode 109, and the drain electrode 210 and applying a lower voltage to the second gate electrode 117, the second gate electrode 117 is changed to the charge storage gate electrode. A charge is injected into 111 . Conditions for operating this FET, for example, when the voltage of the source electrode 109 is 0 V, the voltage of the drain electrode 210 is the high voltage to be used, and the voltage of the second gate electrode 117 is 0 V, from the first gate electrode 116 The apparent threshold voltage Vth is determined by the amount of charge Qth in the charge storage gate electrode 111 . Vth is usually set to a positive voltage. A voltage Vinj lower than that of the first gate electrode 116 and the source electrode 109 is applied to the second gate electrode 117 until the total injection amount reaches Qth. At this time, when the source voltage is 0 V, the voltage of the second gate electrode is Vinj, and the charge amount of the charge storage gate electrode 111 is Qth, the charge of the channel region 106 is substantially extinguished. If a voltage is applied, the capacitance 119 in FIG. 2 changes to a capacitance 123 when the charge amount of the charge storage gate electrode 111 reaches Qth, and the capacitance between the charge storage gate electrode 111 and the source and drain is changed. Since the coupling is weakened, the absolute value of the voltage between the charge storage gate electrode 111 and the first gate electrode 116 and the second gate electrode 117 becomes extremely small, and charge injection stops substantially.

When operating the FET of the present invention after charge injection, in order to reduce the voltage applied to the first gate electrode 116 necessary to turn on and off the current flowing between the source and the drain, the first gate electrode 116 and the charge storage gate electrode 111 is preferably sufficiently larger than the other capacitors. If possible, the capacitor 120 should be the capacitance between the charge storage gate electrode 111 and the region 122 where the charge between the source and the drain is stored in the capacitor 121 formed by the second gate electrode 117 and the charge storage gate electrode 111 . It is desirable to be greater than 119 plus. Alternatively, when operating with the second gate electrode at the same potential as the first gate electrode, it is desirable that the sum of the capacitors 120 and 121 is larger than the capacitor 119 . The overlapping area of the first gate electrode 116 forming the capacitor 120 and the charge storage gate electrode 111 is larger than the overlap area of the second gate electrode 117 and the charge storage gate electrode 111. The area for such a large area is obtained by extending the charge storage gate electrode 111 from the channel region 106 to the drain electrode 210 side in the active region, and forming the block insulating film 112 and the tunnel gate electrode 210 on the top thereof. It can be realized by forming the first gate electrode 116 with the insulating film 115 interposed therebetween.

In the FET of the present invention, the second gate electrode 117 is provided on the portion of the charge storage gate electrode 111 that extends above the isolation region 114 with the tunnel insulating film 115 interposed therebetween. At 113, a current is passed between the second gate electrode 117 and the charge storage gate electrode 111 to store charges in the charge storage gate electrode 111, thereby changing the potential of the charge storage gate electrode. Therefore, the first insulating film 110 is not affected by the charge injection, and the problems of the conventional structure, such as the first insulating film 110 being damaged during the charge injection, can be solved. A normally-off nitride semiconductor FET can be obtained.

Here, when it is desired to obtain a large drain current, a plurality of structures shown in FIG. . At this time, all the second gate electrodes 117 are not connected in parallel, and electron injection is performed by drawing one pad for each transistor or one pad for a plurality of less than the total number of transistors. After adjusting the threshold value, variations in the threshold values of the transistors connected to each other are reduced. Also, if the process of parallel connection is performed by package bonding instead of the wafer process, a semiconductor device in which defective chips are removed and a large current flows is obtained.

In the case of parallel connection, as shown in FIG. 3, the source electrode 109 and the drain electrode 210 are alternately arranged, the charge storage gate 111 is arranged between them, and the first gate electrode 116, the source electrode 109, If the drain electrode 210 is connected, a larger current can be obtained with a smaller area than the above-described parallel connection of single transistors. At this time, when forming the first gate electrode 116 via the block insulating film 112 and the tunnel insulating film 115 in the same manner as in the case of the above-described single unit, if the area thereof is sufficiently large, the charge storage gate electrode 111 and the first gate electrode 116 are formed. A capacitor 120 formed by the first gate electrode 116 is formed by a capacitor 121 formed by the second gate electrode 117 and the charge storage gate electrode 111 and a capacitor 119 formed by the charge storage gate electrode 111 and the source and the drain. growing. At this time, by extending the charge storage gate electrode 111 and the first gate electrode 116 toward the drain side of the active region, it can be expected to play the role of a field plate.

Furthermore, as shown in FIG. 4, the capacitance 120 can be increased by forming an overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 on the isolation region 114 . If the overlapping area on the isolation region 114 is sufficiently large, the extension of the charge storage gate electrode 111 and the first gate electrode 116 toward the drain side may be shortened or eliminated. Alternatively, the overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 may be formed only on the isolation region 114 . In this case also, the charge storage gate electrode 111 can serve as a field plate by extending from the channel region to the drain side in the active region. In this embodiment, the charge storage gate electrode 111 in the active region and the charge storage gate electrode 111 formed on the element isolation region 114 are simultaneously formed with a common conductive film. The charge storage gate electrode 111 and the charge storage gate electrode 111 formed over the element isolation region 114 may be formed of different conductive films and electrically connected.

As shown in FIG. 3, the second gate electrode 117 may be provided one by one for each cell composed of one source/drain and the charge storage gate electrode 111, or may be provided for a plurality of cells. It does not matter if it is set. In the case of one place as a whole, it may be outside the cell as shown in FIG. If there is only one cell in total, the threshold value is adjusted by the charge injection method described above. However, if the cell is divided and the second gate electrode 117 is formed, the charge injection stops for each unit, so the threshold value adjustment is high. be refined.

In the above embodiments, the case of using GaN and AlGaN as nitride semiconductors has been described. Since the bandgap of AlGaN is larger than that of GaN, a conducting channel is formed on the GaN side of the interface between AlGaN and GaN. This conductive channel is used in the embodiments described above. The present invention may use nitride semiconductors other than GaN and AlGaN. For example, nitride semiconductors containing In such as InN, InGaN, and InAlN may be used. Alternatively, a multilayer structure of nitride semiconductors having different compositions may be used. Materials and compositions may be selected so that the main portion of the lower layer is formed of a nitride semiconductor with a small bandgap, and the main portion of the upper layer is formed of a nitride semiconductor with a large bandgap.

For the purpose of protecting the surface of the second nitride semiconductor, another nitride semiconductor having a composition different from that of the second nitride semiconductor may be inserted. For example, when the first nitride semiconductor is GaN and the second nitride semiconductor is AlGaN, a thin GaN layer may be inserted directly above AlGaN.

In the channel region 106, the first insulating film 110 may be formed after the AlGaN layer 104 is partially etched. In this case, since the AlGaN layer 104 becomes thinner, the current flowing through the conductive channel is increased by increasing the positive voltage applied to the first gate electrode. The Fermi level is likely to be fixed at the trap level, and as a result, induction of conduction electrons to the conduction channel is inhibited, and characteristics such as on-resistance are degraded. On the other hand, since the AlGaN layer 104 becomes thinner and the amount of shift of the threshold voltage to the negative side due to polarization decreases, the amount of negative charges injected into the charge storage gate electrode 111 should be reduced in order to obtain a desired positive threshold voltage. can be done. Variation in the etching depth causes variation in the initial threshold voltage, but the variation can be compensated for by the above-described method of automatically stopping charge injection into the charge storage gate electrode 111 or the like.

In the above embodiments, the case where the conductive channel of the channel region is formed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer has been described. On the other hand, in the present invention, a first insulating film is provided directly above a single-layer nitride semiconductor, and a current flows between the source and the drain through a conductive channel formed at the interface between the nitride semiconductor and the first insulating film. It can also be applied to flowing nitride semiconductor transistors. An example of this case is shown in FIG. In FIG. 5, the AlGaN layer 104 in the channel region is removed in the embodiment shown in FIG. A gate electrode 111 is formed. A current between the source and drain during transistor operation flows through a conductive channel formed at the interface between the first insulating film 110 and the GaN layer 103 . Otherwise, it is the same as the embodiment shown in FIG. Adjustment of the threshold voltage of the transistor may also be performed in the same manner as the method described with reference to FIGS. In the nitride semiconductor transistor of this example, the conductive channel is strongly affected by the trap level existing at the interface between the first insulating film 110 and the GaN layer 103, and the electron mobility in the conductive channel is reduced. Induction of electrons into the conductive channel by application of a positive voltage to the gate electrode 116 is hindered. Inferior. However, since there is no shift of the threshold voltage to the negative side due to the polarization of the AlGaN layer, the amount of negative charge injected into the charge storage gate electrode 111 is significantly reduced in order to obtain the positive threshold voltage necessary for the desired normally-off operation. can be reduced. Further, when a desired threshold voltage is reached, charge injection from the second gate electrode 117 to the charge storage gate electrode 111 can be automatically stopped. Similar to the case of the nitride semiconductor transistor described with reference to FIGS.

The nitride semiconductor transistor device of the present invention is useful mainly as a power switch used in power supply circuits and the like. In addition, it is also useful as a high-frequency transistor used for wireless communication, sensors, and the like. When used as a high-frequency transistor, adjusting the threshold voltage to a positive value according to the present invention enables the transistor to operate with only a positive voltage power supply, thereby eliminating the negative voltage power supply that was conventionally required. Even when the threshold voltage of the transistor is kept negative, the method of adjusting the threshold voltage according to the present invention can reduce the variation in the threshold voltage between transistors, or, in the case of a transistor having a plurality of gate electrodes, the difference between the gates within the transistor. Variation in threshold voltage can be reduced, and a good transistor with less variation in characteristics can be obtained.

DESCRIPTION OF SYMBOLS 101... Substrate, 102... Buffer layer, 103... GaN layer, 104... AlGaN layer, 105... Field insulating film, 106... Channel region, 107... Source formation region, 108... Drain forming region 109... Source electrode 210... Drain electrode 110... First insulating film 111... Charge storage gate electrode 112... Block insulating film 113... Charge injection region 114... Element isolation region 115... Tunnel insulating film 116... First gate electrode 117... Second gate electrode 118... Insulating film , 119 . Inter-electrode capacitance, 122 . DESCRIPTION OF SYMBOLS 1001... Substrate, 1002... Buffer layer, 1003... GaN layer, 1004... AlGaN layer, 1005... Insulating film, 1006... Recess etching part, 1007... Gate electrode, 1008 Source electrode 1009 Drain electrode 1010 Conductive channel 1101 Substrate 1102 Buffer layer 1103 GaN layer 1104 AlGaN layer 1105 Insulating film 1106 Recess etching portion 1107 Gate electrode 1108 Source electrode 1109 Drain electrode 1110 Conductive channel 1111 Conductive channel 1201 Conduction band bottom, 1202... Polarization (P) present in the AlGaN layer, 1203... Fermi level (EF), 1204... Trap level, 1205... Positive gate voltage

Claims (24)

a substrate, an electrically inactive element isolation region provided on the substrate, a nitride semiconductor layer provided on the substrate, and a first insulating film provided on the nitride semiconductor layer a charge storage gate electrode provided on at least the first insulating film; a second insulating film provided on the charge storage gate electrode; and a second insulating film provided on the second insulating film. 1 gate electrode, a source electrode and a drain electrode provided on the nitride semiconductor layer with the charge storage gate electrode interposed in the plane direction, and a third insulation provided on the charge storage gate electrode. and a second gate electrode provided on the third insulating film ,
The electric capacitance formed by the first gate electrode and the charge storage gate electrode is greater than the electric capacitance formed by the charge storage gate electrode and the nitride semiconductor layer when the transistor is in an ON state. A nitride semiconductor transistor device characterized by being large . a substrate, an electrically inactive element isolation region provided on the substrate, a nitride semiconductor layer provided on the substrate, and a first insulating film provided on the nitride semiconductor layer a charge storage gate electrode provided on at least the first insulating film; a second insulating film provided on the charge storage gate electrode; and a second insulating film provided on the second insulating film. 1 gate electrode, a source electrode and a drain electrode provided on the nitride semiconductor layer with the charge storage gate electrode interposed in the plane direction, and a third insulation provided on the charge storage gate electrode. and a second gate electrode provided on the third insulating film,
A plurality of the transistors are connected in parallel, the electrodes other than the second gate electrodes are connected in parallel, and one or all of the transistors are provided with the second gate electrodes one by one. A nitride semiconductor transistor device characterized by comprising: The third insulating film is present on the charge storage gate electrode provided on the element isolation region, and the second gate electrode is provided on the third insulating film. 3. The nitride semiconductor transistor device according to item 1 or 2 . A current is passed between the second gate electrode and the charge accumulating gate electrode to accumulate charges in the charge accumulating gate electrode, thereby changing the potential of the charge accumulating gate electrode. 4. The nitride semiconductor transistor device according to any one of claims 1 to 3 . When a current is passed between the second gate electrode and the charge accumulating gate electrode to accumulate charges in the charge accumulating gate electrode, a voltage is applied to the first gate electrode to obtain a charge injection amount. 5. The nitride semiconductor transistor device according to claim 4 , wherein the control of is facilitated. Said a first gate electrode;SaidThe electric capacity between the charge storage gate electrodes isSaida second gate electrode;Said1. The electric capacity between the charge storage gate electrodes is larger than that of the charge storage gate electrodes.5Nitride semiconductor transistor device according to any one of Said a first gate electrode;SaidThe electric capacitance between the charge storage gate electrodes isSaida second gate electrode;SaidThe electric capacitance between the charge storage gate electrodes andSaidsauceelectrodeWhenSaidThe electric capacitance between the charge storage gate electrodes andSaiddrainelectrodeWhenSaid1. The capacitance is larger than the sum of the electric capacitance between the charge storage gate electrodes.5Nitride semiconductor transistor device according to any one of Said on the second gate electrodeSaida source electrode and the drain electrode;SaidBy applying a voltage lower than that of the first gate electrode,Saida second gate electrode;SaidA current is passed between the charge storage gate electrodes, therebySaid2. The method according to claim 1, wherein the charge in the charge storage gate electrode is changed.7A nitride semiconductor transistor device according to any one of Said When the first gate electrode is 0 V or lessSaid1 to 4, characterized in that the transistor is in an off state.8Nitride semiconductor transistor device according to any one of Said a first gate electrode;Said1. The method according to claim 1, wherein said second gate electrode is insulated.9Nitride semiconductor transistor device according to any one of Said a first gate electrode;Said3. The electrical capacity formed by the charge storage gate electrode is larger than the electrical capacity formed by the charge storage gate electrode and the nitride semiconductor layer when the transistor is in an ON state.2to10Nitride semiconductor transistor device according to any one of Said The area of the first gate electrode isSaid2. The claim characterized in that it is larger than the overlapping area of the charge storage gate electrode and the channel region.11nitride semiconductor transistor device. 13. The nitride semiconductor transistor device according to claim 1 , wherein a region where said first gate electrode and said charge storage gate electrode overlap projects from a channel region toward said drain electrode. 14. The nitride semiconductor transistor device according to claim 1 , wherein said second insulating film and said third insulating film are the same insulating film. 15. The nitride semiconductor transistor device according to claim 1 , wherein said third insulating film is a tunnel insulating film. 14. The nitride semiconductor transistor device according to claim 1 , wherein said second insulating film includes a block insulating film. A plurality of the transistors are connected in parallel, the electrodes other than the second gate electrodes are connected in parallel, and one or all of the transistors are provided with the second gate electrodes one by one. 17. The nitride semiconductor transistor device according to any one of claims 1 , 3 to 16 . 18. The nitride semiconductor transistor device according to claim 17 , which has a finger structure in which, when connecting said plurality of transistors, said source electrodes and said drain electrodes are alternately arranged, and said charge storage gate electrode is arranged therebetween. A voltage is applied to the first gate electrode to determine a charge injection amount when a current is passed between the second gate electrode and the charge accumulating gate electrode to accumulate charges in the charge accumulating gate electrode. 19. The nitride semiconductor transistor device according to claim 17 or 18 , wherein the charge amount is adjusted for each portion having the second gate electrode in common when the control is performed using the second gate electrode. 20. The nitride semiconductor transistor device according to claim 1, wherein at least the bottom layer of said first insulating film is made of aluminum oxide. 21. The nitride semiconductor transistor device according to claim 1, wherein said nitride semiconductor layer is made of GaN. The nitride semiconductor layer includes a first nitride semiconductor layer provided on the substrate and a nitride of at least a part of the first nitride semiconductor layer provided on the first nitride semiconductor layer. 21. The nitride semiconductor transistor device according to any one of claims 1 to 20 , comprising a second nitride semiconductor layer containing at least a nitride semiconductor having a bandgap larger than that of the semiconductor. 23. The nitriding process according to claim 22 , wherein said first nitride semiconductor layer is composed of GaN, and said second nitride semiconductor layer is composed of AlxGa1-xN (0<x≤1). object semiconductor transistor device. A package comprising the nitride semiconductor transistor device according to any one of claims 1 to 23 and a package for sealing the nitride semiconductor transistor device, wherein the first gate electrode and the drain electrode of the nitride semiconductor transistor device 2. A nitride semiconductor device, wherein said source electrodes are connected to respective external pins of said package, and said second gate electrodes of said nitride semiconductor transistor device are not connected to external pins.

Images