JP7134816B2 - Chip unique random number generator - Google Patents

Description

The present invention relates to a chip unique random number generating circuit.

A physical unclonable function (PUF) has attracted attention in order to prevent malicious duplication of semiconductor chips. A PUF uses variations in elements formed on a semiconductor chip to generate reproducible random numbers, and is understood as a unique “fingerprint” for each chip. This random number is used, for example, as a secret key for encryption.

The random numbers generated by the PUF can be designed so that they do not exist in memory or other static state, making them robust against reverse engineering (peeping). Utilizing this feature, it is expected to be applied in the field of security.

SRAM (Static Random Access Memory)-PUF has been proposed as an implementation example of PUF. FIG. 1 is a circuit diagram of a cell of an SRAM-PUF circuit. Cell 100 includes a pair of cross-coupled inverters 102,104. The cell bit value immediately after the circuit is activated is determined according to the balance between the logic threshold values _Vth of the inverters 102 and 104, respectively. Since the logic threshold value V _th(gs) varies from cell to cell, the set of values for a plurality of cells is a random number.

Y. Su, et. al. "A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations", JSSC, Vol. 43, No. 1, pp. 69-77, January 2008 D. E. Holcomb, et. al, "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers," IEEE Trans. on Computers, Vol. 58, No. 9, pp. 1198-1210, Sept. 2009.

However, since the variation is very small and varies depending on environmental conditions such as power supply voltage and temperature, there is a problem that the value changes due to the influence of thermal noise and environmental variation, and bit error occurs.

The present invention has been made in view of such problems, and one exemplary purpose of certain aspects thereof is to provide a PUF circuit with a reduced bit error rate.

One aspect of the present invention relates to a chip-specific random number generator (PUF circuit). The chip-specific random number generator circuit includes cross-coupled first and second inverters and an imbalance generator that imparts a controllable imbalance to the electrical states of the first and second inverters.

Arbitrary combinations of the above constituent elements, or conversions of the expressions of the present invention between methods, apparatuses, and the like are also effective as embodiments of the present invention.

According to one aspect of the present invention, the bit error rate can be reduced.

1 is a circuit diagram of a cell of an SRAM-PUF circuit; FIG. 1 is a circuit diagram of a PUF circuit according to an embodiment; FIG. 1 is a circuit diagram of a cell according to an embodiment; FIG. FIGS. 4(a) to 4(c) are diagrams illustrating the screening of unstable cells. FIGS. 5(a) to 5(d) are diagrams for explaining screening using an imbalance generator. 1 is a circuit diagram of a cell according to one embodiment; FIG. FIGS. 7(a) to 7(c) are diagrams showing butterfly curves at power-on of a cell using an EE inverter. 1 is a circuit diagram of a cell according to one embodiment; FIG. 1 is a circuit diagram of a PUF circuit with cells; FIG. 1 is a circuit diagram of a cell and imbalance generator according to one embodiment; FIG. 11(a)-(c) are circuit diagrams of the imbalance generator. 1 is a circuit diagram of a PUF circuit according to one embodiment; FIG. 13 is a circuit diagram of a cell used in the PUF circuit of FIG. 12; FIG. 1 is a circuit diagram of a cell and imbalance generator according to one embodiment; FIG. It is a figure explaining the concept of the bit error improvement method by carrier injection.

(Overview of Embodiment)
This specification discloses a chip-specific random number generation circuit (also referred to as a PUF circuit) according to one embodiment. The chip-specific random number generator circuit includes cross-coupled first and second inverters and an imbalance generator that imparts a controllable imbalance to the electrical states of the first and second inverters.

According to this embodiment, it is possible to screen bits with unstable values by checking the values of the bits while changing the electrical state.

The imbalance generator may be capable of applying different voltages to corresponding ends of the first inverter and the second inverter. This can imbalance the electrical states of the two inverters.

The imbalance generator may be capable of inserting variable impedance into each of the current path of the first inverter and the current path of the second inverter. This can imbalance the electrical states of the two inverters.

The imbalance generator includes a first switch provided between one end of the first inverter and the fixed voltage line, a second switch provided between one end of the second inverter and the fixed voltage line, and one end of the first inverter. and at least one impedance element provided between the one end of the second inverter. The fixed voltage line may be a ground line or a power supply line.

Each of the first inverter and the second inverter may be an EE (Enhancement Enhancement) inverter, and the gate of the load transistor may be connected to the control line. Using an EE inverter can reduce bit errors compared to using a CMOS inverter. However, when an EE inverter is used, a steady current flows through one of the inverters. In order to prevent this, the gate of the load transistor is made controllable for dynamic operation, thereby preventing an increase in power consumption.

Each of the first inverter and the second inverter may be an EE (Enhancement Enhancement) inverter. In this case, the imbalance generator may be capable of applying separate control voltages to the gates of the load transistors of each of the first and second inverters. This makes it possible to imbalance the electrical states of the two inverters.

An imbalance generator may be provided for each cell. This simplifies control.

One imbalance generator may be provided for every plurality of cells. For example, there may be one imbalance generator per word line, one imbalance generator per bit line pair, or one imbalance generator per cell matrix. may be provided, or one imbalance generator may be provided for the entire PUF circuit. Inter-cell interference can be reduced by reducing the number of cells connected to one imbalance generator. Conversely, if the number of cells connected to one imbalance generator is increased, the number of imbalance generators can be reduced and an increase in circuit area can be suppressed.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, or a case in which member A and member B are electrically connected to each other. It also includes the case of being indirectly connected via other members that do not substantially affect the connected state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, as well as the case where they are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

FIG. 2 is a circuit diagram of the PUF circuit 200 according to the embodiment. The PUF circuit 200 includes a plurality of cells C arranged in a matrix of M rows and N columns (M and N are arbitrary integers), M word lines WL ₁ to WL _M , and N bit line pairs BL. _1, \BL ₁ through BL _N, including \BL _N. The symbol \ represents negative logic. Let C _ij be the cell in the i-th row and the j-th column. A sense amplifier SA _j is connected to the bit line pair BL _j, \BL _j of the j-th column (1≦j≦N).

When the semiconductor chip on which the PUF circuit 200 is mounted is activated, each cell stabilizes to a state determined by process variations. A random number is then generated by reading the values of multiple cells.

FIG. 3 is a circuit diagram of a cell 300 according to an embodiment. Cell 300 mainly comprises latch circuit 310 , read circuit 320 and imbalance generator 330 . FIG. 3 shows the cell at the i-th row and the j-th column.

Latch circuit 310 includes a first inverter 312 and a second inverter 314 that are cross-coupled. The read circuit 320 includes a transistor M31 interposed between the output of the first inverter 312 and the bitline BLj, and a transistor M32 interposed between the output of the second inverter 314 and the inverted bitline \ _BLj .

The imbalance generator 330 becomes active during the test process of the semiconductor chip including the PUF circuit 200 to provide a controllable imbalance to the electrical states of the first inverter 312 and the second inverter 314 . When the PUF circuit 200 generates a unique random number after the shipment of the semiconductor chip (during normal operation), the imbalance generator 330 is inactive, and the imbalance generator 330 is inactive to provide an imbalance to the electrical states of the first inverter 312 and the second inverter 314. balance is zero.

The above is the configuration of the PUF circuit 200 . Each cell (latch circuit 210) of the PUF circuit is required to stabilize to the same value each time the circuit is activated. However, since the PUF circuit utilizes minute variations in a pair of inverters that constitute a latch circuit, the value taken by one cell may differ each time it is activated. Such cells are called unstable cells. Since unstable cells cause bit errors, it is necessary to perform processing for detecting unstable cells (screening) in the inspection process of semiconductor chips. Then, the positions (addresses) of unstable cells are held as information, and the unstable cells are not used (masked).

FIGS. 4(a) to 4(c) are diagrams illustrating the screening of unstable cells. In a conventional PUF circuit that does not have the imbalance generator 330, activation and reading of the PUF circuit are repeated many times to detect unstable cells. FIGS. 4A to 4C show probability distributions with a cell value of 1. FIG. Specifically, as shown in FIG. 4A, the probability P1 (P0) that the value is 1 (or 0) is obtained for each cell. Then, as shown in FIG. 4(b), cells with a probability P1 higher than an upper threshold value (for example, 99%) and cells lower than a lower threshold value (for example, 1%) are judged to pass, and the rest are judged to fail. (that is, an unstable cell) and mask it. Since P1+P0=100%, cells with P1<1% correspond to cells with P0>99%. Alternatively, conventionally, the upper threshold value is set to 100% and the lower threshold value is set to 0%, ie, a cell in which even once a value different from the majority is regarded as a failure.

FIG. 4(c) shows the probability distribution when temperature fluctuations occur after the mask of FIG. 4(b). Before the temperature fluctuation occurred, P1<1% in the cell Cx, but due to the temperature fluctuation, 20%<P1<80%. In the cell Cy, P1>99% before the temperature fluctuation occurred, but 80%<P1<99% due to the temperature fluctuation. In other words, the above-described screening alone cannot detect potentially unstable cells that become unstable only due to temperature changes or the like.

This problem causes problems such as an increase in cost and a longer test time if screening is actually performed while changing the temperature. In addition to temperature fluctuations, various other factors such as power supply voltage fluctuations and long-term use (i.e. aging) can affect the probability distribution.

5A to 5D are diagrams for explaining screening using the imbalance generator 330. FIG. At the time of screening, the imbalance generator 330 applies imbalance with a polarity that makes the value of the latch circuit 310 equal to 1, thereby detecting unstable cells. An imbalance generator 330 applies an imbalance with a polarity that makes the value of the latch circuit 310 zero, thereby detecting an unstable cell.

FIG. 5(a) shows the probability distribution when the imbalance is zero, which is the same as that of FIG. 4(a). FIG. 5(b) is the probability distribution when imbalance is applied with the first polarity, and FIG. 5(c) is the probability distribution when imbalance is applied with the second polarity. Finally, in all of FIGS. 5(a) to (c), only the stable cells (P1>99%, P1<1%) are used and the rest are masked (FIG. 5(d) ). Bold Xs represent potentially unstable cells detected due to imbalance introduction.

The above is the operation of the PUF circuit 200 . According to this PUF circuit 200, by applying an imbalance to the latch circuit 310 by the imbalance generator 330 at the time of screening, it is possible to simulate fluctuations in element characteristics that may occur due to temperature fluctuations and power supply voltage fluctuations. It can detect potentially unstable cells caused by various factors such as temperature fluctuations and power supply voltage fluctuations. As a result, the bit error rate during actual operation can be reduced.

The present invention extends to various apparatus and methods grasped as the block diagram and circuit diagram of FIG. 3 or derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific configuration examples and embodiments will be described not for narrowing the scope of the present invention, but for helping to understand the essence and operation of the invention and clarifying them.

FIG. 6 is a circuit diagram of a cell 300A according to one embodiment. In this cell 300A, the first inverter 312 and the second inverter 314 of the latch circuit 310A are EE ((Enhancement Enhancement) inverters. The EE inverter includes not only the lower drive transistors M12 and M22 but also the upper load transistors. 6 and 8, the imbalance generator 330 is omitted.

FIGS. 7(a) to 7(c) are diagrams showing butterfly curves at power-on of a cell using an EE inverter. In FIGS. 7A to 7C, the power supply voltage V _DD is different. As shown in FIG. 7B, as the power supply voltage V _DD rises (V _DD =1.2 V), the monostable point shifts to one side according to the variation. When the power supply voltage V _DD further increases (V _DD =1.6V), it is induced to one of the bistable points, as shown in FIG. 7(c). Thus, by using the EE inverter, the transition from monostable to bistable occurs in the strong inversion state (ON state) of the MOS transistors forming the inverter, so that the transition can be made quickly compared to the CMOS inverter. A stable PUF that is less susceptible to thermal noise is obtained. This means that the proportion of unstable cells can be reduced when the above screening is performed. In other words, the size of the entire PUF circuit 200 can be reduced when a random number of a certain number of bits is required.

The cell 300A of FIG. 6 has the drawback that the power consumption is large because the load transistors M11 and M21 are always on, and a direct current steadily flows through one of the inverters 312 and 314. FIG. The increase in current consumption is resolved by the embodiments described below.

FIG. 8 is a circuit diagram of a cell 300B according to one embodiment. In the cell 300B, the gates of the load transistors M11 and M21 are connected to the row-by-row control line LE _i (i is the row number), and their drains are connected to the column-by-column control line PE _j (j is the column number). be. A plurality of control lines LE and a plurality of control lines PE can be individually activated.

FIG. 9 is a circuit diagram of a PUF circuit 200B comprising cells 300B. In this example, a configuration of 32 rows and 2 columns is shown.

In the bit cell array, the activation voltages (V _LE , V _CELL ) are applied only to the control lines LE _i and PE _j corresponding to the selected bit cells, so that the DC current of the EE inverter flows only to the selected bit cells. become. Therefore, compared with the cell 300A of FIG. 6, it is possible to significantly reduce the power consumption. Power consumption can be further reduced by inactivating all control lines LE and PE after reading. At this time, if the control line PE is set to the inactive voltage before the control line LE, the charge stored in the node inside the cell is quickly erased, so that the resistance to reverse engineering (peeking) can be enhanced.

In the cell 300B of FIG. 8, the gate and drain voltages of the load transistors M11 and M21 are controllable, but only one of them may be controllable.

The configuration of the inverters 312 and 314 that constitute the latch circuit 310 is not limited to the EE inverter, and a CMOS inverter as shown in FIG. 1 can also be used.

Next, the configuration of imbalance generator 330 will be described. FIG. 10 is a circuit diagram of an imbalance generator 330C and a cell 300C according to one embodiment. The imbalance generator 330C is configured to generate a potential difference between the source voltages VSSA and VSSB of the first inverter 312 and the second inverter 314 as an imbalance. 10 shows a combination with the latch circuit 310B of FIG. 8, it may be combined with the latch circuit 310A of FIG.

By introducing a potential difference into the source voltages VSSA and VSSB, the gate-source voltage of the driving transistors M12 and M22 can be changed.

11(a) and (b) are circuit diagrams of an imbalance generator 330C according to one embodiment. As shown in FIG. 11(a), the imbalance generator 330C includes a variable impedance circuit 332, a first switch SWA, and a second switch SWB. A variable impedance circuit 332 is provided between the sources of the drive transistors M12 and M22. A first switch SWA is provided between the source of the driving transistor M12 and the ground, and a second switch SWB is provided between the source of the driving transistor M22 and the ground.

During normal operation, both the first switch SWA and the second switch SWB are turned on, and the imbalance generator 330C is made inactive. During screening, one of the first switch SWA and the second switch SWB is turned on and the other is turned off according to the polarity of the imbalance.

Consider the state where the first switch SWA is on. A direct current _IDC2 flowing through the second inverter 314 flows to the ground via the variable impedance circuit 332 and the first switch SWA. Since a potential difference ΔV=I _DC2 ×R is generated in the variable impedance circuit 332, VSSB=VSSA+ΔV, and a first polarity imbalance is introduced.

When the second switch SWA is on, the DC current _IDC1 flowing through the first inverter 312 flows to the ground via the variable impedance circuit 332 and the second switch SWA. At this time, VSSB=VSSA-ΔV, and a second polarity imbalance is introduced.

By changing the resistance value R, the amount of imbalance (potential difference here) can be adjusted.

As shown in FIG. 11(b), the variable impedance circuit 332 may include multiple MOS transistors connected in parallel. Combining the ON/OFF states of a plurality of transistors can change their combined impedance. The configuration of the variable impedance circuit 332 is not limited to that of FIG. 11(b).

FIG. 11(c) is a circuit diagram of an imbalance generator 330D according to one embodiment. The imbalance generator 330D can insert variable impedances RA and RB into the current path of the first inverter 312 and the current path of the second inverter 314, respectively. Specifically, the imbalance generator 330</b>D includes a first switch SWA, a second switch SWB, a first variable impedance circuit 334 and a second variable impedance circuit 336 .

A first variable impedance circuit 334 is provided in parallel with the first switch SWA between the source of the first inverter 312 and the ground. Similarly, a second variable impedance circuit 336 is provided in parallel with the second switch SWB between the source of the second inverter 314 and ground.

During normal operation, both the first switch SWA and the second switch SWB are turned on.

At the time of screening, at least one of the first switch SWA and the second switch SWB is turned off. When the first switch SWA is off, VSSA=I _DC1 ×RA, and when it is on, VSSA=0V. When the second switch SWB is off, VSSB=I _DC2 ×RB, and when it is on, VSSB=0V. The imbalance generator 330D can generate a variable imbalance by controlling the ON/OFF combination of the switches SWA and SWB and the impedances RA and RB. Here, variable impedance is used to enable adjustment of imbalance, but fixed impedance may be used. That way, the circuit configuration can be simplified.

In one embodiment, imbalance generator 330 is shared by multiple cells. FIG. 12 is a circuit diagram of a PUF circuit 200F according to one embodiment. In this embodiment, imbalance generator 330C is commonly provided for all cells 300F. FIG. 13 is a circuit diagram of a cell 300F used in PUF circuit 200F of FIG. In this embodiment, the sources of the first inverters 312 of all cells 300F are connected in common and the voltage VSSA generated by the imbalance generator 330C can be applied. Also, the sources of the second inverters 314 of all the cells 300F are connected in common, and the voltage VSSB generated by the imbalance generator 330C can be applied. According to this embodiment, the number of imbalance generators 330C can be reduced, and an increase in circuit area can be suppressed.

In another embodiment, one imbalance generator may be provided for each row of cells or one may be provided for each column of cells.

FIG. 14 is a circuit diagram of a cell 300E and an imbalance generator 330E according to one embodiment. In this embodiment, imbalance generator 330E generates imbalance by controlling gate voltages V _G1 and V _G2 of load transistors M11 and M21 of first inverter 312 and second inverter 314, respectively. According to this embodiment, an imbalance can be introduced into the impedances of the load transistors M11 and M21.

Although the application of the imbalance generator has been described as a means for screening unstable cells in the semiconductor chip inspection process, the present invention is not limited to this. For example, the imbalance generator can be used for off-line margin checks and additional screening after shipment of semiconductor chips. In this case, the imbalance may be made smaller than that in the inspection process to reduce the frequency of occurrence of warnings or to reduce the number of additional mask cells.

Next, techniques for further reducing bit errors will be described. FIG. 15 is a diagram for explaining the concept of a method for improving bit errors by carrier injection. The PUF circuit is configured such that a voltage V _HIGH higher than the power supply voltage VDD during normal operation can be applied to the drains of the load transistors M11 and M21 of each cell (that is, the control line PEj). For example, when V _DD =1.5V, V _HIGH =about 3 to 4V.

At a stage (for example, a manufacturing process or an inspection process) prior to the actual use of the latch-type PUF using the EE inverter, values are determined as evaluation data. Then, without changing the value, the voltage (V _PEj ) of the drains of the load transistors M11 and M21 is raised higher than the voltage during normal operation (that is, the power supply voltage V _DD ) for a certain period of time. The length of this fixed period is such that the reliability of the transistor is not degraded by application of a high voltage, and may be, for example, several tens to several hundreds of milliseconds. The application of the high voltage V _HIGH selectively injects hot carriers into two diagonally arranged transistors among the four transistors forming the latch, thereby increasing the imbalance.

For example, when the cell value is "1", Va=Hi and Vb=Lo as shown in FIG. 15, hot carriers are injected into the transistors M21 and M12 having a large drain-source voltage _VDS . Since the original imbalance where Va=Hi and Vb=Lo is in the direction of Vth _(M21) > Vth _(M11) and Vth _(M22) > Vth _(M12) , the imbalance is enhanced by selective hot carrier injection. can do.

At this time, if the _LE voltage (gate voltage) V_LE is set to an optimum voltage different from the _PE voltage V_PE so that the injection amount of hot electrons increases, the imbalance can be expanded efficiently. In general, hot electron injection into the load transistors M11 and M21 can be increased by setting V _LE <V _PE . For example, if V _LE =V _DD , the relationship V _LE <V _PE is naturally satisfied, but a more optimum voltage different from V _DD may be selected as the gate voltage V _LE during carrier injection.

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that this embodiment is merely an example, and that various modifications can be made to the combination of each component and each treatment process, and that such modifications are within the scope of the present invention. be. Such modifications will be described below.

Although the imbalance generator 330C is provided on the source side of the inverter in FIG. 10, it may be provided on the drain side to imbalance the power supply voltage. Imbalance in the power supply voltage introduces an imbalance in the voltage of the inverter and, in turn, the gate voltage of the drive transistor.

200 PUF circuit 300 cell 310 latch circuit 312 first inverter 314 second inverter 320 read circuit 330 imbalance generator 332 variable impedance circuit 334 first variable impedance circuit 336 second variable impedance circuit SWA first switch SWB second switch

Claims (11)

cross-coupled first and second inverters;
an imbalance generator that provides a controllable imbalance in the electrical states of the first inverter and the second inverter;
with
A chip-specific random number generating circuit, wherein the first inverter and the second inverter are EE (Enhancement Enhancement) inverters, and the gate of the load transistor is connected to a control line. cross-coupled first and second inverters;
an imbalance generator that provides a controllable imbalance in the electrical states of the first inverter and the second inverter;
with
each of the first inverter and the second inverter is an EE (Enhancement Enhancement) inverter;
The chip-specific random number generator, wherein the imbalance generator can apply individual control voltages to the gates of the load transistors of the first inverter and the second inverter. A chip-specific random number generator,
cross-coupled first and second inverters;
becomes active in an inspection process of a semiconductor chip having the chip-specific random number generation circuit, and the electrical states of the first inverter and the second inverter are imbalanced with a first polarity, imbalanced with a second polarity and zero imbalanced. an imbalance generator providing
with
A chip-specific random number generating circuit which is not used when the first polarity, the second polarity, and the zero imbalance do not show the same value. 4. The chip-specific random number generator circuit according to claim 3 , wherein said imbalance generator can apply different voltages to one end of said first inverter and one end of said second inverter. 4. The chip-specific random number generating circuit according to claim 3 , wherein said imbalance generator can insert variable impedances into the current path of said first inverter and the current path of said second inverter. The imbalance generator is
a first switch provided between one end of the first inverter and a fixed voltage line;
a second switch provided between one end of the second inverter and the fixed voltage line;
at least one impedance element provided between the one end of the first inverter and the one end of the second inverter;
6. The chip-specific random number generation circuit according to claim 3 , comprising: 7. The chip-specific random number generation circuit according to claim 1, wherein said imbalance generator is provided for each cell. 7. The chip-specific random number generation circuit according to claim 1, wherein one imbalance generator is provided for each of a plurality of cells. In a stage prior to actual use, the value of each cell is determined, and in that state, the drain voltage of the load transistor is raised to a higher value than in normal operation for a predetermined period without changing the cell value. 9. The chip-specific random number generation circuit according to any one of items 1 to 8. each of the first inverter and the second inverter is an EE (Enhancement Enhancement) inverter;
10. The chip-specific random number generator circuit according to claim 9, wherein different voltages are applied to the gates of the load transistors of the first inverter and the second inverter during the predetermined period. 11. The chip-specific random number generator circuit according to claim 10, wherein a gate voltage of said load transistor is lower than a drain voltage.

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