JP7130986B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device.

In order to remove a native oxide film on the surface of a gallium nitride (hereafter, GaN) layer, it is known to form a _SiO2 layer after exposing the GaN layer to ammonia gas in a non-plasma state (see, for example, Patent Documents 1). Further, in order to reduce damage to the surface of the sample to be processed, a gate insulating film having a two-layer structure of an Al ₂ O ₃ film and a SiO ₂ film can be formed by microwave plasma CVD (Chemical Vapor Deposition). known (for example, Patent Document 2).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP-A-2006-114802 [Patent Document 2] JP-A-2012-156245

In a semiconductor device having a MOS structure, it is desirable to reduce the thickness of a transition layer formed between an insulating layer such as a _SiO2 layer and a GaN layer, the transition layer comprising predominantly gallium oxide.

A first aspect of the present invention provides a method of manufacturing a semiconductor device having a gallium nitride based semiconductor layer. A method of manufacturing a semiconductor device includes the steps of introducing at least a metal-containing gas into a reaction chamber for a predetermined time to supply at least the metal-containing gas onto a gallium nitride-based semiconductor layer, and forming an insulating layer. Be prepared. Forming the insulating layer may be at least after introducing the metal-containing gas into the reaction chamber. In the step of forming the insulating layer, the insulating layer may be formed by generating oxygen radicals from the oxygen-containing gas in the reaction chamber and reacting the oxygen radicals with the metal-containing gas on the gallium nitride based semiconductor layer. .

At least in the step of introducing the metal-containing gas into the reaction chamber, the metal-containing gas, but not the oxygen-containing gas, may be supplied at predetermined times. Then, in the step of forming the insulating layer, an oxygen-containing gas may be supplied.

Alternatively, the step of introducing at least the metal-containing gas into the reaction chamber may include supplying the oxygen-containing gas before the predetermined time has elapsed.

The semiconductor device may have a gallium oxide layer between the gallium nitride based semiconductor layer and the insulating layer. The thickness of the gallium oxide layer may be 1 nm or less.

At least in the step of introducing the metal-containing gas into the reaction chamber, the metal-containing gas may be introduced into the reaction chamber at a supply rate of 1.5 Pa·min or more.

The predetermined time may be 20 seconds or more.

In the step of forming the insulating layer, the temperature of the gallium nitride based semiconductor layer may be 300° C. or less.

The insulating layer may contain either silicon oxide or aluminum oxide.

When the insulating layer is silicon oxide, the metal-containing gas may include any of monosilane, disilane and tetraethylorthosilicate (TEOS). Also, when the insulating layer is aluminum oxide, the metal-containing gas may include either trimethylaluminum (TMA) or triethylaluminum (TEA).

The oxygen-containing gas may include any one of oxygen gas, ozone gas and water vapor. Also. The oxygen-containing gas may include either oxygen gas or water vapor, provided that the oxygen-containing gas is supplied before the predetermined time elapses at least in the step of introducing the metal-containing gas into the reaction chamber.

The thickness of the insulating layer may be 1 nm or more.

A second aspect of the present invention provides a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device may further include forming an electrode layer on the insulating layer after forming the insulating layer. The insulating layer may be a gate insulating layer used in MOS structures. The MOS structure may have a gallium nitride-based semiconductor layer, an insulating layer, and an electrode layer.

It should be noted that the above summary of the invention does not list all the necessary features of the invention. Subcombinations of these feature groups can also be inventions.

1 is a cross-sectional view of a lateral MOSFET 100 according to a first embodiment; FIG. 4 is a flow chart showing a method for manufacturing the lateral MOSFET 100. FIG. 3A to 3C are diagrams showing each step of a method for manufacturing the lateral MOSFET 100; FIG. 1 is a diagram showing an outline of a plasma CVD apparatus 200; FIG. FIG. 4 is a diagram illustrating an oxygen gas introduction period and a TEOS gas introduction period; Sample no. 1 shows the XPS analysis results of No. 1. FIG. Sample no. 2 is a diagram showing the XPS analysis results of No. 2. FIG. Sample no. 3 shows the XPS analysis results of No. 3. FIG. Sample no. 6 is a diagram showing the XPS analysis results of No. 6. FIG. Sample no. 7 shows the XPS analysis results of No. 7. FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

FIG. 1 is a cross-sectional view of a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 according to the first embodiment. FIG. 1 is a cross section of a portion of the lateral MOSFET 100 taken along the XZ plane. In this example, the X-axis and the Y-axis are directions perpendicular to each other, and the Z-axis direction is the direction perpendicular to the XY plane. The X, Y and Z axes form a so-called right-handed system. A top surface 52 and a bottom surface 54 of the GaN-based semiconductor 50 may be parallel to the XY plane.

In this example, the positive direction of the Z-axis may be called "up", and the negative direction of the Z-axis may be called "down". However, "above" and "below" do not necessarily mean vertical to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely convenient expressions specifying relative positions in substrates, layers, regions, films, and the like.

The lateral MOSFET 100 may be formed using a chip of the GaN-based semiconductor 50 with a size of 10 mm×10 mm in the XY plane. Lateral MOSFET 100 is an example of a GaN-based semiconductor device. The cross-section shown in FIG. 1 may be a unit structure of lateral MOSFET 100 . The unit structure may extend in the Y-axis direction and be repeatedly provided in the X-axis direction. The plurality of unit features may be arranged to form a substantially rectangular shape in XY plan view. A region provided with a plurality of unit structures may be referred to as an active region. An edge termination structure may be provided around the active region that serves to prevent electric field crowding in the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure and a JTE (Junction Termination Extension) structure.

In this example, each of the substrate and layers forming the GaN-based semiconductor 50 is a GaN semiconductor. However, each of these substrates and layers may further contain one or more elements of the aluminum (Al) element and the indium (In) element. In other words, each of the substrate and layers constituting the GaN-based semiconductor 50 is a mixed crystal semiconductor containing a trace amount of Al element and In element, that is, Al _x In _y Ga _1-xy N (0≦x<1, 0 ≤ y < 1). However, in this example, each of the substrate and the layers constituting the GaN-based semiconductor 50 is a GaN semiconductor where x=y=0 in Al _x In _y Ga _1-x-y N.

A GaN-based semiconductor 50 of this example has an n ⁺ -type GaN substrate 10 , an n-type GaN layer 20 , and a p-type GaN layer 30 . The GaN substrate 10 may be a so-called c-plane GaN substrate. The c-axis direction of the GaN substrate 10 may be parallel to the Z-axis direction. Also, the GaN substrate 10 may be a low-dislocation free-standing substrate having a threading dislocation density of less than 1E+7 cm ⁻² . Note that E means a power of 10, for example, 1E+ ⁷ means 107. The GaN substrate 10 of this example is an n ⁺ -type substrate having a length (that is, thickness) in the Z-axis direction of 350 μm. In this example, the bottom surface of the GaN substrate 10 is called the bottom surface 54 of the GaN-based semiconductor 50 .

The n-type GaN layer 20 may be an epitaxial layer provided on the GaN substrate 10 in contact with the GaN substrate 10 . The GaN layer 20 of this example has a thickness of 1 μm and contains 2E+16 cm ⁻³ Si element as an n-type impurity.

The p-type GaN layer 30 may be an epitaxial layer provided on the GaN layer 20 in contact with the GaN layer 20 . The GaN layer 30 in this example has a thickness of 4 μm and contains 1E+17 cm ⁻³ of Mg as a p-type impurity. Note that the GaN layer 30 is an example of a GaN-based semiconductor layer. In this example, the top surface of the GaN layer 30 is referred to as the top surface 52 of the GaN-based semiconductor 50 .

In this example, n or p means that electrons or holes are the majority carriers, respectively. Regarding + or - written on the right side of n or p, + means that the carrier concentration is higher than that without it, and - means that the carrier concentration is lower than that without it. In this example, the GaN layer 20 is n-type and the GaN layer 30 is p-type. However, in other embodiments, GaN layer 20 may be p-type and GaN layer 30 may be n-type.

The n-type impurities for the GaN semiconductor may be one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In this example, Si element is used as the n-type impurity. Also, the p-type impurity for the GaN semiconductor may be one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium) and Zn (zinc). In this example, Mg element is used as the p-type impurity.

The GaN layer 30 has a pair of n ⁺ -type GaN regions 32 spaced apart from each other in the X-axis direction. In this example, the upper portion of n ⁺ -type GaN region 32 is exposed at top surface 52 . The n ⁺ -type GaN region 32 may be provided from the upper surface 52 to a predetermined depth position shallower than the bottom of the GaN layer 30 . The n ⁺ -type GaN region 32 may be provided from the upper surface 52 to a depth of 0.1 μm.

The lateral MOSFET 100 of this example further includes a gate electrode layer 40 , a gallium oxide layer 42 , a gate insulating layer 44 , a source electrode layer 46 and a drain electrode layer 48 . The gate electrode layer 40, the gate insulating layer 44 and the GaN layer 30 may form a MOS (Metal Oxide Semiconductor) structure.

The MOS structure may have a gallium oxide layer 42 between the gate insulating layer 44 and the GaN layer 30 . Gallium oxide layer 42 is also a transition layer located at the interface between gate insulating layer 44 and GaN layer 30 . The gallium oxide layer 42 is formed, for example, by oxidizing the upper surface 52 of the GaN layer 30 . The composition formula of the gallium oxide layer 42 may be _GaOx . GaO _X includes GaO in which the ratio of the number of Ga atoms and the number of O elements is 1:1, GaO ₂ in which the ratio is 1:2, and Ga ₂ O ₃ in which the ratio is 2:3. and at least one of In addition to Ga and O, the gallium oxide layer 42 may contain other elements (one or more of elements such as Si, Al, N, C and H).

Gallium oxide layer 42 may have a thickness of 1 nm (ie, 10 Å) or less. Also, the thickness of the gallium oxide layer 42 may be equal to or greater than the thickness of one atomic layer of GaN. Since the c-axis in the GaN layer 30 (hexagonal crystal) of this example is parallel to the Z-axis, the thickness of one atomic layer is about 2.5 Å. Thus, the thickness of gallium oxide layer 42 may be about 5 Å or greater, 6 Å or greater, 7 Å or greater, 8 Å or greater, or 9 Å or greater.

Gallium oxide layer 42 (transition layer) is believed to be formed by partially eroding gate insulating layer 44 and p-type GaN layer 30, respectively. It is thought that as the thickness of the gallium oxide layer 42 increases, the upper portion of the GaN layer 30 (that is, the region near the upper surface 52 of the GaN layer 30 ) loses its p-type characteristics and does not respond to the electric field from the gate electrode layer 40 . be done. Therefore, it is desirable that the thickness of the gallium oxide layer 42 is small. If the thickness of the gallium oxide layer 42 is 1 nm or less, the field effect mobility in the lateral MOSFET 100 can be 100 cm ² /V·s or higher.

Parameters affecting the field-effect mobility include (1) roughness scattering caused by physical irregularities on the upper surface 52 of the GaN layer 30, (2) phonon scattering caused by lattice vibration of the crystal lattice in the GaN layer 30, ( 3) Coulomb scattering due to ionized impurities in the GaN layer 30 and fixed charges in the gate insulating layer 44, and (4) interfacial charges due to charges trapped at the interface between the GaN layer 30 and the gate insulating layer 44. Scattering is possible. In the present application, although it is not necessarily clear which of the above (1) to (4) is dominant, the non-responsive region in the GaN layer 30 is reduced by reducing the thickness of the gallium oxide layer 42. By doing so, the field effect mobility is increased.

The thickness of the gallium oxide layer 42 can be determined, for example, from XPS (X-ray Photoelectron Spectroscopy) analysis. See equations (1) and (2) below for details. The thickness of the gallium oxide layer 42 can be measured by TEM (Transmission Electron Microscope) observation or EDX (Energy dispersive X-ray spectrometry) analysis. The size relationship can be specified accurately.

The gate insulating layer 44 of this example is provided on the GaN layer 30 in contact with the GaN layer 30 . More specifically, the gate insulating layer 44 consists of an upper portion of the channel forming region 34 located between the pair of n ⁺ -type GaN regions 32 and a part of the n ⁺ -type GaN region 32 adjacent to the channel forming region 34. provided at the top. It should be noted that the gate insulating layer 44 is an example of an insulating layer formed by a manufacturing method which will be described later. The thickness of the gate insulating layer 44 may be 1 nm or more and 200 nm or less. Although the thickness of the gate insulating layer 44 in this example is 100 nm, the thickness of the gate insulating layer 44 may be 10 nm. As discussed below, the present specification presents a beneficial method of reducing the thickness of the interface transition layer between the GaN layer 30 and the gate insulating layer 44 when forming the gate insulating layer 44 to 1 nm or greater.

Gate insulating layer 44 may include at least one of a silicon oxide layer and an aluminum oxide layer. The gate insulating layer 44 may be a single layer of silicon oxide (SiO ₂ ) or a single layer of aluminum oxide (Al ₂ O ₃ ). Alternatively, gate insulating layer 44 may include an aluminum oxide layer and a silicon oxide layer at least partially located on the aluminum oxide layer. Note that the silicon oxide layer has a wider bandgap than the aluminum oxide layer and is superior in withstand voltage characteristics, which is advantageous. Also in the manufacturing process, the silicon oxide layer is advantageous in that it is easier to wet-etch than the aluminum oxide layer.

The gate insulating layer 44 may be longer than the length in the X-axis direction between the pair of opposing n ⁺ -type GaN regions 32 . The gate electrode layer 40 may be in contact with the gate insulating layer 44 on the gate insulating layer 44 . The gate electrode layer 40 may be separated from the source electrode layer 46 and the drain electrode layer 48 in the X-axis direction. Each of source electrode layer 46 and drain electrode layer 48 may contact n ⁺ -type GaN region 32 and GaN layer 30 at upper surface 52 . Each of the gate electrode layer 40, the source electrode layer 46 and the drain electrode layer 48 may be an aluminum electrode with a thickness of approximately 200 nm.

A channel is formed between the pair of n ⁺ -type GaN regions 32 by forming a predetermined potential difference between the source electrode layer 46 and the drain electrode layer 48 and supplying a predetermined positive potential to the gate electrode layer 40 . A charge inversion region (ie, channel) may be formed in region 34 . Thereby, an electron current flows from the source electrode layer 46 to the drain electrode layer 48 . Supplying a predetermined positive potential to the gate electrode layer 40 is also referred to as turning on the lateral MOSFET 100 . On the other hand, when the supply of the predetermined positive potential to the gate electrode layer 40 is stopped, the channel disappears. This stops electron current flow, ie, lateral MOSFET 100 is turned off.

FIG. 2 is a flow chart showing a method for manufacturing the lateral MOSFET 100. As shown in FIG. In this example, each step is executed in order from step S100 to step S150 (that is, in ascending order of number).

FIG. 3 is a diagram showing each step of the manufacturing method of the lateral MOSFET 100. FIG. Step S<b>100 is a step of epitaxially forming an n-type GaN layer 20 on the GaN substrate 10 and then epitaxially forming a p-type GaN layer 30 on the GaN layer 20 . The epitaxial layers of the GaN layer 20 and the GaN layer 30 may be formed by MOCVD (metal organic chemical vapor deposition). Each epitaxial layer may be formed by HVPE (Hydride Vapor Phase Epitaxy) method instead of MOCVD method.

In this example, the MOCVD method is adopted. In this example, source gas containing trimethylgallium ((CH ₃ ) ₃ Ga, hereinafter abbreviated as TMG), ammonia (NH ₃ ) and monosilane (SiH ₄ ), nitrogen (N ₂ ) and hydrogen (H ₂ ) ) is flowed onto the GaN substrate 10 . At this time, the temperature of the GaN substrate 10 may be 1100.degree. Note that the Si element in monosilane can function as an n-type impurity in the n-type GaN layer 20 . Thereby, an n-type GaN layer 20 having a thickness of 1 μm and containing 2E+16 cm ⁻³ of Si element may be formed.

After forming the GaN layer 20, the GaN layer 30 is formed. In this example, a raw material gas containing TMG, ammonia and biscyclopentadienylmagnesium (Cp ₂ Mg) and a pressure gas containing nitrogen (N ₂ ) and hydrogen (H ₂ ) are flowed over the GaN substrate 10 . At this time, the temperature of the GaN substrate 10 may be 1050.degree. Note that Mg in Cp ₂ Mg can function as a p-type impurity in the GaN layer 30 . This may form a p-type GaN layer 30 having a thickness of 4 μm and containing 1E+17 cm ⁻³ of Mg.

After forming the GaN layer 20 and the GaN layer 30, the GaN-based semiconductor 50 may be removed from the MOCVD apparatus and transferred to a heat treatment apparatus. In order to activate the p-type impurities in the GaN layer 30, the GaN-based semiconductor 50 may be heat-treated in a heat treatment apparatus. In this example, the GaN-based semiconductor 50 may be heat-treated at 650° C. in a nitrogen (N ₂ ) gas atmosphere containing oxygen. This completes S100.

Step S110 is the step of forming the n ⁺ -type GaN region 32 . In this example, a resist mask having an opening for forming the n ⁺ -type GaN region 32 may be formed using a coating device, an exposure device, and the like. After that, using an ion implanter, Si ions may be implanted into the GaN layer 30 through the resist mask at a dose of 3E+15 [cm ⁻² ] from the upper surface 52 to a depth of about 0.1 μm. After that, the resist mask may be removed and an AlN (aluminum nitride) film, an SiO ₂ film, or the like may be formed as a protective film. The GaN-based semiconductor 50 may be moved to a heat treatment apparatus. Then, in order to activate the implanted Si, the GaN-based semiconductor 50 may be heat-treated at 1000° C. in a nitrogen (N ₂ ) gas atmosphere. Further, after the heat treatment, the upper surface 52 of the GaN layer 30 and the n ⁺ -type GaN region 32 may be etched with dilute hydrofluoric acid or the like in order to remove the oxide layer from the upper surface 52 . The upper surface 52 may then be rinsed with pure water.

Step S120 is the step of introducing the metal-containing gas into the reaction chamber 210 of the plasma CVD apparatus for a predetermined time. However, in step S120, the plasma discharge of the plasma CVD apparatus is not performed. Step S120 is a step of introducing at least a metal-containing gas into the reaction chamber 120 without generating plasma while using a plasma CVD apparatus. A portion of the metal-containing gas introduced into reaction chamber 120 may be adsorbed on top surface 52 of GaN-based semiconductor 50 .

The metal-containing gas may be determined according to the type of gate insulating layer 44 to be formed. The metal of the metal-containing gas may refer to a metal whose oxide energy gap is greater than that of GaN. The metals may be Si and Al.

When the gate insulating layer 44 is a silicon oxide layer, the metal-containing gas is any of monosilane ( _SiH4 ), disilane ( _Si2H6 ) and tetraethyl orthosilicate _{(Si(OC2H5)4 , or TEOS} ). may include Also, when the gate insulating layer 44 is an aluminum oxide layer, the metal-containing gas is trimethylaluminum ((CH ₃ ) ₃ Al, or TMA) and triethylaluminum ((C ₂ H ₅ ) ₃ Al, or TEA). may include either

The metal-containing gas can be supplied onto the GaN layer 30 by introducing the metal-containing gas into the reaction chamber for a predetermined period of time. The predetermined time is preferably 20 seconds or longer, and may be 60 seconds. In this example, the predetermined time is 20 seconds and the metal containing gas is TEOS gas. By supplying the TOES gas onto the GaN layer 30 , TEOS molecules can be adsorbed on the upper surface 52 of the GaN layer 30 . About one to three molecular layers of TEOS molecules may be adsorbed on the upper surface 52 .

A lower predetermined time limit may be the time required for one molecular layer of metal-containing gas to adsorb to upper surface 52 . In a subsequent step, the metal-containing gas can be oxidized by an oxygen plasma (also called active oxygen or radical oxygen) at locations contacting the top surface 52 to form a silicon oxide layer or an aluminum oxide layer. Therefore, a silicon oxide layer or aluminum oxide layer is formed by reacting the oxygen radicals with the metal-containing gas at a location remote from the top surface 52 , and then the silicon oxide layer or aluminum oxide layer is deposited on the top surface 52 . The reaction between oxygen radicals and the upper surface 52 of the GaN layer 30 can be reduced compared to the case. Therefore, by performing step S120, the thickness of the gallium oxide layer 42 (transition layer) can be reduced.

If the number of layers of the metal-containing gas increases with time but saturates at a certain time, the upper limit of the predetermined time is the maximum number of molecular layers of the metal-containing gas that can be stacked (e.g., 3 molecules layer) adheres to the upper surface 52 . It should be noted that the production efficiency decreases if the metal-containing gas is introduced into the reaction chamber 210 for several minutes to several tens of minutes, so the upper limit of the predetermined time may be determined in consideration of the production efficiency. Since TEOS molecules repel each other, it is generally difficult to form a TEOS molecular layer exceeding three molecular layers.

At step S 120 , the metal-bearing gas with a flow rate of 0.5 sccm (standard cubic centimeters per minute) or more may be introduced into the reaction chamber 210 , and 2.0 sccm of the metal-bearing gas may be introduced into the reaction chamber 210 . The flow rate of the metal-containing gas may be the flow rate when the internal pressure of the reaction chamber 210 is approximately 270 Pa (the same applies to samples prepared for XPS analysis, which will be described later). Even with a relatively low 0.5 sccm, the effect of reducing the thickness of the gallium oxide layer 42 can be obtained. Also, the relatively high 2.0 sccm is effective because the thickness of the gallium oxide layer 42 can be further reduced compared to 0.5 sccm.

The partial pressures corresponding to TOES gas flow rates of 0.5 sccm and 2.0 sccm are 1.5 Pa and 6 Pa, respectively. The time to introduce the TOES gas into reaction chamber 210 may be 60 seconds or 20 seconds. By supplying the TEOS gas onto the GaN layer 30 for a predetermined time in this way, TEOS molecules can be adsorbed onto the GaN layer 30 . For example, when the TOES supply rate is 1.5 Pa·min (=1.5 Pa·1 min) or more, TEOS molecules are adsorbed onto the GaN layer 30 . Considering the manufacturing time, the TOES supply rate may be 1.5 Pa·min or more, more preferably 2 Pa·min (=6 Pa·20 sec) or more, and 6 Pa·min (=6 Pa·1 min).

In step S120, the temperature of the GaN layer 30 is above room temperature and preferably below 300.degree. In this example, the temperature of the GaN layer 30 is set to 300.degree. When the temperature of the GaN layer 30 exceeds 300° C. (for example, 400° C.), it becomes difficult for the metal-containing gas to be adsorbed on the upper surface 52, so the thickness of the gallium oxide layer 42 tends to increase. The temperature of GaN layer 30 is preferably 300° C. or less to allow metal-containing gases to adsorb to upper surface 52 . The temperatures of the GaN layer 30 and the GaN substrate 10 can be regarded as the same temperature. Therefore, controlling the temperature of the GaN layer 30 may be regarded as controlling the temperature of the GaN substrate 10 .

In step S120 of this example (hereinafter sometimes referred to as the first example), the metal-containing gas is supplied for a predetermined time, but the oxygen-containing gas is not supplied. On the other hand, in step S120 according to the second example, which is a modification of the first example, even if introduction of the oxygen-containing gas into the reaction chamber 210 is started before the predetermined time elapses, good. By introducing the oxygen-containing gas before the predetermined time elapses, there is an advantage that stable ionized oxygen plasma (oxygen radicals) can be easily formed in step S130, which will be described later. The oxygen-containing gas may include any one of oxygen ( _O2 ) gas, ozone ₍ O3) gas and water vapor ( _H2O ). However, when the oxygen-containing gas is ozone (O ₃ ) gas, since the oxygen-containing gas is already active (radical), it is not introduced before the predetermined time has elapsed.

When the oxygen-containing gas is introduced into the reaction chamber 210 in step S120 according to the second example, molecules of the oxygen-containing gas may adsorb between the molecular layer of the metal-containing gas and the upper surface 52 . However, in this case, the oxygen-containing gas is an oxygen-containing gas (for example, oxygen gas and water vapor) other than ozone (O ₃ ) gas. The oxygen-containing gas that is not in a radical state does not oxidize the top surface 52 of the GaN layer 30 . Also, therefore, introducing an oxygen-containing gas into the reaction chamber 210 does not increase the thickness of the gallium oxide layer 42 . The adsorbed oxygen-containing gas may desorb from upper surface 52 in a subsequent step S130.

Step S130 is forming the gate insulating layer 44 by reacting the oxygen radicals with the metal-containing gas. In step S130, the gate insulating layer 44 can be formed mainly by reacting the metal-containing gas adsorbed on the upper surface 52 and the activated oxygen-containing gas.

Step S130 may be performed after a predetermined period of time in step S120. In step S<b>130 of this example, the oxygen-containing gas is supplied to the reaction chamber 210 and oxygen radicals are generated from the oxygen-containing gas within the reaction chamber 210 . Then, the gate insulating layer 44 is formed on the GaN layer 30 by reacting the oxygen radicals with the metal-containing gas. In this example, the oxygen radicals react with the metal-containing gas adsorbed on the upper surface 52, so that the oxidation of the upper surface 52 (that is, the surface of the GaN layer 30) by the oxygen radicals can be suppressed. Therefore, gallium oxide layer 42 can be made thinner than if a reaction-formed silicon oxide layer or aluminum oxide layer were deposited on top surface 52 .

In step S130 according to the third example, which is a modification of the first and second examples, introduction of the metal-containing gas and the oxygen-containing gas into the reaction chamber 210 is started when oxygen radicals are generated. may Also in the third example, the thickness of the gallium oxide layer 42 is reduced compared to the case where the metal-containing gas and oxygen radicals derived from the oxygen-containing gas are reacted after exposing the upper surface 52 of the GaN layer 30 to oxygen radicals. You can get a certain effect to let you.

Step S140 is a step of partially removing the gallium oxide layer 42 and the gate insulating layer 44. FIG. In S<b>140 , the gallium oxide layer 42 and the gate insulating layer 44 are partially removed by etching using a resist mask having openings in regions corresponding to the source electrode layer 46 and the drain electrode layer 48 .

Step S150 is the step of forming the gate electrode layer 40, the source electrode layer 46 and the drain electrode layer 48. FIG. In this example, an Al electrode layer with a thickness of 200 nm is deposited. Next, the gate electrode layer 40 is formed on the gate insulating layer 44 by etching as appropriate. After that, an interlayer insulating film (not shown) may be formed so as to cover the gate electrode layer 40 . Further, openings corresponding to the source electrode layer 46 and the drain electrode layer 48 may be formed in the interlayer insulating film. As the source electrode layer 46, a titanium (Ti) layer and an Al layer may be stacked in this order from the bottom. The drain electrode layer 48 may also have a laminated structure of a Ti layer and an Al layer.

FIG. 4 is a diagram showing an outline of the plasma CVD apparatus 200. As shown in FIG. The plasma CVD apparatus 200 has a reaction chamber 210 , a temperature controller 230 , an exhaust pump 240 , a microwave generator 250 , a waveguide 252 and a plasma generation chamber 254 . In the plasma CVD apparatus 200, an oxide film can be formed by plasmatizing an oxygen-containing gas to generate oxygen radicals and reacting them with the raw material gas. Note that when ozone gas is used as the oxygen-containing gas, the ozone gas may be directly introduced into the reaction chamber 210 from the introduction port 256 without using the microwave generator 250 .

The reaction chamber 210 of this example has a pedestal 212 made of Al inside. The GaN-based semiconductor 50 may be fixed on the pedestal 212 using electrostatic adsorption. A heater 220 may be provided inside the pedestal 212 . The temperature controller 230 may control the temperature of the heater 220 from 100 degrees Celsius to 450 degrees Celsius. In this example, in steps S120 and S130, the temperature of heater 220 is adjusted so that GaN-based semiconductor 50 reaches 300.degree. The exhaust pump 240 may suck the gas inside the reaction chamber 210 through the exhaust port 214 . The exhaust pump 240 may control the pressure inside the reaction chamber 210 from 200Pa to 300Pa.

Microwave generator 250 may be connected to plasma generation chamber 254 via waveguide 252 . The microwave generator 250 converts O ₂ (oxygen) introduced into the plasma generation chamber 254 from the introduction port 256 into plasma to generate oxygen radicals. As shown in FIG. 4, the oxygen radicals may travel inside the reaction chamber 210 .

A metal-bearing gas may be introduced into reaction chamber 210 through inlet 216 . Accordingly, the metal-containing gas and oxygen radicals can be reacted as described in step S130 above. In this example, the metal-containing gas is TEOS gas, so the insulating layer formed is a silicon oxide layer. However, when an Al-containing gas such as TMA is used as the metal-containing gas, an aluminum oxide layer can be formed as the insulating layer.

The plasma CVD apparatus 200 of this example is a remote plasma type film forming apparatus that generates oxygen plasma by microwave discharge. However, the plasma CVD apparatus 200 may use any one of parallel plate discharge, high frequency discharge, DC discharge and surface wave discharge instead of the microwave discharge. Microwave discharge has good gas decomposition efficiency, but parallel plate discharge and high frequency discharge are particularly advantageous when the object to be processed has a large area. In the remote plasma method, since the place where the plasma is generated and the place where the film is formed are separated, damage to the upper surface 52 of the GaN layer 30 by the oxygen plasma can be reduced. The surface wave discharge method can also reduce damage because the discharge is localized on the electrode surface.

FIG. 5 is a diagram for explaining the oxygen gas introduction period and the TEOS gas introduction period. The horizontal axis indicates time, and the vertical axis indicates the type of gas. Time T1 is the time to start introducing the metal-containing gas into reaction chamber 210 . Time T2 is the time to generate oxygen plasma from the oxygen-containing gas and introduce the oxygen plasma into the reaction chamber 210 . Time T3 is the time to finish forming the gate insulating layer 44 .

Note that in the normal film formation example of the silicon oxide layer (normal film formation example), the film is formed after the plasma is stabilized, so the metal-containing gas is introduced after the oxygen plasma is generated. Therefore, time T1 is later than time T2. On the other hand, in this example (first example), the time T1 is earlier than the time T2.

In a first example, the introduction of metal-containing gas into reaction chamber 210 continues from time T1 to time T2. That is, the period from time T1 to time T2 is a pretreatment period during which the metal-containing gas is supplied to the upper surface 52 of the GaN-based semiconductor 50 . Then, the metal-containing gas continues to be introduced into the reaction chamber 210 even after the time T2 without purging with an inert gas or the like. Also, at time T2, the oxygen-containing gas is introduced into the reaction chamber 210 at the same time as the discharge is started. Therefore, this example differs from atomic layer deposition (ALD) in which the precursor gas in the reaction chamber is exhausted after the precursor gas is adsorbed on the surface of the layer to be processed. In this example, time T1 to time T2 are the predetermined times for introducing the metal-containing gas into the reaction chamber 210 . Also, the period from time T2 to time T3 is the time period for forming the gate insulating layer 44 .

By the way, in the second example described above, the introduction of the oxygen-containing gas other than the ozone gas into the reaction chamber 210 is started before the predetermined time elapses. In the second example, at time Tx after time T1 and before time T2, introduction of the oxygen-containing gas into reaction chamber 210 begins (indicated by the dashed line in FIG. 5). Advantageously, this stabilizes the plasma discharge at time T2. However, even if the oxygen-containing gas is introduced at time Tx, the generation of oxygen plasma starts at time T2, so the time for forming the gate insulating layer 44 is from time T2 to time T3.

Also, in the third example described above, the introduction of the metal-containing gas and the introduction of the oxygen radicals are performed at the same timing. That is, the time T1 and the time T2 are the same. A certain effect of reducing the thickness of the gallium oxide layer 42 can also be obtained in the third example, although it is inferior to the first and second examples.

In this example, the example of the planar gate type lateral MOSFET 100 has been described. However, it is of course possible to apply the formation of the gate insulating layer 44 via steps S120 and S130 to planar-gate vertical MOSFETs and trench-gate vertical MOSFETs.

6A to 6E are diagrams showing experimental results of XPS (X-ray Photoelectron Spectroscopy) analysis of a plurality of samples. A plurality of samples (sample Nos. 3 to 10) had a GaN layer 30, a gallium oxide layer 42, and a silicon oxide layer corresponding to the gate insulating layer 44. FIG. However, sample no. 1 and sample no. 2 has a GaN layer 30 and a gallium oxide layer 42, but no silicon oxide layer. Sample no. 1 is a sample without intentional treatment after the GaN layer 30 is epitaxially grown. Sample no. No. 2 is a sample corresponding to the state before deposition of the silicon oxide layer (that is, the sample subjected to the oxygen plasma treatment before deposition) according to the above-described normal deposition example. Sample no. 3 is a sample corresponding to the film formation of the silicon oxide layer according to the normal film formation example described above. Sample no. 4, sample no. 6 and sample no. 9 is a sample corresponding to the third example described above. Sample no. 5, sample no. 7, sample no. 8 and sample no. 10 is a sample corresponding to the second example described above. Sample no. Each condition for 1 to 10 is shown in Table 1. In addition, sample no. 3 to 10, the TEOS flow rate was the same between the pretreatment stage and the silicon oxide layer formation stage.

The thickness of the silicon oxide layer was set to 1 nm to enable XPS analysis. However, sample no. 1 and no. No. 2 did not provide a silicon oxide layer (thickness of silicon oxide layer=0 nm). In this experiment, the interface region between the GaN layer 30 and the gate insulating layer 44 was irradiated with X-rays. AlKα rays were used as X-rays. Also, the angle formed by the direction in which the detector takes in photoelectrons and the horizontal plane of the sample having the laminated structure was set to 45 degrees.

The GaN layer 30 mainly has Ga—N bonds. In contrast, the gallium oxide layer 42 mainly has Ga--O bonds. The photoelectrons emitted by the 2p orbital of Ga atoms undergo chemical shifts of different energies in Ga—N bonds and Ga—O bonds. In FIGS. 6A to 6E, spectra were measured, which are the relationships of the intensity (vertical axis) corresponding to the binding energy (horizontal axis) of the 2p orbital of Ga atoms. 6A to 6E, the horizontal axis is binding energy [eV] and the vertical axis is intensity (c/s, ie, counts per second). In this specification, the 2p orbital of Ga atoms may be referred to as Ga2p.

The measured values in this experiment were obtained by XPS analysis of the interface region including the gallium oxide layer 42 and the GaN layer 30 . The measured values include Ga--N bond components and Ga--O bond components. The energy corresponding to the intensity peak of the pure Ga—N bond can be obtained in advance by, for example, XPS analysis of the GaN layer 30 without the gate insulating layer 44 . Also, the energy corresponding to the intensity peak of the pure Ga—O bond can be obtained in advance by XPS analysis of the oxidized surface of the GaN layer 30 . In this experiment, the energy corresponding to the intensity peak of Ga—N bonds was 1117.4 eV, and the energy corresponding to the intensity peak of Ga—O bonds was 1118.2 eV.

In this experiment, the waveforms of the measured Ga2p values were decomposed using previously obtained waveforms of intensity peaks corresponding to Ga—N bond and Ga—O bond energies, respectively. As a result of resolving the waveform, if the peak value of the Ga—N bond waveform is higher than the peak value of the Ga—O bond waveform, then at least one of the thickness, amount, and volume of the gallium oxide layer 42 in the interface region is It means relatively less. On the other hand, when the peak value of the waveform of Ga—O bonds is higher than the peak value of the waveform of Ga—N bonds as a result of analyzing the waveform, it means that the gallium oxide layer 42 is relatively abundant in the interface region. means.

The thickness d of the gallium oxide layer 42 was calculated using the following formula (1) from the intensity ratio I _OX /I _GaN between the Ga—O bond component and the Ga—N bond component. In addition, in Formula (1), "x" means a product.
d=λ _OX ×cos θ
x ln [(λ _GaN N _GaN )/(λ _{OX NOX} ) x ( _IOX /I _GaN )+1] (1)
where θ is the photoelectron extraction angle, N _GaN and N _OX are the Ga atomic densities in the GaN layer and Ga oxide layer, respectively. λ _GaN and λ _OX are escape depths of Ga2p electrons in the GaN layer and Ga oxide layer, respectively, and were calculated from the semi-empirical formula described in [Non-Patent Document 1]. The electron escape depth λ (nm) for a compound is represented by the following equation (2), where E is the photoelectron energy (eV) and a is the monoatomic layer thickness (nm).
λ(nm)=538aE ⁻² +0.72(a ^3/2 E ^1/2 ) (2)
[Non-Patent Document 1]: Koji Onishi, Yasuhiro Horiike, Kazuhiro Yoshihara, Solid Surface Analysis I, 1st edition, Kodansha, April 20, 1995, p.28.

FIG. 6A shows sample no. 1 shows the XPS analysis results of No. 1. FIG. Sample no. 1 is a sample in which only the GaN layer 30 was formed in step S100 and no insulating layer such as a silicon oxide layer was formed (thickness of silicon oxide layer=0 nm). Moreover, sample no. 1, no metal-containing gas or oxygen-containing gas is flowed over the upper surface 52 after the formation of the GaN layer 30 (“pretreatment”=none). That is, FIG. 6A is the result of XPS analysis of the upper surface 52 of the GaN layer 30 after the epitaxial layer formation step (S100). Sample no. 1, the thickness d of the gallium oxide layer was 0.1 nm. Sample no. The gallium oxide layer in 1 is considered to be a so-called native oxide film.

In FIG. 6A, the curve with the highest intensity peak is the measured spectrum of the 2p orbital of Ga atoms. The "Ga--N component" peak in FIG. 6A is a waveform derived from Ga--N bonds, and the "Ga--O component" peak in FIG. 6A is a waveform derived from Ga--O bonds. The curve with the second highest intensity peak (dashed line) is the combination of the Ga--O bond component and the Ga--N bond component (Ga--O+Ga--N component in FIG. 6A). In FIG. 6A, the peak of the Ga—N bond waveform (Ga—N component in FIG. 6A) was overwhelmingly higher than the peak of the Ga—O bond waveform (Ga—O component in FIG. 6A). That is, sample no. In No. 1, the Ga—O component was much less than the Ga—N component.

FIG. 6B shows sample no. 2 is a diagram showing the XPS analysis results of No. 2. FIG. Sample no. 2, no metal-containing gas or oxygen-containing gas is flowed over the upper surface 52 after the GaN layer 30 is formed, and no silicon oxide layer is formed on the upper surface 52 (thickness of the silicon oxide layer=0 nm). However, sample no. 2, after forming the GaN layer 30 in step S100, the upper surface 52 was irradiated with oxygen radicals (“pretreatment”=oxygen plasma in Table 1). The temperature of the GaN substrate 10 was set to 300° C. when the oxygen radicals were irradiated. This corresponds to the pretreatment stage of the normal deposition example. Sample no. 2, a gallium oxide layer having a thickness d of 1.5 nm was formed.

Also in FIG. 6B, the curve with the highest intensity peak is the measured spectrum obtained by measuring the 2p orbital of Ga atoms. The curve with the second highest intensity peak (dashed line) is the Ga-O+Ga-N component. Also, the curve with the third highest intensity peak is the Ga--O component, and the curve with the fourth highest intensity peak is the Ga--N component. As shown in FIG. 6B, by treating the upper surface 52 with oxygen radicals, sample no. Compared to 1, the gallium oxide layer grew remarkably.

FIG. 6C shows sample no. 3 shows the XPS analysis results of No. 3. FIG. Sample no. 3, the irradiation of oxygen radicals on the upper surface 52 was started after the GaN layer 30 was formed, and then the introduction of the TEOS gas was started later (in Table 1, “pretreatment”=oxygen plasma, “TEOS flow rate”= 0.5 sccm). It should be noted that this situation corresponds to the fact that the time T1 is later than the time T2, when explained with reference to FIG. Thereby, a silicon oxide layer having a thickness of 1 nm was formed on the upper surface 52 . Sample no. 3, the temperature of the GaN substrate 10 was set to 300.degree.

Also in FIG. 6C, the curve with the highest intensity peak is the measured spectrum of the 2p orbital of Ga atoms. The curve with the second highest intensity peak (dashed line) is the Ga-O+Ga-N component. Also, the curve with the third highest intensity peak is the Ga--O component, and the curve with the fourth highest intensity peak is the Ga--N component. Sample No. corresponding to a normal film formation example. The thickness d of the gallium oxide layer in Sample No. 3 is 1 to 10 was the largest. Sample no. 3, the thickness d of the gallium oxide layer was 2.0 nm. In addition, sample no. The peak value of the field effect mobility of 3 was 50 cm ² /V·s.

Sample No. corresponding to the third example described above. In Sample No. 4, only the condition of "pretreatment" was applied. different from 3. Sample no. 4, the thickness d of the gallium oxide layer is the same as that of sample No. 4. 1.1 nm, which is about half of 3. From this, it can be said that not irradiating the upper surface of the GaN layer 30 with oxygen plasma alone is effective in reducing the thickness d of the gallium oxide layer.

Also, sample No. 1 corresponding to the above-described second example. 5 introduced the TEOS gas into the reaction chamber 210 for 1 minute under the condition of "pretreatment" of 0.5 sccm. The point concerned is the sample No. different from 3. Sample no. 4, the thickness d of the gallium oxide layer was 0.8 nm. From this, it can be said that the pretreatment for adsorbing the metal-containing gas on the upper surface 52 of the GaN-based semiconductor 50 is effective in reducing the thickness d of the gallium oxide layer.

FIG. 6D shows sample no. 6 is a diagram showing the XPS analysis results of No. 6. FIG. Sample No. corresponding to the third example described above. 6, after the GaN layer 30 was formed, TEOS gas and oxygen gas were introduced into the reaction chamber 210 and plasma discharge was performed at the same time (in Table 1, “pretreatment”=none, “TEOS flow rate” during plasma discharge= 2.0 sccm). That is, sample no. 6, TEOS gas and oxygen plasma were simultaneously introduced onto top surface 52 . This situation, explained with reference to FIG. 5, corresponds to the fact that time T1 and time T2 are simultaneous. Thereby, a silicon oxide layer having a thickness of 1 nm was formed on the upper surface 52 . Sample no. 6, the temperature of the GaN substrate 10 was set to 300° C., and the flow rate of TEOS was set to 2.0 sccm. Sample no. 6, the thickness d of the gallium oxide layer was 0.9 nm.

Also in FIG. 6D, the curve with the highest intensity peak is the measured spectrum of the 2p orbital of Ga atoms. Also, the curve with the second highest intensity peak (dashed line) is the Ga-O+Ga-N component. However, the curve with the third highest intensity peak is the Ga-N component and the curve with the fourth highest intensity peak is the Ga-O component. Sample no. 6, it can be said that not performing the pretreatment with oxygen plasma is effective in reducing the thickness d of the gallium oxide layer. In addition, sample no. The peak value of the field effect mobility of 6 was 100 cm ² /V·s. Sample no. 3, it can be said that the thickness d of the gallium oxide layer is effective in improving the mobility.

FIG. 6E shows sample no. 7 shows the XPS analysis results of No. 7. FIG. Sample No. corresponding to the second example described above. 7, the TEOS gas was introduced into the reaction chamber 210 for 20 seconds after the GaN layer 30 was formed, and then the oxygen gas was plasma discharged (“pretreatment” = 2.0 sccm, and the TEOS gas was introduced into the reaction chamber 210 for 20 seconds. ). Sample no. 7 corresponds to the formation of the silicon oxide layer from time T2 to time T3 after 20 seconds from time T1 to time T2. That is, sample no. 7 corresponds to the example described in FIGS. Sample no. 7 also formed a silicon oxide layer with a thickness of 1 nm on the upper surface 52 .

Sample no. 7, the temperature of the GaN substrate 10 was set to 300.degree. Sample no. 7, the thickness d of the gallium oxide layer is the same as that of sample No. 7. Smallest on a scale of 1-10. Sample no. 7, the thickness d of the gallium oxide layer was 0.5 nm. Sample no. 10, it can be said that a lower temperature of the GaN substrate 10 is more effective in reducing the thickness d of the gallium oxide layer.

Also in FIG. 6E, the curve with the highest intensity peak is the measured spectrum of the 2p orbital of Ga atoms. Also, the curve with the second highest intensity peak (dashed line) is the Ga-O+Ga-N component. However, the curve with the third highest intensity peak is the Ga-N component and the curve with the fourth highest intensity peak is the Ga-O component. Sample no. 7, the ratio of the peak of the Ga--O component to the peak of the Ga--N component is Higher than 6. This result also clarified the advantage of introducing the TEOS gas before the oxygen plasma irradiation. In addition, sample no. The peak value of the field effect mobility of 7 was 120 cm ² /V·s. Sample no. It was possible to improve the mobility more than 3 and 6.

Sample No. corresponding to the second example described above. In sample No. 8, the TEOS gas was allowed to flow in the "pretreatment". different from 7. Sample no. The thickness d of the gallium oxide layer in sample no. Similar to sample no. It was 0.5 nm, which was the smallest among 1 to 10.

Sample No. corresponding to the third example described above. 9 did not flow TEOS gas in the "pretreatment". Also, the temperature of the GaN substrate 10 was set to 400.degree. The point concerned is the sample No. Different from 7 and 8. Sample no. 4, and sample no. 6 and 9, the thickness d of the gallium oxide layer 42 is smaller when the TEOS flow rate during the formation of the silicon oxide layer is higher.

Sample No. corresponding to the second example described above. 10 flowed TEOS gas at 2.0 sccm in "Pretreatment". The point concerned is the sample No. different from 9. Sample no. The thickness d of the gallium oxide layer 42 of sample No. 10 is 9, the advantage of introducing the TEOS gas before irradiating with the oxygen plasma was made clear. In this experiment, no sample corresponding to the first example was prepared. However, the thickness d of the gallium oxide layer 42 in the sample corresponding to the first example can be equal to or smaller than the thickness d of the gallium oxide layer 42 in the sample corresponding to the second example. It is possible. Therefore, it is reasonably considered that the sample corresponding to the first example can enjoy an advantageous effect equal to or greater than that of the sample corresponding to the second example.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the above embodiments. It is clear from the description of the scope of the claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

The execution order of each process such as actions, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly "before", "before etc., and it should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if the description is made using "first,""next," etc. for convenience, it means that it is essential to carry out in this order. not a thing
[Item 1-1 ]
A method for manufacturing a semiconductor device having a gallium nitride-based semiconductor layer, comprising:
introducing the at least metal-containing gas into a reaction chamber for a predetermined time to supply the at least metal-containing gas onto the gallium nitride based semiconductor layer;
After the step of introducing, oxygen radicals are generated from the oxygen-containing gas in the reaction chamber, and an insulating layer is formed on the gallium nitride based semiconductor layer by reacting the oxygen radicals with the metal-containing gas. stages and
A method of manufacturing a semiconductor device, comprising:
[ Item 1-2]
In the introducing step, the metal-containing gas is supplied for the predetermined time, but the oxygen-containing gas is not supplied;
supplying the oxygen-containing gas in the step of forming the insulating layer;
A method for manufacturing a semiconductor device according to item 1-1 .
[Item 1-3 ]
The method of manufacturing a semiconductor device according to item 1-1, wherein the step of introducing includes supplying the oxygen - containing gas before the predetermined time elapses.
[Item 1-4 ]
The semiconductor device has a gallium oxide layer between the gallium nitride-based semiconductor layer and the insulating layer,
The gallium oxide layer has a thickness of 1 nm or less.
A method of manufacturing a semiconductor device according to any one of Items 1-1 to 1-3 .
[Item 1-5 ]
The method of manufacturing a semiconductor device according to any one of items 1-1 to 1-4, wherein in the introducing step, the metal - containing gas is introduced into the reaction chamber at a supply rate of 1.5 Pa·min or more. .
[Item 1-6 ]
The method of manufacturing a semiconductor device according to any one of items 1-1 to 1-5 , wherein the predetermined time is 20 seconds or longer.
[Item 1-7 ]
The method of manufacturing a semiconductor device according to any one of items 1-1 to 1-6 , wherein in the step of forming the insulating layer, the temperature of the gallium nitride based semiconductor layer is 300° C. or less.
[Item 1-8 ]
The method of manufacturing a semiconductor device according to any one of Items 1-1 to 1-7 , wherein the insulating layer contains either silicon oxide or aluminum oxide.
[Item 1-9 ]
when the insulating layer is silicon oxide, the metal-containing gas includes any one of monosilane, disilane, and tetraethyl orthosilicate (TEOS);
when the insulating layer is aluminum oxide, the metal-containing gas comprises either trimethylaluminum (TMA) or triethylaluminum (TEA);
A method for manufacturing a semiconductor device according to item 1-8 .
[Item 1-10 ]
The oxygen-containing gas includes any one of oxygen gas, ozone gas and water vapor,
When the oxygen-containing gas is supplied before the predetermined time elapses in the introducing step, the oxygen-containing gas includes either oxygen gas or water vapor.
A method for manufacturing a semiconductor device according to any one of Items 1-1 to 1-9 .
[Item 1-11 ]
The method of manufacturing a semiconductor device according to any one of Items 1-1 to 1-10 , wherein the insulating layer has a thickness of 1 nm or more.
[Item 1-12 ]
after forming the insulating layer, further comprising forming an electrode layer on the insulating layer;
The insulating layer is a gate insulating layer used in a MOS structure having the gallium nitride-based semiconductor layer, the insulating layer, and the electrode layer.
A method for manufacturing a semiconductor device according to any one of Items 1-1 to 1-11 .
[Item 2-1]
A method for manufacturing a semiconductor device having a gallium nitride-based semiconductor layer, comprising:
introducing at least the metal-containing gas into a reaction chamber for a predetermined time to adsorb the metal-containing gas onto the upper surface of the gallium nitride-based semiconductor layer;
After the step of introducing, the oxygen-containing gas is turned into plasma in the reaction chamber to generate oxygen radicals, and the oxygen radicals and forming an insulating layer that is an oxide of a metal contained in the metal-containing gas by reacting it with the metal-containing gas;
A method of manufacturing a semiconductor device, comprising:
[Item 2-2]
In the introducing step, the metal-containing gas is supplied for the predetermined time, but the oxygen-containing gas is not supplied;
supplying the oxygen-containing gas in the step of forming the insulating layer;
A method for manufacturing a semiconductor device according to item 2-1.
[Item 2-3]
The method of manufacturing a semiconductor device according to item 2-1, wherein the step of introducing includes supplying the oxygen-containing gas before the predetermined time elapses.
[Item 2-4]
The semiconductor device has a gallium oxide layer between the gallium nitride-based semiconductor layer and the insulating layer,
The gallium oxide layer has a thickness of 1 nm or less.
A method for manufacturing a semiconductor device according to any one of items 2-1 to 2-3.
[Item 2-5]
The semiconductor device according to item 2-4, wherein the gallium oxide layer is formed by reacting oxygen contained in the oxygen-containing gas with the gallium nitride-based semiconductor layer in the step of forming the insulating layer. manufacturing method.
[Item 2-6]
The method of manufacturing a semiconductor device according to any one of items 2-1 to 2-5, wherein in the introducing step, the metal-containing gas is introduced into the reaction chamber at a supply rate of 1.5 Pa·min or more. .
[Item 2-7]
The method of manufacturing a semiconductor device according to any one of items 2-1 to 2-6, wherein the predetermined time is 20 seconds or longer.
[Item 2-8]
The method of manufacturing a semiconductor device according to any one of items 2-1 to 2-7, wherein in the step of forming the insulating layer, the temperature of the gallium nitride based semiconductor layer is 300° C. or less.
[Item 2-9]
The method of manufacturing a semiconductor device according to any one of items 2-1 to 2-8, wherein the insulating layer contains either silicon oxide or aluminum oxide.
[Item 2-10]
when the insulating layer is silicon oxide, the metal-containing gas includes any one of monosilane, disilane, and tetraethyl orthosilicate (TEOS);
when the insulating layer is aluminum oxide, the metal-containing gas comprises either trimethylaluminum (TMA) or triethylaluminum (TEA);
A method for manufacturing a semiconductor device according to item 2-9.
[Item 2-11]
The oxygen-containing gas includes any one of oxygen gas, ozone gas and water vapor,
When the oxygen-containing gas is supplied before the predetermined time elapses in the introducing step, the oxygen-containing gas includes either oxygen gas or water vapor.
A method for manufacturing a semiconductor device according to any one of items 2-1 to 2-10.
[Item 2-12]
The method of manufacturing a semiconductor device according to any one of Items 2-1 to 2-11, wherein the insulating layer has a thickness of 1 nm or more.
[Item 2-13]
After the step of forming the insulating layer, further comprising forming an electrode layer on the insulating layer;
The insulating layer is a gate insulating layer used in a MOS structure having the gallium nitride-based semiconductor layer, the insulating layer, and the electrode layer.
A method for manufacturing a semiconductor device according to any one of items 2-1 to 2-12.

Reference Signs List 10 GaN substrate 20 GaN layer 30 GaN layer 32 n ⁺ -type GaN region 34 channel forming region 40 gate electrode layer 42 gallium oxide layer 44 Gate insulating layer 46 Source electrode layer 48 Drain electrode layer 50 GaN-based semiconductor 52 Upper surface 54 Lower surface 100 Lateral MOSFET 200 Plasma CVD apparatus 210 Reaction chamber 212 Pedestal 214 Exhaust port 216 Inlet 220 Heater 230 Temperature controller 240 Exhaust pump 250 Microwave generator 252 ... waveguide, 254 ... plasma generation chamber, 256 ... inlet

Claims (13)

A method for manufacturing a semiconductor device having a gallium nitride-based semiconductor layer, comprising:
introducing at least the metal-containing gas into a reaction chamber for a predetermined time to adsorb the metal-containing gas onto the upper surface of the gallium nitride based semiconductor layer;
After the step of introducing, the oxygen-containing gas is turned into plasma in the reaction chamber to generate oxygen radicals, and the metal-containing gas is generated on the upper surface of the gallium nitride-based semiconductor layer to which the metal -containing gas is adsorbed. forming an insulating layer that is an oxide of a metal contained in the metal-containing gas by reacting the oxygen radicals with the metal-containing gas while introducing
A method of manufacturing a semiconductor device, comprising: in the introducing step, the metal-containing gas is supplied for the predetermined time but the oxygen-containing gas is not supplied;
2. The method of manufacturing a semiconductor device according to claim 1, wherein said oxygen-containing gas is supplied in said step of forming said insulating layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said step of introducing includes supplying said oxygen-containing gas before said predetermined time elapses. The semiconductor device has a gallium oxide layer between the gallium nitride-based semiconductor layer and the insulating layer,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the gallium oxide layer has a thickness of 1 nm or less. 5. The semiconductor device according to claim 4, wherein said gallium oxide layer is formed by reacting oxygen contained in said oxygen-containing gas with said gallium nitride based semiconductor layer in the step of forming said insulating layer. Production method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein in said introducing step, said metal-containing gas is introduced into said reaction chamber at a supply rate of 1.5 Pa.min or more. 7. The method of manufacturing a semiconductor device according to claim 1, wherein said predetermined time is 20 seconds or longer. 8. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the insulating layer, the temperature of the gallium nitride based semiconductor layer is 300[deg.] C. or less. 9. The method of manufacturing a semiconductor device according to claim 1, wherein said insulating layer contains either silicon oxide or aluminum oxide. when the insulating layer is silicon oxide, the metal-containing gas includes any one of monosilane, disilane, and tetraethyl orthosilicate (TEOS);
10. The method of manufacturing a semiconductor device according to claim 9, wherein when said insulating layer is aluminum oxide, said metal-containing gas contains either trimethylaluminum (TMA) or triethylaluminum (TEA). The oxygen-containing gas includes any one of oxygen gas, ozone gas and water vapor,
11. The oxygen-containing gas according to any one of claims 1 to 10, wherein when the oxygen-containing gas is supplied before the predetermined time elapses in the introducing step, the oxygen-containing gas contains either oxygen gas or water vapor. A method for manufacturing the semiconductor device according to item 1. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer has a thickness of 1 nm or more. forming an electrode layer on the insulating layer after forming the insulating layer;
13. The semiconductor device according to claim 1, wherein said insulating layer is a gate insulating layer used in a MOS structure having said gallium nitride based semiconductor layer, said insulating layer, and said electrode layer. Production method.

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