JP7128026B2 - Reference signal selection circuit - Google Patents

Description

The present invention relates to a reference signal selection circuit in fields such as broadcasting, communication, and measurement.

A sine wave of 10 MHz is often used as a reference signal in the fields of broadcasting, communication and measurement. A desired one signal may be selected from a plurality of reference signals having different signal levels and used as a synchronization signal.

Within equipment in the field of broadcasting and communication, a 10 MHz sinusoidal reference signal is often multiplied to a signal of several GHz to several tens of GHz and generated as a local oscillator signal within the equipment. For example, the noise component when multiplied to several tens of GHz band increases at a ratio of 20 log (several tens of GHz band local oscillator signal/10 MHz reference signal), so high isolation is required against interfering waves.

When selecting a plurality of 10 MHz reference signals, an amplifier is required to match the levels of the signals before inputting them to the selection circuit so that the signals after selection have the same level.
In addition, since the signal is attenuated by a switching element such as a relay in the selection circuit, an amplifier is required at the final stage to correct the passage loss of the selection circuit.
Furthermore, as described above, it is necessary to use relays with high isolation so that non-selected signals do not become interfering waves, and to ensure sufficient isolation between signals.
The following Patent Documents 1 and 2 disclose this type of device.

JP-A-07-280908 JP 2016-005276 A

However, the conventional technology described above has the following problems.
In selective switching of high-frequency signals, isolation and passage loss for signals on the non-selected side pose problems.
When the signal to be selected is a sinusoidal reference signal from a PLL circuit or the like, the signal-to-noise ratio of 50 dBc, which is judged to be of high quality for video and audio signals, is insufficient for the desired signal/interference signal ratio on the non-selected side.
In addition, when the signals are input to the selection circuit, unless the levels of the respective signals are the same, the level will fluctuate depending on the signal to be selected. Therefore, an amplifier is required for the input signal.
Furthermore, if switching circuits are provided in multiple stages in order to improve isolation, signal passage loss increases, so an output amplifier is required at the final output stage of the selected output circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a reference signal selection circuit that provides high isolation, low passing loss, and does not require an amplifier for adjusting the input level. With the goal.

The present invention includes a plurality of sinusoidal reference signals, or one or more sinusoidal reference signals and one or more general purpose logic level square wave reference signals of different signal levels ranging from -4 dBm to +10 dBm. A reference signal selection circuit for selecting a plurality of reference signals of 10 MHz , comprising: a bias circuit provided for each of the sine wave reference signals and converting the sine wave reference signal into a rectangular wave signal ; and the converted rectangular wave. A first conversion circuit including a general-purpose logic circuit that converts a signal into a digital signal defined by general-purpose logic; into a digital signal defined by general-purpose logic, and the converted digital signal output from each of the first conversion circuit, or the first conversion circuit and the A plurality of relays for switching and connecting the converted digital signals output from each of the second conversion circuits to the selected terminal connected to the relay in the next stage and to the non-selected terminal not connected to the next stage are finally connected to 1 a multi-stage selection relay circuit connected in multiple stages so as to select one of the converted digital signals , the last stage relay selecting one of the two selected converted digital signals; and the multi-stage selection relay circuit an EMI filter inserted in series in a power supply path of the bias circuit for each of the bias circuits; and the general-purpose logic circuit for each of the general-purpose logic circuits. and a terminating resistor connected to each of the non-selected terminals of the multi-stage selection relay circuit for suppressing radiation of the non-selected signal to space. in the selection circuit.

In the present invention, the combination of the bias circuit, the general-purpose logic circuit, and the multi-stage selection relay circuit for signal selection provides high isolation, low passage loss, and a reference signal that does not require an amplifier for adjusting the input level. A selection circuit can be provided.

1 is a diagram showing an example of a configuration of a 10 MHz reference signal selection circuit according to Embodiment 1 of the present invention; FIG. 2 is a diagram showing a sinusoidal reference signal input, conversion in a bias circuit, and general logic level waveforms in the 10 MHz reference signal selection circuit of FIG. 1; FIG. 2 is a diagram showing an example of a generated signal waveform in the 10 MHz reference signal selection circuit of FIG. 1; FIG. 2 is a diagram showing an example of a bias circuit in the 10 MHz reference signal selection circuit of FIG. 1; FIG. 2 is a diagram showing an example of power supply pattern connections in the 10 MHz reference signal selection circuit of FIG. 1; FIG. FIG. 4 is a diagram for explaining mutual interference paths of two signals in a general-purpose logic IC; 2 is a diagram showing an example of the configuration of a general-purpose logic circuit in the 10 MHz reference signal selection circuit of FIG. 1; FIG. FIG. 4 is a diagram for explaining a non-selected side interference path in a general selective relay circuit; 2 is a diagram showing an example of the configuration of a multistage selection relay circuit in the 10 MHz reference signal selection circuit of FIG. 1; FIG. 2 is a diagram showing an example of a configuration when the number of stages of multi-stage selection relay circuits in the 10 MHz reference signal selection circuit of FIG. 1 is increased; FIG. It is a diagram showing another example of the configuration of the 10 MHz reference signal selection circuit according to Embodiment 1 of the present invention.

In the present invention, a sinusoidal input 10 MHz reference signal is converted to a general purpose logic level square wave. The inherent logic-generated mutual interference that occurs between selected signals or sine waves when converted to a square wave of general-purpose logic levels determines the path of interference, how the power and signal grounds are taken in the circuit, and This problem is solved by cutting the interference path with an EMI filter and by making the selection relay circuit multi-stage. This allows selection of signals at general logic levels. In the final stage, the signal is reconverted to a 10 MHz sine wave signal by a low-pass filter, so that a 10 MHz signal output of a predetermined level can be selectively supplied without an input/output level adjusting amplifier.

Reference signal selection circuits according to embodiments of the present invention will be described below with reference to the drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and redundant explanations are omitted. A selection circuit for a 10 MHz reference signal will be described below, but the reference signal is not limited to 10 MHz.

Embodiment 1.
FIG. 1 is a diagram showing an example of the configuration of a 10 MHz reference signal selection circuit according to Embodiment 1 of the present invention. A first sine wave reference signal RS1 is input to the first bias circuit 1 . A second sine wave reference signal RS2 is input to the second bias circuit 7 . The first sinusoidal reference signal RS1 and the second sinusoidal reference signal RS2 are each 10 MHz sinusoidal reference signals with different signal levels ranging from -4 dBm to +10 dBm.

The output side of the first bias circuit 1 is connected to a first general-purpose logic IC 4 consisting of a logic circuit. Hereinafter, the logic circuit is also called logic IC. A first EMI (Electro Magnetic Interference) filter 2 is inserted between the first bias circuit 1 and the bias circuit power supply VB. A second EMI filter 3 is inserted between the first general-purpose logic IC 4 and the general-purpose logic IC power supply VGL.

A second general-purpose logic IC 10 is connected to the output side of the second bias circuit 7 . A third EMI filter 8 is inserted between the second bias circuit 7 and the bias circuit power supply VB. A fourth EMI filter 9 is inserted between the second general-purpose logic IC 10 and the general-purpose logic IC power supply VGL.

The output side of the first general purpose logic IC 4 is connected to the first selection relay 5 . The first selection relay 5 switches and connects the output from the first general-purpose logic IC 4 to the selection terminal a and the non-selection terminal b. The selection terminal a is connected to the first input terminal T1 of the third selection relay 133 . The non-selected terminal b is connected to the signal ground SGND via the first terminating resistor 6 .

The output side of the second general purpose logic IC 10 is connected to the second selection relay 11 . The second selection relay 11 switches and connects the output from the second general-purpose logic IC 10 to the selection terminal a and the non-selection terminal b. The selection terminal a is connected to the second input terminal T2 of the third selection relay 133 . The non-selected terminal b is connected to the signal ground SGND via the second termination resistor 12 .

The third selection relay 133 switches between the signals from the first input terminal T1 and the second input terminal T2 and outputs them to the third general-purpose logic IC 14 . A fifth EMI filter 13 is inserted between the third general-purpose logic IC 14 and the general-purpose logic IC power supply VGL. The first to third selection relays 5, 11, 133 constitute a multistage selection relay circuit. The switching of the selection relays 5, 11, 133 is performed by a relay control circuit RC which is powered by a relay power source VR and performs switching control according to a switching signal from the outside.

The output of the third general-purpose logic IC 14 passes through the level adjustment resistor circuit 15 including series and parallel resistors and the low-pass filter 16 in order, and is output from the low-pass filter 16 as a sinusoidal reference output signal RSO of 10 MHz and 0 dBm, for example. . Terminals of the level adjustment resistor circuit 15 and the low-pass filter 16 are connected to the signal ground SGND.

FIG. 2 shows a first sinusoidal reference signal RS1 of 10 MHz with a signal level ranging from −4 dBm to +10 dBm in the reference signal selection circuit of FIG. (1) OUT, a conversion waveform (4) OUT to a digital signal defined by the general-purpose logic in the first general-purpose logic IC 4 is shown. In FIG. 2, GLH indicates the H level of the general-purpose logic IC, GLHTH indicates the H-level determination threshold of the general-purpose logic IC, and GLL indicates the L level of the general-purpose logic IC.

FIG. 3 shows an example of generated signal waveforms in the reference signal selection circuit of FIG. RS1 is the first sine wave reference signal RS1, (1) OUT is the output of the first bias circuit 1, (4) OUT is the output of the first general purpose logic IC 4, RS2 is the second sine wave reference signal RS2, (7) OUT is the output of the second bias circuit 7; (10) OUT is the output of the second general-purpose logic IC 10;

As shown in FIG. 1, the first sinusoidal reference signal RS1 is input to the first bias circuit 1 and the second sinusoidal reference signal RS2 is input to the second bias circuit 7, respectively. That is, AC signals are input to the first bias circuit 1 and the second bias circuit 7 . As shown in FIGS. 2 and 3, for example, in the first bias circuit 1, a sine wave of -4 dBm to +10 dBm is given a DC component that makes the H level determination threshold GLHTH level of the general-purpose logic IC have a pulse duty ratio of 50%. converted to a square wave signal.

FIG. 4 shows an example of a bias circuit composed of transistors in the 10 MHz reference signal selection circuit of FIG. In FIG. 4, VB is a bias circuit power supply, 2 is an EMI filter, 17 is a capacitor, 18 is a resistor, and 19 is a transistor. When a signal of -4 dBm is input to the bias circuit, the amplitude is 0.2 Vp-p (peak-to-peak voltage) in the case of a 50Ω line, and the bias circuit composed of transistors amplifies the amplitude to the bias power supply. Perform square wave conversion. Also, when a +10 dBm signal is input to the bias circuit, the amplitude does not increase by more than the bias voltage, so the same square wave as when a -4 dBm signal is input can be obtained.

Furthermore, the first general-purpose logic IC 4 in FIG. 1 converts the rectangular wave output from the first bias circuit 1 into a digital signal defined by general-purpose logic.

Similarly, on the side of the second sine wave reference signal RS2 in FIG. 1, the second bias circuit 7 converts the sine wave into a rectangular wave signal, and the second general purpose logic IC 10 further converts the rectangular wave into a digital signal which is defined by general purpose logic. converted into a signal and become a general purpose logic level signal. The input sine waves can be handled as the same level by the general-purpose logic ICs 4 and 10 regardless of the input level.

Also, since the general-purpose logic IC has a voltage level of around +5V, the H level signal is ideally +5V. Also, if the output of the general-purpose logic IC is terminated with a resistor of 500Ω, a current of 10 mA flows through the resistor, and a peak power of +17 dBm can be obtained. For example, an input signal input at -4 dBm has a gain of 21 dB, eliminating the need for an amplifier to correct passage loss.

Next, the square-wave digital signal of the first sine-wave reference signal RS1 and the square-wave digital signal of the second sine-wave reference signal RS2 shown in FIG. A 10 MHz reference signal of either one of the digital signals is selected by a two-stage selection circuit consisting of .

The selected 10 MHz reference digital signal is level-adjusted to, for example, 0 dBm by the level adjustment resistor circuit 15 . The level-adjusted reference digital signal is then filtered by a low-pass filter 16 to remove signals of 10 MHz or lower, and is output as a 10 MHz sinusoidal reference output signal RSO. As an example, FIG. 3 shows changes in a series of reference signal waveform transformations when the first sinusoidal reference signal RS1 is selected.

When selecting, the problem is that the signal on the non-selected side interferes with the selected signal, and the signal on the non-selected side is non-additively mixed with the 10 MHz reference output signal of the final stage, which is detected as phase noise. It is to be done.

Interfering paths have various factors, but the present invention can improve the DU ratio (Desired to Undesired Ratio) between the selected signal and the unselected signal by suppressing the following three points of interference.
1) Interference from space 2) General-purpose logic IC interference 3) Interference between relay contacts

In order to eliminate the influence of interference from space, in the reference signal selection circuit according to the present invention, the connection terminal between the signal ground SGND of the reference signal selection circuit and the ground of the device (not shown) incorporating this reference signal selection circuit is not set. The power supply system of the reference signal selection circuit is connected in the relationship between the power supply and the power supply return, and the power supply is wired in a manner similar to a single stroke.
Also, it is characterized in that the return side is set to the signal ground SGND. That is, the termination and power supply return of each circuit are signal grounded to the same level, which is the ground level of the power supply of the reference signal selection circuit.

FIG. 5 shows a system example of power supply pattern connection, that is, power supply and signal grounding, in the 10 MHz reference signal selection circuit of FIG. In FIG. 5, VB denotes a bias circuit power supply, and VBR denotes a bias circuit power supply return of the bias circuit power supply VB. Further, VGL indicates a general-purpose logic IC power supply, and VGLR indicates a general-purpose logic IC power supply return of the general-purpose logic IC power supply VGL.
Although not shown in FIG. 1, the terminals of the bias circuits 1 and 7 and the general-purpose logic ICs 4, 10 and 14 are also connected to the signal ground SGND.

With this connection, the reference signal selection circuit according to the present invention is a circuit whose power supply system returns from the power supply to the power supply return, and is in a floating state from the ground of the device in which the reference signal selection circuit is incorporated, and non-radiating radiation into space. Spatial interference of 10 MHz on the selection side is suppressed.
Signal ground SGND represents a connection to a power supply return to the power supply of the reference signal selection circuit, such as a signal line.

Next, in order to convert to the general-purpose logic level for selection without level adjustment, it is essential to use a general-purpose logic IC. be.

FIG. 6 is a diagram for explaining mutual interference paths of two signals in a general-purpose logic circuit. The first square wave signal RSM1 corresponds, for example, to the square wave of the first sinusoidal reference signal RS1. The second square wave signal RSM2 corresponds to the square wave of the second sinusoidal reference signal RS2. As shown in FIG. 6, the first rectangular wave signal RSM1 is input/output to/from the general-purpose logic, and at the same time, the second rectangular wave signal RSM2 is connected to the power supply terminal through the power supply connection along the path indicated by the broken line IF12 in FIG. Attenuated signals leak from the VGL and cause interference. On the other hand, the second sinusoidal reference signal RS2 also has a path that interferes with the first rectangular wave signal RSM1, as indicated by the dashed-dotted line IF21 in FIG.
Note that the example of FIG. 6 is described using CMOS logic.

7 is a diagram showing an example of the configuration of a general-purpose logic circuit in the 10 MHz reference signal selection circuit of FIG. 1. FIG. In the general-purpose logic IC according to the present invention, in order to cut off the interference path from the general-purpose logic IC, as shown in FIG. is doing.

As shown in FIG. 7, the leakage signal on the path indicated by the long dashed line IF12 generated from the first rectangular wave signal RSM1 passes through the EMI filter 3 and is attenuated. After that, the attenuated leakage signal leaks to the power supply terminal of the general-purpose logic IC 10 for the second rectangular wave signal RSM2 through the power supply connection along the path indicated by the short dashed line IF12a. Since the EMI filter 9 is also connected to the power supply terminal of the IC 10, the leakage signal on the path indicated by the dotted line IF12b reaches the general-purpose logic IC 10 in a state of being further attenuated. Jammers interfering with the system are suppressed.

As for the leakage signal from the second rectangular wave signal RSM2, similarly, the leakage signal generated from the second rectangular wave signal RSM2 on the path indicated by the dashed-dotted line IF21 passes through the EMI filter 9 and is attenuated. After that, the attenuated leakage signal leaks to the power supply terminal of the general-purpose logic IC 4 for the first rectangular wave signal RSM1 through the power supply connection along the path indicated by the short dashed line IF21a. Since the EMI filter 3 is also connected to the power supply terminal of the IC4, the signal reaches the general-purpose logic IC4 in a further attenuated state along the route indicated by the dotted line IF21b, so that the first rectangular wave signal RSM1 interferes with the main signal system. interfering waves are suppressed.

EMI filters 2 and 8 are also connected to the bias circuits 1 and 7 as shown in FIGS. A circuit configuration is adopted in which an EMI filter is connected to a portion of the signal line for the sinusoidal reference signal RS2 that requires power supply connection.

When multiplying the 10MHz reference signal to the 1GHz band by the PLL circuit, it is necessary to increase the attenuation of the interfering interference wave and the carrier/noise ratio (C/N) of the signal generated at 1GHz is 30dB. . In this case, the required C/N ratio for the 10 MHz reference signal is given by the following formula (1).

Increased noise level = 20 x log(1 GHz/10 MHz) = 40 dB
C/N=30dB (at 1GHz)
Therefore, the required C/N at 10MHz is
C/N=40dB+30dB=70dB (1)

FIG. 8 is a diagram for explaining interference paths on the non-selected side in a general selective relay circuit. The first digital signal RSR1 corresponds, for example, to the digital signal of the first sinusoidal reference signal RS1. The second digital signal RSR2 corresponds to the digital signal of the second sinusoidal reference signal RS2. Assume that the first digital signal RSR1 is selected and output. On the non-selected side of the second sinusoidal reference signal RS2, there is a path that interferes with the first digital signal RSR1 as indicated by the dashed-dotted line IF21c in FIG. If the selection relay circuit shown in FIG. 8 is used, a selection relay circuit with extremely high isolation performance is required.

9 is a diagram showing an example of a configuration of a multistage selection relay circuit in the 10 MHz reference signal selection circuit of FIG. 1. FIG. A non-selected terminal b of the first selection relay 5 is signal-grounded SGND via a first termination resistor 6 for suppressing radiation to space, and is terminated by the termination resistor. A non-selected terminal b of the second selection relay 11 is signal grounded SGND via a second termination resistor 12 for suppressing radiation to space, and is terminated by the termination resistor. Of the interference paths from the second digital signal RSR2 to the first digital signal RSR1, the interference path at the second selection relay 11 is indicated by a dashed line IF21c, and the interference path at the third selection relay 133 is indicated by a dotted line IF21d. is indicated.

In the second selection relay 11, the second digital signal RSR2 of the non-selection signal flows to the signal ground SGND through the second termination resistor 12, so that the transition from the second digital signal RSR2 to the first digital signal RSR1 is Leakage signals in interference paths and radiation of signals into space can be suppressed. In this way, when signal selection is performed with a multi-stage selection relay configuration, leakage signals, interference signals, etc. can be suppressed without using special relays with extremely high isolation performance.

FIG. 10 is a diagram showing an example of a configuration in which the number of stages of multistage selection relay circuits in the 10 MHz reference signal selection circuit of FIG. 1 is increased. In the multistage selection relay circuit of FIG. 10, a fourth selection relay circuit is provided between the selection terminal a of the first selection relay 5 and the first input terminal T1 of the third selection relay 133 in contrast to the multistage selection relay circuit of FIG. A selection relay 5a is connected. A fifth selection relay 11 a is connected between the selection terminal a of the second selection relay 11 and the second input terminal T2 of the third selection relay 133 . This constitutes a three-stage multistage selection relay circuit.

A non-selected terminal b of the fourth selection relay 5a is signal-grounded SGND via a third terminating resistor 6a for suppressing radiation to space, and is terminated by the terminating resistor. A non-selected terminal b of the fifth selection relay 11a is signal-grounded SGND via a fourth terminating resistor 12a for suppressing radiation to space, and is terminated by the terminating resistor. An interference path from the second digital signal RSR2 to the first digital signal RSR1 at the fifth selection relay 11a is indicated by a dotted line IF21e.

Thus, by increasing the number of stages of the multi-stage selection relay circuit, the amount of interference wave attenuation increases in proportion to the number of selection relays, and interference waves can be suppressed.

FIG. 11 is a diagram showing another example of the configuration of the 10 MHz reference signal selection circuit according to Embodiment 1 of the present invention. In the reference signal selection circuit of FIG. 11, one of the selected reference signals is a first sinusoidal reference signal RS1, while the other is a square wave reference signal RS3 which is a general purpose logic signal level square wave. Accordingly, no configuration relating to a bias circuit is provided on the side of the rectangular wave reference signal RS3. The rectangular wave reference signal RS3 is directly input to the second general-purpose logic IC 10 and converted into a digital signal defined by the general-purpose logic. Other parts are the same as the reference signal selection circuit of FIG.

As in FIG. 1, a second bias circuit 7 and a third EMI filter 8 are provided on the rectangular wave reference signal RS3 side, and the rectangular wave reference signal RS3 is biased by the second bias circuit 7 with a different bias value. After multiplying by , it may be converted into a digital signal.

Thus, the 10 MHz reference signal selection circuit according to the present invention can be applied to selection of a plurality of reference signals including not only sine wave reference signals but also rectangular wave reference signals, and similar effects can be obtained.

In the above embodiments, two sine-wave reference signals and two rectangular-wave reference signals, which are signals to be selected, have been described. Applicable.
In the above embodiment, the multistage selection relay circuit has two stages and three stages. However, the multistage selection relay circuit can be configured with four stages or more, and the effect of suppressing the interference wave is further improved. improves.

As described above, according to the present invention, when a plurality of reference signals are sine waves of different levels from -4 dBm to +10 dBm, TTL, CMOS level, etc. with a duty of 50% can be obtained without adjusting the level of the reference signal. It is converted into a square wave signal that is a general-purpose logic level, and the logic level signal is selected by a relay. When converted to general-purpose logic, the signal level has an amplitude of 0 V and +5 V, which is a large level with respect to the input level. Therefore, the signal on the non-selected side interferes with the signal on the selected side in the selection relay circuit. Therefore, a circuit is added to ensure isolation between the signal line, the power supply line, and space in the interference path, and the square wave is reconverted to a sine wave by a 10 MHz low-pass filter in the final stage.

Signal selection is performed by setting the signal level passing through the circuit pattern and the relay circuit, which cause signal attenuation, to be the general-purpose logic level. Finally, a low-pass filter converts the general-purpose logic level digital signal into an analog signal. This realizes a selection circuit that outputs a reference signal at a constant level, for example, 0 dBm, without an amplifier for correcting excess loss.

For the input signal of the 10 MHz reference signal before selection, a special high frequency relay with high isolation and low passing loss and an amplifier for input level adjustment for each input are not required.

In addition, this selection circuit has a feature that the allowable input standard value of the 10 MHz input reference signal level ranges from -4 dBm to +10 dBm, and has a wide input level range.

Furthermore, by changing the bias value of the bias circuit or deleting the bias circuit even with the square wave 10 MHz reference signal input, the sine wave 10 MHz reference signal and the square wave 10 MHz reference signal are selected, and the sine wave 10 MHz reference signal is selected. can be output.

1 first bias circuit, 2 first EMI filter, 3 second EMI filter, 4 first general-purpose logic IC, 5 first selection relay, 5a fourth selection relay, 6 first termination resistor, 6a Third termination resistor 7 Second bias circuit 8 Third EMI filter 9 Fourth EMI filter 10 Second general-purpose logic IC 11 Second selection relay 11a Fifth selection relay 12 second termination resistor, 12a fourth termination resistor, 13 fifth EMI filter, 14 third general-purpose logic IC, 15 level adjustment resistor circuit, 16 low-pass filter, 17 capacitor, 18 resistor, 19 transistor, 133 third 3 selection relay, a selection terminal, b non-selection terminal, RC relay control circuit, T1 first input terminal, T2 second input terminal, VB bias circuit power supply, VGL general logic IC power supply, VR relay power supply.

Claims (5)

Multiple 10 MHz signals with different signal levels ranging from -4 dBm to +10 dBm , including multiple sinusoidal reference signals, or including one or more sinusoidal reference signals and one or more general purpose logic level square wave reference signals. A reference signal selection circuit that selects a reference signal,
a bias circuit for converting the sine wave reference signal into a rectangular wave signal provided for each of the sine wave reference signals; and a general purpose logic circuit for converting the converted square wave signal into a digital signal defined by general purpose logic. a first conversion circuit;
a second conversion circuit comprising a general-purpose logic circuit for converting the square-wave reference signal into a digital signal defined by general-purpose logic, provided for each square-wave reference signal when the square-wave reference signal is present;
The converted digital signal output from each of the first conversion circuits or the converted digital signal output from each of the first conversion circuit and the second conversion circuit is transferred to a relay in the next stage. A plurality of relays that switch and connect to the selected terminal connected to and the non-selected terminal that is not connected are connected in multiple stages so as to select one of the converted digital signals at the end, and the relay at the last stage is a multi-stage selection relay circuit for selecting one of the two selected converted digital signals ;
a general-purpose logic circuit connected to the output side of the multistage selection relay circuit;
An EMI filter inserted in series in the power supply path of the bias circuit for each of the bias circuits, and an EMI filter inserted in series in the power supply path of the general -purpose logic circuit for each of the general-purpose logic circuits . When,
a terminating resistor that suppresses radiation to space of the non-selection signal connected to each of the non-selection terminals of the multistage selection relay circuit;
A reference signal selection circuit. 2. The reference signal selection circuit according to claim 1, further comprising a low-pass filter for filtering the signal selected by said multistage selection relay circuit and outputting it as a sinusoidal reference signal. 3. The reference signal selection circuit according to claim 2, further comprising a level adjustment resistance circuit that adjusts the signal level of the signal selected by said multistage selection relay circuit and outputs it to said low-pass filter. 4. The reference signal selection circuit according to any one of claims 1 to 3, wherein said multi-stage selection relay circuit comprises three or more stages of selection relays. 5. The circuit according to claim 1, wherein the terminal of the circuit is signal grounded, the reference signal selection circuit is a circuit in which the power supply system returns from the power supply to the power supply return, and is in a floating state from the ground, and the power supply return side is signal grounded. A reference signal selection circuit according to any one of the preceding items.

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