JP7101736B2 - GaN single crystal substrate and semiconductor laminate - Google Patents

Description

The present invention relates to a nitride crystal substrate, a semiconductor laminate, a method for manufacturing a semiconductor laminate, and a method for manufacturing a semiconductor device.

Group III nitride semiconductors are widely used as materials for constituting semiconductor devices such as light emitting devices and electronic devices. When manufacturing these semiconductor devices, for example, a step of epitaxially growing a semiconductor layer on a nitride crystal substrate made of a group III nitride semiconductor, a step of activating impurities in the semiconductor layer, and the like. A step of heating the nitride crystal substrate may be performed (see, for example, Patent Document 1).

JP-A-2015-185576A

In the step of heating the nitride crystal substrate as described above, it is required to heat the nitride crystal substrate with high accuracy and reproducibility.

An object of the present invention is to provide a technique capable of heating a nitride crystal substrate with high accuracy and reproducibility.

According to one aspect of the invention
A nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities.
The wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate at 27 ° C is α (cm ^-1 ), the free electron concentration in the nitride crystal substrate is n (cm ^-3 ), and K and a are constants, respectively. When the absorption coefficient α is at least 1 μm or more and 3.3 μm or less, a nitride crystal substrate approximated by the following equation (1) and a technique related thereto are provided.
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

According to the present invention, the nitride crystal substrate can be heated with high accuracy and reproducibility.

(A) is a schematic plan view showing the nitride crystal substrate 10 according to the first embodiment of the present invention, and (b) is a schematic cross section showing the nitride crystal substrate 10 according to the first embodiment of the present invention. It is a figure. It is a figure which shows the displacement law of Wien. It is a figure which shows the free electron concentration dependence of the absorption coefficient measured at room temperature (27 degreeC) in the GaN crystal manufactured by the manufacturing method which concerns on 1st Embodiment of this invention. It is a figure which shows the intrinsic carrier concentration with respect to the temperature of a GaN crystal. (A) is a diagram showing the relationship of the absorption coefficient at a wavelength of 2 μm with respect to the free electron concentration in the GaN crystal produced by the production method according to the first embodiment of the present invention, and (b) is a diagram showing the relationship with respect to the free electron concentration. It is a figure which compares the relationship of the absorption coefficient at a wavelength of 2 μm. It is a schematic sectional drawing which shows the semiconductor laminate 1 which concerns on 1st Embodiment of this invention. It is a schematic block diagram of a vapor phase growth apparatus 200. (A) is a diagram showing a state in which a GaN crystal film 6 is thickly grown on a seed crystal substrate 5, and (b) is a diagram showing a plurality of nitride crystals by slicing the thickly grown GaN crystal film 6. It is a figure which shows the state which acquired the substrate 10. (A) is a schematic top view showing a holding member 300 on which the nitride crystal substrate 10 or the semiconductor laminate 1 is placed, and (b) is a schematic top view on which the nitride crystal substrate 10 or the semiconductor laminate 1 is placed. It is a schematic front view which shows the holding member 300. (A) and (b) are schematic cross-sectional views showing a manufacturing process of a semiconductor device. (A) and (b) are schematic cross-sectional views showing a manufacturing process of a semiconductor device. It is a schematic sectional drawing which shows the semiconductor device 2 which concerns on 1st Embodiment of this invention. (A) is a schematic cross-sectional view showing the semiconductor laminate 1 according to the second embodiment of the present invention, and (b) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device. (A) and (b) are schematic cross-sectional views showing a manufacturing process of a semiconductor device. (A) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device, and (b) is a schematic cross-sectional view showing the semiconductor device 2 according to the second embodiment of the present invention.

<First Embodiment of the present invention>
Hereinafter, the first embodiment of the present invention will be described with reference to the drawings.

(1) Nitride Crystal Substrate The nitride crystal substrate 10 according to the present embodiment will be described with reference to FIG. FIG. 1A is a schematic plan view showing a nitride crystal substrate 10 according to the present embodiment, and FIG. 1B is a schematic cross-sectional view showing the nitride crystal substrate 10 according to the present embodiment.

In the following, the main surface of the substrate or the like mainly refers to the upper main surface of the substrate or the like, and may be the surface of the substrate or the like. The back surface of the substrate or the like refers to the lower main surface of the substrate or the like.

As shown in FIGS. 1A and 1B, the nitride crystal substrate 10 (hereinafter, also referred to as substrate 10) of the present embodiment is used when manufacturing the semiconductor laminate 1 and the semiconductor device 2 described later. It is configured as a disk-shaped substrate. The substrate 10 is made of a single crystal of a group III nitride semiconductor, and in this embodiment, is made of, for example, a single crystal of gallium nitride (GaN).

The plane orientation of the main surface of the substrate 10 is, for example, a (0001) plane (+ c plane, Ga polar plane).
The GaN crystal constituting the substrate 10 may have a predetermined off angle with respect to the main surface of the substrate 10. The off-angle refers to the angle formed by the normal direction of the main surface of the substrate 10 and the main axis (c-axis) of the GaN crystal constituting the substrate 10. Specifically, the off angle of the substrate 10 is, for example, 0 ° or more and 1.2 ° or less.

The dislocation density on the main surface of the substrate 10 is, for example, 5 × 10 ⁶ pieces / cm ² or less. If the dislocation density on the main surface of the substrate 10 is more than 5 × 10 ⁶ pieces / cm ² , there is a possibility that the local withstand voltage will be lowered in the semiconductor layer 20 described later formed on the substrate 10. On the other hand, by setting the dislocation density on the main surface of the substrate 10 to 5 × 10 ⁶ pieces / cm ² or less as in the present embodiment, the semiconductor layer 20 formed on the substrate 10 has a local withstand voltage. Can be suppressed.

The main surface of the substrate 10 is an epiready surface, and the surface roughness (arithmetic mean roughness Ra) of the main surface of the substrate 10 is, for example, 10 nm or less, preferably 5 nm or less.

The diameter D of the substrate 10 is not particularly limited, but is, for example, 25 mm or more. If the diameter D of the substrate 10 is less than 25 mm, the productivity of the semiconductor device 2 described later tends to decrease. Therefore, the diameter D of the substrate 10 is preferably 25 mm or more. The thickness T of the substrate 10 is, for example, 150 μm or more and 2 mm or less. If the thickness T of the substrate 10 is less than 150 μm, the mechanical strength of the substrate 10 may decrease and it may be difficult to maintain the self-supporting state. Therefore, the thickness T of the substrate 10 is preferably 150 μm or more. Here, for example, the diameter D of the substrate 10 is 2 inches, and the thickness T of the substrate 10 is 400 μm.

Further, the substrate 10 contains, for example, an n-type impurity (donor). Examples of the n-type impurities contained in the substrate 10 include silicon (Si) and germanium (Ge). Since the n-type impurities are doped in the substrate 10, free electrons having a predetermined concentration are generated in the substrate 10.

(About absorption coefficient, etc.)
In the present embodiment, the substrate 10 satisfies a predetermined requirement for the absorption coefficient in the infrared region.
The details will be described below.

When manufacturing the semiconductor laminate 1 and the semiconductor device 2, for example, as described later, there is a step of epitaxially growing the semiconductor layer 20 on the substrate 10, a step of activating impurities in the semiconductor layer 20, and the like. In addition, a step of heating the substrate 10 may be performed. For example, when the substrate 10 is irradiated with infrared rays to heat the substrate 10, it is important to set the heating conditions based on the absorption coefficient of the substrate 10.

Here, FIG. 2 is a diagram showing Wien's displacement law. In FIG. 2, the horizontal axis indicates the blackbody temperature (° C.), and the vertical axis indicates the peak wavelength (μm) of blackbody radiation. According to Wien's displacement law shown in FIG. 2, the peak wavelength of blackbody radiation is inversely proportional to the blackbody temperature. When the peak wavelength is λ (μm) and the temperature is T (° C.), it has a relationship with λ = 2896 / (T + 273). Assuming that the radiation from a predetermined heating source in the step of heating the substrate 10 is blackbody radiation, infrared rays having a peak wavelength corresponding to the heating temperature will be emitted from the heating source to the substrate 10. .. For example, when the temperature is about 1200 ° C., the infrared peak wavelength λ is 2 μm, and when the temperature is about 600 ° C., the infrared peak wavelength λ is 3.3 μm.

When the substrate 10 is irradiated with infrared rays having such a wavelength, absorption by free electrons (free carrier absorption) occurs in the substrate 10, which causes the substrate 10 to be heated.

Therefore, in the present embodiment, the absorption coefficient in the infrared region of the substrate 10 satisfies the following predetermined requirements based on the free carrier absorption of the substrate 10.

FIG. 3 is a diagram showing the dependence of the absorption coefficient of the GaN crystal produced by the production method according to the present embodiment at room temperature (27 ° C.) on the free electron concentration. Note that FIG. 3 shows the measurement results of a substrate made of GaN crystals manufactured by doping with Si by the manufacturing method described later. In FIG. 3, the horizontal axis indicates the wavelength (nm), and the vertical axis indicates the absorption coefficient α (cm ^-1 ) of the GaN crystal. Further, the free electron concentration in the GaN crystal is set to n, and the absorption coefficient α of the GaN crystal is plotted for each predetermined free electron concentration n. As shown in FIG. 3, in the GaN crystal manufactured by the manufacturing method described later, the absorption coefficient in the GaN crystal increases toward a longer wavelength due to free carrier absorption in a wavelength range of at least 1 μm or more and 3.3 μm or less. It shows a tendency for α to increase (monotonically increase). Further, as the free electron concentration n in the GaN crystal increases, the free carrier absorption in the GaN crystal tends to increase.

Since the substrate 10 used in this embodiment is made of GaN crystals manufactured by the manufacturing method described later, the substrate 10 of this embodiment has a small crystal strain and is other than oxygen (O) and n-type impurities. (For example, impurities compensating for n-type impurities) are hardly contained. This shows the free electron concentration dependence of the absorption coefficient as shown in FIG. As a result, in the substrate 10 of the present embodiment, the absorption coefficient in the infrared region can be approximated as a function of the free carrier concentration and the wavelength as follows.

Specifically, the wavelength is λ (μm), the absorption coefficient of the substrate 10 at 27 ° C is α (cm ^-1 ), the free electron concentration in the substrate 10 is n (cm ^-3 ), and K and a are constants. Then, in the substrate 10 of the present embodiment, the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less (preferably 1 μm or more and 2.5 μm or less) is approximated by the following equation (1).
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

In addition, "the absorption coefficient α is approximated by the equation (1)" means that the absorption coefficient α is approximated by the equation (1) by the method of least squares. That is, the above provision includes not only the case where the absorption coefficient completely matches the equation (1) (satisfies the equation (1)) but also the case where the equation (1) is satisfied within a predetermined error range. The predetermined error is, for example, within ± 0.1α, preferably within ± 0.01α at a wavelength of 2 μm.

The absorption coefficient α in the wavelength range may be considered to satisfy the following equation (1)'.
1.5 × 10 ^-19 nλ ³ ≦ α ≦ 6.0 × 10 ^-19 nλ ³ ... (1)'

Further, in the high-quality substrate among the substrates 10 satisfying the above specifications, the absorption coefficient α in the wavelength range is approximated by the following equation (1)'' (satisfying the equation (1)'').
α = 2.2 × ^10-19 nλ ³ ... (1)''

The provision that "the absorption coefficient α is approximated by the equation (1)" is completely the same as the above-mentioned provision that the absorption coefficient is exactly the same as the equation (1)'(the equation (1)'. It includes not only the case of (satisfying) but also the case of satisfying equation (1)'' within a predetermined error range. The predetermined error is, for example, within ± 0.1α, preferably within ± 0.01α at a wavelength of 2 μm.

In FIG. 3 described above, the measured value of the absorption coefficient α in the GaN crystal manufactured by the manufacturing method described later is shown by a thin line. Specifically, the measured value of the absorption coefficient α when the free electron concentration n is 1.0 × 10 ¹⁷ cm ^-3 is shown by a thin solid line, and when the free electron concentration n is 1.2 × 10 ¹⁸ cm ^-3 . The measured value of the absorption coefficient α of is shown by a thin dotted line, and the measured value of the absorption coefficient α when the free electron concentration n is 2.0 × 10 ¹⁸ cm ^-3 is shown by a thin single point chain line. On the other hand, in FIG. 3 described above, the function of the above equation (1) is shown by a thick line. Specifically, the function of the equation (1) when the free electron concentration n is 1.0 × 10 ¹⁷ cm ^-3 is shown by a thick solid line, and when the free electron concentration n is 1.2 × 10 ¹⁸ cm ^-3 . The function of Eq. (1) is shown by a thick dotted line, and the function of Eq. (1) when the free electron concentration n is 2.0 × 10 ¹⁸ cm ^-3 is shown by a thick alternate long and short dash line. As shown in FIG. 3, the measured value of the absorption coefficient α in the GaN crystal manufactured by the manufacturing method described later can be accurately fitted by the function of the equation (1). In the case of FIG. 3 (in the case of Si doping), the absorption coefficient α is accurately approximated to the equation (1) when K = 2.2 × ^10-19 .

By approximating the absorption coefficient of the substrate 10 by the equation (1) in this way, the absorption coefficient of the substrate 10 can be accurately designed based on the concentration n of free electrons in the substrate 10.

Further, in the present embodiment, for example, in the wavelength range of at least 1 μm or more and 3.3 μm or less, the absorption coefficient α of the substrate 10 satisfies the following formula (2).
0.15λ ³ ≤ α ≤ 6λ ³ ... (2)

If α <0.15λ ³ , the substrate 10 cannot sufficiently absorb infrared rays, and the heating of the substrate 10 may become unstable. On the other hand, by setting 0.15λ ³ ≦ α, infrared rays can be sufficiently absorbed by the substrate 10 and the substrate 10 can be heated stably. On the other hand, when 6λ ³ <α, it corresponds to the concentration of n-type impurities in the substrate 10 exceeding a predetermined value (1 × 10 ¹⁹ at · cm ^-3 or more) as described later, and the substrate 10 Crystallinity may decrease. On the other hand, by setting α ≦ 6λ ³ , it corresponds to the concentration of n-type impurities in the substrate 10 being equal to or less than a predetermined value, and good crystallinity of the substrate 10 can be ensured.

The absorption coefficient α of the substrate 10 preferably satisfies the following formula (2)'or (2)''.
0.15λ ³ ≤ α ≤ 3λ ³ ... (2)'
0.15λ ³ ≤ α ≤ 1.2λ ³ ... (2)''
This makes it possible to stably heat the substrate 10 while ensuring better crystallinity of the substrate 10.

Further, in the present embodiment, for example, in the wavelength range of at least 1 μm or more and 3.3 μm or less, the difference between the maximum value and the minimum value of the absorption coefficient α in the main surface of the substrate 10 (the minimum value is subtracted from the maximum value). Difference. When Δα is defined as “difference in in-plane absorption coefficient of the substrate 10”), Δα (cm ^-1 ) satisfies the equation (3).
Δα ≦ 1.0 ・ ・ ・ (3)
When Δα> 1.0, the heating efficiency due to the irradiation of infrared rays may become non-uniform in the main surface of the substrate 10. On the other hand, by setting Δα ≦ 1.0, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10.

It is preferable that Δα satisfies the equation (3)'.
Δα ≦ 0.5 ・ ・ ・ (3)'
By setting Δα ≦ 0.5, the heating efficiency due to the irradiation of infrared rays can be stably made uniform in the main surface of the substrate 10.

The provisions of equations (2) and (3) regarding the absorption coefficients α and Δα can be replaced with, for example, the provisions at a wavelength of 2 μm.

That is, in the present embodiment, for example, the absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2 cm ^-1 or more and 48 cm ^-1 or less. The absorption coefficient of the substrate 10 at a wavelength of 2 μm is preferably 1.2 cm ^-1 or more and 24 cm ^-1 or less, and more preferably 1.2 cm ^-1 or more and 9.6 cm ^-1 or less.

Further, in the present embodiment, for example, the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is within 1.0 cm ^-1 , preferably within 0.5 cm ^-1 . be.

Although the upper limit of the in-plane absorption coefficient difference of the substrate 10 has been described, the lower limit of the in-plane absorption coefficient difference of the substrate 10 is preferably zero because the smaller it is, the better. Even if the in-plane absorption coefficient difference of the substrate 10 is 0.01 cm ^-1 , the effect of this embodiment can be sufficiently obtained.

Here, the requirements for the absorption coefficient of the substrate 10 are defined at a wavelength of 2 μm corresponding to the peak wavelength of infrared rays when the temperature is about 1200 ° C. However, the effect of satisfying the above requirements for the absorption coefficient of the substrate 10 is not limited to when the temperature is about 1200 ° C. This is because the spectrum of infrared rays emitted from the heating source has a predetermined wavelength width according to Stefan-Boltzmann's law, and has a component having a wavelength of 2 μm even if the temperature is other than 1200 ° C. Therefore, if the absorption coefficient of the substrate 10 satisfies the above requirements at a wavelength of 2 μm corresponding to a temperature of 1200 ° C., the absorption coefficient of the substrate 10 and the inside of the main surface of the substrate 10 can be obtained even at a wavelength other than 1200 ° C. The difference between the maximum value and the minimum value of the absorption coefficient in is within a predetermined range. As a result, even if the temperature is other than 1200 ° C., the substrate 10 can be stably heated and the heating efficiency with respect to the substrate 10 can be made uniform in the main surface.

By the way, FIG. 3 above is the result of measuring the absorption coefficient of the GaN crystal at room temperature (27 ° C.). Therefore, when considering the absorption coefficient of the substrate 10 under a predetermined temperature condition in the step of heating the substrate 10, the free carrier absorption of the GaN crystal under the predetermined temperature condition is the GaN crystal under the temperature condition of room temperature. It is necessary to consider how it changes with respect to the free carrier absorption of.

FIG. 4 is a diagram showing the intrinsic carrier concentration with respect to the temperature of the GaN crystal. As shown in FIG. 4, in the GaN crystal constituting the substrate 10, the concentration of the intrinsic carrier concentration _ni that is thermally excited between the bands (between the valence band and the conduction band) increases as the temperature increases. .. However, even if the temperature of the GaN crystal is around 1300 ° C., the concentration of the intrinsic carrier concentration ni that is thermally excited between the bands of the GaN crystal is less than 7 × 10 ¹⁵ cm ^-3 , and the _n -type impurities. It is well below the concentration of free carriers produced in the GaN crystal by the doping of (eg 1 × 10 ¹⁷ cm ^-3 ). That is, it can be said that the free carrier concentration of the GaN crystal is within the so-called extrinsic region in which the free carrier concentration is determined by doping with n-type impurities under the temperature condition that the temperature of the GaN crystal is less than 1300 ° C.

That is, in this embodiment, thermal excitation is performed between the bands of the substrate 10 at least under temperature conditions (room temperature (27 ° C.) or more and 1250 ° C. or less) in the manufacturing process of the semiconductor laminate 1 and the semiconductor device 2 described later. The concentration of the intrinsic carrier to be formed is lower than the concentration of free electrons generated in the substrate 10 by doping with n-type impurities under the temperature condition of room temperature (for example, 1/10 times or less). Thereby, it can be considered that the free carrier concentration of the substrate 10 under the predetermined temperature condition in the step of heating the substrate 10 is substantially equal to the free carrier concentration of the substrate 10 under the temperature condition of room temperature. Free carrier absorption under temperature conditions can be considered to be approximately equal to free carrier absorption at room temperature. That is, as described above, when the absorption coefficient in the infrared region of the substrate 10 satisfies the above-mentioned predetermined requirement at room temperature, the absorption coefficient in the infrared region of the substrate 10 substantially satisfies the above-mentioned predetermined requirement even under a predetermined temperature condition. It can be considered to be maintained.

Further, in the substrate 10 of the present embodiment, the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the equation (1). Therefore, at a predetermined wavelength λ, the absorption coefficient α of the substrate 10 is determined. It has a relationship that is almost proportional to the free electron concentration n.

FIG. 5A is a diagram showing the relationship between the absorption coefficient at a wavelength of 2 μm and the free electron concentration in the GaN crystal produced by the production method according to the present embodiment. In FIG. 5A, the lower solid line (α = 1.2 × ^10-18 n) is a function in which K = 1.5 × ^10-19 and λ = 2.0 are substituted into equation (1). Yes, the upper solid line (α = 4.8 × ^10-18 n) is a function in which K = 6.0 × ^10-19 and λ = 2.0 are substituted into equation (1). Further, FIG. 5A shows not only a Si-doped GaN crystal but also a Ge-doped GaN crystal. Moreover, the result of measuring the absorption coefficient by the transmission measurement and the result of measuring the absorption coefficient by the spectroscopic ellipsometry method are shown. As shown in FIG. 5A, when the wavelength λ is 2.0 μm, the absorption coefficient α of the GaN crystal produced by the production method described later has a relationship substantially proportional to the free electron concentration n. ing. Further, the measured value of the absorption coefficient α in the GaN crystal manufactured by the manufacturing method described later is within the range of 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 by the function of the equation (1). It can be fitted with high accuracy. Since the GaN crystal produced by the production method described later is of high quality, the measured value of the absorption coefficient α is the function of the equation (1) when K = 2.2 × ^10-19 , that is, α. In many cases, fitting can be performed accurately by = 1.8 × ^10-18 n.

In the present embodiment, the free electron concentration n in the substrate 10 satisfies the following predetermined requirements based on the fact that the absorption coefficient α of the substrate 10 described above is proportional to the free electron concentration n.

In the present embodiment, for example, the free electron concentration n in the substrate 10 is 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ¹⁹ cm ^-3 or less. Thereby, from the equation (1), the absorption coefficient of the substrate 10 at a wavelength of 2 μm can be set to 1.2 cm ^-1 or more and 48 cm ^-1 or less. The free electron concentration n in the substrate 10 is preferably 1.0 × 10 ¹⁸ cm ^-3 or more and 5.0 × 10 ¹⁸ cm ^-3 or less, and 1.0 × 10 ¹⁸ cm ^-3 or more 2. It is more preferably 0 × 10 ¹⁸ cm ^-3 or less. As a result, the absorption coefficient of the substrate 10 at a wavelength of 2 μm can be preferably 1.2 cm ^-1 or more and 24 cm ^-1 or less, and more preferably 1.2 cm ^-1 or more and 9.6 cm ^-1 or less.

Further, as described above, the difference between the maximum value and the minimum value of the absorption coefficient α in the main surface of the substrate 10 is defined as Δα, and the difference between the maximum value and the minimum value of the free electron concentration n in the main surface of the substrate 10 is defined as Δα. When Δn is set and the wavelength λ is 2.0 μm, the following equation (4) can be obtained by differentiating the equation (1).
Δα = 8KΔn ・ ・ ・ (4)

In the present embodiment, for example, the difference Δn between the maximum value and the minimum value of the free electron concentration n in the main surface of the substrate 10 is 8.3 × 10 ¹⁷ cm ^-3 or less, preferably 4.2 × 10 ¹⁷ cm. It is within ^-3 . Thereby, from the equation (4), the difference Δα between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm can be set to 1.0 cm ^-1 or less, preferably 0.5 cm ^-1 or less.

Although the upper limit of Δn has been described, the lower limit of Δn is preferably zero because the smaller it is, the better. Even if Δn is 8.3 × 10 ¹⁵ cm ^-3 , the effect of this embodiment can be sufficiently obtained.

In the present embodiment, the free electron concentration n in the substrate 10 is equal to the concentration of the n-type impurities in the substrate 10, and the concentration of the n-type impurities in the substrate 10 satisfies the following predetermined requirements. ..

In the present embodiment, for example, the concentration of n-type impurities in the substrate 10 is 1.0 × 10 ¹⁸ at · cm ^-3 or more and 1.0 × 10 ¹⁹ at · cm ^-3 or less. As a result, the free electron concentration n in the substrate 10 can be set to 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ¹⁹ cm ^-3 or less. The concentration of n-type impurities in the substrate 10 is preferably 1.0 × 10 ¹⁸ at · cm ^-3 or more and 5.0 × 10 ¹⁸ at · cm ^-3 or less, preferably 1.0 × 10 ¹⁸ at. -It is more preferable that it is cm ^-3 or more and 2.0 × 10 ¹⁸ at · cm ^-3 or less. As a result, the free electron concentration n in the substrate 10 is preferably 1.0 × 10 ¹⁸ cm ^-3 or more and 5.0 × 10 ¹⁸ cm ^-3 or less, and more preferably 1.0 × 10 ¹⁸ cm ^-3 or more. It can be 2.0 × 10 ¹⁸ cm ^-3 or less.

Further, in the present embodiment, for example, the difference between the maximum value and the minimum value of the concentration of n-type impurities in the main surface of the substrate 10 (hereinafter, also referred to as the difference in in-plane concentration of n-type impurities) is 8.3 ×. It is within 10 ¹⁷ at · cm ^-3 , preferably within 4.2 × 10 ¹⁷ at · cm ^-3 . As a result, the difference Δn between the maximum and minimum free electron concentrations n in the main surface of the substrate 10 is equal to the in-plane concentration difference of the n-type impurities, and is preferably within 8.3 × 10 ¹⁷ cm ^-3 . It can be within 4.2 × 10 ¹⁷ cm ^-3 .

Although the upper limit of the in-plane concentration difference of n-type impurities has been described, the lower limit of the in-plane concentration difference of n-type impurities is preferably zero because the smaller it is, the better. Even if the in-plane concentration difference of the n-type impurities is 8.3 × 10 ¹⁵ at · cm ^-3 , the effect of the present embodiment can be sufficiently obtained.

Further, in the present embodiment, the concentration of each element in the substrate 10 satisfies the following predetermined requirements.

In the present embodiment, among Si, Ge and O used as n-type impurities, the concentration of O, whose addition amount is relatively difficult to control, is extremely low, and the concentration of n-type impurities in the substrate 10 is added. The amount is determined by the total concentration of Si and Ge, which is relatively easy to control.

That is, the concentration of O in the substrate 10 is negligibly low with respect to the total concentration of Si and Ge in the substrate 10, for example, 1/10 or less. Specifically, for example, the concentration of O in the substrate 10 is less than 1 × 10 ¹⁷ at · cm ^-3 , while the total concentration of Si and Ge in the substrate 10 is 1 × 10 ¹⁸ at · cm. ^-3 or more and 1.0 × 10 ¹⁹ at · cm ^-3 or less. Thereby, the concentration of the n-type impurity in the substrate 10 can be controlled by the total concentration of Si and Ge, which is relatively easy to control the addition amount. As a result, the free electron concentration n in the substrate 10 can be accurately controlled to be equal to the total concentration of Si and Ge in the substrate 10, and the maximum value of the free electron concentration in the main surface of the substrate 10 can be controlled. The difference Δn between the minimum value and the minimum value can be accurately controlled so as to satisfy a predetermined requirement.

Further, in the present embodiment, the concentration of impurities other than the n-type impurities in the substrate 10 is negligibly low with respect to the concentration of the n-type impurities in the substrate 10 (that is, the total concentration of Si and Ge), for example. It is 1/10 or less. Specifically, for example, the concentration of impurities other than the n-type impurities in the substrate is less than 1 × 10 ¹⁷ at · cm ^-3 . This makes it possible to reduce the factors that hinder the generation of free electrons from n-type impurities. As a result, the free electron concentration n in the substrate 10 can be accurately controlled to be equal to the concentration of the n-type impurities in the substrate 10, and the maximum and minimum values of the free electron concentration in the main surface of the substrate 10 can be controlled. The difference Δn from the value can be accurately controlled so as to satisfy a predetermined requirement.

The present inventors have confirmed that the concentration of each element in the substrate 10 can be stably controlled so as to satisfy the above requirements by adopting the manufacturing method described later.

According to the manufacturing method described later, the concentrations of O and carbon (C) in the substrate 10 can be reduced to less than 5 × 10 ¹⁵ at · cm ^-3 , and further, iron (Fe) in the substrate 10 can be reduced. , Chromium (Cr), boron (B), etc., have been found to be able to be reduced to less than 1 × 10 ¹⁵ at · cm ^-3 . It was also found that, according to this method, it is possible to reduce the concentration of elements other than these to less than the lower limit of detection in the measurement by the secondary ion mass spectrometry (SIMS). ing.

Further, in the substrate 10 manufactured by the manufacturing method described later in the present embodiment, the absorption coefficient due to free carrier absorption is smaller than the absorption coefficient of the conventional substrate. Therefore, the substrate 10 of the present embodiment has a higher absorption coefficient than the conventional substrate. , It is estimated that the mobility (μ) is high. As a result, even when the free electron concentration in the substrate 10 of the present embodiment is equal to the free electron concentration in the conventional substrate, the resistivity (ρ = 1 / enμ) of the substrate 10 of the present embodiment is conventional. It is lower than the resistivity of the substrate. Specifically, when the free electron concentration n in the substrate 10 is 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ¹⁹ cm ^-3 or less, the resistivity of the substrate 10 is, for example, 2.2 mΩ. -Cm or more and 17.4 mΩ-cm or less.

(2) Semiconductor Laminates Next, the semiconductor laminate (crystal laminate) 1 according to the present embodiment will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the semiconductor laminate 1 according to the present embodiment.

First, the outline of the semiconductor laminate 1 of the present embodiment will be described.

As shown in FIG. 6, the semiconductor laminate 1 of the present embodiment is configured as a substrate-like intermediate used in manufacturing the semiconductor device 2 described later. The semiconductor laminate 1 has, for example, a substrate 10 and a semiconductor layer (semiconductor laminated structure, semiconductor laminate, or epitaxial growth layer) 20.

The substrate 10 is the above-mentioned nitride crystal substrate, and the absorption coefficient in the infrared region of the substrate 10 satisfies the above-mentioned requirements.

The semiconductor layer 20 is formed by epitaxially growing on the main surface of the substrate 10. The semiconductor layer 20 is made of a single crystal of a group III nitride semiconductor, and in this embodiment, for example, it is made of a single crystal of GaN like the substrate 10.

In the present embodiment, the surface (main surface) of the semiconductor layer 20 satisfies a predetermined requirement for reflectance in the infrared region. Specifically, the reflectance of the surface of the semiconductor layer 20 is 5% or more and 30% or less in a wavelength range of at least 1 μm or more and 3.3 μm or less. As a result, in the process of heating the substrate 10 (semiconductor laminate 1), infrared rays can be sufficiently delivered to the substrate 10. As a result, the substrate 10 can be stably heated.

The surface roughness (arithmetic mean roughness Ra) of the surface of the semiconductor layer 20 is, for example, 1 nm or more and 30 nm or less. Thereby, the reflectance of the surface of the semiconductor layer 20 can be set to 5% or more and 30% or less in a wavelength range of at least 1 μm or more and 3.3 μm or less.

Next, a specific configuration of the semiconductor laminate 1 of the present embodiment will be described.

The semiconductor laminate 1 of the present embodiment is configured as an intermediate used, for example, when manufacturing a semiconductor device 2 as a pn junction diode having a high withstand voltage. The semiconductor layer 20 in the semiconductor laminate 1 has, for example, a laminated structure. Specifically, the semiconductor layer 20 includes, for example, a base n-type semiconductor layer 21, a drift layer 22, a first p-type semiconductor layer 23, and a second p-type semiconductor layer 24.

(Base n-type semiconductor layer)
The base n-type semiconductor layer 21 is provided so as to be in contact with the main surface of the substrate 10 as a buffer layer that inherits the crystallinity of the substrate 10 and stably epitaxially grows the drift layer 22. Further, the base n-type semiconductor layer 12 is configured as an n-type GaN layer containing n-type impurities. Examples of the n-type impurities contained in the base n-type semiconductor layer 12 include Si and Ge, as in the case of the substrate 10. The concentration of n-type impurities in the base n-type semiconductor layer 12 is substantially equal to that of the substrate 10, for example, 1.0 × 10 ¹⁸ at · cm ^-3 or more and 1.0 × 10 ¹⁹ at · cm ^-3 or less.

The thickness of the base n-type semiconductor layer 21 is thinner than the thickness of the drift layer 22, for example, 0.1 μm or more and 3 μm or less.

(Drift layer)
The drift layer 22 is provided on the base n-type semiconductor layer 21 and is configured as an n-type GaN layer containing a low-concentration n-type impurity. Examples of the n-type impurities in the drift layer 22 include Si and Ge, as in the n-type impurities in the underlying n-type semiconductor layer 21.

The concentration of n-type impurities in the drift layer 22 is lower than the concentration of n-type impurities in the substrate 10 and the underlying n-type semiconductor layer 21, for example, 1.0 × 10 ¹⁵ at · cm ^-3 or more 5.0 × 10. It is ¹⁶ at · cm ^-3 or less. By setting the concentration of n-type impurities in the drift layer 22 to 1.0 × 10 ¹⁵ at · cm ^-3 or more, the on-resistance of the semiconductor device 2 can be reduced. On the other hand, by setting the concentration of n-type impurities in the drift layer 22 to 5.0 × 10 ¹⁶ at · cm ^-3 or less, a predetermined withstand voltage of the semiconductor device 2 can be ensured.

The drift layer 22 is provided thicker than, for example, the base n-type semiconductor layer 21 in order to improve the withstand voltage of the semiconductor device 2. Specifically, the thickness of the drift layer 22 is, for example, 3 μm or more and 40 μm or less. By setting the thickness of the drift layer 22 to 3 μm or more, a predetermined withstand voltage of the semiconductor device 2 can be secured. On the other hand, by setting the thickness of the drift layer 22 to 40 μm or less, the on-resistance of the semiconductor device 2 can be reduced.

(1st p-type semiconductor layer)
The first p-type semiconductor layer 23 is provided on the drift layer 22 and is configured as a p-type GaN layer containing p-type impurities (acceptors). Examples of the p-type impurity in the first p-type semiconductor layer 23 include magnesium (Mg). The concentration of p-type impurities in the first p-type semiconductor layer 23 is, for example, 1.0 × 10 ¹⁷ at · cm ^-3 or more and 2.0 × 10 ¹⁹ at · cm ^-3 or less.

The thickness of the first p-type semiconductor layer 23 is thinner than the thickness of the drift layer 22, for example, 100 nm or more and 500 nm or less.

(2nd p-type semiconductor layer)
The second p-type semiconductor layer 24 is provided on the first p-type semiconductor layer 23 and is configured as a p-type GaN layer containing a high concentration of p-type impurities. Examples of the p-type impurities in the second p-type semiconductor layer 24 include Mg, as in the case of the first p-type semiconductor layer 23. Further, the p-type impurity concentration in the second p-type semiconductor layer 24 is higher than the p-type impurity concentration in the first p-type semiconductor layer 23, for example, 5.0 × 10 ¹⁹ at · cm ^-3 or more 2.0 ×. It is 10 ²⁰ at · cm ^-3 or less.
By keeping the concentration of p-type impurities in the second p-type semiconductor layer 24 within the above range, the contact resistance between the second p-type semiconductor layer 24 and the p-type electrode described later can be reduced.

The thickness of the second p-type semiconductor layer 24 is thinner than the thickness of the first p-type semiconductor layer 23, for example, 10 nm or more and 50 nm or less.

(3) Manufacturing Method of Semiconductor Laminate and Manufacturing Method of Semiconductor Device Next, the manufacturing method of the semiconductor laminate 1 and the manufacturing method of the semiconductor device 2 according to the present embodiment will be described with reference to FIGS. 6 to 12. FIG. 7 is a schematic configuration diagram of the vapor phase growth apparatus 200. FIG. 8A is a diagram showing a state in which a GaN crystal film 6 is thickly grown on a seed crystal substrate 5, and FIG. 8B is a diagram showing a state in which a thickly grown GaN crystal film 6 is sliced to obtain a plurality of nitrides. It is a figure which shows the state which acquired the physical crystal substrate 10. FIG. 9A is a schematic top view showing a holding member 300 on which the nitride crystal substrate 10 or the semiconductor laminate 1 is placed, and FIG. 9B is a schematic top view on which the nitride crystal substrate 10 or the semiconductor laminate 1 is mounted. It is a schematic front view which shows the holding member 300 to be placed. 10 (a), 10 (b), 11 (a) and 11 (b) are schematic cross-sectional views showing a manufacturing process of a semiconductor device. FIG. 12 is a schematic cross-sectional view showing the semiconductor device 2 according to the present embodiment. Hereinafter, the step is abbreviated as S.

(S110: Substrate preparation process)
First, the substrate preparation step S110 for preparing the substrate 10 is performed. The substrate preparation step S110 of the present embodiment includes, for example, a substrate manufacturing step S112, a measurement step S114, and a determination step S116.

(S112: Substrate manufacturing process)
The substrate 10 is manufactured by using the hydride vapor phase growth apparatus (HVPE apparatus) 200 shown below.

(Configuration of HVPE device)
The configuration of the HVPE apparatus 200 used for manufacturing the substrate 10 will be described in detail with reference to FIG. 7.

The HVPE apparatus 200 includes an airtight container 203 in which the film forming chamber 201 is internally configured. An inner cover 204 is provided in the film forming chamber 201, and a susceptor 208 as a base on which a seed crystal substrate (hereinafter, also referred to as a seed substrate) 5 is arranged at a position surrounded by the inner cover 204. Is provided. The susceptor 208 is connected to the rotation shaft 215 of the rotation mechanism 216, and is configured to be rotatable according to the drive of the rotation mechanism 216.

At one end of the airtight container 203, a gas supply pipe 232a for supplying hydrogen chloride (HCl) gas into the gas generator 233a, a gas supply pipe 232b for supplying ammonia (NH ₃ ) gas into the inner cover 204, and an inner cover 204. A gas supply pipe 232c for supplying the doping gas described later, and a gas supply for supplying a mixed gas (N ₂ / H ₂ gas) of nitrogen (N ₂ ) gas and hydrogen (H ₂ ) gas as a purge gas into the inner cover 204. A pipe 232d and a gas supply pipe 232e that supplies _N2 gas as a purge gas into the film forming chamber 201 are connected. The gas supply pipes 232a to 232e are provided with flow rate controllers 241a to 241e and valves 243a to 243e, respectively, in this order from the upstream side. A gas generator 233a for accommodating a Ga melt as a raw material is provided downstream of the gas supply pipe 232a. The gas generator 233a is provided with a nozzle 249a for supplying gallium chloride (GaCl) gas generated by the reaction of HCl gas and Ga melt toward the seed substrate 5 or the like arranged on the susceptor 208. There is. On the downstream side of the gas supply pipes 232b and 232c, nozzles 249b and 249c for supplying various gases supplied from these gas supply pipes to the seed substrate 5 and the like arranged on the susceptor 208 are connected, respectively. .. The nozzles 249a to 249c are arranged so as to allow gas to flow in a direction intersecting the surface of the susceptor 208. The doping gas supplied from the nozzle _249c is a mixed gas of a doping raw material gas and a carrier gas such as _N2 / H2 gas. As for the doping gas, HCl gas may be flown together for the purpose of suppressing the thermal decomposition of the halide gas as the doping raw material. The doping raw material gas constituting the doping gas may be, for example, dichlorosilane (SiH ₂ Cl ₂ ) gas or silane (SiH ₄ ) gas in the case of silicon (Si) doping, or germanium (Ge) doping in the case of germanium (Ge) doping. It is conceivable to use tetrachlorogerman (GeCl ₄ ) gas, dichlorogerman (GeH ₂ Cl ₂ ) gas or germanium (GeH ₄ ) gas, respectively, but the present invention is not limited thereto.

At the other end of the airtight container 203, an exhaust pipe 230 for exhausting the inside of the film forming chamber 201 is provided. The exhaust pipe 230 is provided with a pump (or blower) 231. Zone heaters 207a and 207b are provided on the outer periphery of the airtight container 203 to heat the inside of the gas generator 233a and the seed substrate 5 on the susceptor 208 to a desired temperature for each region. Further, a temperature sensor (but not shown) for measuring the temperature in the film forming chamber 201 is provided in the airtight container 203.

The above-mentioned components of the HVPE device 200, particularly each member for forming various gas flows, are described below, for example, in order to enable crystal growth with a low impurity concentration as described later. It is configured.

Specifically, as shown in FIG. 7 so as to be distinguishable by the hatch type, the airtight container 203 is heated to the crystal growth temperature (for example, 1000 ° C. or higher) by receiving radiation from the zone heaters 207a and 207b. It is preferable to use a member made of a quartz-free and boron-free material as a member that constitutes a high-temperature region that is a region in which the gas supplied to the seed substrate 5 comes into contact. Specifically, as the member constituting the high temperature region, for example, it is preferable to use a member made of silicon carbide (SiC) coated graphite. On the other hand, in a relatively low temperature region, it is preferable to construct the member using high-purity quartz. That is, in the high temperature region where the temperature becomes relatively high and comes into contact with HCl gas or the like, each member is composed of SiC coated graphite instead of high-purity quartz. Specifically, the inner cover 204, the susceptor 208, the rotating shaft 215, the gas generator 233a, the nozzles 249a to 249c, and the like are made of SiC coated graphite. Since the core tube constituting the airtight container 203 can only be made of quartz, an inner cover 204 that surrounds the susceptor 208, the gas generator 233a, and the like is provided in the film forming chamber 201. The walls at both ends of the airtight container 203, the exhaust pipe 230, and the like may be configured by using a metal material such as stainless steel.

For example, according to "Polyakov et al. J. Poly. Phys. 115, 183706 (2014)", it is disclosed that growth of a GaN crystal having a low impurity concentration can be realized by growing at 950 ° C. .. However, such low-temperature growth causes deterioration of the obtained crystal quality, and good thermal properties, electrical characteristics, and the like cannot be obtained.

On the other hand, according to the above-mentioned HVPE apparatus 200 of the present embodiment, each member is configured by using SiC coated graphite in a high temperature region where the temperature becomes relatively high and comes into contact with HCl gas or the like. As a result, impurities such as Si, O, C, Fe, Cr, and Ni caused by quartz, stainless steel, and the like are supplied to the crystal growth portion even in a temperature range suitable for growing GaN crystals, for example, 1050 ° C. or higher. It can be blocked. As a result, it is feasible to grow a GaN crystal having high purity and good thermal and electrical characteristics.

Each member included in the HVPE device 200 is connected to a controller 280 configured as a computer, and is configured so that a processing procedure and processing conditions described later are controlled by a program executed on the controller 280. There is.

(Manufacturing process of substrate 10)
Subsequently, with reference to FIG. 7, a series of processes from epitaxially growing a GaN single crystal on the seed substrate 5 using the above-mentioned HVPE apparatus 200 and then slicing the grown crystal to obtain the substrate 10. I will explain in detail. In the following description, the operation of each part constituting the HVPE device 200 is controlled by the controller 280.

The manufacturing process of the substrate 10 includes a carry-in step, a crystal growth step, a carry-out step, and a slice step.

(Bring-in step)
Specifically, first, the furnace opening of the reaction vessel 203 is opened, and the seed substrate 5 is placed on the susceptor 208. The seed substrate 5 placed on the susceptor 208 serves as a base (seed) for manufacturing the substrate 10 described later, and is a plate-shaped one made of a single crystal of GaN, which is an example of a nitride semiconductor.

When placing the seed substrate 5 on the susceptor 208, the surface of the seed substrate 5 mounted on the susceptor 208, that is, the main surface (crystal growth surface, base surface) on the side facing the nozzles 249a to 249c. Is the (0001) plane of the GaN crystal, that is, the + C plane (Ga polar plane).

(Crystal growth step)
In this step, after the delivery of the seed substrate 5 into the reaction chamber 201 is completed, the furnace opening is closed, and H 2 gas or H 2 gas or H ₂ gas into the reaction chamber 201 is carried out while heating and exhausting the inside of the reaction chamber 201. Start supplying H ₂ gas and N ₂ gas. Then, in a state where the inside of the reaction chamber 201 reaches a desired treatment temperature and treatment pressure and the atmosphere in the reaction chamber 201 becomes a desired atmosphere, the HCl gas and _NH3 gas are supplied from the gas supply pipes 232a and 232b. Is started, and GaCl gas and _NH3 gas are supplied to the surface of the seed substrate 5, respectively.

As a result, as shown in the cross-sectional view in FIG. 8A, the GaN crystal grows epitaxially on the surface of the seed substrate 5 in the c-axis direction, and the GaN crystal 6 is formed. At this time, by supplying the SiH ₂ Cl ₂ gas, it becomes possible to add Si as an n-type impurity to the GaN crystal 6.

In this step, in order to prevent thermal decomposition of the GaN crystals constituting the seed substrate 5, when the temperature of the seed substrate 5 reaches 500 ° C. or before that, the _NH3 gas into the reaction chamber 201 is charged. It is preferable to start the supply. Further, in order to improve the uniformity of the in-plane film thickness of the GaN crystal 6, it is preferable to carry out this step in a state where the susceptor 208 is rotated.

In this step, the temperature of the zone heaters 207a and 207b is set to, for example, 700 to 900 ° C. in the heater 207a for heating the upstream portion in the reaction chamber 201 including the gas generator 233a, and the reaction including the susceptor 208 is set. The heater 207b for heating the downstream portion of the chamber 201 is preferably set to a temperature of, for example, 1000 to 1200 ° C. As a result, the susceptor 208 is adjusted to a predetermined temperature of 1000 to 1200 ° C. In this step, the internal heater (but not shown) may be used in the off state, but as long as the temperature of the susceptor 208 is in the above-mentioned range of 1000 to 1200 ° C., the temperature control using the internal heater is performed. You may do it.

The following are exemplified as other processing conditions in this step.
Processing pressure: 0.5 to 2 atmospheres Partial pressure of GaCl gas: 0.1 to 20 kPa
Partial pressure of _NH3 gas / Partial pressure of GaCl gas: 1 to 100
_Partial pressure of H2 gas / Partial pressure of GaCl gas: 0-100
Partial pressure of SiH ₂ Cl ₂ gas: 2.5 × 10 ^-5 to 1.3 × 10 ^-3 kPa

Further, when supplying GaCl gas and _NH3 gas to the surface of the seed substrate 5, _N2 gas as a carrier gas may be added from each of the gas supply pipes 232a to 232b. By adding _N2 gas and adjusting the blowout flow rate of the gas supplied from the nozzles 249a to 249b, the distribution of the supply amount of the raw material gas on the surface of the seed substrate 5 is appropriately controlled and uniform over the entire in-plane. It is possible to realize a stable growth rate distribution. A rare gas such as Ar gas or He gas may be added instead of the N ₂ gas.

(Delivery step)
After growing a GaN crystal 6 having a desired thickness on the seed substrate 5, a gas generator is provided while supplying _NH3 gas and _N2 gas into the reaction chamber 201 and exhausting the inside of the reaction chamber 201. _The supply of HCl gas to 233a, the supply of H2 gas into the reaction chamber 201, and the heating by the zone heaters 207a and 207b are stopped, respectively. Then, when the temperature in the reaction chamber 201 drops to 500 ° C. or lower, the supply of NH ₃ gas is stopped, the atmosphere in the reaction chamber 201 is replaced with N ₂ gas, and the pressure is restored to atmospheric pressure. Then, in the reaction chamber 201, for example, a temperature of 200 ° C. or lower, that is, a temperature at which the GaN crystal ingot (seed substrate 5 having the GaN crystal 6 formed on the main surface) can be carried out from the reaction vessel 203. To lower the temperature. After that, the crystal ingot is carried out from the inside of the reaction chamber 201 to the outside.

(Slice step)
Then, by slicing the carried-out crystal ingot in a direction parallel to the growth plane of the GaN crystal 6, for example, one or more substrates 10 can be obtained as shown in FIG. 8 (b).
Since the various compositions and various physical properties of the substrate 10 are as described above, the description thereof will be omitted. This slicing process can be performed using, for example, a wire saw, an electric discharge machine, or the like. The thickness of the substrate 10 is 250 μm or more, for example, about 400 μm. After that, the surface (+ c surface) of the substrate 10 is subjected to a predetermined polishing process to make this surface an epiready mirror surface. The back surface (−c surface) of the substrate 10 is a lap surface or a mirror surface.

(S114: Measurement step)
After the plurality of substrates 10 are manufactured, each of the plurality of substrates 10 is irradiated with light, and the absorption coefficient in the infrared region is measured in each of the plurality of substrates 10. At this time, the absorption coefficient in the infrared region is measured at at least two points or more in the main surface of the substrate 10. At this time, the measurement points in the main surface of the substrate 10 are, for example, 2 points or more and 10 points or less, preferably 3 points or more and 5 points or less. If there is only one measurement point, the difference in absorption coefficient in the main surface of the substrate 10 cannot be obtained. On the other hand, if the number of measurement points exceeds 10, the time required for the measurement step becomes long, and the productivity of the substrate 10 may decrease.

Further, it is preferable to measure the absorption coefficient at least at the center of the main surface of the substrate 10 and a position radially separated from the center of the main surface of the substrate 10 by a predetermined distance. Here, since the GaN crystal 6 is grown while rotating the seed substrate 5 in the substrate manufacturing step S112, the absorption coefficient of the substrate 10 tends to be concentrically equal to the center of the main surface of the substrate 10. Therefore, by measuring the absorption coefficient at least at the center of the main surface of the substrate 10 and at a position radially separated from the center of the main surface of the substrate 10 by a predetermined distance, the distribution of the absorption coefficient in the main surface of the substrate 10 can be obtained. It can be accurately grasped (predicted). The measurement position other than the center of the main surface of the substrate 10 is, for example, a position separated from the center of the main surface of the substrate 10 in the radial direction by a distance of 20% or more and 80% or less with respect to the radius of the substrate 10. ..

(S116: Judgment step)
Next, based on the measured absorption coefficient of the substrate 10, it is determined whether or not the substrate 10 satisfies a predetermined requirement for the absorption coefficient in the infrared region. Specifically, for example, it is determined whether the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the above equation (1). Further, for example, the absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2 cm ^-1 or more and 48 cm ^-1 or less, and the maximum and minimum values of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 are set. Determine if the difference is within 1.0 cm ^-1 . At this time, the above determination is performed for each of the plurality of substrates 10 obtained in the substrate manufacturing step S112.

Next, based on the above determination result, the substrate 10 satisfying the above requirement for the absorption coefficient in the infrared region is selected as a non-defective product from among the plurality of substrates 10, and the substrate 10 not satisfying the above requirement is excluded. As a result, the substrate 10 that can be heated with high accuracy and reproducibility in the step of heating the substrate 10 described later can be selected as a non-defective product, and the heating efficiency in the step of heating the substrate 10 described later can be improved. The substrate 10 that can be made uniform can be selected as a non-defective product.

The absorption coefficient of the substrate 10 at a wavelength of 2 μm is 1.2 cm ^-1 or more and 24 cm ^-1 or less, and the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is. It may be determined whether or not it is within 0.5 cm ^-1 , and among the plurality of substrates 10, the substrate 10 that satisfies the above requirements for the absorption coefficient in the infrared region may be selected as the best product.

As a result, as shown in FIG. 1, the substrate 10 of the present embodiment is manufactured.

Hereinafter, the semiconductor laminate 1 and the semiconductor device 2 are manufactured using the substrate 10 selected as a non-defective product (or the best product). In the following steps, as at least one step, the substrate 10 is irradiated with at least infrared rays to heat the substrate 10. Examples of the step of heating the substrate 10 in the present embodiment include a semiconductor layer forming step S120, an activation annealing step S130, a protective film forming step S143, and an ohmic alloy step S146.

(S120: Semiconductor layer forming step)
Next, for example, by the organic metal vapor phase growth method (MOVPE: Metalorganic Vapor Phase Epitaxy), the substrate 10 is irradiated with at least infrared rays, and the semiconductor layer 20 is epitaxially grown on the substrate 10.

At this time, if the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled accurately. Further, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, the crystallinity, thickness, concentration of various impurities, and the like of the semiconductor layer 20 can be controlled with high accuracy, and can be made uniform in the main surface of the substrate 10.

Specifically, for example, the semiconductor layer 20 of the present embodiment is formed by the following procedure.

First, the substrate 10 is carried into the processing chamber of the MOVPE apparatus (not shown).

At this time, as shown in FIGS. 9A and 9B, the substrate 10 is placed on the holding member 300. The holding member 300 has, for example, three convex portions 300p, and is configured to hold the substrate 10 by the three convex portions 300p. As a result, when the substrate 10 is heated, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays instead of transferring heat from the holding member 300 to the substrate 10. Here, when the substrate 10 is heated by heat transfer from a plate-shaped holding member (or when heat transfer is performed in combination), the substrate 10 is placed on the surface thereof depending on the back surface state of the substrate 10 and the front surface state of the holding member. It becomes difficult to heat uniformly over the entire area. Further, the substrate 10 may be warped as the substrate 10 is heated, and the contact condition between the substrate 10 and the holding member may gradually change. Therefore, the heating conditions of the substrate 10 may become non-uniform over the entire in-plane area. On the other hand, in the present embodiment, such a problem is solved by using the holding member 300 as described above and heating the substrate 10 mainly by irradiating the substrate 10 with infrared rays. The substrate 10 can be heated stably and uniformly in the main surface.

In order to reduce the influence of heat transfer, the convex portion so that the contact area between the convex portion 300p and the substrate 10 is 5% or less, preferably 3% or less of the supported surface of the substrate 10. It is preferable to properly select the shape and dimensions of 300p.

After the substrate 10 is placed on the holding member 300, hydrogen gas and NH ₃ gas (further N ₂ gas) are supplied to the processing chamber of the MOVPE apparatus, and the substrate 10 is supplied from a predetermined heating source (for example, a lamp heater). The substrate 10 is heated by irradiating it with infrared rays. When the temperature of the substrate 10 reaches a predetermined growth temperature (for example, 1000 ° C. or higher and 1100 ° C. or lower), for example, trimethylgallium (TMG) as a group III organometallic raw material and _NH3 gas as a group V raw material are added to the substrate 10. Supply to. At the same time, for example, _SiH4 gas is supplied to the substrate 10 as an n-type impurity raw material. As a result, the base n-type semiconductor layer 21 as the n-type GaN layer is epitaxially grown on the substrate 10.

Next, the drift layer 22 as an n-type GaN layer containing an n-type impurity having a lower concentration than that of the base n-type semiconductor layer 21 is epitaxially grown on the base n-type semiconductor layer 21.

Next, the first p-type semiconductor layer 23 as the p-type GaN layer is epitaxially grown on the drift layer 22. At this time, instead of the n-type impurity raw material, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) is supplied to the substrate 10 as a p-type impurity raw material.

Next, the second p-type semiconductor layer 24 as a p-type GaN layer containing p-type impurities having a higher concentration than that of the first p-type semiconductor layer 23 is epitaxially grown on the first p-type semiconductor layer 23.

When the growth of the second p-type semiconductor layer 24 is completed, the supply of the group III organometallic raw material and the heating of the substrate 10 are stopped. Then, when the temperature of the substrate 10 becomes 500 ° C. or lower, the supply of the group V raw material is stopped. After that, the atmosphere in the processing chamber of the MOVPE apparatus is replaced with _N2 gas to return to atmospheric pressure, the temperature in the processing chamber is lowered to a temperature at which the substrate can be carried out, and then the grown substrate 10 is carried out from the processing chamber. ..

As a result, as shown in FIG. 6, the semiconductor laminate 1 of the present embodiment is manufactured.

(S130: Activation annealing step)
Next, for example, the semiconductor laminate 1 is annealed by irradiating the substrate 10 with at least infrared rays in an atmosphere of an inert gas using a predetermined heat treatment device (not shown). As a result, hydrogen (H) bonded to the p-type impurities is desorbed from each of the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24, and the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24 are separated from each other. It activates (electrically) the p-type impurities in each.

At this time, at least the drift layer 22 of the semiconductor layers 20 is difficult to be heated because the free electron concentration is low and the absorption coefficient in the infrared region is low. On the other hand, in the present embodiment, at least the substrate 10 is heated by irradiation with infrared rays from a predetermined heating source (for example, a lamp heater) to heat the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24.

Further, at this time, if the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled accurately. .. Further, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, the activation degree (activation rate, free hole concentration) of the p-type impurities in each of the first p-type semiconductor layer 23 and the second p-type semiconductor layer 24 is accurately controlled, and the inside of the main surface of the substrate 10 is controlled. Can be made uniform with.

At this time, the holding member 300 shown in FIGS. 9A and 9B is used to heat the substrate 10. As a result, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays instead of transferring heat from the holding member 300 to the substrate 10. As a result, the substrate 10 can be heated stably and uniformly in the main surface.

At this time, the atmosphere of the inert gas is set to be an atmosphere containing a rare gas such as _N2 gas or argon (Ar) gas. Further, the temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 500 ° C. or higher and 700 ° C. or lower, and the annealing time is set to, for example, 3 minutes or longer and 30 minutes or lower.

(S140: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S140 for manufacturing the semiconductor device 2 using the above-mentioned semiconductor laminate 1 is performed. The semiconductor device manufacturing step S140 of the present embodiment is, for example, a mesa forming step S141, a first p-type electrode forming step S142, a protective film forming step S143, a second p-type electrode forming step S144, and an n-type electrode forming step S145. And the ohmic alloy step S146.

(S141: Mesa forming step)
Next, in a state where a predetermined resist pattern (not shown) is formed on the second p-type semiconductor layer 24, for example, by a reactive ion etching method (RIE), the second p-type semiconductor layer 24, the second A part of the 1p type semiconductor layer 23 and the drift layer 22 is etched.

As a result, as shown in FIG. 10A, the mesa structure 29 is formed on the second p-type semiconductor layer 24, the first p-type semiconductor layer 23, and the drift layer 22. After that, the resist pattern is removed.

(S142: First p-type electrode forming step)
Next, a palladium (Pd) / nickel (Ni) film is formed by, for example, a sputtering method so as to cover the surfaces of the mesa structure 29 and the drift layer 22, and the Pd / Ni film is patterned into a predetermined shape by photolithography.

As a result, as shown in FIG. 10B, the first p-type electrode (first anode) 320 is formed on the upper surface of the mesa structure 29, that is, on the second p-type semiconductor layer 24.

(S143: Protective film forming step)
Next, an SOG (Spin On Glass) film is formed so as to cover the surfaces of the mesa structure 29 and the drift layer 22 by, for example, a spin coating method. At this time, the thickness of the SOG film is set to, for example, 100 nm or more and 500 nm or less.

Next, for example, the semiconductor laminate 1 is annealed by irradiating the substrate 10 with at least infrared rays in an atmosphere of an inert gas such as _N2 gas by a predetermined heat treatment device (not shown). As a result, the organic solvent component is volatilized from the SOG film, and the SOG film is cured.

At this time, since the absorption coefficient of the SOG film in the infrared region is low, the SOG film itself is difficult to be heated by irradiation with infrared rays. On the other hand, in the present embodiment, at least the substrate 10 is heated by irradiation with infrared rays from a predetermined heating source (for example, a lamp heater) to heat the SOG film.

Further, at this time, if the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled accurately. .. Further, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, the film quality of the SOG film (the degree of volatilization of the solvent from the SOG film, the degree of curing, etc.) can be accurately controlled and made uniform in the main surface of the substrate 10.

At this time, the holding member 300 shown in FIGS. 9A and 9B is used to heat the substrate 10. As a result, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays instead of transferring heat from the holding member 300 to the substrate 10. As a result, the substrate 10 can be heated stably and uniformly in the main surface.

At this time, the atmosphere of the inert gas is set to be an atmosphere containing a rare gas such as _N2 gas or Ar gas. Further, the temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 200 ° C. or higher and 500 ° C. or lower, and the annealing time is set to, for example, 30 minutes or longer and 3 hours or lower.

After forming the SOG film, a silicon oxide film (SiO ₂ film) is formed on the SOG film by, for example, a sputtering method. The thickness of the SiO ₂ film is, for example, 100 nm or more and 500 nm or less. After forming the SiO ₂ film on the SOG film, these oxide films are patterned into a predetermined shape by photolithography.

As a result, as shown in FIG. 11A, the surface of the drift layer 22 outside the mesa structure 29, the side surface of the mesa structure 29, and a part of the surface of the second p-type semiconductor layer 24 (the upper surface of the mesa structure 29). A protective film 40 is formed so as to cover the surrounding area).

(S144: Second p-type electrode forming step)
Next, a Ti / Al film is formed by, for example, a sputtering method so as to cover the first p-type electrode 32 and the protective film 40 in the opening of the protective film 40, and the Ti / Al film is patterned into a predetermined shape by photolithography. ..

As a result, as shown in FIG. 11B, the mesa structure 29 is in contact with the first p-type electrode 32 within the opening of the protective film 40 and extends outward from the first p-type electrode 32 on the protective film 40. A second p-type electrode (p-type electrode pad) 34 is formed so as to cover it. Specifically, the second p-type electrode 34 is a part of the surface of the drift layer 22 outside the mesa structure 29, the side surface of the mesa structure 29, and the mesa structure 29 when the semiconductor laminate 1 is viewed from above. It is formed so as to overlap the upper surface. As a result, it is possible to suppress the concentration of the electric field near the end of the first p-type electrode 32 and the pn junction interface near the side surface of the mesa structure 29.

(S145: n-type electrode forming step)
Next, a Ti / Al film is formed on the back surface side of the substrate 10 by, for example, a sputtering method, and the Ti / Al film is patterned into a predetermined shape by photolithography. As a result, the n-type electrode 36 is formed on the back surface side of the substrate 10.

(S146: Ohmic alloy process)
Next, for example, the semiconductor laminate 1 is annealed by irradiating the semiconductor laminate 1 with at least infrared rays in an atmosphere of an inert gas by a predetermined heat treatment device (not shown). As a result, the adhesion of each metal film constituting each of the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36 is improved, and the contact resistance of the first p-type electrode 32 with respect to the second p-type semiconductor layer 24 is improved. , The contact resistance of the second p-type electrode 34 with respect to the first p-type electrode 32 and the contact resistance of the n-type electrode 36 with respect to the substrate 10 are reduced.

At this time, the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36 are directly heated by irradiation with infrared rays from a predetermined heating source (for example, a lamp heater). Further, the substrate 10 is heated by irradiation with infrared rays, and the first p-type electrode 32, the second p-type electrode 34, and the n-type electrode 36 are heated.

Further, at this time, if the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled accurately. .. Further, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, the contact resistance of the first p-type electrode 32 with respect to the second p-type semiconductor layer 24, the contact resistance of the second p-type electrode 34 with respect to the first p-type electrode 32, and the contact resistance of the n-type electrode 36 with respect to the substrate 10 are the main components of the substrate 10. Can be uniform in the plane.

At this time, the holding member 300 shown in FIGS. 9A and 9B is used to heat the substrate 10. As a result, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays instead of transferring heat from the holding member 300 to the substrate 10. As a result, the substrate 10 can be heated stably and uniformly in the main surface.

At this time, the atmosphere of the inert gas is set to be an atmosphere containing a rare gas such as _N2 gas or Ar gas. Further, the temperature of the substrate 10 (semiconductor laminate 1) is set to, for example, 500 ° C. or higher and 700 ° C. or lower, and the annealing time is set to, for example, 30 minutes or more and 3 hours or lower.

After that, the semiconductor laminate 1 is diced and cut into chips having a predetermined size.

As a result, as shown in FIG. 12, the semiconductor device 2 of the present embodiment is manufactured.

(4) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) The substrate 10 manufactured by the manufacturing method of the present embodiment has a small crystal strain and contains almost no impurities other than O and n-type impurities (for example, impurities compensating for n-type impurities). It has become. As a result, in the substrate 10 of the present embodiment, the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the above equation (1) (α = nKλ ^a ) using a predetermined constant K and constant a. be able to. As a result, the heating conditions in the step of irradiating the substrate 10 with at least infrared rays to heat the substrate 10 can be easily set, and the substrate 10 can be heated with high accuracy and reproducibility.

For reference, in a GaN crystal manufactured by a conventional manufacturing method, it is difficult to accurately approximate the absorption coefficient α by using the above-defined constant K and the above-mentioned constant a by the above equation (1).

Here, FIG. 5B is a diagram comparing the relationship between the free electron concentration and the absorption coefficient at a wavelength of 2 μm. FIG. 5B shows not only the absorption coefficient of the GaN crystal produced by the production method of the present embodiment but also the absorption coefficient of the GaN crystal described in the papers (A) to (D).
Paper (A): A. S. Barker Physical Review B 7 (1973) p743 Fig. 8
Paper (B): P.M. Perlin, Physics Review Letter
75 (1995) p296 Fig. Estimated from a curve of 1 0.3 GPa.
Paper (C): G.M. Bentoumi, Medical Science Engineering B50 (1997) p142-147 Fig. 1
Paper (D): S. Pourowski, J.M. Crystal Growth 189-190 (1998) p. 153-158 Fig. 3 However, T = 12K

As shown in FIG. 5 (b), the absorption coefficient α of the conventional GaN crystals described in the papers (A) to (D) is larger than the absorption coefficient α of the GaN crystal produced by the production method of the present embodiment. rice field. Further, the slope of the absorption coefficient α in the conventional GaN crystal was different from the slope of the absorption coefficient α in the GaN crystal manufactured by the manufacturing method of the present embodiment. In the papers (A) and (C), it seems that the slope of the absorption coefficient α changes as the free electron concentration n increases. Therefore, in the conventional GaN crystals described in the papers (A) to (D), it is difficult to accurately approximate the absorption coefficient α by using the above-defined constant K and the above-mentioned constant a by the above equation (1). there were. Specifically, for example, the constant K may be higher than the above-specified range, or the constant a may be a value other than 3.

This is considered to be due to the following reasons. It is considered that a large crystal strain was generated in the conventional GaN crystal due to the manufacturing method thereof. When crystal distortion occurs in a GaN crystal, many dislocations occur in the GaN crystal. Therefore, in the conventional GaN crystal, dislocation scattering occurs, and it is considered that the absorption coefficient α becomes large or varies due to the dislocation scattering. Alternatively, it is considered that the concentration of O mixed unintentionally was high in the GaN crystal manufactured by the conventional manufacturing method. When O is mixed in a GaN crystal at a high concentration, the lattice constants a and c of the GaN crystal become large (reference: Fris G. Van de Walle, Physical Review B vol. 68, 165209 (2003)). Therefore, in the conventional GaN crystal, it is considered that a local lattice mismatch occurs between the portion contaminated by O and the portion having a relatively high purity, and crystal strain occurs in the GaN crystal. As a result, in the conventional GaN crystal, it is considered that the absorption coefficient α becomes large or varies. Alternatively, it is considered that in the GaN crystal produced by the conventional production method, the compensating impurities compensating for the n-type impurities were unintentionally mixed, and the concentration of the compensating impurities was high. When the concentration of the compensating impurity is high, a high concentration of n-type impurities is required in order to obtain a predetermined free electron concentration. Therefore, it is considered that in the conventional GaN crystal, the total impurity concentration including the compensating impurity and the n-type impurity is high, and the crystal strain is large. As a result, in the conventional GaN crystal, it is considered that the absorption coefficient α becomes large or varies. It has been confirmed that the GaN free-standing substrate that actually contains O and has a distorted lattice has a higher absorption coefficient α (lower mobility) than the substrate 10 of the present embodiment having the same free electron concentration. ..

For this reason, in the conventional GaN crystal, it is difficult to accurately approximate the absorption coefficient α by using the above-mentioned constant K and the constant a by the above equation (1). That is, in the conventional GaN crystal, it is difficult to accurately design the absorption coefficient based on the concentration n of free electrons. For this reason, in the conventional substrate made of GaN crystals, in the step of irradiating the substrate with at least infrared rays to heat the substrate, the heating efficiency tends to vary depending on the substrate, and it is difficult to control the temperature of the substrate. As a result, the reproducibility of the temperature of each substrate may be low.

On the other hand, the substrate 10 manufactured by the manufacturing method of the present embodiment has a small crystal strain and is in a state of containing almost no impurities other than O and n-type impurities. The absorption coefficient of the substrate 10 of the present embodiment is less affected by scattering (dislocation scattering) caused by crystal strain, and mainly depends on ionized impurity scattering. As a result, the variation in the absorption coefficient α of the substrate 10 can be reduced, and the absorption coefficient α of the substrate 10 can be approximated by the above equation (1) using a predetermined constant K and a constant a. Since the absorption coefficient α of the substrate 10 can be approximated by the above equation (1), the absorption coefficient of the substrate 10 is accurately designed based on the concentration n of free electrons generated by doping the n-type impurity into the substrate 10. can do. By accurately designing the absorption coefficient of the substrate 10 based on the concentration n of free electrons, it is possible to easily set the heating conditions in the step of irradiating the substrate 10 with at least infrared rays to heat the substrate 10. The temperature of the substrate 10 can be controlled with high accuracy. As a result, the temperature reproducibility of each substrate 10 can be improved. In this way, in the present embodiment, the substrate 10 can be heated with high accuracy and reproducibility.

(B) In the present embodiment, by growing the semiconductor layer 30 on the substrate 10 having a small crystal strain, the crystal strain can be reduced also in the semiconductor layer 30, and the crystallinity of the semiconductor layer 30 can be improved. can. Further, by accurately controlling the temperature of the substrate 10, the crystallinity, thickness, concentration of various impurities, and the like of the semiconductor layer 20 and the like growing on the substrate 10 can be controlled with high accuracy. As a result, the semiconductor layer 2 can be manufactured with high quality, and the characteristics of each semiconductor device 2 can be made uniform.

For example, when the semiconductor device 2 is a light emitting device such as a light emitting diode or a laser diode, the light emitting efficiency of the semiconductor device 2 as the light emitting element can be improved by reducing the crystal distortion of the light emitting layer. Further, since the amount of indium (In) taken up depends on the growth temperature of the light emitting layer, the composition ratio of In in the light emitting layer can be controlled accurately by controlling the temperature of the substrate 10 with high accuracy. As a result, the emission wavelength of each semiconductor device 2 as a light emitting element can be made uniform.

(C) In the substrate 10 manufactured by the manufacturing method of the present embodiment, the absorption coefficient due to free carrier absorption is smaller than the absorption coefficient of the conventional substrate. Therefore, the resistivity of the substrate 10 of the present embodiment is the conventional substrate. It is lower than the resistivity of.

Here, for reference, in the conventional GaN crystal, as shown in FIG. 5 (b), the mobility (μ) is low because the absorption coefficient due to free carrier absorption at a predetermined free electron concentration is large. Conceivable. Therefore, it is considered that the resistivity (ρ = 1 / enμ) is high in the conventional GaN crystal. As a result, it is considered that the on-resistance was high in the conventional semiconductor device using the substrate made of GaN crystal.

In order to obtain a desired resistivity in a conventional GaN crystal, it is conceivable to increase the concentration of n-type impurities. However, as the concentration of the n-type impurity increases, the mobility tends to decrease. Therefore, in order to obtain the desired resistivity in the conventional GaN crystal, the concentration of the n-type impurity is excessively increased. It needed to be high. Therefore, in the conventional GaN crystal, the crystal strain tends to be large. As a result, in the conventional GaN crystal, the absorption coefficient α tends to be large or fluctuate.

On the other hand, in the substrate 10 manufactured by the manufacturing method of the present embodiment, the absorption coefficient due to free carrier absorption is smaller than the absorption coefficient of the conventional substrate. Therefore, the substrate 10 of the present embodiment has a higher absorption coefficient than the conventional substrate. , It is estimated that the mobility is high. As a result, even when the free electron concentration in the substrate 10 of the present embodiment is equal to the free electron concentration in the conventional substrate, the resistivity of the substrate 10 of the present embodiment is higher than the resistivity of the conventional substrate. It's getting low. As a result, the on-resistance of the semiconductor device 2 using the substrate 10 of the present embodiment can be reduced.

Further, in the substrate 10 of the present embodiment, the concentration of n-type impurities for obtaining a desired resistivity can be made lower than the concentration of n-type impurities in the conventional substrate. As a result, the crystal strain can be reduced and the crystallinity of the substrate 10 can be improved. As a result, it is possible to obtain a desired resistivity of the substrate 10 while reducing the variation in the absorption coefficient α of the substrate 10.

(D) By setting the absorption coefficient α of the substrate 10 of the present embodiment to 0.15λ ³ ≦ α, infrared rays can be sufficiently absorbed by the substrate 10 and the substrate 10 can be heated stably. Can be done. Further, by setting Δα ≦ 1.0, in the step of heating the substrate 10, the heating efficiency by irradiation with infrared rays can be made uniform in the main surface of the substrate 10. Thereby, the quality of the semiconductor laminate 1 manufactured by using the substrate 10 can be made uniform in the main surface of the substrate 10. As a result, the quality and yield of the semiconductor device 2 manufactured by using the semiconductor laminate 1 can be improved.

(E) The concentration of intrinsic carriers thermally excited between the bands of the substrate 10 under the temperature condition of 27 ° C. or higher and 1250 ° C. or lower is the free electron generated in the substrate 10 by doping with n-type impurities under the temperature condition of 27 ° C. Is lower than the concentration of. By satisfying this condition, it can be considered that the free carrier concentration of the substrate 10 under a predetermined temperature condition in the step of heating the substrate 10 is substantially equal to the free carrier concentration of the substrate 10 under the temperature condition of room temperature. can. Thereby, it can be considered that the free carrier absorption under a predetermined temperature condition is almost equal to the free carrier absorption at room temperature. That is, as described above, when the absorption coefficient in the infrared region of the substrate 10 satisfies the above-mentioned predetermined requirement at room temperature, the absorption coefficient in the infrared region of the substrate 10 substantially satisfies the above-mentioned predetermined requirement even under a predetermined temperature condition. It can be considered to be maintained.

(F) The concentration of free electrons generated in the substrate 10 by doping with n-type impurities is 1 × 10 ¹⁸ cm ^-3 or more under the temperature condition of 27 ° C., and the free electron concentration in the main surface of the substrate 10. The difference between the maximum and minimum values of is within 8.3 × 10 ¹⁷ cm ^-3 . As a result, the absorption coefficient of the substrate 10 at a wavelength of 2 μm can be set to 1.2 cm ^-1 or more, and the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the substrate 10 is 1. It can be within 0.0 cm ^-1 .

(G) The concentration of O in the substrate 10 is 1/10 times or less the total concentration of Si and Ge in the substrate 10. Thereby, the concentration of the n-type impurity in the substrate 10 can be controlled by the total concentration of Si and Ge, which is relatively easy to control the addition amount. By making it possible to easily control the concentration of n-type impurities in the substrate 10, the free electron concentration n in the substrate 10 can be accurately controlled so as to satisfy a predetermined requirement, and the concentration in the main surface of the substrate 10 can be controlled. The difference Δn between the maximum value and the minimum value of the free electron concentration can be accurately controlled so as to satisfy a predetermined requirement. As a result, the absorption coefficient of the substrate 10 can be adjusted accurately and with good reproducibility, and the absorption coefficient in the main surface of the substrate 10 can be stably made uniform.

<Second Embodiment of the present invention>
In the above-described embodiment, the case where the semiconductor laminate 1 is configured to manufacture the semiconductor device 2 as a pn junction diode has been described, but as in the second embodiment below, the semiconductor laminate 1 is other than the other. Devices may be configured to manufacture. In this embodiment, only the elements different from the above-described embodiment will be described.

(1) Semiconductor Laminate The semiconductor laminate 1 according to the present embodiment will be described with reference to FIG. 13 (a). FIG. 13A is a schematic cross-sectional view showing the semiconductor laminate 1 according to the present embodiment.

As shown in FIG. 13A, the semiconductor laminate 1 of the present embodiment is configured as an intermediate used, for example, when manufacturing a semiconductor device 2 as a Schottky barrier diode (SBD). The semiconductor laminate 1 has, for example, a substrate 10 and a semiconductor layer 20. Further, the semiconductor layer 20 has, for example, a base n-type semiconductor layer 21 and a drift layer 22, and does not have a p-type semiconductor layer. The substrate 10, the base n-type semiconductor layer 21, and the drift layer 22 are the same as the substrate 10, the base n-type semiconductor layer 21, and the drift layer 22 of the first embodiment, respectively. However, the drift layer 22 has a portion to be injected with p-type impurities (not shown).

(2) Manufacturing Method of Semiconductor Laminate and Manufacturing Method of Semiconductor Device Next, the manufacturing method of the semiconductor laminate 1 and the manufacturing method of the semiconductor device 2 according to the present embodiment will be described with reference to FIGS. 13 to 15. 13 (b), 14 (a), (b), and 15 (a) are schematic cross-sectional views showing a manufacturing process of a semiconductor device, and FIG. 15 (b) is a semiconductor device according to the present embodiment. 2 is a schematic cross-sectional view showing 2.

(S210 to S220: Substrate preparation process and semiconductor layer forming process)
As shown in FIG. 13A, the semiconductor laminate 1 is manufactured in the same manner as in the substrate preparation step S110 to the semiconductor layer forming step S120 of the first embodiment except that the p-type semiconductor layer is not formed.

(S240: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S240 for manufacturing the semiconductor device 2 using the above-mentioned semiconductor laminate 1 is performed. The semiconductor device manufacturing step S240 of the present embodiment includes, for example, an ion injection step S241, an activation annealing step S242, a protective film forming step S243, a p-type electrode forming step S244, an n-type electrode forming step S245, and an ohmic. It has an alloy step S246.

(S2411: Ion implantation step)
First, as shown in FIG. 13B, a surface-side cap layer 52 made of a silicon nitride film (SiNx film) or an aluminum nitride film (AlN film) is formed on the semiconductor layer 20 by, for example, a sputtering method. As a result, damage to the drift layer 22 can be suppressed when ions are implanted into the drift layer 22, and nitrogen (N) escape from the drift layer 22 is suppressed in the activation annealing step S242 described later. can do. At this time, the thickness of the surface side cap layer 52 is set to, for example, 20 nm or more and 50 nm or less.

After the surface side cap layer 52 is formed, a predetermined resist pattern 54 is formed on the surface side cap layer 52 as shown in FIG. 14 (a). At this time, in the resist pattern 54, an opening (not shown) is formed at the position of the injected portion of the drift layer 22 in a plan view. In this embodiment, the opening of the resist pattern 54 is formed into a ring shape, for example, in a plan view.

After the resist pattern 54 is formed, the p-type impurity is ion-implanted into the implanted portion of the drift layer 22 through the opening of the resist pattern 54. As a result, a p-type region 25 containing p-type impurities is formed in the drift layer 22 (for example, a part of the surface side region of the drift layer 22). The p-shaped region 25 has a ring shape in a plan view, for example.

At this time, the p-type impurity to be ion-implanted is selected from the group consisting of, for example, Mg, C, iron (Fe), beryllium (Be), zinc (Zn), vanadium (V), and antimony (Sb). At least one. At this time, the acceleration voltage at the time of ion implantation of the p-type impurity is, for example, 10 keV or more and 100 keV or less, and the dose amount is, for example, 1 × 10 ¹³ cm ^-2 or more and 1 × 10 ¹⁵ cm ^-2 or less. .. As a result, the maximum value of the p-type impurity concentration in the p-type region 25 becomes, for example, 1 × 10 ¹⁸ at · cm ^-3 or more and 1 × 10 ²⁰ at · cm ^-3 or less, and p from the surface of the drift layer 22. The depth of the mold region 25 is, for example, 50 nm or more and 300 nm or less.

After ion implantation of the p-type impurity, the resist pattern 54 is removed.

(S242: Activation annealing step)
Next, as shown in FIG. 14B, a back surface side cap layer 56 made of a SiNx film or an AlN film is formed on the back surface side of the substrate 10 by, for example, a sputtering method. As a result, nitrogen (N) escape from the substrate 10 can be suppressed in the activation annealing step S242 described later. At this time, the thickness of the back surface side cap layer 56 is set to, for example, 20 nm or more and 50 nm or less.

After the back surface side cap layer 56 is formed, the semiconductor laminate 1 is annealed by irradiating the substrate 10 with at least infrared rays in an atmosphere of an inert gas, for example, by a predetermined heat treatment device (not shown). As a result, the crystal damage received by the semiconductor layer 20 in the ion implantation step S241 is recovered, and the p-type impurities in the p-type region 25 are incorporated into the crystal lattice and activated (electrically).

At this time, at least the drift layer 22 of the semiconductor layers 20 is difficult to be heated because the free electron concentration is low and the absorption coefficient in the infrared region is low. On the other hand, in the present embodiment, at least the substrate 10 is heated by irradiation with infrared rays from a predetermined heating source (for example, a lamp heater) to heat the semiconductor layer 20.

Further, at this time, if the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the substrate 10 can be stably heated by irradiating the substrate 10 with infrared rays, and the temperature of the substrate 10 can be controlled accurately. .. Further, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, the activation degree (activation rate, free hole concentration) of the p-type impurities in the p-type region 25 can be accurately controlled and made uniform in the main surface of the substrate 10.

At this time, the holding member 300 shown in FIGS. 9A and 9B is used to heat the substrate 10. As a result, the substrate 10 can be heated mainly by irradiating the substrate 10 with infrared rays instead of transferring heat from the holding member 300 to the substrate 10. As a result, the substrate 10 can be heated stably and uniformly in the main surface.

Further, at this time, in the annealing treatment, for example, the temperature rise from the start temperature to the annealing temperature is performed in a time within the range of 3 to 30 seconds, and the holding at the annealing temperature is performed for a time within the range of 20 seconds to 3 minutes. After that, the temperature is lowered from the annealing temperature to the stop temperature within a time range of 1 to 10 minutes, which is the treatment procedure and treatment conditions. The stop temperature and the start temperature are set to temperatures in the range of, for example, 500 to 800 ° C., respectively. The annealing temperature is, for example, a temperature within the range of 1100 ° C. or higher and 1250 ° C. or lower. The atmosphere of the inert gas for the annealing treatment is an atmosphere containing a rare gas such as _N2 gas or Ar gas, and the pressure thereof is, for example, a pressure in the range of 100 to 250 kPa.

When the annealing treatment is completed, the front surface side cap layer 52 and the back surface side cap layer 56 are removed with a predetermined solvent as shown in FIG. 15 (a).

(S244: p-type electrode forming step)
Next, a Pd / Ni film is formed so as to cover the semiconductor layer 20 by, for example, a sputtering method, and the Pd / Ni film is patterned into a predetermined shape by photolithography. As a result, the p-type electrode 31 is formed so that the outer peripheral portion of the p-type electrode 31 overlaps with the p-type region 25 in a plan view.

(S145: n-type electrode forming step)
Next, a Ti / Al film is formed on the back surface side of the substrate 10 by, for example, a sputtering method, and the Ti / Al film is patterned into a predetermined shape by photolithography. As a result, the n-type electrode 36 is formed on the back surface side of the substrate 10.

(S246: Ohmic alloy process)
Next, the ohmic alloy step S246 is performed in the same manner as in the ohmic alloy step S146 of the first embodiment.

After that, the semiconductor laminate 1 is diced and cut into chips having a predetermined size.

As a result, as shown in FIG. 15B, the semiconductor device 2 of the present embodiment is manufactured. In the semiconductor device 2, since the p-type region 25 as a guard ring is formed on the surface side of the drift layer 22, the electric field concentration around the p-type electrode 31 can be suppressed. As a result, the withstand voltage of the semiconductor device 2 can be improved.

(3) Effects obtained by the present embodiment In the present embodiment, in the activation annealing step S242 after ion implantation, the semiconductor layer 20 is heated by heating the substrate 10 that satisfies the above requirements for the absorption coefficient in the infrared region. , Activates p-type impurities in the p-type region 25.

Here, the activation annealing step after ion implantation is often performed at a high temperature and in a short time in order to activate p-type impurities while suppressing crystal damage. Therefore, if it is difficult to design the absorption coefficient based on the free electron concentration n as in the case of a conventional substrate made of GaN crystals, the heating efficiency may vary greatly depending on the substrate. As a result, there is a possibility that the degree of activation of p-type impurities varies from substrate to substrate, and the crystal damage (for example, N omission) of the semiconductor layer varies from substrate to substrate. Further, if the heating efficiency varies in the main surface of the substrate, the activation degree of p-type impurities varies in the main surface of the substrate, and the crystal damage of the semiconductor layer does not occur in the main surface of the substrate. It may occur evenly.

On the other hand, in the present embodiment, the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, so that the temperature of the substrate 10 heated by the irradiation of infrared rays can be accurately measured in the activation annealing step S242 after ion implantation. It can be controlled and the reproducibility of the temperature of each substrate 10 can be improved. As a result, it is possible to suppress variations in the degree of activation of p-type impurities for each substrate. Further, it is possible to suppress the variation in the crystal damage of the semiconductor layer for each substrate, and it is possible to easily suppress the crystal damage of the semiconductor layer itself by forming an appropriate cap layer. Further, when the substrate 10 satisfies the above requirements for the absorption coefficient in the infrared region, the heating efficiency due to the irradiation of infrared rays can be made uniform in the main surface of the substrate 10. As a result, in the activation annealing step S242, the activation degree of the p-type impurities can be made uniform in the main surface of the substrate 10 (semiconductor layer 20), and the occurrence of local crystal damage in the semiconductor layer 20 can be suppressed. can do. As a result, the quality and yield of the semiconductor device 2 manufactured by using the semiconductor laminate 1 can be improved.

<Other embodiments>
The embodiment of the present invention has been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof.

In the above-described embodiment, the case where the substrate 10 and the semiconductor layer 20 are each made of GaN has been described, but the substrate 10 and the semiconductor layer 20 are not limited to GaN, and are, for example, AlN, aluminum gallium nitride (AlGaN), and nitrided. Group III nitride semiconductors such as indium (InN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), that is, Al _x In _y Ga _1-x-y N (0 ≦ x ≦ 1, 0 ≦ y). It may be made of a group III nitride semiconductor represented by the composition formula of ≦ 1, 0 ≦ x + y ≦ 1).

In the above embodiment, the case where the semiconductor layer 20 is made of the same group III nitride semiconductor (GaN) as the substrate 10 has been described, but the semiconductor layer 20 is made of a group III nitride semiconductor different from the substrate 10. May be good.

In the above-described embodiment, the case where the substrate 10 is manufactured by using the seed substrate 5 made of a GaN single crystal in the substrate manufacturing step S112 has been described, but the substrate 10 may be manufactured by the following method. For example, a GaN layer provided on a dissimilar substrate such as a sapphire substrate is used as an underlayer, and a crystal ingot in which a GaN layer is thickly grown via a nanomask or the like is peeled from the dissimilar substrate, and a plurality of substrates 10 are peeled from the crystal ingot. May be cut out.

In the above-described embodiment, the case where the semiconductor layer 20 is formed by the MOVPE method in the semiconductor layer forming step S120 has been described, but other vapor phase growth methods such as the HVPE method and liquids such as the flux method and the amonothermal method have been described. The semiconductor layer 20 may be formed by the phase growth method.

In the first embodiment described above, the semiconductor device 2 is a pn junction diode, and in the second embodiment described above, the case where the semiconductor device 2 is an SBD has been described. However, the semiconductor device 2 is a substrate containing an n-type impurity. If 10 is used, it may be configured as another device. For example, the semiconductor device 2 may be a light emitting diode, a laser diode, a junction barrier Schottky diode (JBS), a bipolar transistor, or the like.

In the above-mentioned second embodiment, the case where the p-type impurity is ion-implanted into the semiconductor layer 20 in the ion implantation step S241 has been described, but other impurities such as the n-type impurity are ion-implanted into the semiconductor layer 20 as needed. You may.

<Preferable Aspect of the Present Invention>
Hereinafter, preferred embodiments of the present invention will be described.

(Appendix 1)
A nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities.
The wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate at 27 ° C is α (cm ^-1 ), the free electron concentration in the nitride crystal substrate is n (cm ^-3 ), and K and a are constants, respectively. The absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is a nitride crystal substrate approximated by the following equation (1).
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

(Appendix 2)
The nitride crystal substrate according to Appendix 1, wherein the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following equation (1)''.
α = 2.2 × ^10-19 nλ ³ ... (1)''

(Appendix 3)
When the difference between the maximum value and the minimum value of the absorption coefficient α in the main surface of the nitride crystal substrate is Δα, the absorption coefficient α and the Δα are obtained in a wavelength range of at least 1 μm or more and 3.3 μm or less. The nitride crystal substrate according to Appendix 1 or 2, which satisfies the following formulas (2) and (3).
α ≧ 0.15λ ³ ... (2)
Δα ≦ 1.0 ・ ・ ・ (3)

(Appendix 4)
A nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities.
The absorption coefficient of the nitride crystal substrate at a wavelength of 2 μm is 1.2 cm ^-1 or more.
A nitride crystal substrate in which the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is within 1.0 cm ^-1 .

(Appendix 5)
The concentration of intrinsic carriers thermally excited between the bands of the nitride crystal substrate under the temperature condition of 27 ° C. or higher and 1250 ° C. or lower is determined in the nitride crystal substrate by doping with the n-type impurity under the temperature condition of 27 ° C. The nitride crystal substrate according to any one of Supplementary note 1 to 4, which is lower than the concentration of free electrons generated in.

(Appendix 6)
The concentration of free electrons generated in the nitride crystal substrate by doping with the n-type impurity is 1 × 10 ¹⁸ cm ^-3 or more under the temperature condition of 27 ° C.
The difference between the maximum value and the minimum value of the free electron concentration in the main surface of the nitride crystal substrate is described in any one of Supplementary note 1 to 5 within 8.3 × 10 ¹⁷ cm ^-3 . Nitride crystal substrate.

(Appendix 7)
The concentration of the n-type impurity in the nitride crystal substrate is 1.0 × 10 ¹⁸ at · cm ^-3 or more.
The difference between the maximum value and the minimum value of the concentration of the n-type impurity in the main surface of the nitride crystal substrate is 8.3 × 10 ¹⁷ at · cm ^-3 or less. The nitride crystal substrate according to one.

(Appendix 8)
The nitride according to any one of Supplementary note 1 to 7, wherein the concentration of oxygen in the nitride crystal substrate is 1/10 times or less the total concentration of silicon and germanium in the nitride crystal substrate. Crystal substrate.

(Appendix 9)
The concentration of oxygen in the nitride crystal substrate is less than 1 × 10 ¹⁷ at · cm ^-3 .
The nitride crystal substrate according to Appendix 8, wherein the total concentration of silicon and germanium in the nitride crystal substrate is 1 × 10 ¹⁸ at · cm ^-3 or more.

(Appendix 10)
A nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities,
A semiconductor layer provided on the nitride crystal substrate and made of a group III nitride semiconductor,
Have,
The wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate at 27 ° C is α (cm ^-1 ), the free electron concentration in the nitride crystal substrate is n (cm ^-3 ), and K and a are constants, respectively. The absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is a semiconductor laminate approximated by the following equation (1).
α = nKλ ^a ... (1) (However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

(Appendix 11)
A nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities,
A semiconductor layer provided on the nitride crystal substrate and made of a group III nitride semiconductor,
Have,
The absorption coefficient of the nitride crystal substrate at a wavelength of 2 μm is 1.2 cm ^-1 or more.
A semiconductor laminate in which the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface of the nitride crystal substrate is within 1.0 cm ^-1 .

(Appendix 12)
The semiconductor laminate according to Appendix 10 or 11, wherein the reflectance of the surface of the semiconductor layer is 5% or more and 30% or less in a wavelength range of at least 1 μm or more and 3.3 μm or less.

(Appendix 13)
The semiconductor laminate according to any one of Supplementary note 10 to 12, wherein the semiconductor layer is provided on the nitride crystal substrate and has a p-type semiconductor layer containing p-type impurities.

(Appendix 14)
The semiconductor laminate according to any one of Supplementary note 10 to 12, wherein the semiconductor layer has a portion to be injected with impurities.

(Appendix 15)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
In the step of preparing the nitride crystal substrate,
As the nitride crystal substrate, the wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate at 27 ° C. is α (cm ^-1 ), and the free electron concentration in the nitride crystal substrate is n (cm ^-3 ). A method for producing a semiconductor laminate, wherein a substrate is prepared in which the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following equation (1) when K and a are constants.
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

(Appendix 16)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
In the step of preparing the nitride crystal substrate,
As the nitride crystal substrate, the absorption coefficient at a wavelength of 2 μm is 1.2 cm ^-1 or more, and the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface is 1.0 cm ^-1 . A method for manufacturing a semiconductor laminate that prepares a substrate that is within the range.

(Appendix 17)
The method for producing a semiconductor laminate according to Appendix 15 or 16, wherein the step of heating the nitride crystal substrate includes a step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the nitride crystal substrate.

(Appendix 18)
A step of epitaxially growing a p-type semiconductor layer containing p-type impurities as a layer constituting the semiconductor layer on the nitride crystal substrate.
As a step of heating the nitride crystal substrate, a step of heating the nitride crystal substrate to activate the p-type impurities in the p-type semiconductor layer and a step of activating the p-type impurities.
17. The method for manufacturing a semiconductor laminate according to Appendix 17.

(Appendix 19)
A step of ion-implanting a predetermined conductive type impurity into the semiconductor layer,
As a step of heating the nitride crystal substrate, a step of heating the nitride crystal substrate to activate the impurities in the semiconductor layer and a step of activating the impurities in the semiconductor layer.
17. The method for manufacturing a semiconductor laminate according to Appendix 17.

(Appendix 20)
A step of forming an electrode so as to be in contact with at least one of the back surface of the nitride crystal substrate and the main surface of the semiconductor layer.
As a step of heating the nitride crystal substrate, a step of heating the nitride crystal substrate to reduce the contact resistance of the electrode and a step of reducing the contact resistance of the electrode.
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 17 to 19.

(Appendix 21)
The step of forming a protective film on the semiconductor layer and
As a step of heating the nitride crystal substrate, a step of heating the nitride crystal substrate to cure the protective film and a step of curing the protective film.
The method for manufacturing a semiconductor laminate according to any one of Supplementary note 17 to 20 having the above.

(Appendix 22)
In the step of preparing the nitride crystal substrate, the seed crystal substrate and the raw material containing the Group III element are carried into the reaction vessel, and the halogen of the raw material is brought into the seed crystal substrate heated to a predetermined crystal growth temperature. It has a crystal growth step of growing a crystal of the nitride of the Group III element on the seed crystal substrate by supplying the compound and the nitride.
In the crystal growth step,
As a member constituting the high temperature region in the reaction vessel, which is a region heated to at least the crystal growth temperature and is a region in contact with the gas supplied to the seed crystal substrate, at least the surface thereof does not contain quartz. The method for producing a semiconductor laminate according to any one of Supplementary note 17 to 21, which uses a member made of a boron-free material.

(Appendix 23)
The method for manufacturing a semiconductor laminate according to Appendix 22, wherein a member made of silicon carbide-coated graphite is used as a member constituting the high temperature region.

(Appendix 24)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
The step of preparing the nitride crystal substrate is
The step of measuring the absorption coefficient of the nitride crystal substrate in the infrared region at 27 ° C.
Based on the measured absorption coefficient of the nitride crystal substrate, the wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate is α (cm ^-1 ), and the free electron concentration in the nitride crystal substrate is n. A step of determining whether the absorption coefficient α in a wavelength range of at least 1 μm or more and 3.3 μm or less is approximated by the following equation (1) when (cm ^-3 ), K, and a are constants, respectively. ,
A method for manufacturing a semiconductor laminate having.
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

(Appendix 25)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
The step of preparing the nitride crystal substrate is
A step of measuring the absorption coefficient in the infrared region at at least two points in the main surface of the nitride crystal substrate, and a step of measuring the absorption coefficient in the infrared region.
Based on the measured absorption coefficient of the nitride crystal substrate, the absorption coefficient of the nitride crystal substrate at a wavelength of 2 μm is 1.2 cm ^-1 or more, and the wavelength in the main surface of the nitride crystal substrate. The step of determining whether the difference between the maximum value and the minimum value of the absorption coefficient at 2 μm is within 1.0 cm ^-1 .
A method for manufacturing a semiconductor laminate having.

(Appendix 26)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
In the step of preparing the nitride crystal substrate,
As the nitride crystal substrate, the wavelength is λ (μm), the absorption coefficient of the nitride crystal substrate at 27 ° C. is α (cm ^-1 ), and the free electron concentration in the nitride crystal substrate is n (cm ^-3 ). , K and a are constants, and the absorption coefficient α in the wavelength range of at least 1 μm or more and 3.3 μm or less is a method for manufacturing a semiconductor device for preparing a substrate approximated by the following equation (1).
α = nKλ ^a ... (1)
(However, 1.5 × 10 ^-19 ≦ K ≦ 6.0 × 10 ^-19 , a = 3)

(Appendix 27)
A step of preparing a nitride crystal substrate composed of Group III nitride crystals and containing n-type impurities, and
The step of irradiating the nitride crystal substrate with at least infrared rays to heat the nitride crystal substrate, and
Have,
In the step of preparing the nitride crystal substrate,
As the nitride crystal substrate, the absorption coefficient at a wavelength of 2 μm is 1.2 cm ^-1 or more, and the difference between the maximum value and the minimum value of the absorption coefficient at a wavelength of 2 μm in the main surface is 1.0 cm ^-1 . A method for manufacturing a semiconductor device that prepares a substrate that is within the range.

1 Semiconductor laminate 2 Semiconductor device 10 Nitride crystal substrate (substrate)
20 Semiconductor layer

Claims (7)

A GaN single crystal substrate doped with n-type impurities.
The concentration of free electrons generated in the GaN single crystal substrate by doping with the n-type impurities is 1 × 10 ¹⁸ cm ^-3 or more under the temperature condition of 27 ° C.
The difference in free electron concentration measured at any two points in the main surface of the GaN single crystal substrate is within 8.3 × 10 ¹⁷ cm ^-3 .
The concentration of boron in the GaN single crystal substrate is less than 1 × 10 ¹⁵ at · cm ^-3 .
The absorption coefficient of light having a wavelength of 2 μm in the GaN single crystal substrate is 1.2 cm ^-1 or more.
A GaN single crystal substrate in which the difference in absorption coefficient of light having a wavelength of 2 μm measured at any two points within the main surface of the GaN single crystal substrate is within 1.0 cm ^-1 . A GaN single crystal substrate doped with n-type impurities.
The concentration of the n-type impurity in the GaN single crystal substrate is 1.0 × 10 ¹⁸ at · cm ^-3 or more.
The difference between the n-type impurities measured at any two points in the main surface of the GaN single crystal substrate is within 8.3 × 10 ¹⁷ at · cm ^-3 .
The concentration of boron in the GaN single crystal substrate is less than 1 × 10 ¹⁵ at · cm ^-3 .
The absorption coefficient of light having a wavelength of 2 μm in the GaN single crystal substrate is 1.2 cm ^-1 or more.
A GaN single crystal substrate in which the difference in absorption coefficient of light having a wavelength of 2 μm measured at any two points within the main surface of the GaN single crystal substrate is within 1.0 cm ^-1 . The concentration of intrinsic carriers thermally excited between the bands of the crystal under the temperature condition of 27 ° C. or higher and 1250 ° C. or lower is the concentration of free electrons generated in the crystal by doping the n-type impurity under the temperature condition of 27 ° C. The GaN single crystal substrate according to claim 1 or 2, which is lower than that. The GaN according to any one of claims 1 to 3, wherein the concentration of oxygen in the GaN single crystal substrate is 1/10 times or less the total concentration of silicon and germanium in the GaN single crystal substrate. Single crystal substrate. The concentrations of oxygen and carbon in the GaN single crystal substrate are less than 5 × 10 ¹⁵ at · cm ^-3 .
The GaN single crystal substrate according to any one of claims 1 to 4, wherein the concentrations of iron and chromium in the GaN single crystal substrate are less than 1 × 10 ¹⁵ at · cm ^-3 . A GaN single crystal substrate doped with n-type impurities,
A semiconductor layer provided on the GaN single crystal substrate and made of a single crystal of a group III nitride semiconductor,
Have,
The concentration of free electrons generated in the GaN single crystal substrate by doping with the n-type impurities is 1 × 10 ¹⁸ cm ^-3 or more under the temperature condition of 27 ° C.
The difference in free electron concentration measured at any two points in the main surface of the GaN single crystal substrate is within 8.3 × 10 ¹⁷ cm ^-3 .
The concentration of boron in the GaN single crystal substrate is less than 1 × 10 ¹⁵ at · cm ^-3 .
The absorption coefficient of light having a wavelength of 2 μm in the GaN single crystal substrate is 1.2 cm ^-1 or more.
A semiconductor laminate in which the difference in absorption coefficient of light having a wavelength of 2 μm measured at any two points in the main surface of the GaN single crystal substrate is within 1.0 cm ^-1 . A GaN single crystal substrate doped with n-type impurities,
A semiconductor layer provided on the GaN single crystal substrate and made of a single crystal of a group III nitride semiconductor,
Have,
The concentration of the n-type impurity in the GaN single crystal substrate is 1.0 × 10 ¹⁸ at · cm ^-3 or more.
The difference between the n-type impurities measured at any two points in the main surface of the GaN single crystal substrate is within 8.3 × 10 ¹⁷ at · cm ^-3 .
The concentration of boron in the GaN single crystal substrate is less than 1 × 10 ¹⁵ at · cm ^-3 .
The absorption coefficient of light having a wavelength of 2 μm in the GaN single crystal substrate is 1.2 cm ^-1 or more.
A semiconductor laminate in which the difference in absorption coefficient of light having a wavelength of 2 μm measured at any two points in the main surface of the GaN single crystal substrate is within 1.0 cm ^-1 .

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