JP7101147B2 - Semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device or the like.

A semiconductor device (power module) equipped with a power semiconductor element (power device) used as a switching element is currently indispensable for controlling an electric motor or the like. Since such a semiconductor device controls a large current, a large amount of heat is generated in the semiconductor element, and not only the semiconductor element but also its surroundings (joint portion and the like) become hot. Therefore, the semiconductor device is required to have high heat resistance. The heat resistance here can be rephrased as the reliability that the function is maintained for a long time even in a high temperature environment.

Japanese Unexamined Patent Publication No. 2017-199807

In order to ensure the heat resistance of the semiconductor device, silicon carbide (SiC) having a wide bandgap is used for the semiconductor. However, since SiC has a high Schottky barrier, it is necessary to form an ohmic contact electrode (ohmic electrode) with sufficiently reduced contact resistance.

In Patent Document 1, an ohmic electrode is formed by irradiating a Mo layer and a Ni layer laminated on the back surface of a SiC substrate with a laser. The ohmic electrode of Patent Document 1 has a structure in which a block-shaped Mo carbide formed near the interface with SiC is surrounded by Ni silicide. The formation of block-shaped Mo-carbide suppresses the diffusion and precipitation of high-resistance graphite. Although Mo-carbide is covalently bondable and does not have low resistance, low resistance of the ohmic electrode is ensured by the metal-bondable Ni silicide generated at the interface with SiC.

As a result of further research by the present inventor, it has been newly found that a semiconductor device having such an ohmic electrode may cause bonding failure such as peeling when bonded to a metal layer (wiring). That is, in an ohmic electrode having a block-shaped Mo carbide as in Patent Document 1, the strength that can withstand the residual stress after bonding (appropriately referred to as “bonding strength” or “adhesion strength”) is not always sufficient. all right.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a highly reliable semiconductor device capable of suppressing the occurrence of junction defects starting from an ohmic electrode.

As a result of diligent research to solve this problem, the present inventor has succeeded in obtaining a semiconductor device in which peeling or the like does not occur in the vicinity of the ohmic electrode by reviewing the structure of the ohmic electrode. By developing this result, the present invention described below was completed.

《Semiconductor device》
(1) The present invention is a semiconductor device including a semiconductor element made of a semiconductor having an ohmic electrode, a metal body bonded to the semiconductor element, and a bonding portion for joining the ohmic electrode and the metal body. The semiconductor is made of silicon carbide, the ohmic electrode contains molybdenum carbide, molybdenum silicide and nickel silicide, and the molybdenum carbide is a semiconductor device uniformly distributed in the ohmic electrode.

(2) In the case of the semiconductor device of the present invention, the ohmic electrode does not become the starting point of bonding failure (peeling, breakage, etc.), and high reliability is ensured. The reason for this is not clear, but it is considered that molybdenum carbide (also referred to as "Mo carbide") is uniformly distributed in the ohmic electrode rather than in a block shape.

Incidentally, the ohmic electrode of the present invention contains molybdenum silicide (also referred to as "Mo silicide") which is not found in the conventional ohmic electrode, and the structures of the two are completely different. Further, in the ohmic electrode of the present invention, nickel silicide (also referred to as “Ni silicide”) is distributed almost uniformly, and the contact resistance is sufficiently small. The contact resistance can be, for example, 1 × 10 ⁻³ Ωcm ² or less, and further can be 1 × 10 ⁻⁴ Ωcm ² or less.

"others"
(1) Whether or not the Mo carbide referred to in the present specification is "uniformly" distributed is confirmed, for example, from an element map image. If you dare to say, "uniform" can be said to be a state in which there are no Mo-carbide particles (nano-sized lumps) having a maximum length of more than 15 nm and even more than 10 nm. The element map image is generated by, for example, electron energy loss spectroscopy (EELS) or energy dispersive X-ray analysis (EDX) using a scanning transmission electron microscope (STEM).

(2) Unless otherwise specified, "x to y" in the present specification includes a lower limit value x and an upper limit value y. A range such as "a to b" may be newly established with any numerical value included in the various numerical values or numerical ranges described in the present specification as a new lower limit value or upper limit value. Unless otherwise specified, "x to ynm" as used herein means xnm to ynm. The same applies to other unit systems (μm, Ωcm ² , etc.).

It is explanatory drawing which illustrates the manufacturing process of a semiconductor element. The beam profile of the irradiated laser. It is a schematic cross-sectional view which illustrates the joining process of a semiconductor element. It is a photograph which shows the state after SLID joining which concerns on Sample 1. It is a photograph which shows the state after SLID joining which concerns on a sample C1. It is an XRD profile which concerns on a sample 1 and a sample C1. It is a STEM image and an element map image which concerns on the ohmic electrode of a sample 1. It is an enlarged STEM image related to the ohmic electrode of sample 1. It is a STEM image and an element map image which concerns on the ohmic electrode of the sample C1. 8 is an enlarged STEM image of the ohmic electrode of sample C1. It is an AES profile of the ohmic electrode which concerns on a sample 1. It is an AES profile of the ohmic electrode which concerns on a sample C1. 3DAP image and element map image of the ohmic electrode according to the sample 1.

One or more components arbitrarily selected from the present specification may be added to the components of the present invention. The contents described in the present specification may be applied not only to the semiconductor device of the present invention but also to a manufacturing method thereof and the like. A component related to "method" can also be a component related to "thing".

<< Ohmic electrode >>
(1) The ohmic electrode contains Mo carbide, Mo silicide and Ni silicide. It is preferable that not only Mo carbide but also Mo silicide and Ni silicide are uniformly distributed in the ohmic electrode. Furthermore, it is preferable that these compounds are distributed without forming a long-period crystal structure and are amorphous. This is confirmed by the fact that the peak appearing in the X-ray diffraction profile (pattern) is not sharp but broad.

Although it is difficult to specify the ratio of each compound, it is preferable that Ni and Mo contained in the ohmic electrode are about the same or have more Ni than Mo. The atomic number ratio of Mo to Ni (Mo / Ni) is, for example, preferably 0.6 to 1 and further preferably 0.7 to 0.9.

The thickness of the ohmic electrode is, for example, 30 to 300 nm and further 50 to 150 nm. The thickness may be, for example, the shortest distance (minimum value of the interfacial distance) observed by an electron microscope (the same applies to other thicknesses).

(2) As long as the above-mentioned ohmic electrode can be obtained, the manufacturing method thereof does not matter. Ohmic electrodes can be formed, for example, by laser annealing. Laser annealing is performed by irradiating a Mo layer and a Ni layer laminated on one surface of a semiconductor with a laser. Local heating is possible by laser irradiation. As a result, damage to the element portion (device structure) already manufactured by ion implantation, oxide film formation, or the like can be avoided on the other surface (surface) of the semiconductor.

The Mo layer and Ni layer are formed by vapor deposition such as sputtering. The thickness of each layer is, for example, 20 to 200 nm and further 40 to 160 nm. The Mo layer and the Ni layer may have the same thickness, but the Mo layer may be thinner than the Ni layer by about 10 to 30 nm.

Next, as the laser (light source), a solid-state laser (semiconductor laser-excited solid-state laser, lamp-excited solid-state laser, etc.), an excimer laser, or the like can be used. Solid-state lasers include YAG lasers, _YVO4 lasers, and the like. Excimers (excited dimers) include F ₂ (wavelength 157 nm), ArF (wavelength 193 nm), KrF (wavelength 248 nm), XeCl (wavelength 308 nm), XeF (wavelength 351 nm) and the like.

As the laser, for example, a pulse laser having a pulse width of 100 nsec or less and further 70 nsec or less may be used. If the output of the laser oscillator and the oscillation frequency are constant, it is possible to irradiate a laser with high energy density by shortening the pulse width. By irradiating a laser with a short pulse width, heat diffusion is suppressed and the thermal effect on the outside of the irradiation surface is suppressed.

For laser irradiation, for example, the effective irradiation area per pulse is 2500 μm ² or more, further 3000 μm ² , and the energy density (output density) of the effective irradiation area is 2.3 to 3 J / cm ² and further 2.4 to 2. It is recommended to set it to 7. J / cm ² . If the effective irradiation area or energy density is too small, it becomes difficult for Mo silicide to be generated and Mo carbide to be uniformly distributed. The effective irradiation area and energy density may be large, but there are restrictions on the device.

The ratio of superimposing the irradiation area of the pulse laser (pulse lap ratio) is adjusted by the oscillation frequency, scanning speed, size of the irradiation area (or focal position of the pulse laser), and the like. Although it depends on the characteristics of the pulse laser, the pulse lap rate may be, for example, 20 to 95% or even 33 to 75%.

The pulse wrap rate is calculated by (p / p0) × 100 (%) (p0: beam diameter, p: overlap diameter of adjacent pulsed light). Here, the beam diameter (p0) is the width (diameter) when the beam intensity becomes the half width level of the peak intensity value, which is measured on the plane orthogonal to the laser axis. The overlapping diameter (p) of adjacent pulsed light is p0-c (c: distance between centers between adjacent beams).

The oscillation frequency of the pulse laser may be, for example, 10 kHz to 100 kHz. If the oscillation frequency is too low, the scanning speed will decrease. If the oscillation frequency is excessive, the laser energy density may decrease.

The irradiation range changes depending on the focal position of the laser. The focal position may be deviated from the outermost surface of the metal layer, but the closer to the outermost surface, the more stable the energy density can be annealed in each region. Laser irradiation may be performed in a vacuum atmosphere or an inert gas atmosphere in order to avoid the formation of unnecessary compounds on the surface of the metal layer (Mo layer or Ni layer).

《Joint part》
The joint portion has a joint layer for joining an ohmic electrode of a semiconductor element and a metal body made of a conductive material. The bonding layer may be a Sn-based solder layer (Sn-Ag-Cu-based solder layer, Sn-Cu-based solder layer, etc.), but if the bonding layer is a heat-resistant bonding layer having a higher melting point, the heat resistance of the semiconductor device can be improved. It is preferable to plan. The heat-resistant bonding layer may be made of, for example, a high melting point material having a melting point of 300 ° C. or higher, further 400 ° C. or higher. Examples of such a heat-resistant bonding layer include an intermetallic compound layer and a metal sintered layer. The heat-resistant bonding layer may be a high-temperature solder layer (Zn—Al-based solder layer, Bi-based solder layer).

The intermetallic compound layer is formed, for example, by a solid-liquid interdiffusion reaction (SLID) between a low melting point metal and a high melting point metal. According to the SLID bonding, a heat-resistant bonding layer made of an intermetallic compound (IMC) having a melting point higher than the heating temperature at the time of bonding can be obtained. As a combination of low melting point metal / high melting point metal, there are Sn / Ni, Sn / Cu, Sn / Ag, Sn / Pt, Sn / Au and the like. For example, when the Sn layer and the Ni layer are brought into contact with each other and heated at about 350 ° C. for about 5 minutes, Sn is melted to obtain an intermetallic compound layer (heat-resistant bonding layer) made of Ni—Sn (IMC). Incidentally, the melting point of Sn is about 230 ° C., the melting point of Ni is about 1450 ° C., and the melting point of Ni ₃ Sn ₄ is about 795 ° C.

The metal sintered layer can be formed, for example, by heating the pace of metal nanoparticles (Ag nanoparticles, Cu nanoparticles, etc.) applied between the surfaces to be bonded. Like the intermetallic compound layer, the metal sintered layer also has a melting point higher than the heating temperature at the time of joining and is excellent in heat resistance.

The heat-resistant bonding layer is usually very thin (for example, about 1 to 10 μm in thickness), hard and low ductility. Therefore, the heat-resistant joint layer has lower stress relaxation property at the joint than the soft and thick Sn-based solder layer. Even when such a heat-resistant joint layer is used, the reliability of the joint portion and thus the semiconductor device can be ensured if the above-mentioned ohmic electrode is present.

Aside from the ultra-thin metal layer (Ti layer, etc.) provided to ensure adhesion, the joint portion may be substantially only the joint layer. However, a stress relaxation layer made of a metal (Al, Cu, etc.) having high ductility (low Young's modulus) may intervene.

《Metal body》
The metal body is bonded to the ohmic electrode of the semiconductor element and is made of a conductive material such as Cu (alloy) or Al (alloy). The metal body may be in the form of a layer, a foil, a sheet, a block, or the like. The metal body is, for example, a wiring layer, a mounting electrode, a heat conductive member (heat sink, heat spreader, etc.) and the like.

<< Semiconductor element >>
The semiconductor element is a transistor or diode made of SiC, and is particularly a power device that controls a large current. Examples of the power transistor include MOSFET (metal oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor) and the like. Examples of the power diode include SBD (Schottky barrier diode), FRD (fast recovery diode) and the like.

The ohmic electrode is formed on the opposite surface side of the element portion (device structure), for example, and becomes a back surface electrode. The back surface electrode is, for example, a cathode electrode for a power diode, a drain electrode or a collector electrode on the opposite side of the gate electrode for a power transistor, and the like.

<< Semiconductor element >>
(1) An example of a manufacturing process of a semiconductor element such as a power MOSFET or a power diode is shown in FIG. 1A. First, an n-type SiC wafer (simply referred to as a “SiC substrate”) doped with impurities is prepared. An element portion (device structure) is formed on one side (surface) of the polished SiC substrate by ion implantation or the like (device forming step). The opposite surface (back surface) side is ground and polished to a desired thickness (board thinning step).

Mo and Ni are sequentially vapor-deposited on the polished back surface by sputtering (metal layer forming step). Sputtering is performed in a vacuum atmosphere (the same applies to other sputterings). The Mo layer and Ni layer laminated on the back surface of the SiC substrate are irradiated with a pulse laser to perform laser annealing (annealing step). As a result, an ohmic electrode (layer) is formed on the back surface of the SiC substrate. The metal layer forming step and the annealing step are collectively called the backside electrode forming step. After that, the SiC substrate on which the element portion and the ohmic electrode are formed is divided by blade dicing or the like (not shown) to obtain a chip (semiconductor element).

(2) In this embodiment, an evaluation chip 1 assuming a power diode was manufactured based on the above-mentioned manufacturing process (see FIG. 1C). As shown in FIG. 1C, the evaluation chip 1 is deposited on one surface (back surface) of the polished SiC substrate 10 (□ 4 mm × t0.28 mm) by sputtering on the ohmic electrode 12 (back surface electrode) and the ohmic electrode 12. The Ti layer 131 (thickness 0.1 μm) and the Ni layer 132 (thickness 3 μm) are formed in this order.

The ohmic electrode 12 was formed by irradiating (laser annealing) a laminated Mo layer (thickness 70 nm) and a Ni layer (thickness 100 nm) with a laser. Laser irradiation was performed by two types of beam profiles shown in FIG. 1B (Sample 1, Sample C1).

First, the beam profile was irradiated with a pulse laser having a top hat shape (a shape with a flat region). At this time, the type of laser: YVO ₄ , pulse width: <60 nsec, oscillation frequency: 20 kHz, effective irradiation area per pulse: 7800 μm ² , energy density of the effective irradiation area: 2.0 to 3.0 J / cm ² And said. The evaluation chip 1 thus obtained is referred to as sample 1. The effective irradiation area was determined by measuring the shape using a beam profile.

Next, as in the prior art (see JP-A-2017-199807), laser annealing was performed by irradiating a pulse laser having a Gaussian-shaped (spier-shaped) beam profile. The laser irradiation conditions at this time were laser type: YVO ₄ , pulse width: <60 nsec, oscillation frequency: 20 kHz, effective irradiation area: 31400 μm ² , energy density: 1.0 to 2.0 J / cm ² . The evaluation chip 1 thus obtained is referred to as sample C1.

《Semiconductor device》
(1) Joining As shown in FIG. 1C, the evaluation chip 1 and the metal plate 2 (metal body / wiring body) were joined. The metal plate 2 is composed of a Cu plate 20 (□ 20 mm × t3 mm) in which a Ni layer 232 (thickness 3 μm) and a Sn layer 231 (thickness 5 μm) are vapor-deposited in order by sputtering.

The evaluation chip 1 and the metal plate 2 were superposed by applying 0.5 MPa, and heated as they were in a heating furnace in a hydrogen reducing atmosphere for 350 ° C. × 15 minutes. After this heating, the furnace was cooled to room temperature to obtain a module M (bonded body / semiconductor device) in which the evaluation chip 1 and the metal plate 2 were SLID-bonded.

The joint portion 3 between the evaluation chip 1 and the metal plate 2 is composed of an intermetallic compound layer 30 and Ni layers 3131 and 3231 on both sides thereof. The intermetallic compound layer 30 was a uniform bonding layer made of Ni ₃ Sn ₄ having a thickness of about 4 μm. The Ni layers 3131 and 3231 are the remaining layers of the Ni layers 131 and 231 after the SLID reaction, respectively.

(2) Evaluation Eight modules M were manufactured for each of sample 1 and sample C1. The state of observing each module M with an ultrasonic microscope image (observation image) is shown in FIGS. 2A and 2B (both figures are collectively referred to as "FIG. 2"). The white portion of the observation image indicates the presence of a joint defect such as peeling in the joint portion 3. As is clear from FIG. 2, no joining defect was observed in the module M according to the sample 1. On the other hand, in the module M related to the sample C1, large bonding defects were observed in half (4/8).

"analysis"
As shown in FIG. 2, in order to clarify the factors that the difference between the ohmic electrodes (difference in laser annealing conditions) greatly affects the occurrence of bonding defects (also simply referred to as “bonding property”), the sample 1 and the sample are sampled. Various analyzes (measurements / observations) shown below were performed on each ohmic electrode of C1.

(1) XRD
The XRD profile obtained by analyzing the ohmic electrode of each sample with an X-ray diffractometer (manufactured by Rigaku Co., Ltd./X-ray used: Cu—Kα ray) is summarized in FIG.

In Sample 1, in addition to MoC (an example of Mo carbide) and Ni ₂ Si (an example of Ni silicide), only peaks showing MoSi ₂ (an example of Mo silicide) were observed, and all peaks were broad. .. On the other hand, in sample C1, no peak indicating Mo silicide (for example, MoSi ₂ ) was observed, and a peak indicating Ni alone or Mo alone was observed. A sharp peak indicating MoC was also observed.

From these XRD profiles, it was clarified that the ohmic electrode according to the sample 1 and the ohmic electrode according to the conventional sample C1 have significantly different tissue structures and products.

(2) STEM-EDX
The cross section of each sample near the ohmic electrode was observed and analyzed with a scanning transmission electron microscope (TEAM EDS System manufactured by Hitachi High-Technologies Corporation) and an energy dispersive X-ray analyzer attached to the scanning transmission electron microscope. The STEM image (bright field image) and the element map image of the sample 1 are shown in FIG. 4A, and the enlarged STEM image is shown in FIG. 4B. Further, the STEM image (bright field image) and the element map image related to the sample C1 are shown in FIG. 5A, and the enlarged STEM image is shown in FIG. 5B, respectively.

As is clear from FIGS. 4A and 4B (both figures are simply referred to as "FIG. 4"), Mo, Ni, C and Si are uniformly distributed in the ohmic electrode according to the sample 1 and are blocked. No compound or the like was found. The MoC layer observed near the junction interface of SiC was uniform and very thin with a thickness of less than 5 nm.

On the other hand, as is clear from FIGS. 5A and 5B (both figures are simply referred to as "FIG. 5"), the ohmic electrode according to the sample C1 has a side of about 16 to 24 nm in the vicinity of the junction interface of SiC. Block-shaped Mo carbide was observed.

(3) AES
The results of Auger electron spectroscopy (AES) of the ohmic electrodes of Sample 1 and Sample C1 from the surface side thereof are shown in FIGS. 6A and 6B (both figures are simply referred to as "FIG. 6"), respectively.

As can be seen from FIG. 6A, it was clarified that the ohmic electrode according to the sample 1 has a structure in which Mo, Ni, C and Si are uniformly distributed. This tendency was similar near the junction interface of SiC.

On the other hand, as can be seen from FIG. 6B, in the ohmic electrode related to the sample C1, Mo and C increased rapidly in the vicinity of the junction interface of SiC, and it was confirmed that a large amount of MoC was present. This result is also consistent with the presence of MoC in blocks, as shown in FIG.

(4) 3DAP
FIG. 7 shows a 3DAP image and an element map image obtained by analyzing the ohmic electrode related to the sample 1 using an atom probe electric field ion microscope (LEAP4000XSi manufactured by AMETEK). The element map image is intended for a region having a thickness of 5 nm from the junction interface of SiC.

As is clear from FIG. 7, it was found that in the ohmic electrode according to the sample 1, Mo, Ni, C and Si were uniformly distributed even in the vicinity of the junction interface of SiC. If we dare to say the size of Mo carbide on the XY plane (the Z direction is the thickness direction), it can be said that it is 5 nm or less in the vertical direction and 15 nm or less in the horizontal direction, even if it is roughly estimated. Therefore, it was clarified that the Mo carbide in the ohmic electrode according to the sample 1 was at most 15 nm or less (less than). Incidentally, in the case of the ohmic electrode according to the sample C1, the size of the Mo carbide was about 25 nm in the vertical direction and 16 to 30 nm in the horizontal direction.

<< Consideration >>
Based on the above, as shown in FIG. 2, the reason why the bondability is different due to the difference in the ohmic electrode is considered as follows.

Since the SLID junction is performed at a relatively high temperature, a large residual stress may act on the junction between the semiconductor element and the metal body according to the difference in the coefficient of thermal expansion thereof. Further, the intermetallic compound layer produced by SLID bonding is very hard and thin, and has poor stress relaxation property, unlike the conventional solder layer (thickness of about 100 μm). Therefore, the residual stress generated by the joining can act directly on the ohmic electrode.

Under such circumstances, the ohmic electrode according to the sample 1 has Mo-carbide and the like uniformly distributed, there is almost no portion that becomes the starting point of fracture, and the high (adhesion) strength causes a bonding defect. It is probable that it was not. On the other hand, in the ohmic electrode related to the sample C1, it is considered that the block-shaped Mo-carbide became the starting point of fracture and caused a joining defect.

When the peeled surface (fracture surface) of the ohmic electrode related to the sample C1 in which the bonding defect was observed was observed by SEM-EDX, it is consistent with the fact that Mo carbide was detected.

By the way, it can be said that such a situation is the same even when the bonding layer is a metal sintered layer. The metal sintered layer is formed by heating a paste containing metal nanoparticles at a high temperature while pressurizing the paste. Therefore, the metal sintered layer is also much harder and thinner than the solder layer (thickness 30 to 50 μm). As a result, in the case of the metal sintered layer as well as in the case of the intermetallic compound layer, the residual stress generated by the joining can be concentrated on the ohmic electrode. Therefore, it can be said that the strength of the ohmic electrode greatly affects the bondability and thus the reliability of the semiconductor device even in the case of the metal sintered layer.

Even in the ohmic electrode related to the sample C1, if the bonding layer is a thick solder layer, it is considered that the ohmic electrode does not break immediately after the bonding. However, considering the accumulation of stress due to long-term use, it is considered difficult to secure sufficient durability with the ohmic electrode according to the sample C1 even if the bonding layer is a solder layer. Therefore, in order to ensure the reliability of the semiconductor device for a long period of time, it can be said that the ohmic electrode is preferably in a state in which Mo carbide is uniformly distributed, regardless of the type of the bonding layer.

M module (semiconductor device)
1 chip (semiconductor element)
10 SiC substrate 12 Ohmic electrode 2 Metal plate 3 Joint part 30 Intermetallic compound layer (joint layer)

Claims (3)

A semiconductor device made of a semiconductor having an ohmic electrode and
A metal body bonded to the semiconductor element and
A joint that joins the ohmic electrode and the metal body,
It is a semiconductor device equipped with
The semiconductor consists of silicon carbide
The ohmic electrode comprises molybdenum carbide, molybdenum silicide and nickel silicide.
The molybdenum carbide is a semiconductor device uniformly distributed in the ohmic electrode. The semiconductor device according to claim 1, wherein the joint portion has a heat-resistant joint layer having a melting point of 300 ° C. or higher. The semiconductor device according to claim 2, wherein the heat-resistant bonding layer is an intermetallic compound layer or a metal sintered layer.

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