JP7100309B2 - Nitride semiconductor substrate, method for manufacturing nitride semiconductor substrate, equipment for manufacturing nitride semiconductor substrate and nitride semiconductor device - Google Patents

Description

Application of Article 30, Paragraph 2 of the Patent Act Announced at the "9th Nanostructure / Eaxial Growth Lecture" on July 13, 2017 "9th Nanostructure / Eaxial Growth Lecture" on July 13, 2017 Published in a booklet On August 25, 2017, the website for posting the proceedings of the "78th Autumn Academic Lecture Meeting of the Society of Applied Physics" (https://confit.atlas.jp/guide/event/jsup2017a/subject/ Published on 7p-A301-5 / advanced) Published on August 25, 2017 at "2017 78th Fall Academic Lecture Meeting of the Society of Applied Physics [Lecture Proceedings]" (DVD) August 25, 2017 Published on the "78th Applied Physics Society Autumn Academic Lecture" on September 7, 2017 Announced at the "78th Applied Physics Society Autumn Academic Lecture" on September 26, 2017 Announced at "The 8th Asia-Pacific Workshop on Widegap Septembers"

The present invention relates to a nitride semiconductor substrate, a method for manufacturing a nitride semiconductor substrate, a device for manufacturing a nitride semiconductor substrate, and a nitride semiconductor device.

LEDs and laser diodes (LDs) using nitride semiconductors are used in a wide range of applications. In particular, a blue light source (wavelength around 450 nm) using InGaN (indium gallium nitride) as a light emitting material is widely used in indoor lighting and in-vehicle headlamps.

In recent years, research and development of an ultraviolet light source (wavelength 200 nm to 400 nm) using AlN (aluminum nitride), GaN (gallium nitride), AlGaN (aluminum gallium nitride), etc. as a light emitting material has been active (for example, Patent Document 1, 2). Applications of the ultraviolet light source include protein analysis, DNA analysis, sterilization, water purification, material processing, and corneal removal for vision correction. Ultraviolet light sources such as 4th harmonic (wavelength 266nm) and 5th harmonic (wavelength 213nm) of YAG laser, or KrF excimer laser and ArF excimer laser have already been put into practical use and are used to meet the above-mentioned demand. ..

Japanese Unexamined Patent Publication No. 2017-0551116 Japanese Unexamined Patent Publication No. 2008-30137

"Polymer waveguides with optimized overlap integral for modal dispersion phasematching" W. Wirges, et.al, Appl. Phys. Lett. 70, 3347 (1997)

However, these light sources are extremely inefficient or very large and difficult to carry outside the laboratory, so they can only be used in special environments such as laboratories. Semiconductor-based ultraviolet light sources using AlGaN are also expected, but it is difficult to obtain high-quality crystals at this stage, and it will take several years at the longest to obtain excellent characteristics like the InGaN-based blue light source. It is thought that it will take about a year.

The present invention is intended to solve the above-mentioned problems, and is a nitride semiconductor substrate having a polarity reversal structure, a flat surface, and a high-quality crystal layer formed, a method for manufacturing a nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate. It is an object of the present invention to provide a nitride semiconductor device.

In order to achieve the above purpose, if an optical system that uses an existing InGaN blue laser as a light source and AlN as a nonlinear optical crystal to generate a second harmonic is constructed, it is possible to generate ultraviolet light with high coherency. can.

Therefore, in the nitride semiconductor substrate according to one aspect of the present invention, Al _x Gay In _{(1-xy) N} (0 ≦) is formed on the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. It has a group III nitride semiconductor crystal layer composed of an aggregate of crystal grains of a group III nitride semiconductor represented by x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1), and the group III nitride semiconductor crystal. In the layer, a polarity reversal layer structure having a group III polarity and a nitrogen polarity is provided in a direction parallel to the surface of the substrate.

According to this aspect, since the crystal layer has a group III polar and nitrogen polar polar inversion layer structure, it is possible to realize a member having a nonlinear optical crystal by processing this crystal layer to an appropriate size. can.

Further, in the method for manufacturing a nitride semiconductor substrate according to one aspect of the present invention, Al _x Gay In _{(1-xy) N} is applied to the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. Group III nitride represented by (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1) Group III nitride semiconductor buffer layer composed of aggregates of crystal grains of group III nitride semiconductor is formed. A set of two semiconductor substrates is used as the first semiconductor substrate set, and the group III nitride semiconductor crystal layers of each of the group III nitride semiconductor substrates of the first semiconductor substrate set are arranged facing each other in a heating furnace. The first installation step to be installed inside, the heating step to heat the first semiconductor substrate set while controlling the temperature of the heating furnace to 1300 ° C. or higher and 1750 ° C. or lower, and the two bonded group III. It includes a substrate peeling step of peeling at least one of the nitride semiconductor substrates.

According to this aspect, a nitride semiconductor substrate for a member having a nonlinear optical crystal can be obtained by a very simple manufacturing method.

Further, the device for manufacturing a nitride semiconductor substrate according to one aspect of the present invention controls the heating furnace, the heater for heating the heating furnace, and at least the heater to control the temperature in the heating furnace. Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, A set of two group III nitride semiconductor substrates on which a group III nitride semiconductor buffer layer composed of aggregates of crystal grains of a group III nitride semiconductor represented by 0 ≦ y ≦ 1 and (x + y) ≦ 1) is formed. A holder that has an opening for accommodating a plurality of semiconductor substrate sets, and that regulates the movement of the semiconductor substrate set housed in the opening, and a holder that is arranged in the heating furnace and has the opening of the holder. It has a lid arranged to cover it.

According to this aspect, a nitride semiconductor substrate for a member having a nonlinear optical crystal can be obtained by the above-mentioned simple manufacturing method.

Further, using the nitride semiconductor substrate having the above characteristics, the group III nitride semiconductor crystal layer is formed in a waveguide having a width w, a thickness h, and a length l, and the width w and the thickness are formed. h, the length l is calculated based on the incident wavelength of the laser beam incident in the direction of the length l.

According to this aspect, as a nitride semiconductor device having a nonlinear optical crystal, for example, an optical second harmonic generation element (SHG element) is realized, and output light having a wavelength of 1/2 of the incident laser light wavelength is efficiently used. You can get it well.

According to the present invention, a nitride semiconductor substrate having a polar inversion layer structure, a flat surface and a high-quality crystal layer formed therein, a method for manufacturing a nitride semiconductor substrate, an apparatus for manufacturing a nitride semiconductor substrate, and nitride It is possible to provide a physical semiconductor device.

Further, it becomes possible to provide a highly efficient SHG element by using the above-mentioned substrate.

It is a schematic diagram of the nitride semiconductor substrate which concerns on Embodiment 1. FIG. It is a figure which shows the electron micrograph which shows the state which the group III polarity and the nitrogen polarity are inverted in the group III crystal layer of the nitride semiconductor substrate shown in FIG. 1. It is an electron micrograph which made the magnification of the electron micrograph shown in FIG. 2 2.5 million times. It is a schematic diagram of the crystal structure which has a plurality of polar inversion layers. It is sectional drawing which shows the manufacturing method of the nitride semiconductor substrate which concerns on Embodiment 1. FIG. It is a flowchart which shows the manufacturing method of the nitride semiconductor substrate which concerns on Embodiment 1. It is a schematic diagram which drew each step (a)-(e) of FIG. 5 three-dimensionally. It is a schematic diagram for demonstrating the amount of warpage of the semiconductor substrate which concerns on Embodiment 1. FIG. It is a schematic diagram which made the semiconductor substrates which concern on Embodiment 1 face each other. It is a schematic diagram which shows the example of the combination of the semiconductor substrate which concerns on Embodiment 1. FIG. This is the result of observing the (11-20) plane of the AlN crystal layer in the semiconductor device according to the first embodiment with HAADF-STEM. It is an image which observed the surface state of the semiconductor substrate which concerns on Embodiment 1 by the dynamic mode of the atomic force microscope. It is the result of the X-ray diffraction locking curve measurement (XRC) of the nitride semiconductor substrate 1 which concerns on Embodiment 1. It is a Raman spectroscopic measurement result of the semiconductor substrate which concerns on Embodiment 1. FIG. It is an X-ray diffraction pole figure of (10-12) of the semiconductor substrate which concerns on Embodiment 1. FIG. It is a schematic block diagram of the manufacturing apparatus which concerns on Embodiment 2. FIG. It is a schematic block diagram of the substrate assembly holder which concerns on Embodiment 2. FIG. It is the result of the X-ray diffraction locking curve measurement (XRC) of the nitride semiconductor substrate which concerns on Embodiment 3. It is a measurement result of the spectroscopic ellipsometry of the nitride semiconductor substrate which concerns on Embodiment 3. It is a schematic diagram which shows the structure of the SHG device which concerns on Embodiment 3. FIG. FIG. 3 is an electric field distribution diagram of the SHG device according to the third embodiment. This is an example of the design of the waveguide according to the third embodiment.

Prior to the description of specific embodiments, the main techniques of the present invention will be described.

As described above, the nitride semiconductor substrate according to one aspect of the present invention has an Al _x Gay In _{(1-xy) on} the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. It has a group III nitride semiconductor crystal layer composed of an aggregate of crystal grains of a group III nitride semiconductor represented by N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1), and has the group III nitride. In the nitride semiconductor crystal layer, a polarity inversion layer structure having a group III polarity and a nitrogen polarity is provided in a direction parallel to the surface of the substrate.

Here, the group III nitride semiconductor is aluminum nitride, gallium nitride, aluminum gallium nitride, or aluminum gallium nitride indium, and the thickness of the group III nitride semiconductor crystal layer is 20 nm or more and 2000 nm or less. The polar reversal layer structure may be a bonded structure bonded at the atomic level.

Further, the polarity inversion layer structure may be formed by joining two group III nitride semiconductor crystal layers.

Further, the half width of the X-ray diffraction locking curve on the (10-12) plane of the group III nitride semiconductor crystal layer may be 1000 arcsec or less.

Further, the group III nitride semiconductor crystal layer may have two or more polar inversion layer structures.

Further, in the method for manufacturing a nitride semiconductor substrate according to one aspect of the present invention, Al _x Gay In _{(1-xy) N} is applied to the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. Group III nitride represented by (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1) Group III nitride semiconductor buffer layer composed of aggregates of crystal grains of group III nitride semiconductor is formed. A set of two semiconductor substrates is used as the first semiconductor substrate set, and the group III nitride semiconductor crystal layers of each of the group III nitride semiconductor substrates of the first semiconductor substrate set are arranged facing each other in a heating furnace. The first installation step to be installed inside, the heating step to heat the first semiconductor substrate set while controlling the temperature of the heating furnace to 1300 ° C. or higher and 1750 ° C. or lower, and the two bonded group III. It includes a substrate peeling step of peeling at least one of the nitride semiconductor substrates.

Here, in the first installation step, the first semiconductor substrate set is housed in a holder for restricting the movement of the first semiconductor substrate set, and the holder is provided with a cover member that closes the opening of the holder. The opening of the cover member may be closed, the gap between the cover member and the substrate facing the cover member may be set to 0.5 mm or less, and the inert gas may be supplied into the heating furnace during heating.

Further, the group III has a film forming step of further growing a group III nitride semiconductor buffer layer on the group III nitride semiconductor crystal layer of the group III nitride semiconductor substrate obtained in the substrate peeling step. The thickness of the nitride semiconductor buffer layer is 10 nm or more and 1000 nm or less, the amount of warpage of the semiconductor substrate is 30 μm or less, and in the first installation step, the first semiconductor substrate set is placed in the holder. , The D-cut surfaces of the group III nitride semiconductor substrate may be aligned, or may be installed so as to face each other by ± 60 °, ± 120 °, or 180 ° from the positions where the D-cut surfaces are aligned.

Further, in the first installation step, a plurality of the first semiconductor substrate sets may be installed in the holder.

Further, the group III nitride obtained by joining the group III nitride semiconductor crystal layers of the group III nitride semiconductor substrate obtained in the substrate peeling step or the group III nitride semiconductor crystal layers obtained in the substrate peeling step. The group III nitride semiconductor substrate on which the physical semiconductor substrate and the group III nitride semiconductor buffer layer are formed is used as a second semiconductor substrate set, and each of the group III nitride semiconductor substrates of the second semiconductor substrate set is used. The second installation step of installing the group III nitride semiconductor crystal layers facing each other in close contact with each other in the heating furnace may be included.

Further, the second installation step, the heating step, and the substrate peeling step may be repeated a plurality of times in this order.

Further, the group III nitride semiconductor substrate obtained in the substrate peeling step has a crystal growth step of growing a crystal of the group III nitride semiconductor thin film on the group III nitride semiconductor crystal layer, and the crystal growth is performed. The group III nitride obtained by forming the two group III nitride semiconductor substrates obtained in the step or the group III nitride semiconductor substrate obtained in the crystal growth step and the group III nitride semiconductor buffer layer. The physical semiconductor substrate is used as a third semiconductor substrate group, and the group III nitride semiconductor thin films of each of the group III nitride semiconductor substrates of the third semiconductor substrate group are brought into close contact with each other and installed in a heating furnace. A third installation step may be included.

Further, the third installation step, the heating step, and the substrate peeling step may be repeated a plurality of times in this order.

The group III nitride semiconductor is aluminum nitride, gallium nitride, aluminum gallium nitride, or aluminum gallium nitride indium, and the material of the holder is a group III nitride semiconductor, carbon, boron nitride, or aluminum oxide (sapphire). ), Ceramic, silicon carbide, refractory metal (molybdenum, tungsten, iridium and alloys thereof), gallium, and tantalum carbide.

Further, in the heating step, the temperature of the heating furnace is controlled multiple times during one heating to a temperature between two different points of 1300 ° C. or higher and 1750 ° C. or lower, or controlled to a plurality of different temperatures. You may.

Further, the device for manufacturing the nitride semiconductor substrate according to the present embodiment is a control device for controlling the temperature in the heating furnace by controlling the heating furnace, the heater for heating the heating furnace, and at least the heater. Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, 0) on the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon, which is arranged in the heating furnace. A set of two group III nitride semiconductor substrates on which a group III nitride semiconductor buffer layer composed of aggregates of crystal grains of a group III nitride semiconductor represented by ≦ y ≦ 1 and (x + y) ≦ 1) is formed. A holder that has an opening for accommodating a plurality of semiconductor substrate sets and regulates the movement of the semiconductor substrate set housed in the opening, and a holder that is arranged in the heating furnace and covers the opening of the holder. It has a lid arranged so as to.

Further, the group III nitride semiconductor crystal layers of each group III nitride semiconductor substrate of the semiconductor substrate set are brought into close contact with each other facing each other, and the opening and the holder have a depth for accommodating a plurality of sets of the semiconductor substrate sets. On the plurality of sets of semiconductor substrates, a weighting member for applying a load to the semiconductor substrate sets is installed, and the temperature control device changes the temperature of the heating furnace to 1300 ° C. or higher and 1750 ° C. or lower. The temperature between two points may be controlled a plurality of times, or may be controlled to a plurality of different temperatures.

Further, in the nitride semiconductor device according to another embodiment, the nitride semiconductor substrate having the above-mentioned characteristics is used, and the group III nitride semiconductor crystal layer has a shape having a width w, a thickness h, and a length l. The width w, the thickness h, and the length l are calculated based on the incident wavelength of the laser beam incident on the direction of the length l.

Further, when the incident wavelength is λ ₁ and the wavelength of the output light of the nitride semiconductor device is λ ₂ , the refractive index at the incident wavelength of the Group III nitride semiconductor crystal layer is n ₁ and the refractive index at the emission wavelength. ₁ = _{n 2 when} one of the values of the width w or the thickness h is fixed and then the unfixed value of the width w or the thickness h is changed. The value of w or h at the time of becoming may be calculated.

Here, the group III nitride semiconductor crystal layer other than the incident surface and the exit surface in the direction of the length l may be covered with a protective layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, aluminum nitride is referred to as AlN, aluminum gallium nitride is referred to as AlGaN, aluminum gallium nitride is referred to as AlGaInN, sapphire is referred to as _{Al2O3 ,} and silicon carbide is referred to as SiC.

In addition, all of the embodiments described below show a preferable specific example of the present invention. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, steps, the order of steps, etc. shown in the following embodiments are examples, and are not intended to limit the present invention. The present invention is specified by the scope of claims. Therefore, among the components in the following embodiments, the components not described in the independent claims are described as arbitrary components.

(Embodiment 1)
[1. Nitride semiconductor substrate configuration]
The nitride semiconductor substrate 1 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic view of a nitride semiconductor substrate 1 according to the present embodiment. FIG. 2 is an electron micrograph showing a state in which the c-axis crystal orientation (group III polarity and nitrogen polarity) of the nitride semiconductor substrate 1 shown in FIG. 1 is inverted in the crystal layer.

The nitride semiconductor substrate 1 according to the present embodiment is a nitride semiconductor substrate used for, for example, a polarity inversion type SHG element. The nitride semiconductor substrate 1 has a group III nitride represented by Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1) on the surface of the substrate. It has a group III nitride semiconductor crystal layer composed of an aggregate of crystal grains of a physical semiconductor. Further, the nitride semiconductor substrate 1 has a polarity inversion layer structure having an Al polarity and a nitrogen polarity, which are Group III polarities, in the group III nitride semiconductor crystal layer.

Specifically, as shown in FIG. 1, the nitride semiconductor substrate 1 includes a sapphire substrate 2 which is an example of a substrate, an aluminum nitride (AlN) crystal layer 3 which is an example of a group III nitride semiconductor, and aluminum nitride. It has a crystal layer 4.

The aluminum nitride crystal layer 3 and the aluminum nitride crystal layer 4 formed on the sapphire substrate 2 have spontaneous polarization or piezo polarization which are antiparallel to each other along the c-axis direction of the sapphire substrate 2. Here, focusing on the Al—N bonds in the Ultz ore type crystal that are parallel to the c-axis, the case where Al is located on the sapphire substrate side is the Al polarity, and the case where N is located is the nitrogen polarity crystal orientation. It is common to define. Therefore, the aluminum nitride crystal layer 3 and the aluminum nitride crystal layer 4 have Al polarity and nitrogen polarity, respectively. Hereinafter, regarding the aluminum nitride crystal layer arranged on the sapphire substrate 2, the aluminum nitride crystal layer having Al polarity is referred to as a + cAlN crystal layer. Further, the aluminum nitride crystal layer having nitrogen polarity is called a -cAlN crystal layer. In the present embodiment, the aluminum nitride crystal layer 3 is a + cAlN crystal layer and is a first group III nitride semiconductor crystal layer. The aluminum nitride crystal layer 4 is a −cAlN crystal layer and is a second group III nitride semiconductor crystal layer.

Here, the structure in which the aluminum nitride crystal layers 3 and 4 in which the Al polarity and the nitrogen polarity are inverted are laminated is referred to as a polarity inversion structure. That is, a structure in which a -cAlN crystal layer is laminated on a + cAlN crystal layer is called a polarity inversion structure. Further, in the polarity inversion structure with the aluminum nitride crystal layers 3 and 4, the layer in which the Al polarity and the nitrogen polarity are inverted is defined as the polarity inversion layer. The polarity inversion layer has a structure within a thickness of 1 to 2 atoms, and has an aspect of an interface between the aluminum nitride crystal layers 3 and 4. Further, in the nitride semiconductor substrate 1, the structure in which the −cAlN crystal layer is laminated on the + cAlN crystal layer is a polar inversion structure in which the interface between the + cAlN crystal layer and the −cAlN crystal layer is parallel to the surface of the sapphire substrate 2. Is arranged. That is, in the nitride semiconductor substrate 1, the polarity inversion layer exists in the direction parallel to the surface of the sapphire substrate 2 as shown in FIG.

Since the nitride semiconductor substrate 1 is schematically represented in FIG. 1, the sapphire substrate and the aluminum nitride crystal layers 3 and 4 appear to have the same thickness, but the sapphire substrate 2 is actually 200 μm or more. The size is about 1000 μm or less, and the aluminum nitride crystal layers 3 and 4 are each about 10 nm or more and 1000 nm or less. Therefore, the total thickness of the aluminum nitride crystal layers 3 and 4 is produced in the range of about 20 nm or more and 2000 nm or less. The nitride semiconductor substrate 1 shown in FIG. 1 has a polarity inversion layer near the center of the thickness at the interface between the aluminum nitride crystal layers 3 and 4. However, the aluminum nitride crystal layers 3 and 4 do not have to have the same thickness. Therefore, the polarity inversion layer is not necessarily formed near the center of the total thickness of the crystal layers 3 and 4, and the position of the polarity inversion layer depends on the characteristic requirements of the device obtained by processing the nitride semiconductor substrate 1. Can be set freely.

FIGS. 2A and 2B are electron micrographs showing a state in which the group III polarity and the nitrogen polarity of the nitride semiconductor substrate 1 are inverted in the group III crystal layer. More specifically, the electron micrographs shown in FIGS. 2 (a) and 2 (b) are observation images (STEM images) of a nitride semiconductor substrate by HAADF-STEM (high-angle scattering annular dark-field scanning transmission electron microscope). In FIGS. 2A and 2B, the sapphire substrate of the nitride semiconductor substrate, the + cAlN crystal layer showing positive polarity when one direction of the sapphire substrate in the c-axis direction is positive, and the c-axis direction. A -cAlN crystal layer showing a negative polarity when the direction opposite to the positive direction is negative is observed. The portion where the polarity is reversed, that is, the interface between the + cAlN crystal layer and the −cAlN crystal layer is the interface when the AlN substrates are bonded by the method described later. Note that FIG. 2B shows the results of measuring a part of the vicinity of the interface between the + cAlN crystal layer and the −cAlN crystal layer in the semiconductor substrate shown in FIG. 2A at a high magnification of 15 million times. ing.

In the STEM image, the heavier the atom, the brighter it looks. From this, it can be seen that in (b) of FIG. 2, the white dot indicates an Al atom heavier than the N atom, and the N atom exists in the portion extending like the tail of the comet. .. The + cAlN crystal layer and the -cAlN crystal layer were originally two independent AlN substrates, but a clear atomic image was seen at the interface, indicating that they show extremely high crystallinity. .. The polarity reversal from the + cAlN crystal layer to the −cAlN crystal layer occurs in the monatomic layer, and realizes a steep polarity reversal that was difficult with the conventional crystal growth method. Here, the disorder of the atomic structure is 1 nm or less, the + cAlN crystal layer and the -cAlN crystal layer are completely bonded at the level of 1 to 2 atoms, and the + cAlN crystal layer and the -cAlN crystal layer It can be read from the STEM image that the amorphous layer does not exist at the interface.

Further, when the interatomic distance of the Al atom was extracted from the STEM image, it was 2.8 Å at the bonded interface and 2.5 Å at the location away from the bonded interface. Since the interatomic distance is about 10% larger at the bonding interface, it is considered that impurities such as oxygen and carbon are contained in the bonding interface, and the atomic bond is formed through these. Further, FIG. 3 shows a photograph in which the magnification of the electron micrograph described above is 2.5 million times. It can be observed that the length of the arrow shown in FIG. 3 is 10 nm, the interface extends straight to several tens of nm, and the interface having a good crystal state and polar inversion structure continues.

Here, FIG. 4 shows a development example (modification example) of the nitride semiconductor substrate 1 according to the present embodiment. The nitride semiconductor substrate 1 may include not only the aluminum nitride crystal layers 3 and 4 but also a plurality of aluminum nitride crystal layers on the sapphire substrate 2 as described below. FIG. 4 is a schematic diagram of a crystal structure having a plurality of polar inversion layers.

FIG. 4A shows a crystal structure having two polar inversion layers by adding the aluminum nitride crystal layer 5 to the aluminum nitride crystal layers 3 and 4 of FIG. FIG. 4B shows a crystal structure having three polar inversion layers by further adding an aluminum nitride crystal layer 6. As described above, in order to clearly indicate the degree of freedom in design regarding the position of the polarity inversion layer, the thicknesses of the aluminum nitride crystal layers 3 and 4 and the aluminum nitride crystal layers 5 and 6 in FIGS. 4 (a) and 4 (b) are shown. Is shown differently.

The substrate is not limited to the sapphire substrate 2, and may be a substrate composed of at least one of sapphire, silicon carbide (SiC), aluminum nitride (AlN), and silicon (Si). Further, the aluminum nitride crystal layer constituting the first group III nitride semiconductor and the second group III _nitride semiconductor is not limited to aluminum nitride ( _AlN ), and is not limited to aluminum nitride (AlN _). Aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum gallium nitride indium (AlNGaIn) represented by N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1). ) May be. The first group III nitride semiconductor and the second group III nitride semiconductor can be bonded even if they are made of different group III nitride materials, but from the viewpoint of suppressing stress due to the difference in thermal expansion coefficient and dangling bonds generated at the interface. Therefore, it is preferable that they are made of the same material.

[2. Nitride semiconductor substrate manufacturing method]
Next, a method for manufacturing the nitride semiconductor substrate 1 used in the above-mentioned polarity reversal type SHG element and the like will be described with reference to FIGS. 5 and 6. FIG. 5 is a cross-sectional view showing a method of manufacturing the nitride semiconductor substrate 1 according to the present embodiment. FIG. 6 is a flowchart showing a method of manufacturing the nitride semiconductor substrate 1 according to the present embodiment. FIG. 7 is a diagram for three-dimensionally drawing each step (a) to (e) of FIG. 5 to further promote understanding. Since the process shown in FIG. 7 is the same as that in FIG. 5, the description thereof will be omitted.

In the following, the heat-treated AlN buffer layers 3a and 3b are referred to as AlN crystal layers 3a and 3b, respectively. Further, the AlN buffer layers 3a and 3b having Al polarity and the AlN crystal layers 3a and 3b are referred to as + cAlN buffer layers 3a and 3b and + cAlN crystal layers 3a and 3b, respectively. Similarly, the AlN buffer layer 3b and the AlN crystal layer 3b having nitrogen polarity are referred to as -cAlN buffer layer 3b and -cAlN crystal layer 3b, respectively.

As shown in FIGS. 5 and 6, the method for manufacturing the nitride semiconductor substrate 1 is roughly divided into the following six steps.

First, as shown in FIG. 5A, a step of forming an AlN buffer layer 3a on the sapphire substrate 2a is performed (step S11). The AlN buffer layer 3a is a precursor of the aluminum nitride crystal layer 3, and is a layer that becomes the aluminum nitride crystal layer 3 by being heat-treated in a later configuration. The AlN buffer layer 3a is formed into a film by a sputtering method under the conditions of, for example, 700 W and 600 ° C. The AlN buffer layer 3a generated at this time has a thickness of, for example, 200 nm. The substrate on which the AlN buffer layer 3a is formed on the sapphire substrate 2a is referred to as a group III nitride semiconductor substrate (hereinafter, simply referred to as “semiconductor substrate”).

The formation of the AlN buffer layer 3a is not limited to the sputtering method, but may be a MOVPE method, a hydride vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, or the like. good. Further, the plane orientation of the sapphire substrate 2 on which the AlN buffer layer is formed is not limited to the sapphire c plane, and the a-plane, r-plane, n-plane, m-plane and the error of the off angle within ± 4 ° from those planes. May be included. Further, as described above, the material of the substrate is not limited to sapphire, and may be SiC, AlN, silicon, or the like. Further, as the substrate, a substrate that has been annealed once by the method of Patent Document 1 and whose crystal state has been improved may be used.

Further, a group III nitride semiconductor substrate formed of the sapphire substrate 2b and the AlN buffer layer 3b is prepared in the same manner as the group III nitride semiconductor substrate formed of the sapphire substrate 2a and the AlN buffer layer 3a.

Next, as shown in FIG. 5B, a semiconductor substrate having an AlN buffer layer 3a formed on the sapphire substrate 2a and a semiconductor substrate having an AlN buffer layer 3b formed on the sapphire substrate 2b are divided into two. A semiconductor substrate set is formed as a set of sheets, and the surfaces (AlN surfaces) on which the AlN buffer layers 3a and 3b are arranged in each semiconductor substrate are brought into close contact with each other (step S12). The semiconductor substrate set at this time is the first semiconductor substrate set. Here, the crystal orientation of the AlN buffer layers 3a and 3b of the two semiconductor substrates facing each other has a degree of freedom of rotation around the c-axis, but the crystal orientation in this plane (for example, the a-axis orientation) The deviation is preferably within ± 1 °, or within ± 60 ± 1 °, ± 120 ± 1 °, and 180 ± 1 °. Further, in order to fix the two semiconductor substrates, the two semiconductor substrates are placed in a cylindrical holder having the same bottom surface shape as the sapphire substrates 2a and 2b, and the state in which the inert gas is substantially retained is further determined. It is desirable to cover the holder with a cover member. The distance between the cover member and the facing sapphire substrate 2b is 0.5 mm or less, preferably 0.1 mm or less. The holder and lid will be described in detail later.

Next, as shown in FIG. 5 (c), heat treatment is performed on the semiconductor substrate assembly in which the AlN surfaces are opposed to each other and brought into close contact with each other. The heat treatment is a heat treatment step using an electric furnace or the like. For example, heat treatment is performed at a temperature of 1700 ° C. for 3 hours. The heat treatment conditions are selected according to the group III semiconductor, the substrate material, the amount of warpage of the substrate, and the like. For example, the allowable range is 1300 ° C. or higher and 1750 ° C. or lower for the temperature, 10 minutes or more and 5 hours or less for the time, and preferably 30 minutes or more and 3 hours or less for the time. Control to constantly supply and discharge an inert gas such as nitrogen gas in order to discharge impurities while keeping the inside of the furnace at about 0.3 atm or more and 3 atm or less with an inert gas such as nitrogen during the heat treatment. It is carried out. However, the gas does not substantially flow on the surface facing the main surface of the semiconductor substrate group and its surroundings, and the AlN component is suppressed from being dissociated and escaped during the heat treatment, and the surface is flat and high quality AlN. The nitride semiconductor substrate 1 on which the crystal layer is formed is manufactured.

The processing shown in steps S11 to S13 is similar to the content described in Patent Document 1. However, while the technique described in Patent Document 1 is a technique for remarkably improving the crystal quality of the AlN crystal layer of a semiconductor substrate alone, the technique according to the present invention remarkably improves the crystal quality of the AlN crystal layer. Using technology, two semiconductor substrates are joined with atomic level accuracy.

Next, as shown in FIG. 5D, a process of peeling off the sapphire substrate 2b is performed on one of the two semiconductor substrates (step S14). The nitride semiconductor substrate 1 from which the sapphire substrate 2b has been peeled off has a configuration in which an Al-polar AlN crystal layer 3a is arranged on the sapphire substrate 2a and a nitrogen-polar AlN crystal layer 3b is arranged on the AlN crystal layer 3a. ing. The evaluation results of the AlN crystal layer whose polarity has been inverted by such a manufacturing method will be described below.

In this embodiment, two AlN crystal layers 3a and 3b having a thickness of 200 nm formed by a sputtering method are used. As illustrated in FIG. 8, the polarity of the AlN crystal layer 3a formed by the sputtering method is Al polarity, which is expressed as + cAlN. Conversely, the nitrogen (N) polar AlN crystal layer 3b is expressed as −cAlN. As described above, when stacking wafers, the angles of cuts called orientation flats (hereinafter referred to as orientation flats) are matched so that the in-plane crystal orientations (for example, a-axis orientations) of the two AlN crystal layers match. ing. Further, the heat treatment was performed with the heat treatment (or annealing) temperature set to 1700 ° C. and the heat treatment time set to 3 hours. The sapphire substrate 2 is peeled off by inserting the blade B (see (d) in FIG. 7), and the blade B is inserted into the bonding interface and mechanically peeled off by the principle of the lever. Other methods such as precision cutting may be used.

Next, (e) and (f) of FIG. 5, steps S15 and S16 of FIG. 6 are steps of processing the semiconductor substrate obtained as described above as a device. In this embodiment, the SHG element will be briefly described as an example. The details of the SHG element will be described in detail later.

First, as shown in FIG. 5 (e), the + cAlN crystal layer 3a and the −cAlN crystal layer 3b laminated on the sapphire substrate 2a are subjected to a general method in a semiconductor processing process such as lithography and dry etching. It is formed into a pattern of the waveguide core layer (step S15). After that, as shown in FIG. 5 (f), the clad layer 7 is formed as a protective layer for confining light in the waveguide core layer. The clad layer 7 is formed by sputtering aluminum oxide (Al ₂ O ₃ ) into a sapphire substrate 2a and a waveguide core layer in the y-axis direction of the + cAlN crystal layer 3a and the −cAlN crystal layer 3b (see (a) in FIG. 20). ) Is formed by forming a film so as to cover other than the incident surface and the emitted surface (step S16). Further, in order to prevent the evanescent wave from leaking not only into the clad layer but also into the air above the clad layer when the fundamental wave and the SH wave propagate in the waveguide in the SHG element, the film thickness of AlO _x is set to 1 μm. ing.

At the stage (d) of FIG. 5, it is also possible to peel off the other sapphire substrate 2a as needed to leave only the + cAlN crystal layer 3a and the −cAlN crystal layer 3b having the polarity inversion structure. However, for convenience of processing, the + cAlN crystal layer 3a and the −cAlN crystal layer 3b having the polarity inversion structure may be removed from the sapphire substrate 2a after the step (e) in FIG. 5 is completed. Thereby, the + cAlN crystal layer 3a and the −cAlN crystal layer 3b can be used as a clad layer, and the entire circumference of the waveguide core layer can be made of the same material. Examples of the material of the clad layer 7 include silicon oxide (SiO) in the case of an SHG element.

Here, in the step (b) of FIG. 5, it is important for each semiconductor substrate used for bonding the nitride semiconductor substrate 1 to select the amount of warpage of each semiconductor substrate and the initial crystal quality within a range in which bonding is likely to occur. It becomes a condition. Therefore, the amount of warpage and the initial crystal quality of the semiconductor substrate used for bonding will be described below.

FIG. 8 is a schematic diagram for explaining the amount of warpage of the semiconductor substrate used for joining. In FIG. 8, the amount of warpage of the semiconductor substrate is drawn larger than the actual amount of warpage for easy understanding. In FIG. 8, P is the center point of the radius of curvature, R is the radius of curvature, and r1 is the amount of warpage of the substrate.

For example, as shown in FIG. 8, an AlN buffer layer 3a is formed on a circular sapphire substrate 2a having a diameter of 2 inches and a thickness of 400 μm. For example, the film thickness of the AlN buffer layer 3a is set to 200 nm. Further, the sapphire substrate 2a has a concave warp in which the center of the wafer is warped in a substantially spherical shape, and the radius of curvature R of the warp is about 89 m. When the radius of curvature is concave and about 89 m, the amount of warpage (depth from the peripheral edge of the substrate) near the center of the substrate is about 5 μm. The surface roughness of the AlN buffer layer 3a is about 0.2 nm or more and 0.3 nm or less. When such a semiconductor substrate is used and the AlN surfaces of the two semiconductor substrates are brought into close contact with each other facing each other, the two semiconductor substrates are bonded to each other by the atomic bond between the AlN buffer layers 3a.

On the other hand, when a semiconductor substrate having a film thickness of the AlN buffer layer 3a of 200 nm, a radius of curvature R of about 11 m, and a surface roughness of about 0.4 nm or more and 0.6 nm or less is used, the two semiconductor substrates are atomic. It was not possible to make an interbond. When the radius of curvature is about 11 m, the amount of warpage near the center of the substrate is about 45 μm.

As described above, even if the heat treatment is performed under substantially the same conditions, there are some that can form a bonded body of the AlN buffer layer 3a and some that cannot, but this is affected by the amount of warpage of the semiconductor substrate, the surface roughness, and the like. However, when the sapphire substrate 2a of the semiconductor substrate set in which the bonded body was formed is peeled off and observed, interference fringes cannot be seen from the surface, so there is no evidence that an air layer has entered, and the sapphire substrate 2a is completely bonded over the entire surface. , All wafer surfaces can be utilized for devices. Needless to say, the unbonded semiconductor substrate can be used as a substrate having an excellent crystal layer of an AlN single layer.

Further, as will be described later, when joining two semiconductor substrates, the two semiconductor substrates are brought into close contact with each other of a plurality of sets of nitride semiconductor substrates in the holder, and the semiconductor substrate sets are stacked. Therefore, the semiconductor substrate set at the bottom is weighted with a weight of 6.8 g for the two upper semiconductor substrates or a weight of 13.6 g for the four semiconductor substrates. .. Here, it is effective to mount a weighting member 182 (see FIG. 17) having the same shape as the substrate and having as little warpage as possible and having a radius of curvature R of about 30 m or more on the semiconductor substrate assembly.

Materials used for the weighting member 182 include group III nitride semiconductors, carbon, boron nitride, aluminum oxide (sapphire), ceramics, silicon carbide, refractory metals (molybdenum, tungsten, iridium, etc.) and alloys thereof. Etc.), zirconia, tantalum carbide can be selected.

Furthermore, in order to realize joining more reliably, a load of about 1 hour or more and 20 hours or less and 25 kPa or more and 500 kPa or less is applied in a state where the two substrates are bonded together before the heat treatment for the purpose of improving the amount of warpage. It is also included in the scope of the present invention to use a semiconductor substrate set having an improved amount of warpage.

The relationship between the maximum value r1 near the center of the warp and the radius of curvature R in the semiconductor substrate is the warp amount r1 (μm) corresponding to R (m) = 5, 10, 20, 40, 60, 80, 100 in the case of a 2-inch wafer. ) = 84, 42, 21, 10, 7, 5, 4 or so. When the radius of curvature is about 20 m, the amount of warpage is within about 20 μm, and it is considered that joining is easy. Further, it is preferable that the amount r1 of the warp of the substrate is small as described above for bonding.

FIG. 9 is a schematic view of semiconductor substrates having a concave warp facing each other. In FIG. 9, the concave semiconductor substrates described in FIG. 8 are placed in close contact with each other facing each other. The sapphire substrates 2a and 2b shown in FIG. 9A have the same thickness, but may have different thicknesses. Further, the AlN buffer layers 3a and 3b shown in FIG. 9 have, for example, a thickness of about 10 nm or more and 1000 nm or less. The AlN buffer layers 3a and 3b may have the same thickness or different thicknesses. In particular, the AlN buffer layers 3a and 3b may have different thicknesses in terms of device design such as optical characteristics after bonding.

Here, r0 in FIG. 9A indicates the maximum gap formed near the center of the semiconductor substrate. As described above, if the amount of warpage of the two semiconductor substrates is 20 μm, the maximum gap r0 is about 40 μm. Since the diameter of the wafer is about 50.8 mm at 2 inches, the maximum gap r0 is drawn large in FIG. 9, but a slight gap actually remains. It is more preferable that the gap is small in order to form a bonded body.

Although not shown, the two semiconductor substrates are housed in a holder that regulates the radial movement of the semiconductor substrate, and are covered with a cover member to control the temperature for heat treatment, as will be described later. Before raising it, it goes through the process of evacuating once in the heating furnace. The reason why the inside of the heating furnace is evacuated is to discharge impurities. Therefore, the holder or the cover member is provided with one or a plurality of air vent holes having a diameter of 1 mm. Here, in the process of creating a vacuum while gradually increasing the temperature, by raising the temperature to about 1300 ° C. or higher and 1750 ° C. or lower, a force acts in the direction in which the maximum gap r0 becomes smaller due to the relationship of expansion and hardness softening. .. As a result, as shown in FIG. 9 (b), in addition to passing through a completely flat state and having a good initial surface roughness, the crystal quality becomes very good due to the annealing effect. Therefore, it is considered that an interatomic bond has occurred on the surface of the AlN buffer layers 3a and 3b. Therefore, it is desirable that the shape and amount of warpage of the two semiconductor substrates are almost the same. Rather than making the thicknesses of the nitride semiconductor layers uniform, it is conceivable that the pair is determined by measuring the amount of warpage even if the thicknesses are different. On the other hand, since one of the sapphire substrates 2a and 2b is peeled off and becomes unnecessary, it is effective to match the peeling method with the thickness of what remains as the sapphire substrate in order to make the amount of warpage uniform. ..

Here, a method for facilitating the peeling of the sapphire substrate 2b in FIG. 5D will be described. In the experiment, there were cases where a substrate that could be completely isolated and a crystal layer having an AlN polarity inversion structure remained on the substrate on the partially isolated side. Both of the sapphire substrates 2a and 2b can be used in making the device, but it is preferable that one or both of the substrates can be completely peeled off. Therefore, before forming the AlN buffer layer 3a on the sapphire substrate 2a shown in FIG. 8, a BN (boron nitride) film or a BGaN (boron nitride) film having a size of 10 nm or more and 50 nm or less is provided as a release layer. , The substrate can be easily peeled off, and the productivity can be improved. This release layer may be formed on both of the two group III nitride semiconductor substrates constituting the group III nitride semiconductor substrate set, but since it is sufficient that one of the substrates is easily peeled off, the release layer has a group III nitride. A semiconductor substrate set can be made of a nitride semiconductor substrate and a group III nitride semiconductor substrate having no release layer. In addition, cleaning of the peeled surface can be performed as needed. Regardless of the presence or absence of the peeling layer, it is effective to perform cleaning for 5 minutes or more and 30 minutes or less while supplying hydrogen gas in a temperature range of about 1000 ° C. or more and 1250 ° C. or less.

Further, it is effective to combine basic substrates as shown in FIG. 10 to form a semiconductor substrate set. FIG. 10A shows a substrate in which an AlN buffer layer 3a is formed on a sapphire substrate 2a. FIG. 10B shows a substrate in which a + cAlN-polarity AlN crystal layer 3 and a −cAlN-polarity AlN crystal layer 4 are bonded onto a sapphire substrate 2, and is the form described with reference to FIG. The sapphire substrate 2a and the AlN buffer layer 3a of FIG. 10A are shown before the heat treatment, and the AlN layer is an AlN buffer layer to distinguish it from the AlN crystal layer, but it is described as an AlN film. There is also. FIG. 10 (c) shows a substrate in which a + cAlN polar AlN crystal layer 3 and a −cAlN polar AlN crystal layer 4 are bonded on a sapphire substrate 2, and an AlN buffer layer 5a is further formed on the substrate. It is a substrate, and the uppermost AlN buffer layer 5a is in a state where it has not undergone heat treatment. Here, (a)-(a), (a)-(b), (a)-(c), and (b)-(c) can be considered as a combination of semiconductor substrate sets. As the bonded semiconductor substrate, (b) and (c) are in a state where they can be used alone for a device, and (a)-(b), (a)-(c), (b)-. By repeating (c), it is possible to obtain a nitride semiconductor substrate having a number of polar inversion layers.

Here, it is said that the AlN buffer layer before the heat treatment has smaller AlN crystal grains than the AlN crystal layer after the heat treatment. In Patent Document 1, when the substrate temperature is raised to 1700 ° C., adjacent grains are coalesced in the AlN buffer layer, and the surface of the AlN buffer layer is flattened. In addition, although dislocations exist at the boundaries between grains, the number of grains occupied per unit area decreases as the temperature of the substrate to be heat-treated increases due to the coalescence of the grains to form large grains. Therefore, the number of dislocations per unit area also decreases. Therefore, it is explained that in the AlN crystal layer after the heat treatment, the through-dislocation density is reduced, the surface flatness is good, and a high-quality AlN crystal layer can be obtained. Therefore, the + cAlN polarity before the heat treatment described above is for the purpose of explanation after the joining, and includes those that become the + cAlN polarity during the heat treatment.

[3. Characteristics of Nitride Semiconductor Substrate]
Hereinafter, the characteristics of the nitride semiconductor substrate 1 manufactured by the above method will be described.

First, using FIG. 11, HAADF-STEM (High-angle Annular Dark) was used to describe the structural characteristics of the AlN crystal layer on the side where one of the sapphire substrates was peeled off near the peeled surface, which was obtained in step (d) of FIG. Field Scanning Transmission Electron Microscopy) This will be explained using an image. FIG. 11 shows the results of observing the (11-20) plane of the AlN crystal layer in the nitride semiconductor substrate 1 with HAADF-STEM.

HAADF-STEM is a material observation method using transmitted electrons. An image can be obtained by applying a finely squeezed electron beam to the sample while scanning it, and detecting the transmitted electrons scattered at a high angle with an annular detector. In a general TEM image, information such as strain and defects of a crystal lattice can be obtained, but in HAADF-STEM, information on a crystal composition can be obtained. The purpose of using HAADF-STEM in this observation is to discriminate between Al atoms and N atoms with a high-magnification atomic image and to observe the state of polarity inversion.

FIG. 11A shows the results of observing the (11-20) plane of the AlN crystal layer in the nitride semiconductor substrate 1 with HAADF-STEM. Further, FIG. 11B is an enlarged image of a part of FIG. 11A. The film thickness of the + cAlN crystal layer in the nitride semiconductor substrate 1 was 194 nm, which was in agreement with the value expected at the time of film formation by the sputtering method, but the film thickness of the -cAlN crystal layer was 178 nm, which was compared with the + c side. It turned out that it was thinned by about 15 nm.

The reason for this is considered to be that when the sapphire substrate in one of the nitride semiconductor substrates 1 was peeled off, the AlN film having a thickness of 15 nm was brought to the peeled sapphire substrate side (see (b) in FIG. 11). ). From the experimental results so far, it is known that a -cAlN crystal layer is formed at the interface between the sapphire substrate and the + cAlN crystal layer by about 20 nm, and the region of the -cAlN crystal layer has weak mechanical strength and is the starting point of peeling. It is possible that

The surface of the AlN crystal layer from which the sapphire substrate was mechanically peeled by the above-mentioned method was relatively flat, contrary to the act of mechanical peeling. FIG. 12 shows an image of the surface state observed by the dynamic mode of an atomic force microscope (AFM). FIG. 12 is an image of the nitride semiconductor substrate 1 in which the surface state is observed by the dynamic mode of the atomic force microscope. The surface roughness in the 5 × 5 μm range shown in FIG. 12 (a) is 0.90 nm in RMS value, and the surface roughness in the 1 × 1 μm range shown in FIG. 12 (b) is 0. It was 82 nm.

Generally, it is said that bonding is possible if the surface roughness is 1 nm or less, and as described in FIG. 4, it is possible to realize a multi-layered polarity inversion structure with four or more layers by repeating this process. be. Alternatively, a three-layer polarity inversion structure can be produced by forming a + cAlN crystal layer on the two-layer polarity inversion structure by a sputtering method. By adding the above-mentioned peeled + cAlN film of about 15 nm to form a film, the -cAlN crystal layer (about 20 nm), the + cAlN crystal layer (about 170 nm), and the -cAlN crystal layer (about 170 nm) are formed when viewed from the sapphire substrate side. ), + CAlN crystal layer (about 20 nm) can be balanced.

Next, using FIG. 13, the crystal on the side from which one of the sapphire substrates was peeled off, which was obtained in the step (d) of FIG. 5, was subjected to X-ray diffraction on the (0002) plane by an X-ray diffractometer (XRD). The results of rocking curve measurement (XRC) of X-ray diffraction on the (10-12) plane are shown. FIG. 13 shows the X-ray diffraction locking curve measurement (XRC) result of the nitride semiconductor substrate 1, (a) is the measurement result of the (0002) plane, and (b) is the measurement result of the (10-12) plane. .. The broken lines shown in FIGS. 13 (a) and 13 (b) are the results (examples) of the AlN crystal layer having a polarity reversal structure produced by the method of the present embodiment, and the solid line is immediately after the sputtering film formation. The result of the AlN film (AlN single film) (Comparative Example 1) is shown as a reference value. 13 (a) shows the X-ray diffraction result on the (0002) plane, and FIG. 13 (b) shows the X-ray diffraction result on the (10-12) plane.

In the AlN crystal layer obtained by heat-treating the AlN buffer layers 3a and 3b so as to face each other, the result of X-ray diffraction on the (10-12) plane tends to be significantly improved. The FWHM is very good at 302 arcsec, which is the same as when the substrates on which the is formed are brought into close contact with each other and heat-treated. Although the FWHM of the (0002) plane of the AlN crystal layer was slightly deteriorated, no significant adverse effect was confirmed. Therefore, it was confirmed that the effect of improving the crystallinity by the heat treatment was sufficiently maintained even when the polarity reversal by joining was introduced.

In addition, the lattice constants of the c-axis and a-axis of the AlN crystal layer estimated from the 2θ-ω measurement (c-axis is 4.990 Å and tension 1.16%, a-axis is 3.098 Å and compression 0.45%). ) And the biaxial stress derived from it (biaxial stress σ _xx = 2.11 GPa) are the results that are almost the same as the results at the time of annealing the AlN single film substrate. Therefore, the AlN crystal layer in the nitride semiconductor substrate 1 produced by the above-mentioned method has characteristics suitable for devices such as SHG devices.

Moreover, the Raman spectroscopic measurement result will be described with reference to FIG. 14 (a). FIG. 14 is a Raman spectroscopic measurement result of the nitride semiconductor substrate 1.

Raman spectroscopy is a measurement method that evaluates the crystal structure and structural quality from Raman scattered light generated when a sample is irradiated with light. It is known that the wavelength of Raman scattered light reflects the crystal structure of the sample and shifts to the longer wave side than the incident light by the phonon energy corresponding to the intrinsic mode of lattice vibration, and this amount of change is called Raman shift. I'm out. The crystallinity of the AlN crystal layer having a polar inversion structure produced by the method of the present embodiment was evaluated from the Raman shift amount and the half width at half maximum of the Raman spectrum.

There are several peaks in the Raman spectrum of the AlN film, but the typical E ₂ (high) peak changes the Raman shift amount in proportion to the amount of strain in the crystal, resulting in structural imperfections. It is known that the line width (FWHM) is reflected and widened. If it is a single-layer film AlN substrate, it exists at 658 cm ^-1 as shown by a broken line in FIG. 14 (a). The crystals having the polarity reversal structure on the side where one of the sapphire substrates was peeled off, which was obtained in the step (d) of FIG. 5, are shown in the solid line AlNE ₂ (high) shown in FIG. 14 (a). The Raman shift amount is 663.6 cm ^-1 , which is almost the same as the value after annealing of the single-layer film AlN substrate. The peak FWHM was 5.8 cm ^-1 , showing good crystallinity.

Further, FIG. 14 (b) shows the relationship between the empirically obtained Raman shift amount and σ _xx . From the Raman shift amount, the biaxial stress generated in the plane of the crystal can be derived. The proportional relationship between the two is empirically determined, and the proportionality coefficient is said to be -4.04 cm ^-1 / GPa. When the biaxial stress is obtained from this, it means that a compressive stress of 1.47 GPa is generated. This value is 30% lower than the biaxial stress σ _xx value 2.11 GPa obtained from the 2θ-ω measurement of XRD, but it is still found that a large compressive stress is generated by Raman spectroscopy. It was also revealed from.

In addition, how to place the wafer and the angular deviation of the in-plane crystal orientation of the + cAlN crystal layer and the −cAlN crystal layer will be described. FIG. 15 is an X-ray diffraction pole figure of (10-12) of the nitride semiconductor substrate 1.

Since an angular deviation in the in-plane crystal orientation was expected between the + cAlN crystal layer and the -cAlN crystal layer depending on how the wafer was placed, the pole figure of (10-12) was measured and shown in FIG. The pole diagram is a mapping of the X-ray diffraction measurement results with the fanning angle χ in the radial direction of the circle and the rotation angle φ in the circumferential direction. Generally, it is used to evaluate the crystal orientation when the crystal grows on a dissimilar substrate, but in the present embodiment, the angle deviation of the in-plane crystal orientation between the + cAlN crystal layer and the −cAlN crystal layer is set. It is used for evaluation. Each graph of FIG. 15 is a result of selecting a point where the diffraction amount for measurement is maximum for the fanning angle χ, fixing the fanning angle χ, and rotating the nitride semiconductor substrate 1 for measurement.

Since the AlN crystal layer has a hexagonal crystal structure and the hexagonal crystal structure is rotationally symmetric six times, the peaks when observed from the six directions in the polar diagram also reflect the characteristics. There is. As far as the pole figure is seen, there is no deviation in each peak position, but in order to evaluate in more detail, the result of fine φ scan of each peak is also shown. In some observation results, a double peak waveform is seen, but the peak interval is 0.87 degrees at the maximum, and the angular deviation between the + cAlN crystal layer and the -cAlN crystal layer is suppressed to 1 degree or less. It can be said that. The angle of 1 degree is not a valid number that is required in principle, but considering the symmetry of the crystal, it is better that the angle deviation is as small as possible.

As described above, the nitride semiconductor substrate 1 having the polarity inversion layer structure according to the present embodiment is a semiconductor substrate having a polarity inversion structure, a flat surface, and a high quality crystal layer formed. As a result, the nitride semiconductor substrate 1 exhibits very good optical characteristics as crystals, so that it is possible to provide a nitride semiconductor substrate suitable for a light source such as an ultraviolet light emitting device.

[4. Effect, etc.]
As described above, according to the nitride semiconductor substrate 1 according to the present embodiment, a semiconductor substrate in which a group III nitride semiconductor buffer layer such as AlN is formed on a substrate such as sapphire is made into a semiconductor substrate set as a set of two. By heat-treating the group III nitride semiconductor buffer layers facing each other in close contact with each other, a semiconductor substrate having a steep polarity inversion layer on the order of atomic layers can be realized on a wafer scale. In addition, the heat treatment at this time can simultaneously improve the crystallinity. Further, according to the present invention, "a special joining pressure application mechanism combining a ball screw or a pneumatic cylinder and a bellows type linear introduction mechanism", which is indispensable for the conventionally used hydrophilized joining, and "surface activation joining" such as "Surface activation joining" It realizes a great effect that "high vacuum environment" can be eliminated.

As described with reference to FIG. 2, the absence of the amorphous layer in the polarity inversion layer is important for application to SHG devices and the like. In the SHG element, the maximum amplitude of the fundamental wave matches the bonding interface (polarity inversion layer) of AlN crystal layers with different polarities, and it is expected that light absorption will occur due to the overlap with the amorphous layer. be. More specifically, since the structure of the amorphous layer is disordered, band tailing occurs in which the refractive index and absorption coefficient change slowly, and in the SHG element that requires high light intensity, two photons that resonate with this tail level occur. Absorption is likely to occur, which can lead to large light absorption.

From this, the nitride semiconductor substrate 1 according to the present embodiment is suitable as a substrate for manufacturing a pseudo-phase matching type SHG device, as will be described later.

(Embodiment 2)
Next, the manufacturing apparatus 60 for the above-mentioned group III nitride semiconductor substrate set will be described.

FIG. 16 is a schematic configuration diagram of the manufacturing apparatus 60 according to the present embodiment. In order to facilitate understanding, FIG. 16 simplifies the manufacturing apparatus 60 and shows only a cross-sectional view and a main configuration when viewed from the front.

FIG. 16 shows the overall configuration of the manufacturing apparatus 60. The manufacturing apparatus 60 includes a heating furnace 61, a container 62, a container lid 63, a hole 64, a substrate assembly holder 65, a temperature sensor 66, a command device 67, a comparison device 68, a control device 69, and an inflow. It includes a gas pipe 70, an inflow gas control valve 71, an exhaust gas pipe 72, an exhaust gas control valve 73, and heating heaters 74a, 74b, 74c and 74d.

The heating furnace 61 is a furnace space in the manufacturing apparatus 60. A door (not shown) for opening and closing a nitride semiconductor substrate is provided in front of or behind the heating furnace 61 (not shown).

The overall shape of the heating furnace 61, which is the manufacturing apparatus 60, is a substantially rectangular cuboid or a substantially columnar shape. The material of the heating furnace 61 is a highly heat-resistant material such as carbon or boron nitride.

The container 62 is a container made of high-purity carbon. The container 62 also functions as a heat generating member when the heating method in the heating furnace 61 is induction heating. High-purity carbon is originally a substance that is stable against high temperatures, and has the characteristics of being easy to process and inexpensive.

The container lid 63 is a lid of the container 62, and is a container for making a semiconductor substrate set having an AlN buffer layer to be heat-treated integrally with the container 62 into a substantially airtight state.

The hole 64 is a hole for venting the inert gas filled in the heating furnace 61. The hole 64 is a hole for removing the gas in the container 62 when the inside of the heating furnace 61 is vacuum-replaced before starting the heating of the semiconductor substrate assembly. In the present embodiment, the holes 64 are provided in the container lid 63 at two locations with a diameter of about 1 mm. The hole 64 is not limited to the container lid 63, and may be provided in the container 62 of the container 62.

The substrate assembly holder 65 is arranged in the heating furnace 61 and is a holder for restricting the movement of the semiconductor substrate assembly when heating the above-mentioned semiconductor substrate assembly. Two sets of semiconductor board sets 81 are installed in the board set holder 65. Although the substrate assembly holder 65 uses high-purity carbon, it has melting points such as group III nitride semiconductors, carbon, boron nitride, aluminum oxide (sapphire), ceramics, silicon carbide, and refractory metals (molybdenum, tungsten, iridium, etc.). You can choose from high materials and alloys of these), zirconia, and tantalum carbide.

Although one temperature sensor 66 is shown in the drawing, a plurality of temperature sensors 66 are arranged in the heating furnace 61 in order to see the distribution of the internal temperature in the heating furnace 61. In this embodiment, the container lid 63 also serves as the lid of the substrate assembly holder 65, but an independent lid may be provided on the substrate assembly holder 65. The configuration of the board assembly holder 65 will be described in detail later.

The heating heaters 74a to 74d are arranged outside the heating furnace 61 and have a function of heating the substrate assembly holder 65 arranged inside the heating furnace 61. The heating heaters 74a to 74d are, for example, induction heating type heating heaters.

The command device 67 is a device that issues commands such as start, stop, heating control, vacuuming, and inflow / discharge control of inert gas, etc., according to the instructions of the operator. More specifically, the command device 67 uses a computer controlled by a program. As described above, there is also a program that replaces the inside of the heating furnace 61 with a vacuum and then raises the temperature at a high speed while inflowing nitrogen gas, and lowers the temperature rise rate to about 1/2 after 900 ° C to 1300 ° C. It is incorporated in this command device 67.

The comparison device 68 quantifies the measured value detected by the barometric pressure sensor (not shown) that detects the pressure in the heating furnace 61, and compares it with the instruction from the command device 67. The output of the comparison device 68 is transmitted to the control device 69, and outputs a signal for controlling the inflow gas control valve 71, the exhaust gas control valve 73, and the heating heaters 74a to 74d. The inflow gas pipe 70 and the exhaust gas pipe 72 are not limited to one, respectively. Further, since it is advantageous to keep the inflow gas at a high temperature at the time of raising the temperature, a heating device for the inflow gas (not shown) may be provided.

The manufacturing apparatus 60 for the nitride semiconductor substrate 1 according to the present embodiment is a buffer made of a group III nitride semiconductor having a thickness of 10 nm or more and 1000 nm or less inside the heating furnace 61 which is heated and controlled by the heating heaters 74a to 74d. It has a substrate assembly holder 65 that has a layer precursor and holds one or more sets of semiconductor substrates made of at least one of sapphire, silicon carbide, and aluminum nitride when the semiconductor substrate is heated. The heating heater may be induction heating, radio wave heating, resistance heating, combustion heating of gas, petroleum, etc., as long as it is controlled by a control device 69 or the like and uniformly overheats the inside of the heating furnace 61. ..

The heating furnace 61 at the time of heat treatment is once vacuum-replaced at room temperature in order to discharge impurities in the heating furnace 61. After that, while raising the temperature by the heating heaters 74a to 74d, an inert gas such as nitrogen, argon, or helium, or a gas obtained by adding ammonia to the inert gas enters the inside of the heating furnace 61 through the inflow gas control valve 71. Filled. In addition, organometallics such as ammonia, oxygen, silane (SiH ₄ ), monomethylsilane (SiH ₃ CH ₃ ), German (GeH ₄ ), trimethylaluminum (TMA), and trimethylgallium (TMG) are mainly composed of inert gas. Gas may also be mixed. The mixing ratio is preferably 20% or less with respect to the inert gas. Through the exhaust gas control valve 73, the nitrogen gas or the like is controlled to have a constant atmospheric pressure, and impurities generated in the furnace space are constantly discharged so as to be a constant amount or less.

Here, the gas that can be used may be a gas of a type other than the above, except for a corrosive gas such as chlorine, or may be used as a mixed gas. In order to produce the nitride semiconductor substrate 1 having the polar inversion layer structure described in the first embodiment, the temperature is 1300 ° C. or higher and 1750 ° C. or lower, and the time is 10 minutes or longer using a heating furnace as described above. The allowable range is 5 hours or less, preferably 30 minutes or more and 3 hours or less. Further, the temperature is controlled to a temperature between two different points (for example, 1400 ° C. and 1700 ° C.) of 1300 ° C. or higher and 1750 ° C. or lower multiple times every 10 to 20 minutes, or to be different temperatures (for example). It may be controlled by a temperature control device at 1400 ° C. for 10 minutes, 1500 ° C. for 30 minutes, and 1700 ° C. for 60 minutes. These temperatures and times are selected depending on the material of the substrate and the group III semiconductor layer.

Next, the substrate assembly holder 165 will be described with reference to FIG. 17A and 17B are schematic configuration views of the substrate assembly holder 165 according to the present embodiment, where FIG. 17A shows a top sectional view and FIG. 17B shows a side sectional view. The board set holder 165 shown in FIG. 17 corresponds to the board set holder 65 in FIG. 16, and three sets of semiconductor board sets 181 are installed inside.

As shown in FIG. 17, the substrate assembly holder 165 has an opening which is a space for accommodating the semiconductor substrate assembly 181 inside. Further, a lid 163 is arranged above the substrate assembly holder 165 so as to cover the opening.

Further, a hole 164 for gas replacement is provided inside the substrate assembly holder 165. The holes 164 are holes having a diameter of about 1 mm penetrating the side wall of the substrate assembly holder 165, and are provided in two or several places in the substrate assembly holder 165. Although it is necessary for vacuuming, the hole diameter is made small so that the movement of the inert gas inside the holder is minimized, and the gas does not substantially flow inside the substrate assembly holder 165. It is in a state.

Further, a weighting member 182 that presses the semiconductor substrate assembly 181 from above is arranged inside the substrate assembly holder 165. The weighting member 182 also has a function of adjusting the gap between the semiconductor substrate assembly 181 and the lid so as to be 0.5 mm or less, preferably 0.1 mm or less. The weight of the weighting member 182 is, for example, about 13 g or more and 14 g or less with respect to about four semiconductor substrates. The material of the weighting member is the melting point of group III nitride semiconductor, carbon, boron nitride, aluminum oxide (sapphire), ceramic, silicon carbide, refractory metal (molybdenum, tungsten, iridium, etc.) as well as the substrate assembly holder 165 and lid 163. You can choose from high materials and alloys of these), zirconia, and tantalum carbide.

Further, as shown in FIG. 17A, when the substrate assembly holder 165 is viewed from above, the orientation flat regulating member 183 is provided on a part of the side wall of the substrate assembly holder 165. As described with reference to FIG. 15, a plurality of orientation flat control members 183 are provided by pressing the orientation flat portion of the semiconductor substrate in order to reduce the influence of the deviation of the crystal axis of the semiconductor substrate assembly 181 housed in the substrate assembly holder 165. It is a member that unifies the arrangement position (orientation) of the semiconductor substrate in the plane. The shape of the orientation flat regulating member 183 is preferably the same as the shape of the cut portion of the orientation flat, but it may be a cylindrical shape having an elliptical cross section or a rectangular cuboid as shown in FIG. The material of the orientation flat regulating member 183 may be appropriately changed depending on the member of the substrate assembly holder 165.

(Embodiment 3)
Hereinafter, an SHG device (second harmonic generation element) using a nitride semiconductor substrate 1 having a polarity inversion layer using the nitride semiconductor of the present invention will be described with reference to the drawings.

Prior to the description of the SHG device, the performance of the semiconductor substrate having the single-layer AlN crystal layer heat-treated by the technique of Patent Document 1 will be described. In producing the polarity reversal type SHG device described later, a substrate having a single-layer AlN crystal layer after heat treatment according to Patent Document 1 was measured. FIG. 18 shows the results of X-ray diffraction locking curve measurement (XRC), (a) is the measurement result of the (0002) plane of the single-layer AlN crystal layer, and (b) is the result of (10) of the single-layer AlN crystal layer. -12) The measurement result of the surface is shown.

As shown in FIG. 18A, for the (0002) plane of the single-layer AlN crystal layer, the half width of the X-ray diffraction locking curve was 532 arcsec before the heat treatment, but became 49 arcsec after the heat treatment. ing. Further, as shown in FIG. 18B, for the (10-12) plane of the single-layer AlN crystal layer, the value of 6031 arcsec before the heat treatment becomes 287 arcsec after the heat treatment, and the crystallinity is greatly improved. ing.

FIG. 19 shows the measurement results of the spectral ellipsometry of the nitride semiconductor substrate 1. From the measurement results of the spectral _ellipsometry , the wavelength dispersions of the normal refractive index no and the abnormal refractive index _ne were measured.

The measurement results in FIG. 19 are consistent with the paper "R. Goldhahn," Dielectric Function of Nitride Semiconductors: Recent Experimental Results ", ACTA PHYSICA POLONICA A, Vol 104 (2003)", which studied the wavelength dispersion of the refractive index of nitrides. There was a tendency to do. In FIG. 19, no ( _FFA AlN) is the normal refractive index of the nitride semiconductor substrate 1, _ne (FFA AlN) is the abnormal refractive index of the nitride semiconductor substrate 1, and no ( _ref . [6]) is. The normal refractive index, _ne (ref. [6]) in the above-mentioned paper is the abnormal refractive index in the above-mentioned paper. The abnormal refractive index is the refractive index for the abnormal light ray, and is the refractive index for the electromagnetic wave polarized in the z-axis direction at the coordinates of FIG. 20 (a) described later. Similarly, the refractive index is the refractive index for ordinary light rays, and at the coordinates (a) in FIG. 20, it is the refractive index for electromagnetic waves polarized in any direction in the xy plane.

From the measurement results of FIG. 19, it was possible to experimentally confirm that the nitride semiconductor substrate 1 has good crystallinity and that the nitride semiconductor substrate 1 can be used as an optical element.

Here, if an optical system is assembled using an existing InGaN blue laser as a light source and an optical member that generates a second harmonic with an AlN crystal layer as a nonlinear optical crystal, ultraviolet light with high coherency is generated. be able to. Therefore, the SHG device using the AlN crystal layer of the nitride semiconductor substrate 1 manufactured by the above method as an optical member will be described below.

FIG. 20 is a schematic diagram showing the configuration of the SHG device by the steps shown in FIGS. 5 (e) and 5 (f). FIG. 20A is a schematic cross-sectional view of the SHG device 300. Further, FIG. 20B is a perspective view of the SHG device 300.

The SHG device 300 according to the present embodiment has a waveguide 301 and a clad layer 302 made of sapphire. The waveguide 301 has a + cAlN crystal layer 303 and a −cAlN crystal layer 304. The + cAlN crystal layer 303 and the −cAlN crystal layer 304 have a polarity inversion structure produced by the above-mentioned method.

Here, in the waveguide 301, the nitride semiconductor substrate 1 is used to form an AlN crystal layer having a polarity inversion structure into a waveguide having a waveguide width w, a waveguide thickness h, and a waveguide length l. It is a thing. At this time, the waveguide width w, the waveguide thickness h, and the waveguide length l are the incident of the laser beam incident on the direction of the waveguide length l, that is, the y-axis direction shown in FIG. 20 (a), as described later. Calculated based on the wavelength.

Here, the mechanism of the second harmonic generation centering on the polarity inversion layer will be described with reference to FIG. 20A.

The waveguide 301 composed of the + cAlN crystal layer 303 and the −cAlN crystal layer 304 has optical non-linearity. In order to obtain a second harmonic (SH wave) by the waveguide 301 having optical non-linearity, it is necessary to satisfy the phase matching condition. That is, since the light (fundamental wave) input to the waveguide 301 and the generated light (SH wave) have different speeds in the crystal, they cancel each other out when the phases of the light are different by π. Therefore, in the waveguide 301, it is common to perform phase matching by utilizing the birefringence of the anisotropic crystal. That is, the refractive indexes of the fundamental wave and the SH wave are matched by properly adjusting the angle of incidence on the anisotropic crystal. As a result, the phase matching condition is satisfied in the waveguide 301, so that the SH wave can be efficiently generated. The details of birefringence phase matching are described in "Basics of Harmonic Conversion by Nonlinear Optical Crystals" (Journal of Plasma and Fusion Research Vol.85, No.5 May 2009 P239-242).

Here, since the AlN crystal layer requires a large cost for producing a self-supporting substrate, the conventional birefringence phase matching method that requires an AlN crystal of several mm square is not practical. Moreover, since birefringence is weak, phase matching using birefringence is impossible in the deep ultraviolet wavelength region. Therefore, pseudo-phase matching using an AlN crystal layer (thin film) whose polarity has been inverted is used. The output from the SHG device 300 needs to satisfy the phase matching in the y-axis direction (propagation direction) and the z-axis direction (vertical direction) as shown by the following (Equation 1). At this time, the phase matching in the y-axis direction utilizes the mode dispersion in the waveguide, and the phase matching in the z-axis direction utilizes the polarity inversion of AlN. In (Equation 1), l is the waveguide length of the waveguide extending in the y-axis direction, k is the wave number of light, and d ₃₃ is the nonlinear optical coefficient.

First, the term related to the y-axis can be expressed as (Equation 2).

In (Equation 2), λ _ω indicates the wavelength of the fundamental wave, n _ω indicates the effective refractive index of the fundamental wave, and n 2 _ω indicates the effective refractive index of the SH wave. When the effective refractive indexes of the fundamental wave and the SH wave match, Δk becomes 0, and the first term shows 1 as a sinc function, so that high SHG efficiency can be obtained. Here, the general birefringence is not used, and the phase matching condition is satisfied by using the mode dispersion as described above. That is, by using a high-order mode in which the node of the electric field distribution exists in the center of the layer of the waveguide for the SH wave, the matching of the effective refractive index that does not match between the basal-order modes is realized.

20 (a) is a side view of the waveguide 301, and FIG. 20 (b) is a perspective view of the waveguide 301. In FIG. 20 (a), the electric field distribution (TM ₀₀ E _z ^ω ) of the fundamental wave propagating in the waveguide 301 formed by the AlN crystal layer and the electric field distribution (TM ₀₁ E _z 2 ^ω ) of the SH wave are shown by solid lines. Shows. Further, the electric field distribution diagram shown in FIG. 21 (a) is a _plot of the electric field distribution of ^TM ₀₀ E _z ^ω on the _xz plane in FIG. 21 (b). In FIGS. 21 (a) and 21 (b), the distribution indicated by Bl in the field shows a positive value, and the distribution indicated by Rd shows a negative value.

Here, TM means a Transverse magnetic mode, and in FIG. 20A, it refers to an electromagnetic wave in which a magnetic field component exists only in the x-axis direction. Further, the subscripts i and j of TM _ij represent the number of nodes of the electric field distribution in the x-axis direction and the z-axis direction, respectively. In FIG. 20 (a), TM ₀₀ E _z ^ω has no node, but TM ₀₁ E _z 2 ^ω has one node in the center. Taking advantage of the fact that AlN has a high refractive index and sapphire (Al ₂ O ₃ ) has a low refractive index, the effective refractive index of both can be adjusted by adjusting the electric field distribution in each material. In addition, in (a) of FIG. 20, the broken line described in the vicinity showing the curve of TM ₀₀ E _z ^ω and TM ₀₁ E _z 2 ^ω indicates the position of the electric field 0.

For example, the electric field distribution can be adjusted by appropriately adjusting the thickness h and the waveguide width w. Although the sapphire substrate 302 is left in FIG. 20 (b), as described in the stage of FIG. 5 (d), the substrate can be completely peeled off and another clad layer can be applied all around the circumference. In the case of the SHG element, if silicon oxide (SiO ₂ ) is used, the light confinement effect can be further improved and the wavelength conversion efficiency can be improved.

However, since TM ₀₁ ^{Ez 2ω} _has positive and negative electric fields, there is a problem that the overlap integral of the phase matching term becomes 0 in the case of an AlN film having a normal single polarity. Therefore, it is necessary to perform the above-mentioned polarity inversion and invert the code of the nonlinear optical coefficient d ₃₃ (z) at the film thickness corresponding to the node of the SH wave electric field distribution. As a result, the integral term of (Equation 1) becomes a non-zero value, and SHG light is output. Through these efforts, the phase matching conditions in the y-axis direction and the z-axis direction are finally satisfied, and highly efficient SHG output can be realized.

A detailed explanation of the pseudo-phase matching type SHG by mode dispersion phase matching and polarization inversion is described in the paper "Polymer waveguides with optimized overlap integral for modal dispersion phase matching".

In this way, if an optical system is assembled using an existing InGaN blue laser as a light source and an SHG device that generates a second harmonic using the AlN crystal layer of the nitride semiconductor substrate 1 as a nonlinear optical crystal, coherent properties can be obtained. Can generate high ultraviolet light.

The advantages of using the AlN crystal layer as a nonlinear optical crystal include the following three points.
(1) Since the absorption edge wavelength of the AlN crystal layer is 210 nm, it is transparent in a wide ultraviolet region.
(2) It has a nonlinear optical coefficient d ₃₃ higher than that of the existing nonlinear optical crystals BBO (barium borate) and CLBO (cesium cesium lithium borate).
(3) The AlN crystal layer is a chemically and mechanically stable material, and is not deliquescent and toxic like BBO and CLBO.

Next, FIG. 22 shows an example of the design of the waveguide 301 according to the present embodiment. The following shows an example of designing the waveguide width w in the waveguide 301. The horizontal axis of the graph shown in FIG. 22 is the waveguide width, and the vertical axis is the effective refractive index of the fundamental wave (incident wavelength λ ₁ = 532 nm) and the SH wave (emission wavelength λ ₂ = 266 nm). The film thickness of the AlN crystal layer constituting the waveguide 301 was h = 110 nm, and the waveguide length was l = 1 mm.

FIG. 22 shows a curve in which the effective refractive indexes n _{eff, 1} and n _{eff, 2} of TM ₀₀ Ez ^ω and TM ₀₁ Ez 2 ^ω change depending on the waveguide width w of the waveguide 301. When the waveguide width w of the waveguide 301 is set to the waveguide width w = 1.94 μm, which is the intersection of the two curves, the difference in the effective refractive index becomes zero, and the wavelength conversion efficiency becomes maximum. In this design, a wavelength of λ ₁ = 532 nm was used as the fundamental wave, because the SH wave of the YAG laser is used for the convenience of the measurement system. When performing wavelength conversion at a shorter wavelength, if the design is performed at a wavelength near λ ₁ = 450 nm, phase matching can be satisfied with an SH wave having λ ₂ = 225 nm.

Here, in the above-mentioned design example, the refractive index at the incident wavelength of the crystal layer is n ₁ when the incident wavelength is λ ₁ and the wavelength of the output light output from the SHG device is λ ₂ = λ _1/2 . When the refractive index at the emission wavelength is n ₂ , the film thickness (wavelength of the waveguide) h of the AlN crystal layer is fixed at h = 110 nm, and the value of the waveguide width w is changed, n ₁ = n ₂ . The value of the waveguide width w is obtained. The tolerance of n ₁ and n ₂ is preferably 0.1% or less, more preferably ± 0.005% when calculated by (n ₁ − n ₂ ) / n ₁ . The design of the waveguide 301 is not limited to this, and for example, a graph in which the value of the waveguide width w is fixed and the film thickness h of the AlN crystal layer is changed can be used.

As described above, as described above, the nitride semiconductor substrate on which the group III nitride semiconductor buffer layer such as AlN is formed is formed into a semiconductor substrate set as a set of two wafers, and the group III nitride semiconductor crystal layers are brought into close contact with each other facing each other. By performing the heat treatment, a semiconductor substrate having a steep polarity inversion layer on the order of atomic layers can be realized on a wafer scale. In addition, this heat treatment can also improve the crystallinity at the same time. Therefore, by processing the nitride semiconductor substrate 1 having the above-mentioned polarity inversion layer into a waveguide shape, a pseudo-phase matching type SHG device can be manufactured. As a result, a light emitting device having a wavelength of 200 nm can be realized by combining a semiconductor laser having a wavelength of 400 nm and the above-mentioned SHG device.

(Other embodiments)
Although the nitride semiconductor substrate, the method for manufacturing the nitride semiconductor substrate, and the nitride semiconductor device according to the present invention have been described above based on the embodiments, the present invention is not limited to the embodiments. The present invention also includes a form obtained by subjecting an embodiment to a modification that a person skilled in the art can think of, and another form realized by arbitrarily combining components in a plurality of embodiments.

For example, in the above-described embodiment, the nitride semiconductor substrate on which the group III nitride semiconductor buffer layer is formed is formed into a semiconductor substrate set as a set of two, and the group III nitride semiconductor crystal layers are brought into close contact with each other facing each other. The group III nitride semiconductor substrate to which the group III nitride semiconductor crystal layer obtained in the substrate peeling step was bonded and the group III nitride semiconductor substrate to which the group III nitride semiconductor buffer layer was formed were subjected to the heat treatment. The second semiconductor substrate set is set, and the group III nitride semiconductor crystal layers of each group III nitride semiconductor substrate of the second semiconductor substrate set are placed in close contact with each other facing each other in the heating furnace (second installation step). , May be heat-treated. Further, the second installation step, the heating step, and the substrate peeling step may be repeated a plurality of times in this order.

Further, the group III nitride semiconductor substrate obtained in the substrate peeling step has a crystal growth step of growing a crystal of the group III nitride semiconductor thin film on the group III nitride semiconductor crystal layer, which is obtained in the crystal growth step. The third semiconductor is a group III nitride semiconductor substrate formed by two group III nitride semiconductor substrates or a group III nitride semiconductor substrate obtained in the crystal growth step and a group III nitride semiconductor buffer layer. As a substrate set, the group III nitride semiconductor thin films of each group III nitride semiconductor substrate of the third semiconductor substrate set are placed in close contact with each other facing each other in a heating furnace (third installation step) and heat-treated. May be good. Further, the third installation step, the heating step, and the substrate peeling step may be repeated a plurality of times in this order.

Further, the configuration of the manufacturing apparatus, the shape of the holder, and the like are not limited to the above-mentioned configuration and shape, and may be appropriately changed.

INDUSTRIAL APPLICABILITY The present invention can be used for an ultraviolet light emitting element used as a light source for lighting, sterilization, photolithography, laser processing machine, medical equipment, DNA analyzer, light source for phosphor, spectral distribution analysis, ultraviolet curing and the like. .. In addition to optical devices, it can be expected to be applied to various electronic components.

1 Nitride semiconductor substrate 2, 2a, 2b Sapphire substrate 3, 3a, 3b, 5, 5a Aluminum nitride crystal layer (first group III nitride semiconductor crystal layer)
4, 6 Aluminum Nitride Crystal Layer (Second Group III Nitride Semiconductor Crystal Layer)
7, 302 Clad layer 61 Heating furnace 62 Container 63 Container lid 64 Hole 65, 165 Board assembly holder 66 Temperature sensor 67 Command device 68 Comparison device 69 Control device 70 Inflow gas piping 71 Inflow gas control valve 72 Exhaust gas piping 73 Exhaust gas control Valves 74a, 74b, 74c, 74d Heater 163 Lid 164 Hole 181 Semiconductor substrate assembly 182 Weighting member 183 Orifura regulation member 300 SHG device (nitride semiconductor device)
301 Waveguide 303 + cAlN crystal layer 304-cAlN crystal layer

Claims (16)

Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1 on the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. ), A group III nitride semiconductor crystal layer composed of an aggregate of crystal grains of a group III nitride semiconductor, and a polarity inversion layer having a group III polarity and a nitrogen polarity in the group III nitride semiconductor crystal layer. The structure is parallel to the surface of the substrate and has a structure.
The group III nitride semiconductor is aluminum nitride, gallium nitride, aluminum gallium nitride, or aluminum gallium nitride indium.
The thickness of the group III nitride semiconductor crystal layer is 20 nm or more and 2000 nm or less.
The polarity inversion layer structure is a bonding structure bonded at the atomic level .
The inside of the group III nitride semiconductor crystal layer constitutes an SHG (Second Harmonic Generation) element.
Nitride semiconductor substrate. The nitride semiconductor substrate according to claim 1, wherein the polarity inversion layer structure is formed by joining two group III nitride semiconductor crystal layers. The nitride semiconductor substrate according to claim 1 or 2, wherein the half width of the X-ray diffraction locking curve on the (10-12) plane of the group III nitride semiconductor crystal layer is 1000 arcsec or less. The nitride semiconductor substrate according to any one of claims 1 to 3, which has two or more polar inversion layer structures in the group III nitride semiconductor crystal layer. Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, (x + y) ≦ 1 on the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon. ), A group III nitride semiconductor substrate on which a group III nitride semiconductor buffer layer composed of aggregates of crystal grains of the group III nitride semiconductor is formed is used as a set of two to form a first semiconductor substrate set. The first installation step of arranging the group III nitride semiconductor crystal layers of each group III nitride semiconductor substrate of the first semiconductor substrate group facing each other and installing them in the heating furnace,
A heating step of heating the first semiconductor substrate set while controlling the temperature of the heating furnace to 1300 ° C. or higher and 1750 ° C. or lower.
A substrate peeling step of peeling at least one of the two bonded group III nitride semiconductor substrates is included.
In the first installation step, the first semiconductor substrate set is housed in a holder for restricting the movement of the first semiconductor substrate set, and the opening of the holder is opened by a cover member that closes the opening of the holder. Closed, the gap between the cover member and the facing substrate is set to 0.5 mm or less.
Supplying the inert gas into the heating furnace during heating
A method for manufacturing a nitride semiconductor substrate. It has a film forming step of growing a group III nitride semiconductor buffer layer on the group III nitride semiconductor crystal layer of the group III nitride semiconductor substrate obtained in the substrate peeling step.
The thickness of the group III nitride semiconductor buffer layer is 10 nm or more and 1000 nm or less.
The amount of warpage of the semiconductor substrate is 30 μm or less, and the amount of warpage is 30 μm or less.
In the first installation step, the first semiconductor substrate set is arranged in the holder so that the D-cut surfaces of the group III nitride semiconductor substrate are aligned, or the D-cut surface of the group III nitride semiconductor substrate is arranged. The method for manufacturing a nitride semiconductor substrate according to claim 5 , wherein the nitride semiconductor substrate is installed in an arrangement facing ± 60 °, ± 120 °, or 180 ° from the aligned positions. The method for manufacturing a nitride semiconductor substrate according to claim 5 or 6 , wherein a plurality of the first semiconductor substrate sets are installed in the holder in the first installation step. The group III nitride semiconductor in which the group III nitride semiconductor crystal layers of the group III nitride semiconductor substrate obtained in the substrate peeling step are bonded to each other or the group III nitride semiconductor crystal layers obtained in the substrate peeling step are bonded to each other. The substrate and the group III nitride semiconductor substrate on which the group III nitride semiconductor buffer layer is formed are used as a second semiconductor substrate group, and the III of each of the group III nitride semiconductor substrates of the second semiconductor substrate group is used. The method for manufacturing a nitride semiconductor substrate according to any one of claims 5 to 7 , further comprising a second installation step of placing the group nitride semiconductor crystal layers facing each other in close contact with each other in a heating furnace. The method for manufacturing a nitride semiconductor substrate according to claim 8 , wherein the second installation step, the heating step, and the substrate peeling step are repeated a plurality of times in this order. It has a crystal growth step of growing a crystal of a group III nitride semiconductor thin film on the group III nitride semiconductor crystal layer of the group III nitride semiconductor substrate obtained in the substrate peeling step.
The two group III nitride semiconductor substrates obtained in the crystal growth step or the group III nitride semiconductor substrate obtained in the crystal growth step and the group III nitride semiconductor buffer layer are formed. The group III nitride semiconductor substrate is used as a third semiconductor substrate group, and the group III nitride semiconductor thin films of each of the group III nitride semiconductor substrates of the third semiconductor substrate group are brought into close contact with each other in a heating furnace. The method for manufacturing a nitride semiconductor substrate according to any one of claims 5 to 7 , which comprises a third installation step of installing the nitride semiconductor substrate. The method for manufacturing a nitride semiconductor substrate according to claim 10 , wherein the third installation step, the heating step, and the substrate peeling step are repeated a plurality of times in this order. The group III nitride semiconductor is aluminum nitride, gallium nitride, aluminum gallium nitride, or aluminum gallium nitride indium.
The material of the holder is at least one of group III nitride semiconductor, carbon, boron nitride, aluminum oxide (sapphire), ceramic, silicon carbide, refractory metal (molybdenum, tungsten, iridium and alloys thereof), zirconia, and tantalum carbide. The method for manufacturing a nitride semiconductor substrate according to any one of claims 5 to 11 . In the heating step, the temperature of the heating furnace is controlled multiple times during one heating to a temperature between two different points of 1300 ° C. or higher and 1750 ° C. or lower, or controlled to a plurality of different temperatures. Item 6. The method for manufacturing a nitride semiconductor substrate according to any one of Items 5 to 12 . With a heating furnace,
A heater that heats the heating furnace and
A control device that controls the temperature inside the heating furnace by controlling at least the heater, and
Al _x Gay In _{(1-xy) N} (0 ≦ x ≦ 1, 0 ≦ y) is placed on the surface of a substrate composed of sapphire, silicon carbide, aluminum nitride, and silicon, which is arranged in the heating furnace. A semiconductor consisting of a set of two group III nitride semiconductor substrates on which a group III nitride semiconductor buffer layer composed of aggregates of crystal grains of a group III nitride semiconductor represented by ≤1 and (x + y) ≤1) is formed. A holder that has an opening for accommodating a plurality of substrate sets and regulates the movement of the semiconductor substrate set housed in the opening.
It has a lid arranged in the heating furnace and arranged so as to cover the opening of the holder.
The group III nitride semiconductor crystal layers of each of the group III nitride semiconductor substrates of the semiconductor substrate set face each other and adhere to each other.
The opening and the holder have a depth for accommodating a plurality of the semiconductor substrate sets.
A nitride semiconductor substrate manufacturing apparatus in which a weighting member that applies a load to the semiconductor substrate set is installed on the plurality of semiconductor substrate sets. The nitride semiconductor substrate according to claim 14 , wherein the control device controls the temperature of the heating furnace to a temperature between two different points of 1300 ° C. or higher and 1750 ° C. or lower a plurality of times, or controls the temperature to a plurality of different temperatures. manufacturing device. Nitride semiconductor device
Using the nitride semiconductor substrate according to any one of claims 1 to 4, the group III nitride semiconductor crystal layer is formed in a waveguide having a width w, a thickness h, and a length l.
The width w, the thickness h, and the length l are calculated based on the incident wavelength of the laser beam incident in the direction of the length l .
When the incident wavelength is λ1 and the wavelength of the _output light of the nitride semiconductor device is λ2, the refractive index at the incident wavelength of the group III nitride semiconductor crystal layer is n1 and the refractive index at the emission wavelength is n2 _. , W when n ₁ = n ₂ when the unfixed value of the width w or the thickness h is changed after fixing one of the values of the width w or the thickness h. Or the value of h is calculated,
The group III nitride semiconductor crystal layer other than the entrance surface and the exit surface in the length l direction is covered with a protective layer.
Nitride semiconductor device.

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