JP7098695B2 - Anomaly detection method for electronic devices and their startup - Google Patents

Description

The present invention relates to a self-diagnosis technique for detecting an abnormal state in an electronic device.

A general electronic device has a user interface (hereinafter referred to as "UI") for displaying information and accepting operations to a user. This UI is also used to notify when an abnormality occurs in the device, but if any abnormality occurs in the part related to the screen display of the UI, the notification of the occurrence of the abnormality cannot be displayed. .. In this case, the user or the like cannot know where and what kind of abnormality has occurred in the device, and it takes a lot of time and effort to identify the abnormal part and grasp its contents.

In this regard, for example, in Patent Document 1, the display mode of the display LED when a failure occurs is determined in advance for each of a plurality of circuit blocks of the electronic device, and when the failure is detected, the place where the failure occurs is determined. A technique for identifying a faulty part by lighting an LED in a corresponding display mode is disclosed.

Japanese Unexamined Patent Publication No. 10-268850

In the above-mentioned conventional technique, a microcomputer connected to a plurality of circuit blocks via a bus fails by taking in the diagnosis result determined and held in each block via an I / O port with each circuit block. Notification control is performed (see FIG. 1 and the like in Patent Document 1). Here, if the technology of Patent Document 1 is applied to a multifunctional electronic device such as an MFP (Multi Function Peripheral) having a plurality of functions such as print, copy, and fax, the number of modules subject to failure detection increases, and the failure occurs. The number of I / O ports between the main controller responsible for notification control and each functional module increases, leading to an increase in cost.

Further, in the case of an electronic device in which the above-mentioned UI display control is performed by a module independent of the main controller, an abnormality related to the UI display cannot be detected unless an I / O port for connecting the module and the main controller is provided. Furthermore, if the UI display operates normally, it is sufficient to notify the failure by the screen display on the UI. There is no need to bother to use LEDs to notify even failures that are not related to UI display.

Therefore, one aspect of the present invention is to provide a mechanism for diagnosing an abnormality related to UI display. Another aspect of the present invention is that in an electronic device that controls UI display with a module independent of the main controller, it is possible to detect an abnormality related to UI display and notify a user or the like without increasing the number of I / O ports. The purpose is to.

The electronic device according to the present invention is an electronic device in which a display and a device for supplying a signal to the display are electrically connected, and an image to be displayed on the display and a control signal for controlling the display are obtained. The image processing means to be output to the display, the determination means for determining whether or not the control signal is normal, and the notification means for notifying based on the result of the determination are provided , and the determination means is provided to the display. If the control signal does not change within a predetermined period after the signal indicating that the power supply is normal is input, it is determined as an abnormality of the display .

According to the present invention, in an electronic device that controls UI display with a module independent of the main controller, an abnormality related to UI display is detected without increasing the number of I / O ports, and the occurrence of the abnormality is notified to a user or the like. can do.

System configuration diagram including MFP according to the first embodiment Block diagram showing the internal configuration of the main controller and UI module (A) is a block diagram showing the internal structure of the self-diagnosis device, and (b) is a block diagram showing the internal structure of the self-diagnosis unit. (A) is a block diagram showing the details of the first abnormality detection unit and the second abnormality detection unit in the self-diagnosis device, and (b) is a block diagram showing the details of the abnormality detection unit in the self-diagnosis unit. A timing chart that explains the detection operation (normal time) of the first abnormality detection unit and the second abnormality detection unit in the self-diagnosis device. (A) is a timing chart explaining the operation when an abnormality in the startup sequence of the main CPU is detected, and (b) is a timing chart explaining the operation when an abnormality in the power supply sequence of the second power supply is detected. Timing chart explaining the detection operation (normal time) of the abnormality detection unit in the self-diagnosis unit A timing chart that explains the operation when an abnormality in the image display sequence of the LCD is detected. (A) to (c) are flowcharts showing the flow of abnormality detection control at the time of starting the MFP. A diagram showing an example of an error display screen

Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the following embodiments do not limit the present invention, and not all combinations of features described in the present embodiment are essential for the means for solving the present invention.

Embodiment 1

(System configuration)
FIG. 1 is a system configuration diagram including an MFP 100 as an electronic device to which this embodiment can be applied. The MFP 100 is composed of a main controller 101, a dedicated module 102 that handles a user interface, a scanner 103, a printer 104, a first power supply 105, and a second power supply 106, and is connected to the server 110 via a LAN 120. For convenience of explanation, the dedicated module 102 that bears the user interface is hereinafter referred to as "UI module 102". The server 110 is an information collection server that acquires and stores error information and the like of the MFP 100. Although not shown in FIG. 1, one or a plurality of PCs that send print jobs to the MFP 100 are connected to the LAN 120. Further, the MFP 100 is also connected to a device having a FAX communication function via a telephone line (not shown). Hereinafter, an outline of the hardware configuration of the MFP 100 will be described with reference to FIG. 1.

(Hardware configuration of MFP)
The main controller 101 is a module that is responsible for the main control that collectively controls each part of the MFP 100. For example, it converts and stores various data, sends and receives various data to and from the server 110, and controls the power supplied to the inside of the MFP 100. The UI module 102 is a module responsible for controlling the UI display, which is responsible for displaying and operating various information for displaying various information to the user and for the user to perform various input operations. The scanner 103 is a module that optically reads a document placed on a document table (not shown) or an ADF (Auto Document Feeder) to acquire image data. The printer 104 is a module that prints out various image data processed by the main controller 101. The first power supply 105 and the second power supply 106 are modules that convert the AC commercial power supply supplied from the power supply plug 107 into a DC power supply and supply it to the inside of the MFP 100. The power supply of the second power supply 106 is controlled to be turned on / off by a power supply control signal from the main controller 101. In the normal power mode, both the first power supply 105 and the second power supply 106 are turned on, and power is supplied to predetermined supply destinations as described later. On the other hand, in the power saving mode, the first power supply 105 remains on, but the second power supply 106 is turned off. Here, the power saving mode is an operation of reducing power consumption by stopping the power supply except for a predetermined device in the main controller 101 when the MFP 100 is in a hibernation state in which various jobs are not processed. Refers to the mode. The main controller 101 can accept a job even in this power saving mode, and when the job is accepted, a High power control signal is output to the second power supply 106 to switch the second power supply 106 on, and the normal power mode is entered. And migrate.

(Details of hardware configuration)
Next, the main controller unit 101 and the UI module 102, which are important components of the MFP 100 in the present embodiment, will be described in detail. FIG. 2 is a block diagram showing an internal configuration of the main controller 101 and the UI module 102. In FIG. 2, among the lines connecting to each block, the thick line indicates the power supply line and the thin line indicates the signal line.

<Main controller>
First, the main controller 101 will be described in detail. The main controller 101 includes a main CPU 201, an IO controller 205, a scanner I / F207, and a printer I / F208. Further, the main controller 101 includes each device of the image generation device 202, the self-diagnosis device 203, the power supply control device 204, the image processing device 206, and the second power supply voltage detection device 209. The main CPU 201, which collectively controls the inside of the main controller 101, is an example of a processor including a hardware circuit. The main CPU 201 controls an image generation device 202 such as a GPU (Graphics Processing Unit) to generate an image to be displayed by the UI module 102. Further, the main CPU 201 controls communication with an external device connected to the LAN 120 via a LAN controller (not shown). The self-diagnosis device 203 self-diagnoses the presence or absence of an abnormality in each device in the main controller 101 and each module connected to the main controller 101 when the MFP 100 is started, and if an abnormality is detected, what is wrong. To identify. Here, the "start-up" of the MFP 100 includes both when the main power switch (not shown) is turned on and when the MP 100 returns from the above-mentioned power saving mode and shifts to the normal power mode. As the self-diagnosis device 203, for example, a CPLD (Complex Programmable Logic Device) is used. Details of the self-diagnosis device 203 will be described later.

The power control device 204 receives power from the first power supply 105, and supplies power to the inside of the main controller 101 and other modules connected to the main controller 101 based on the diagnosis result of the self-diagnosis device 203 and the like. Control. The DC power supply from the first power supply 105 is supplied to the self-diagnosis device 203 in the main controller 101, the power supply control device 204, the IO controller 205, and the sub CPU 210 in the UI module 102. Then, the DC power supply from the second power supply 106 is supplied to the remaining devices / modules that do not operate in the power saving mode such as the main CPU 201. The IO controller 205 is connected to the main CPU 201 by, for example, PCI Express, and controls the UI module 102. Further, the IO controller 205 is connected to the self-diagnosis device 203 by an internal bus. The main CPU 201 accesses the self-diagnosis device 203 via the IO controller 205, and controls each device and the UI module 102 in the main controller 101 according to the diagnosis result stored in the self-diagnosis device 203. In FIG. 2, the nighttime power supply supplied from the first power supply 105 and the power supply supplied from the second power supply 106 are directly connected to each block indicating the device or module. However, the configuration is not limited to such a configuration, and a configuration in which a DC-DC converter or a regulator is used to branch to a power supply voltage required for each block may be used. However, the nighttime power supply supplied from the first power supply 105 is supplied at an earlier timing than the power supply supplied from the second power supply 106.

The image processing device 206 performs various image processing on the input image data. The scanner I / F 207 receives the scanned image data from the scanner 103 and outputs it to the image processing device 206. The printer I / F 208 outputs the image data processed by the image processing device 206 to the printer 104. The second power supply voltage detection unit 209 detects the DC power supply from the second power supply 106 and checks whether or not the DC power supply is normally supplied. Specifically, when it is detected that the power supply from the second power supply 106 to each part in the main controller 101 is performed at a normal voltage level, a 2nd Power Good signal is generated. When this 2nd Power Good signal is asserted, the main CPU 201 starts to start.

<UI module>
Next, the UI module 102 will be described in detail. The UI module 102 includes a sub CPU 210, an image conversion device 211, an LCD 212, an LCD power supply 213, an LCD power supply voltage detection device 214, and an LED 215. The sub CPU 210 for controlling each part in the UI module 102 is connected to the IO controller 205 by, for example, a UART, and communicates between the main CPU 201 and the CPU via the IO controller 205. The UART is an integrated circuit that converts a serial communication signal and a parallel communication signal, and is an abbreviation for Universal Asynchronous Receiver-Transmitter.

The self-diagnosis unit 216 exists in the sub CPU 210. The self-diagnosis unit 216 diagnoses the presence or absence of an abnormality related to the UI display including disconnection or disconnection of the cable between the main controller 101 and the UI module 102 when the MFP 100 is started. At the time of this startup, as described above, the time of returning from the power saving mode is included. Then, when the self-diagnosis unit 216 detects an abnormality, the sub CPU 210 notifies the main CPU 201 that an abnormality related to the UI display has occurred by communication between CPUs via the IO controller 205. The details of the self-diagnosis unit 216 will be described later.

The image conversion device 211 converts the DisplayPort standard image for UI display output from the image generation device 202 into an LVDS standard image that can be output by the LCD 212. The LCD power supply unit 213 supplies power for the backlight of the LCD 212 in response to the power supply control signal from the power supply control device 204. When the LCD power supply voltage detection device 214 detects by the power supply voltage (LCD VCC) that the power supply from the LCD power supply unit 213 to the LCD 212 is performed at a normal voltage level, the LCD Power Good signal is generated and output to the sub CPU 210. .. Further, at least a part of the control signals from the image conversion device 211 to the LCD 212 is input to the sub CPU 210, and is used for diagnosing the presence or absence of an abnormality related to the UI display in the self-diagnosis unit 216 in the sub CPU 210. The control signal from the image conversion device 211 to the LCD 212 controls, for example, a Panel power enable signal for turning on the panel power, a Backlight enable signal for turning on the backlight, and a PWM frequency of the backlight. There are PWM signals and so on. The LED 215 is a light emitting element for notifying the user of the occurrence of the abnormality when the self-diagnosis device 203 or the self-diagnosis unit 216 detects an abnormality. In the present embodiment, the lighting / extinguishing of the LED 215 is controlled by the self-diagnosis device 203 and the main CPU 201 via the IO controller 205.

(Self-diagnosis device)
Subsequently, the self-diagnosis device 203 in the main controller 101 will be described in detail. FIG. 3A is a block diagram showing the internal structure of the self-diagnosis device 203. First, the outline of the diagnosis in the self-diagnosis device 203 will be described with reference to FIG. 3 (a).

The self-diagnosis device 203 includes a first abnormality detection unit 301, a second abnormality detection unit 302, an internal clock generation unit 303, and a diagnosis result holding unit 304. The self-diagnosis device 203 of the present embodiment has two abnormality detection units, but may be configured to have one or three or more. The self-diagnosis device 203 detects different types of abnormalities generated in the MFP 100 based on two types of monitoring signals input to the first abnormality detecting unit 301 and the second abnormality detecting unit 302, respectively. Specifically, the first abnormality detection unit 301 detects an operation abnormality of the main CPU 201, and the second abnormality detection unit 302 detects a supply abnormality of the second power supply 106.

Here, two types of monitoring signals input to each abnormality detection unit will be described. One of the monitoring signals is a signal (hereinafter, referred to as “trigger signal”) that changes at the start of the sequence, which is a trigger in the sequence to be diagnosed. The other monitoring signal is a signal for determining whether or not there is an abnormality in the diagnosis target sequence (hereinafter, referred to as a "check signal"). The check signal is preferably a signal that can confirm that the diagnosis target sequence has been completed normally, but is not limited to this.

The internal clock generation unit 303 generates a drive clock signal to be used in the self-diagnosis device 203, and outputs the drive clock signal to the first abnormality detection unit 301, the second abnormality detection unit 302, and the diagnosis result holding unit 304. By using a clock signal independent of the system clock signal used in the main controller 101, it is possible to detect and display an abnormality even when the system clock generator (not shown) is not operating. .. When the first abnormality detection unit 301 and the second abnormality detection unit 302 detect an abnormality, they output a high level abnormality detection signal to the diagnosis result holding unit 304, respectively. In response to this, the diagnosis result holding unit 304 outputs an interrupt signal to the IO controller 205. When the interrupt signal is input, the IO controller 205 accesses a register (not shown) in the diagnosis result holding unit 304 and confirms the content of the abnormality.

<Details of anomaly detection unit>
FIG. 4A is a block diagram showing details of the first abnormality detection unit 301 and the second abnormality detection unit 302. The first abnormality detection unit 301 includes a first timer 401 and a first abnormality determination unit 402, and the second abnormality detection unit 302 includes a second timer 403 and a second abnormality determination unit 404.

The first abnormality detection unit 301 detects an abnormality in the main CPU 201 by using the 2nd Power Good signal from the second power supply voltage detection unit 209 as the above-mentioned trigger signal and the operation signal of the main CPU 201 as the above-mentioned check signal. .. The 2nd Power Good signal is input to the first timer 401, and the main CPU operation signal is input to the first abnormality determination unit 402. Here, the main CPU operation signal is obtained by softly writing High to the register in the self-diagnosis device 203 via the internal bus when the IO controller 205 accesses the main CPU 201 when the IO controller 205 starts up and receives a response. Occur. That is, the main CPU operation signal is a signal that changes from the Low level to the High level before the first timer 401 finishes the above-mentioned count when the main CPU 201 is normally started. The first timer 401 operates on the internal clock signal and starts counting for a predetermined time (for example, 10 sec) when the input 2nd Power Good signal changes to the High level. Then, the first abnormality determination unit 402 diagnoses the main CPU abnormality signal indicating that the main CPU 201 has not started normally when the main CPU operation signal is not at the high level at the time when the count of the predetermined time by the first timer 401 has elapsed. Output to the holding unit 304.

The second abnormality detection unit 303 uses the power supply control signal for turning on the second power supply 106 as the above-mentioned trigger signal and the 2nd Power Good signal from the second power supply voltage detection unit 209 as the above-mentioned check signal. The supply abnormality of the second power source 106 is detected. The power supply control signal for the second power supply 106 is input to the second timer 403, and the 2nd Power Good signal is input to the second abnormality determination unit 404.

The second timer 403 operates with an internal clock signal, and when a power control signal for the second power supply 106 is input, it starts counting for a predetermined time (for example, 2 sec). When the power is normally supplied from the second power supply 106, the above-mentioned 2nd Power Good signal changes from the Low level to the High level before the second timer 403 finishes counting for a predetermined time. Therefore, the second abnormality determination unit 404 indicates that the power is not normally supplied from the second power supply 106 when the 2nd Power Good signal is not at the high level at the time when the count of the predetermined time by the second timer 403 has elapsed. The power supply abnormality signal is output to the diagnosis result holding unit 304.

<Timing of abnormality detection>
5 and 6 are timing charts illustrating the detection operations of the first abnormality detection unit 301 and the second abnormality detection unit 302. First, the timing chart will be described from the timing chart when there is no problem in the boot sequence of the main CPU 201 and the power supply sequence of the second power supply unit 106 shown in FIG.

When the main power switch (not shown) of the MFP 100 is turned on, the power supply from the first power supply 105 is started, and the power supply from the second power supply 106 is started with a slight delay. The power supply control signal for turning on the second power supply 106 is input to the second abnormality detection unit 302 as a second trigger signal, whereby the second timer 403 starts counting. If the 2nd Power Good signal as the second check signal is at the High level when the predetermined time t_2 has elapsed (counted up) in the second timer 403, the second abnormality determination unit 404 will supply power from the second power supply 106. Judging that it was done normally, the second power supply abnormality signal is maintained at the Low level. Next, when the 2nd Power Good signal as the first trigger signal reaches the High level, the first timer 401 in the first abnormality detection unit 302 starts counting. If the main CPU operation signal as the first check signal is at the High level when the predetermined time t_1 elapses (counts up) in the first timer 401, the first abnormality determination unit 402 determines that the main CPU 201 has started normally. do. Then, the main CPU abnormality signal is also maintained at the Low level. The diagnosis result holding unit 304 indicates that there is no abnormality in the start sequence of the main CPU 201 or the power supply sequence by the second power supply 106 in the internal register (not shown) in response to the fact that all the abnormality signals are at the Low level. Save the flags etc. as the diagnosis result. In this case, it is assumed that the internal register of the diagnosis result holding unit 304 has at least the number of bits equal to or greater than the number of abnormality detecting units. Then, the diagnosis result holding unit 304 outputs an interrupt signal to the IO controller 205 via the internal bus. Upon receiving the interrupt signal, the IO controller 205 accesses the internal register of the diagnosis result holding unit 304 to acquire the diagnosis result, and it is confirmed that there is no abnormality.

Next, the timing chart when there is an abnormality in the boot sequence of the CPU 201 shown in FIG. 6A will be described. When the 2nd Power Good signal as the first trigger signal reaches the High level, the first timer 401 in the first abnormality detection unit 301 starts counting. Since the main CPU operation signal as the first check signal remains at the Low level when the predetermined time t_1 elapses (counts up) in the first timer 401, the first abnormality determination unit 402 sets the activation sequence of the main CPU 201. Judge that there is an abnormality. Then, the main CPU abnormality signal output to the diagnosis result holding unit 304 is changed to the High level. On the other hand, since there is no abnormality in the power supply sequence of the second power supply 106, the output of the second power supply abnormality signal maintains the Low level. The diagnosis result holding unit 304 receives that the main CPU abnormality signal is at the High level and the second power supply abnormality signal is at the Low level, and stores the diagnosis result indicating the contents in the internal register. That is, although there is no abnormality in the power supply sequence of the second power supply 106, a flag or the like indicating that there is an abnormality in the startup sequence of the main CPU 201 is saved. Then, the diagnosis result holding unit 304 outputs an interrupt signal to the IO controller 205 via the internal bus. Upon receiving the interrupt signal, the IO controller 205 accesses the internal register of the diagnosis result holding unit 304 to acquire the diagnosis result, and the abnormality of the main CPU 201 is confirmed.

Next, a timing chart when there is an abnormality in the power supply sequence of the second power supply 106 shown in FIG. 6B will be described. When the power supply control signal as the second trigger signal reaches the High level, the second timer 403 in the second abnormality detection unit 302 starts counting. Since the 2nd Power Good signal as the second check signal remains at the Low level when the predetermined time t_2 has elapsed (counted up) in the second timer 403, the second abnormality determination unit 404 is normal from the second power supply 106. It is judged that the power supply is not performed. Then, the second power supply abnormality signal output to the diagnosis result holding unit 304 is changed to the High level. Since the 2nd Power Good signal remains at the Low level, the first timer 401 in the first abnormality detection unit 301 does not start counting (omitted in FIG. 6B). When an abnormality is detected in the power supply of the second power supply 106 in this way, the occurrence of the abnormality is notified the next time the reboot process is performed and the same abnormality is detected. That is, when the diagnosis result holding unit 304 detects an abnormality in the same power supply sequence after rebooting, it outputs an interrupt signal to the IO controller 205 via the internal bus. Upon receiving the interrupt signal, the IO controller 205 accesses the internal register of the diagnosis result holding unit 304 to acquire the diagnosis result, and an abnormality in the power supply sequence of the second power supply 106 is confirmed.

In this way, in the self-diagnosis device 203 in the main controller 101, the two abnormality detection units diagnose whether there is an abnormality in the startup sequence of the main CPU 201 and whether there is an abnormality in the power supply sequence of the second power supply 106. Will be.

(Self-diagnosis department)
Subsequently, the self-diagnosis unit 216 in the sub CPU 210 will be described in detail. FIG. 3B is a block diagram showing the internal structure of the self-diagnosis unit 216. In the present embodiment, the self-diagnosis unit is provided as one of the functions in the sub CPU 210, but it may be provided in the UI module 102 as a device independent of the sub CPU 210. First, the outline of the diagnosis in the self-diagnosis unit 216 will be described with reference to FIG. 3 (b).

The self-diagnosis unit 216 is composed of an abnormality detection unit 311, an internal clock generation unit 312, and a diagnosis result holding unit 313, similarly to the self-diagnosis device 203 described above. The self-diagnosis unit 216 of the present embodiment has one abnormality detection unit, but may have two or more units. Similar to the self-diagnosis device 203, the self-diagnosis unit 216 diagnoses the presence or absence of an abnormality related to the UI display in the UI module 102 based on the two types of monitoring signals input to the abnormality detection unit 311.

<Details of anomaly detection unit>
FIG. 4B is a block diagram showing details of the abnormality detection unit 311. The abnormality detection unit 311 includes a timer 411 and an abnormality determination unit 412. The abnormality detection unit 311 uses the LCD Power Good signal from the LCD power supply voltage detection unit 214 as the trigger signal and the Backlight enable signal as the check signal, respectively, and detects an abnormality in the image display for the UI by the LCD 212. The Backlight enable signal as the check signal is just an example, and may be the Panel power enable signal or the PWM signal described above. Further, when an organic EL is used for the UI display instead of the LCD, the signal required for the control may be a check signal. The LCD Power Good signal is input to the timer 411, and the Backlight enable signal is input to the abnormality determination unit 412. The timer 411 operates on the internal clock signal and starts counting for a predetermined time (for example, 3 sec) when the input LCD Power Good signal changes to the High level. Then, the abnormality determination unit 412 outputs an LCD abnormality signal indicating that the LCD 212 is not operating normally to the diagnosis result holding unit 313 when the Backlight enable signal is not at the High level at the time when the timer 411 counts for a predetermined time. In this way, the abnormality detection unit 311 in the self-diagnosis unit 214 detects the presence or absence of an abnormality in the image display by the LCD 212.

<Timing of abnormality detection>
7 and 8 are timing charts illustrating the detection operation of the abnormality detection unit 311. First, the timing chart when there is no abnormality in the image display sequence of the LCD 212 shown in FIG. 7 will be described.

When the main power switch (not shown) of the MFP 100 is turned on, the power supply from the first power supply 105 is started, and the power supply from the second power supply 106 is started with a slight delay. Then, when the LCD power supply 213 starts supplying power according to the power supply control signal from the power supply control device 204, the LCD power supply voltage detection unit 214 outputs a high level LCD Power Good signal to the sub CPU 210. This LCD Power Good signal is input to the abnormality detection unit 311 in the self-diagnosis unit 216, whereby the internal timer 411 starts counting. If the Backlight enable signal as a check signal is at the High level when the predetermined time t elapses (counts up) in the timer 411, the abnormality determination unit 412 determines that there is no abnormality in the image display sequence of the LCD 212, and the LCD abnormality. Leave the signal at Low level. In response to the fact that the LCD abnormality signal is at the Low level, the diagnosis result holding unit 313 stores a flag or the like indicating that there is no abnormality in the LCD 212 in the internal register (not shown) as the diagnosis result. It is the same as the above-mentioned diagnosis result holding unit 304 in that the internal register of the diagnosis result holding unit 311 has at least the number of bits equal to or more than the number of abnormality detecting units. Then, the diagnosis result holding unit 311 outputs an interrupt signal to the IO controller 205 via the above-mentioned UART. Upon receiving the interrupt signal, the IO controller 205 accesses the internal register of the diagnosis result holding unit 311 to acquire the diagnosis result, and it is confirmed that there is no abnormality in the image display sequence of the LDC 212.

Subsequently, a timing chart when there is an abnormality in the image display sequence of the LCD 212 shown in FIG. 8 will be described. When the LCD Power Good signal as the trigger signal reaches the High level, the timer 411 in the abnormality detection unit 311 starts counting. Since the Backlight enable signal as the check signal remains at the Low level when the predetermined time t elapses (counts up) in the timer 411, the abnormality determination unit 412 determines that the image display sequence of the LCD 212 has an abnormality. As a result, the LCD anomaly signal changes to the High level. In response to this, the diagnosis result holding unit 313 stores the diagnosis result such as a flag indicating that there is an abnormality in the image display by the LCD 212 in the internal register. Then, the diagnosis result holding unit 313 outputs an interrupt signal to the IO controller 205 via the UART. Upon receiving the interrupt signal, the IO controller 205 accesses the internal register of the diagnosis result holding unit 313 to acquire the diagnosis result, and it is confirmed that the image display sequence of the LCD 212 has an abnormality.

(Control flow for abnormality detection)
Next, the abnormality detection control at the time of starting the MFP 100 will be described. 9 (a) to 9 (c) are flowcharts showing the flow of abnormality detection control, and the execution subject is different from each other. The execution subject of the flow of FIG. 9A is the self-diagnosis device 203, the execution subject of the flow of FIG. 9B is the self-diagnosis unit 216, and the execution subject of the flow of FIG. 9C is the main CPU 201. Note that some or all of the processes shown in these flows may be realized by software. The symbol "S" in the description of each control flow represents a step.

<Abnormality detection control of self-diagnosis device>
First, the abnormality detection control in the self-diagnosis device 203 will be described with reference to the flow of FIG. 9A. In the case of the present embodiment, self-diagnosis is first performed to see if there is any abnormality in the startup sequence of the main CPU 201 or the power supply sequence of the second power supply 106 (S901). The next step is different depending on the result of this self-diagnosis (S902). When an abnormality is found in the boot sequence of the main CPU 201 or the power supply sequence of the second power supply 106, the LED 215 is turned on in a predetermined lighting mode capable of identifying the abnormality (S903). Here, it is sufficient that the predetermined lighting mode can at least distinguish between the abnormality detection based on the self-diagnosis result of the self-diagnosis device 203 and the abnormality detection based on the self-diagnosis result of the self-diagnosis unit 216 described later. For example, when the number of LEDs is one, the number of blinks per unit time is different between the case of abnormality detection by the self-diagnosis device 203 and the case of abnormality detection by the self-diagnosis unit 216. Further, when the number of LEDs is plurality, different LEDs may be turned on depending on whether the abnormality is detected by the self-diagnosis device 203 or the self-diagnosis unit 216. On the other hand, as a result of the self-diagnosis, if there is no abnormality in the startup sequence of the main CPU 201 or the power supply sequence of the second power supply 106, it is determined that at least the main CPU 201 has started normally, and the abnormality detection control is terminated. Become.

<Abnormality detection control of self-diagnosis unit>
Subsequently, the abnormality detection control in the self-diagnosis unit 216 will be described with reference to the flow of FIG. 9B. First, a self-diagnosis is made to see if there is any abnormality in the image display sequence of the LCD 212 (S911). The next step is different depending on the result of this self-diagnosis (S912). When an abnormality is detected in the image display sequence of the LCD 212, the main CPU 201 is notified to that effect by inter-CPU communication (S913). On the other hand, if no abnormality is detected in the image display sequence of the LCD 212, it is determined that there is no abnormality in the UI display on the LCD 212, and the abnormality detection control is terminated.

<Main CPU abnormality detection control>
Next, the abnormality detection control in the main CPU 201 will be described with reference to the flow of FIG. 9 (c). The abnormality detection control according to this flow is performed when an abnormality is not detected in the abnormality detection control shown in the flow of FIG. 9A described above. That is, the condition that the abnormality detection control is performed is that the power supply from the second power supply 106 is normally performed and the main CPU 201 is normally started.

When the main CPU 201 is operating normally, first, the sub CPU 210 of the UI module 102 and the CPUs communicate with each other, and the diagnosis result by the self-diagnosis unit 216 is acquired (S921). Then, the next step to be performed differs depending on the acquired diagnosis result (S922). If there is no abnormality in the image display sequence of the LCD 212, this abnormality detection control ends. On the other hand, when an abnormality is detected, the LED 215 is turned on in a predetermined lighting mode capable of identifying the abnormality on the UI module 102 side (S923). The predetermined lighting mode is as described above. Then, when an abnormality is detected in the other modules including the UI module 102 excluding the main CPU 201, the information regarding the detected abnormality is transmitted to the server 110 via the LAN 120 (S924). Here, the information regarding the abnormality includes at least information on the content of the abnormality and the location of the abnormality, and may further include information indicating whether or not a serviceman needs to take action. The server 110 displays a screen using this error information, for example, as shown in FIG. 10, on a monitor or the like (not shown). In the screen example of FIG. 10, 1001 is a display column indicating a defect status currently occurring. "E0123" indicates the error content with an error code, "4567" indicates an abnormal part with a module (part) code, and "1" indicates the necessity of a service call (for example, 1: yes, 0: no). There is. Further, 1002 is a display column showing a history of defects that have occurred in the past. The user can grasp where in the MFP 100 the abnormality has occurred from the display mode of the LED 215 and the error display screen by the server 110. Then, for example, by notifying the serviceman of the abnormal part when informing the serviceman of the failure, the serviceman can identify and dispatch the parts related to the failure. If the LAN 120 is connected to an external network, the service person may be notified directly via the external network.

As described above, according to the present invention, the user can grasp the abnormal part by the display mode of the light emitting element represented by the LED and the screen information displayed on the server even if the UI screen of the electronic device is pitch black. Can be done. In addition, the UI module itself of the electronic device has an abnormal self-diagnosis function and is configured to notify the main controller using inter-CPU communication, eliminating the need to expand the I / O port on the main controller side. , The cost increase can be suppressed.

Claims (13)

An electronic device in which a display and a device that supplies a signal to the display are electrically connected.
An image to be displayed on the display, an image processing means for outputting a control signal for controlling the display to the display, and an image processing means for outputting the control signal to the display.
A determination means for determining whether or not the control signal is normal, and
Notification means for notifying based on the result of the determination,
Equipped with
The determination means determines that the display is abnormal when the control signal does not change until a predetermined period elapses after the signal indicating that the power supply to the display is normal is input.
An electronic device characterized by that. The electronic device according to claim 1, wherein the control signal includes a first signal for turning on the power of the display. The electronic device according to claim 1 or 2, wherein the control signal includes a second signal for turning on the backlight of the display. The electronic device according to claim 3, wherein the control signal includes a third signal for controlling the PWM frequency of the backlight. Has a CPU
The electronic device according to any one of claims 1 to 4, wherein the determination means is the CPU. The electronic device according to claim 5, wherein the CPU is included in the same module as the display. The determination means is
It has a timer that counts the predetermined period, and has
The electronic device according to claim 1 , wherein the timer operates with a clock signal different from the clock signal used in the image processing means. The electronic device has at least two operation modes, a normal power mode and a power saving mode having lower power consumption than the normal power mode.
The determination means makes the determination when the electronic device is started, and the determination means makes the determination.
The first to seventh aspects of the present invention include both when the main power switch of the electronic device is turned on and when the electronic device returns from the power saving mode and shifts to the normal power mode. The electronic device according to any one of the items. The electronic device according to claim 8 , wherein the power source of the display is a power source that is not supplied in the power saving mode. The electronic device according to any one of claims 1 to 9 , wherein the device is a device that converts received image data into image data that can be displayed on the display. The electronic device according to claim 1, wherein the signal indicating that the power supply to the display is normal is input to the determination means when the power supply for the display starts the power supply. The electronic device according to claim 1, wherein the counting is started when a signal indicating that the power supply to the display is normal is input to the determination means during the predetermined period. .. A method of controlling an electronic device in which a display and a device that supplies a signal to the display are electrically connected.
An image to be displayed on the display, a step of outputting a control signal for controlling the display to the display, and a step of outputting the control signal to the display.
The step of determining whether or not the control signal is normal, and
The step of notifying based on the result of the determination and
Including
In the determination step, if the control signal does not change until a predetermined period elapses after the signal indicating that the power supply to the display is normal is input, it is determined as an abnormality of the display. ,
A control method characterized by that.

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