JP7088868B2 - Communication equipment, communication methods and programs - Google Patents

Description

The present invention relates to communication devices, communication methods and programs.

In IPv4 (Internet Protocol version 4) / IPv6 (Internet Protocol Version 6) communication, a process in which a node on the communication path selects a forwarding destination according to the destination address of the packet (that is, the IP address set as the destination). Is called an IP lookup. IP lookup is a core part of communication functions in routers and end nodes, and performance improvement is required regardless of software or hardware.

So far, several methods have been proposed to process IP lookups at high speed by software. For example, as one of the conventional methods, there is a method described in Patent Document 1.

In recent years, with the spread of NFV (Network Functions Virtualization), various network functions have been realized by software. Since the NFV functions include DPI (Deep Packet Inspection), which requires more complicated processing than a routing-only device, it is required to reduce the processing load of IP lookup.

Japanese Patent No. 5960863

However, the calculation time required for IP lookup processing is not sufficiently short with respect to the transmission speed currently used by communication carriers, and there is still a demand for reduction in calculation time. For example, 100Gbps Ethernet is currently used as the main transmission standard in communication carrier networks, but it is difficult for software routers to process IP lookups for 100Gbps level traffic without delay with one CPU (Central Processing Unit) core. Is.

As a method for accelerating packet processing including IP lookup, there are methods that use GPU (Graphics Processing Unit), FPGA (Field-Programmable Gate Array), etc. in addition to CPU, but these methods use GPU and FPGA. It is necessary to add hardware such as. Packet processing by software has advantages such as being able to be executed on a general-purpose server with low installation cost, being easy to modify, and reducing the development cost of new functions, but special hardware such as GPU and FPGA is required. Adding will undermine these advantages.

The present invention has been made in view of the above points, and an object of the present invention is to realize high-speed IP lookup processing.

In order to achieve the above object, in the communication device according to the embodiment of the present invention, the receiving means for receiving the packet, the information regarding the next hop, and the information regarding the next layer when the route table is expressed by Multiway Trie are respectively. Using an array composed of a plurality of array elements included, information on the next hop of the destination address of a plurality of packets received by the receiving means is acquired in parallel from the array by a longest match using a SIMD operation. It is characterized by having a lookup processing means and a transmitting means for transmitting each of the plurality of packets received by the receiving means according to each of the information regarding the plurality of next hops acquired by the lookup processing means.

It is possible to realize high-speed IP lookup processing.

It is a figure which shows an example of the whole structure of the communication apparatus which concerns on this embodiment. It is a figure for demonstrating an example of a longest match by Multiway Trie. It is a figure for demonstrating an example of an array expansion of a route table. It is a figure (part 1) for explaining an example of optimization. It is a figure (2) for explaining an example of optimization. It is a flowchart which shows an example of the IP lookup process (IPv4) which concerns on this embodiment. It is a figure for demonstrating an example of extraction (first time) of the area used for lookup. It is a figure for demonstrating an example of the generation of the index of the array element to be looked up first. It is a figure for demonstrating an example of acquisition of a node from an array-expanded route table. It is a figure for demonstrating an example of extraction of an inf value. It is a figure for demonstrating an example of extraction of a jmp value. It is a figure for demonstrating an example of holding an inf value of an object with continuous lookup. It is a figure for demonstrating an example of the extraction (the second and subsequent times) of the area used for a lookup. Next, it is a figure for demonstrating an example of generating an index of an array element to be looked up. It is a flowchart which shows an example of the IP lookup process (IPv6) which concerns on this embodiment. It is a figure for demonstrating an example of extraction of the first 64 bits of an IPv6 address. It is a figure for demonstrating an example of extraction of the first 32 bits of an IPv6 address. It is a figure for demonstrating an example of sorting. It is a figure which shows an example of the hardware composition of the communication apparatus which concerns on this embodiment.

Hereinafter, embodiments of the present invention (hereinafter, also referred to as “the present embodiments”) will be described. In the present embodiment, a communication device 10 that realizes high-speed IP lookup processing by IP lookup of a plurality of destination addresses in parallel using SIMD (Single Instruction / Multiple Data) operations will be described.

A SIMD operation is an operation that processes multiple data at the same time with a single instruction. While SIMD operation is very effective for problems to which parallel calculation can be applied, it can be applied to existing software as it is due to the limited number of operation instructions that can be used and the high overhead of conditional branching. In many cases, the performance does not improve. Therefore, in the present embodiment, as will be described later, the IP lookup process can be performed by devising the data structure of the route table that enables the IP lookup process to be processed by the SIMD operation and the processing procedure of the IP lookup process. Achieve high speed.

Here, it is assumed that the communication device 10 according to the present embodiment is a computer (for example, a general-purpose server, a PC (personal computer), etc.) that realizes packet processing including IP lookup processing by software (program).

<Overall configuration of communication device 10>
First, the overall configuration of the communication device 10 according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram showing an example of the overall configuration of the communication device 10 according to the present embodiment.

As shown in FIG. 1, the communication device 10 according to the present embodiment has a receiving unit 101, a lookup processing unit 102, and a transmitting unit 103 as functional units.

The receiving unit 101 receives a packet transmitted or transferred from another device, another device (for example, another communication device 10) or the like.

The lookup processing unit 102 executes IP lookup processing using a SIMD operation. That is, the lookup processing unit 102 selects a forwarding address from the route table according to the destination address of the packet received by the receiving unit 101. Here, the forwarding address is an IP address of another device or another device to which the packet is forwarded, and is also referred to as, for example, "route information" or "next hop". Hereinafter, the forwarding address is mainly referred to as route information.

Here, the route table is a table (table) in which the destination network (network address) and the route information are associated with each other, and is also referred to as a routing table. In the present embodiment, as will be described later, the routing table is a FIB (Forwarding Information Base) that holds routing information in the form of an array.

The transmission unit 103 transfers the packet received by the reception unit 101 to the transfer destination selected by the lookup processing unit 102.

Here, the entire procedure of this embodiment is the following 1 to 3.

1. 1. The route information is retained as RIB (Routing Information Base).

2. 2. Convert RIB to FIB. At this time, the FIB is held in the form of an array.

3. 3. A longest match is performed on the destination address by the SIMD operation for the FIB, and the route information to be the transfer destination is selected (that is, the IP lookup process using the SIMD operation is executed).

Of these, the above 1 and 2 need to be performed in advance before executing the IP lookup process. The above 1 and 2 may be performed by the lookup processing unit 102, or may be referred to as another functional unit different from the lookup processing unit 102 (for example, a “route table creation unit” or the like, which is not shown). The functional part) may do it.

<1. Retain route information as RIB>
First, the procedure for holding the route information as RIB will be described. In this embodiment, the RIB is held as a Multiway Trie. A Multiway Trie is a Trie tree that represents a width of 2 bits or more in one hierarchy. In contrast to the Trie (that is, the so-called Binary Trie), which is composed of binary trees, the Multiway Trie, which is composed of probably trees, generally has the advantage that there are fewer operations to follow the tree when performing matching.

In the longest match in Multiway Trie, route information is selected by the following Step1 to Step4.

Step1) After cutting out the destination address according to the width of the corresponding layer of Multiway Trie, by matching with the cut out address, the corresponding node in the corresponding layer is obtained.

Step2) If the node holds the route information, the route information is temporarily saved.

Step3) If the node holds a pointer to the next hierarchy, return to Step1 above.

Step4) Then, if the node acquired in Step 1 above does not hold a pointer to the next layer, the route information temporarily saved last in Step 2 above is the forwarding address (that is, the result of the longest match). It becomes.

In the RIB according to this embodiment, one layer of Multiway Trie is expressed as one array. At this time, each element of the array (hereinafter, the element of the array is also referred to as an "array element") holds the route information and the pointer to the next hierarchy. An example of this longest match by RIB is shown in FIG. In the example shown in FIG. 2, the routing table having the destination networks "1.0.0.0/8", "1.0.1.0/24" and "192.0.2.0/24" is represented by RIB, and the destination address (Destination). ) Shows the case where "192.0.2.1" is a longest match. Further, in the example shown in FIG. 2, a pointer to the next hierarchy (including the case of NULL) is set in the table of each array element constituting the RIB, and route information is set in the hop.

Further, in the RIB (and FIB) of the present embodiment, the width of the first layer is 16 bits and the width of the second and subsequent layers is 8 bits in order to speed up the lookup. In the example shown in FIG. 2, Tbl0 is a table representing an array representing the first layer (number of elements: 2 ¹⁶ = 65536), and Tbl1 and Tbl2 are arrays belonging to the second layer (number of elements: 2 ⁸ = 256). It is a table representing each.

The reason why the width of the first layer is 16 bits is that (1) in reality, most routes have a prefix length of 8 to 24 bits, so if the width of the first layer is 8 bits, it is more than twice in many cases. Lookup is required, (2) the width of the layer can be changed only in 8-bit units because the shuffle instruction in byte units of SIMD operation is used in lookup, and (3) one layer is 24 bits wide. This is because the efficiency of using the memory space of FIB is poor. However, if these (1) to (3) are not taken into consideration, the width of the first layer may be 8 bits or 24 bits.

<2. Convert RIB to FIB>
Next, the procedure for converting RIB to FIB will be described. The FIB according to the present embodiment is constructed by converting the Multiway Trie constructed as a RIB into an array format (that is, expanding the array as one array). The sequence expansion of the RIB shown in FIG. 2 is shown in FIG. As described above, the route table according to this embodiment is an FIB in which RIBs are sequenced and expanded.

As a general rule, each line of the FIB represents one layer of 8-bit width (256 elements) in Multiway Trie, but the 0th line represents a special purpose and the 1st to 256th lines represent one layer of 16-bit width (65536 elements).

Each array element that makes up the FIB has a 32-bit space, and the inf value that indicates the index number of the route information when matching the node corresponding to the array element and the jmp value that indicates the index number to the next hierarchy are set. Hold. Therefore, the FIB is represented by a two-dimensional array of 256 32-bit array elements arranged in one row. However, in the present embodiment, the index number of the array element in the i-th row and j-th column of this two-dimensional array is represented by i × 256 + j and is treated as a one-dimensional array.

Here, the array element in line 0 (that is, the array element for special purpose) is used to perform a meaningless lookup for the destination address where the lookup is finished, and it is used for the jmp value of all the array elements. Is set to 0 (that is, jmp = 0). In the IP lookup process according to the present embodiment, since a plurality of destination addresses are looked up in parallel using SIMD calculation, the lookup of all the destination addresses is completed even for the destination addresses for which the lookup has already been completed. You need to repeat the same lookup until. Then, the IP lookup process ends when all the destination addresses reach the 0th line of the FIB.

When looking up the destination address "192.0.2.1" using the FIB shown in FIG. 3, first, look up using "192.0" which is the first 16 bits of the destination address and the array elements on the 1st to 256th lines. The up is done, and the array elements in the 193rd row and 0th column are matched. Next, a lookup is performed using the part "2" from the beginning of the destination address to the 17th to 24th bits and the array element on the 258th line corresponding to the jmp value "258" of the array element. The array elements in the second row and column will match. At this time, the inf value "X" of the matched array element is retained.

Finally, a lookup is performed using the part "1" from the beginning of the destination address to the 25th to 32nd bits and the array element on the 0th line corresponding to the jmp value "0" of the array element, and 0. The array elements in the first row and column match, and the longest match ends. As a result, the route information corresponding to the finally held inf value "X" becomes the forwarding address (that is, the result of the longest match).

Here, in the present embodiment, the following two optimizations are performed when converting the RIB into the FIB.

-Optimization 1: Pre-expanding the index number (inf value) of the route information to the terminal node In the RIB according to this embodiment, whether or not the matched node holds the route information every time the matching of one layer is performed. I checked it and held it temporarily. However, at least one CPU instruction is required to check whether the node holds the route information. Therefore, in advance, the route information of the upper layer is recursively expanded to the part until the node having the route information of the lower layer appears (that is, the node where the result of the longest match becomes the route information of the upper layer). Therefore, the CPU instruction for performing the above confirmation can be eliminated. An example of this optimization is shown in FIG.

In the example shown in FIG. 4, the inf value “X” held by the upper node (the array element in the second row and the 0th column) is expanded as the inf value of each array element in the 257th row. This eliminates the need to check or determine whether each node holds route information at the time of lookup (that is, whether the inf value of the array element corresponding to the node is NULL), and IP look. It is possible to speed up the up processing.

-Optimization # 2: Route aggregation Route aggregation is a well-known method that treats multiple routes with the same next hop as a single route with a shorter prefix length. An example of this optimization is shown in FIG.

In the example shown in FIG. 5, the information held by each array element in the 257th row can be aggregated in the upper node (array element in the 2nd row and 0th column), so that the information is deleted. As a result, the size of the FIB can be reduced, which can be expected to improve the hit rate of the CPU cache.

<3. IP lookup processing using SIMD operation>
Next, the IP lookup process will be described using the SIMD operation.

≪IP lookup processing (IPv4) ≫
Hereinafter, the IP lookup process when the IP address is IPv4 will be described with reference to FIG. FIG. 6 is a flowchart showing an example of the IP lookup process (IPv4) according to the present embodiment.

In this embodiment, as an example, an Intel AVX2 is assumed as a SIMD extension instruction set, and a case where simultaneous processing of eight destination addresses using a 256-bit wide register is realized will be described. However, this embodiment can be similarly applied to other architectures other than Intel AVX2.

In SIMD, there may be multiple mounting methods to achieve the same operation or processing result, but in this embodiment, the mounting method with the lowest CPU instruction latency is adopted in all Intel AVX2. And.

Step S101: The lookup processing unit 102 loads eight destination addresses (IPv4 addresses) from the memory into the register by a load instruction (for example, VMOVDQA or the like) which is one of the SIMD operation instructions. It is assumed that these eight destination addresses are continuously held in the memory in advance. Each of these eight destination addresses is the destination address of the packet received by the receiving unit 101.

Step S102: Next, the lookup processing unit 102 extracts the area used for lookup from the register. For example, as shown in FIG. 7, the eight destination addresses loaded in the register are Dst1, Dst2, ..., Dst8, and the area composed of these Dst1, Dst2, ..., Dst8 is dst. At this time, the lookup processing unit 102 copies the upper 16 bits of each of Dst1 to Dst8 to the lower 16 bits of the 32-bit area of another register by the shuffle instruction (for example, VPSHUFB) which is one of the SIMD operation instructions. do. In the following, the 32-bit area to which the upper 16 bits of each of Dst1 to Dst8 are copied will be referred to as Tgt1 to Tgt8, respectively, and the area composed of these eight Tgt1 to Tgt8 will be referred to as tgt.

In the present embodiment, the width of the first layer is 16 bits, but when the width of the first layer is 8 bits, for example, the lookup processing unit 102 is the upper 8 of each of Dst1 to Dst8. The bits may be copied to the lower 8 bits of the 32-bit area of another register. Similarly, for example, when the width of the first layer is 24 bits, the lookup processing unit 102 may copy the upper 24 bits of each of Dst1 to Dst8 to the lower 24 bits of the 32-bit area of another register. good.

Step S103: Next, the lookup processing unit 102 generates an index of the array element to be looked up first. For example, as shown in FIG. 8, the lookup processing unit 102 requests an addition instruction (VPDDD), which is one of the SIMD operation instructions, for each of Tgt1 to Tgt8 constituting the tgt obtained in step S103 above. Adds 256. This skips row 0 of the route table represented by the FIB (ie, skips array elements from index numbers "0" to "255") and sets the next lookup to lines 1-256 (ie). , Equivalent to setting in the array element of the first layer). Hereinafter, the result of adding 256 to each of Tgt1 to Tgt8 is referred to as Idx1 to Idx8, and the area composed of these Idx1 to Idx8 is referred to as idx. At this point, these Idx1 to Idx8 are the index numbers of the array elements (nodes) used for the initial lookup of each of Dst1 to Dst8.

Step S104: Next, the lookup processing unit 102 acquires a node (that is, an array element) from an array (that is, an array-expanded route table) on the memory. For example, as shown in FIG. 9, the lookup processing unit 102 routes through the array elements of the index numbers stored in each of Idx1 to Idx8 by a gather instruction (for example, VPGATHERDD) which is one of the SIMD operation instructions. Get it from the table and store it in the register. Hereinafter, the area in which the index number array elements stored in each of Idx1 to Idx8 are stored is referred to as Val1 to Val8, and the area composed of these eight Val1 to Val8 is referred to as val. As a result, each of Val1 to Val8 stores an inf value (16 bits) indicating the index number of the route information and a jmp value (16 bits) indicating the index number to the next layer. Note that "jmp value x 256 + 8-bit width value to be looked up next" is the index number of the array element to be looked up next on the array-expanded route table (FIB).

In the past, the performance of the gather instruction was low, and it was difficult to perform table lookup processing such as IP lookup at high speed. However, in recent years, the performance of the gather instruction has improved, and in step S104 above. It is possible to execute the process at high speed by the gather instruction.

Step S105: Next, the lookup processing unit 102 acquires the inf value from val. For example, as shown in FIG. 10, the lookup processing unit 102 uses a shuffle instruction (for example, VPSHUFB), which is one of the SIMD operation instructions, to set the upper 16 bits of each of Val1 to Val8 in the 32-bit area of another register. Copy to the lower 16 bits respectively. Hereinafter, the 32-bit area in which the upper 16 bits of each of Val1 to Val8 are copied is referred to as Inf1 to Inf8, respectively, and the area composed of these eight Inf1 to Inf8 is referred to as inf. As a result, the inf values stored in Val1 to Val8 are stored in Inf1 to Inf8, respectively.

Step S106: Next, the lookup processing unit 102 acquires the jmp value from val. For example, as shown in FIG. 11, the lookup processing unit 102 uses a shuffle instruction (for example, VPSHUFB), which is one of the SIMD operation instructions, to set the lower 16 bits of each of Val1 to Val8 in the 32-bit area of another register. Copy to the lower 16 bits respectively. In the following, the 32-bit area to which the lower 16 bits of Val1 to Val8 are copied will be referred to as Jmp1 to Jmp8, respectively, and the area composed of these eight Jmp1 to Jmp8 will be referred to as jmp. As a result, the jmp values stored in Val1 to Val8 are stored in Jmp1 to Jmp8, respectively.

The processing order of steps S105 and S106 is not specified. That is, the process of step S105 may be executed after the process of step S106 is executed.

Step S107: Next, the lookup processing unit 102 holds the inf value of the target whose lookup is continuing (that is, the destination address whose jmp value is not 0). For example, as shown in FIG. 12, the lookup processing unit 102 first uses a comparison instruction (for example, VPCMPEQD), which is one of the SIMD operation instructions, to select a mask (msk) that selects only targets whose jmp value is not 0. create. That is, the lookup processing unit 102 creates Msk1 to Msk8 by comparing whether or not the jmp value stored in each of Jmp1 to Jmp8 is 0 by the comparison instruction, and is composed of these Msk1 to Msk8. Let msk be the area to be created. For Msk1, for example, if the jmp value stored in Jmp1 is 0, all bit values are 1 in the 32-bit area, and if the jmp value stored in Jmp1 is not 0, all bit values are set. It is a 32-bit area of 0. The same applies to Msk2 to Msk8.

Next, the lookup processing unit 102 holds the inf value of the target whose lookup is continued from msk and jmp in another register by a blend instruction (for example, VPBLENDVB) which is one of the SIMD operation instructions. .. That is, the lookup processing unit 102 mixes (blends) Msk1 to Msk8 and Inf1 to Inf8, respectively, by the blend instruction, and overwrites the result in the 32-bit area, respectively. Let these 32-bit areas be Nhop1 to Nhop8, respectively, and let the area composed of these eight Nhop1 to Nhop8 be nhop. In Nhop1 to Nhop8, the inf value of the target whose lookup is continuing is stored. Note that mixing (blending) means that each element of the two bit strings is conditionally copied. At this time, using the most significant bit of Msk1 to Msk8 as a condition, Inf1 to Inf8 and Nhop1 to Nhop8 are mixed, respectively, to obtain new Nhop1 to Nhop8. This will copy Inf1 to the new Nhop1 if the most significant bit of Msk1 is 0, and copy Nhop1 to the new Nhop1 if the most significant bit of Msk1 is 1. The same applies to Inf2 to Inf8 and Nhop2 to Nhop8.

By performing the above optimization 1 (that is, pre-expanding the index number (inf value) of the route information to the terminal node) when converting RIB to FIB, Msk1 to Msk8 and Inf1 to Inf8 The result of mixing (blending) each of and can always be overwritten with Nhop1 to Nhop8.

Step S108: Next, the lookup processing unit 102 determines whether or not all the jmp values are 0. That is, the lookup processing unit 102 determines whether or not all of Jmp1 to Jmp8 constituting jmp are 0 by a test instruction (for example, VPTEST or the like) which is one of the SIMD operation instructions.

If it is determined in step S108 above that all jmp values are 0, the lookup processing unit 102 ends the IP lookup processing. In this case, the route information indicated by the inf value (that is, the index number of the route information) stored in each of Nhop1 to Nhop8 is the next hop (forwarding destination address) of the destination address stored in each of Dst1 to Dst8. Become. Therefore, after that, each packet is forwarded to the next hop by the transmission unit 103.

On the other hand, if it is not determined in step S108 that all jmp values are 0, the lookup processing unit 102 proceeds to the process of step S109.

Step S109: The lookup processing unit 102 extracts the area used for the next lookup from the register. For example, as shown in FIG. 13, in the second lookup, the lookup processing unit 120 uses a shuffle instruction (for example, VPSHUFB, etc.), which is one of the SIMD operation instructions, to perform the upper 17 bits of each of Dst1 to Dst8. Copy the 8 bits up to the 24th bit to the lower 8 bits of the 32-bit area of another register. These 32-bit areas are also Tgt1 to Tgt8, respectively, and the area composed of eight Tgt1 to Tgt8 is tgt. In the third lookup, the lookup processing unit 120 uses a shuffle instruction, which is one of the SIMD calculation instructions, to set the 8 bits from the upper 25th bit to the 32nd bit of each of Dst1 to Dst8 to another register. It can be copied to the lower 8 bits of the 32-bit area of.

The control mask of the shuffle instruction used in the processes of steps S102 and S109 (that is, the mask for controlling which bit of dst is copied to tgt) is, for example, one of the SIMD operation instructions. Update by adding with a certain _mm256_add_epi32 ().

Step S110: Next, the lookup processing unit 102 generates an index of the array element to be looked up next. For example, as shown in FIG. 14, the lookup processing unit 102 shifts each of Jmp1 to Jmp8 of the current jmp to the left by 1 byte (8 bits), and then an OR operation instruction which is one of the SIMD operation instructions. Execute tgt and OR operation by (for example, VPOR). This means that after multiplying the jmp values stored in each of Jmp1 to Jmp8 by 256, the OR operation is performed with each of Tgt1 to Tgt8. The 32-bit area in which the results of these OR operations are stored is also designated as Idx1 to Idx8, and the area composed of these Idx1 to Idx8 is designated as idx. These Idx1 to Idx8 are the index numbers of the array elements (nodes) used for the next lookup of each of Dst1 to Dst8.

Then, the lookup processing unit 102 returns to the processing of step S104. As a result, the processing after step S104 (that is, the lookup of the next 8-bit portion of each destination address) is executed using the above Ind. That is, the processes of steps S104 to S110 are repeatedly executed for each predetermined 8-bit portion included in each destination address.

In this embodiment, the IP lookup process that looks up eight destination addresses in parallel has been described, but by using the pipeline process, a plurality of IP lookup processes can be executed in parallel. .. For example, by implementing the IP lookup process with two loop unrolls, it is possible to look up 16 destination addresses at the same time by the pipeline process (however, it is processed sequentially in the pipeline process). Is executed, so it is not strictly simultaneous, but a sequential lookup.) Similarly, it can be implemented with three or more loop unrolls.

Further, in the present embodiment, it is assumed that the communication device 10 is installed on the network of the communication carrier and the IP lookup process is repeatedly executed for each of the eight destination addresses. The communication device 10 can be installed, for example, on a relatively low-speed network. On a relatively slow network, it is possible that eight destination addresses do not exist when starting the execution of the IP lookup process. In such a case, for example, a 32-bit length bit string in which all 0s can be regarded as a destination address, and IP lookup processing can be performed on eight destination addresses including one or more of these destination addresses. good.

≪IP lookup processing (IPv6) ≫
Hereinafter, the IP lookup process when the IP address is IPv6 will be described with reference to FIG. FIG. 15 is a flowchart showing an example of the IP lookup process (IPv6) according to the present embodiment.

Since the bit length of an IPv4 address is 32 bits, the bit length of an IPv6 address is 128 bits, so in IP lookup processing (IPv6), eight IPv6 addresses are cut out by 32 bits from the beginning. , Performs the same processing as IP lookup processing (IPv4). Then, when the lookup for 32 bits is completed, if there is a destination address for which the lookup continues, the next 32 bits are repeatedly cut out. Also, after the lookup is completed, the order of the lookup results (that is, the inf value indicating the next hop) and the order of the destination addresses do not match, so the lookup results are rearranged.

Step S201: The lookup processing unit 102 loads two destination addresses (IPv6 addresses) from the memory into the register by a load instruction (for example, VMOVDQA or the like), which is one of the SIMD operation instructions, for a total of eight. It is assumed that these eight destination addresses are continuously held in the memory in advance. Each of these eight destination addresses is the destination address of the packet received by the receiving unit 101.

Step S202: Next, the lookup processing unit 102 extracts the first 64 bits of the four destination addresses (IPv6). For example, as shown in FIG. 16, it is assumed that the destination addresses are Dst1, Dst2, ..., Dst8, and Dst1 and Dst2, Dst3 and Dst4, Dst5 and Dst6, Dst7 and Dst8 are loaded in the same register, respectively. The region composed of Dst1 and Dst2 is dst_1, the region composed of Dst3 and Dst4 is dst_2, the region composed of Dst5 and Dst6 is dst_3, and the region composed of Dst7 and Dst8 is dst_4. Further, for example, the 1st to 32nd bits of Dst1 are expressed as Dst1 [0:31], and the 33rd to 64th bits are expressed as Dst1 [32:63]. The same applies to other bit parts and other destination addresses Dst2 to Dst8.

At this time, the lookup processing unit 102 extracts the first 64 bits of Dst1, Dst2, Dst5, and Dst6 by an unpack instruction (for example, VPUNPCKLDQ, etc.), which is one of the SIMD operation instructions, and copies them to another register. .. In the following, the area of this register will be dst_1_3. The latter 32 bits (that is, Dst1 [32:64], Dst5 [32:64], Dst2 [32:64], Dst6 [32:64]) are discarded in the next step S203.

Similarly, the lookup processing unit 102 extracts the first 64 bits of Dst3, Dst4, Dst7, and Dst8 by the unpack instruction, which is one of the SIMD operation instructions, and copies them to another register. In the following, the area of this register will be dst_2_4. The latter 32 bits (that is, Dst3 [32:64], Dst7 [32:64], Dst4 [32:64], Dst8 [32:64]) are discarded in the next step S203.

Step S203: Next, the lookup processing unit 102 extracts the first 32 bits of the eight destination addresses (IPv6). For example, as shown in FIG. 17, the lookup processing unit 102 extracts the first 32 bits of Dst1, Dst2, Dst5, and Dst6 by an unpack instruction (for example, VPUNPCKLDQ, etc.), which is one of the SIMD operation instructions. Copy to another register. Hereinafter, the area of this register is referred to as upk.

Step S204: Next, the lookup processing unit 102 executes the processing of steps S102 to S103 of FIG. 6 using upk. That is, the lookup processing unit 102 regards upk as dst and executes the processes of steps S102 to S103 of the IP lookup process (IPv4) shown in FIG.

Step S205: Next, the lookup processing unit 102 executes the processing of steps S104 to S107 of FIG.

Step S206: Next, the lookup processing unit 102 determines whether or not all the jmp values are 0, as in the processing of step S108 of FIG.

If it is not determined in step S206 that all jmp values are 0 (that is, if lookup continues), the lookup processing unit 102 proceeds to the process of step S207.

On the other hand, when it is determined in step S206 that all jmp values are 0 (that is, when the lookup is not continued), the lookup processing unit 102 proceeds to the process of step S209.

Step S207: When the lookup processing unit 102 has performed a lookup for 32 bits (that is, all the bit strings in each 32-bit area of dst1 to dst8 of the upk regarded as dst have been looked up. Case), a logical shift instruction (for example, VPSRLDQ, etc.), which is one of the SIMD operation instructions, shifts dst_1 to dst_4 to the left by 32 bits, respectively. However, if the 32-bit lookup has not been performed yet, the processing of this step will not be executed. Note that all the bit strings in each 32-bit area of dst1 to dst8 have been looked up, for example, when looking up every 8 bits, it means that the lookup was performed 4 times. 16 After looking up in bits, if you look up every 8 bits, it means that the lookup was done 3 times.

Then, the lookup processing unit 102 executes the processing of steps S202 to S203 using the 32-bit left-shifted dst_1 to dst_4. As a result, the next 32-bit part of the destination address (IPv6) is extracted as upk.

Step S208: The lookup processing unit 102 executes the processes of steps S109 to S110 of FIG. That is, the lookup processing unit 102 regards upk as dst and executes the processes of steps S109 to S110 of the IP lookup process (IPv4) shown in FIG. Then, the lookup processing unit 102 returns to the processing of step S205.

Step S209: The lookup processing unit 102 rearranges Nhop1 to Nhop8 in which the lookup result is stored. For example, as shown in FIG. 18, in the present embodiment, the nhop is configured in the order of Nhop1, Nhop3, Nhop5, Nhop7, Nhop2, Nhop4, Nhop6, Nhop8. In addition, inf values (that is, index numbers of route information) indicating the next hops of dst1 to dst8 are stored in Nhop1 to Nhop8, respectively. At this time, the lookup processing unit 102 arranges Nhop1 to Nhop8 in the order of Nhop1, Nhop2, Nhop3, Nhop4, Nhop5, Nhop6, Nhop7, Nhop8 by a rearrangement instruction (for example, VPSRLDQ) which is one of the SIMD operation instructions. Change. This gives the next hop for each destination address (IPv6).

In this embodiment, sorting is performed after the lookup is completed, but before the lookup, Dst1 to Dst8 constituting upk are arranged in the order of Dst1, Dst2, Dst3, Dst4, Dst5, Dst6, Dst7, Dst8. You may sort them. However, when sorting before lookup, sorting is required for each 32-bit cutout. On the other hand, as in the present embodiment, if the sorting is performed after the lookup is completed, the sorting can be performed only once, so that the sorting can be performed efficiently.

<Hardware configuration of communication device 10>
Next, the hardware configuration of the communication device 10 according to the present embodiment will be described with reference to FIG. FIG. 19 is a diagram showing an example of the hardware configuration of the communication device 10 according to the present embodiment.

As shown in FIG. 19, the communication device 10 according to the present embodiment has, as hardware, an input device 201, a display device 202, an external I / F 203, a communication I / F 204, a processor 205, and a storage device 206. And have. Each of these hardware is connected so as to be communicable via the bus B.

The input device 201 is, for example, a keyboard, a mouse, a touch panel, or the like. The display device 202 is, for example, a display or the like. The communication device 10 does not have to have at least one of the input device 201 and the display device 202.

The external I / F 203 is an interface with an external device. The external device includes a recording medium 203a and the like. The communication device 10 can read or write the recording medium 203a via the external I / F 203. For example, one or more programs that realize each functional unit (that is, the receiving unit 101, the lookup processing unit 102, and the transmitting unit 103) of the communication device 10 may be recorded on the recording medium 203a.

The communication I / F 204 is an interface for connecting the communication device 10 to the communication network.

The processor 205 is, for example, a CPU or the like. The processor 207 has a built-in register. Each functional unit included in the communication device 10 is realized by causing the processor 205 to execute a process by one or more programs stored in the storage device 206.

The storage device 206 is an auxiliary storage device such as a RAM (Random Access Memory), an HDD (Hard Disk Drive), or an SSD (Solid State Drive). The storage device 206 may include a ROM (Read Only Memory). Various programs and data are stored in the storage device 206. Examples of these programs and data include an OS (Operating System), an application program, one or more programs that realize each functional unit of the communication device 10, a route table, and the like.

The communication device 10 according to the present embodiment can realize the above-mentioned IP lookup process by having the hardware configuration shown in FIG. In the example shown in FIG. 19, the case where the communication device 10 according to the present embodiment is realized by one device (computer) is shown, but the present invention is not limited to this. The communication device 10 according to the present embodiment may be realized by a plurality of devices (computers). Further, one device (computer) may include a plurality of processors 205 and a plurality of storage devices 206.

<Summary>
As described above, the communication device 10 according to the present embodiment can perform IP lookup of a plurality of destination addresses in parallel by using SIMD calculation. Therefore, in the communication device 10 according to the present embodiment, it is possible to realize high-speed IP lookup processing.

Moreover, since the communication device 10 according to the present embodiment uses the SIMD calculation in order to speed up the IP lookup process, it has the following two merits.

Advantage 1: Low cost
Since the SIMD arithmetic function is often installed as standard in processors for servers that are widely distributed today, IP lookup processing is performed without additional special hardware (for example, GPU or FPGA). Can be speeded up. Moreover, since the development process of the process using SIMD calculation is the same as that of ordinary software, the development cost does not increase.

Advantage 2: Scalability to multi-core
Since SIMD calculation is a mechanism that can be used for each CPU core of a unit, it is possible to simultaneously use the multi-core scaling method that has been used conventionally.

The present invention is not limited to the above-described embodiment disclosed specifically, and various modifications and modifications can be made without departing from the scope of claims.

10 Communication device 101 Receiver 102 Lookup processing 103 Transmitter

Claims (6)

The receiving means for receiving packets and
Using an array composed of a plurality of array elements containing information on the next hop and information on the next hierarchy when the routing table is represented by Multiway Trie, each hierarchy of the routing table is divided into the hierarchy. Correspondingly, a bit string having a predetermined length is extracted from each of a plurality of destination addresses acquired from the plurality of packets received by the receiving means, and the extracted plurality of bit strings and the array elements constituting the hierarchy are subjected to SIMD calculation. By repeatedly acquiring the information about the next hop and the information about the next layer contained in the matched array element by matching by the longest match using, the information about the next hop of the destination address of the plurality of packets is obtained. Lookup processing means to acquire from the array in parallel,
When the destination address is an IPv6 address, an extraction means that extracts a bit string from the destination address every 32 bits until the information about the next layer acquired by the lookup processing means reaches a predetermined value, and an extraction means.
A transmission means for transmitting each of the plurality of packets received by the reception means according to each of the information regarding the plurality of next hops acquired by the lookup processing means.
Have,
The lookup processing means is
The bit string extracted by the extraction means is regarded as the destination address of the IPv4 address, and the information regarding the next hop of the destination address and the information regarding the next layer are repeatedly acquired from the array in parallel. Communication device. As an optimization, the array has a lower array element when the information about the next hop is pre-expanded in a lower hierarchy and there is a higher sequence element containing information about the same next hop. The communication device according to claim 1, wherein at least one of them has been deleted. The lookup processing means is
When the destination address is an IPv4 address and the layer composed of the array elements to be matched is the first layer, a bit string having a length of 16 bits is extracted from the beginning of the plurality of destination addresses. Match the extracted multiple bit strings with the array elements that make up the hierarchy, and acquire the information about the next hop and the information about the next hierarchy contained in the matched array elements.
When the layer composed of the array elements to be matched is the second layer or later, a bit string having an 8-bit length is extracted from the beginning of the unextracted portion of the plurality of destination addresses for each layer. A claim characterized in that the extracted plurality of bit strings are matched with the array elements constituting the hierarchy, and the information regarding the next hop and the information regarding the next hierarchy included in the matched array elements are repeatedly acquired. The communication device according to 1 or 2 . The lookup processing means is
The number of destination addresses in which information about the next hop is acquired in parallel by the longest match using the SIMD operation is N, the number of parallel executions by the pipeline processing is M, and N × M by the pipeline processing. The communication device according to any one of claims 1 to 3 , wherein information about the next hop of the destination address is acquired at the same time. The receiving procedure for receiving packets and
Using an array composed of a plurality of array elements containing information on the next hop and information on the next hierarchy when the routing table is represented by Multiway Trie, each hierarchy of the routing table is divided into the hierarchy. Correspondingly, a bit string of a predetermined length is extracted from each of a plurality of destination addresses acquired from each of the plurality of packets received in the reception procedure, and the extracted plurality of bit strings and the array elements constituting the hierarchy are subjected to SIMD calculation. By repeatedly acquiring the information about the next hop and the information about the next layer contained in the matched array element by matching by the longest match using, the information about the next hop of the destination address of the plurality of packets is obtained. The lookup processing procedure to acquire from the array in parallel and
When the destination address is an IPv6 address, an extraction procedure for extracting a bit string from the destination address every 32 bits until the information regarding the next layer acquired in the lookup processing procedure reaches a predetermined value, and an extraction procedure.
A transmission procedure for transmitting each of the plurality of packets received in the reception procedure according to each of the information regarding the plurality of next hops acquired in the lookup processing procedure, and a transmission procedure for transmitting each of the plurality of packets received in the reception procedure.
The computer runs ,
The lookup processing procedure is
The bit string extracted in the extraction procedure is regarded as the destination address of the IPv4 address, and the information regarding the next hop of the destination address and the information regarding the next layer are repeatedly acquired from the array in parallel. Communication method. The receiving procedure for receiving packets and
Using an array composed of a plurality of array elements containing information on the next hop and information on the next hierarchy when the routing table is represented by Multiway Trie, each hierarchy of the routing table is divided into the hierarchy. Correspondingly, a bit string of a predetermined length is extracted from each of a plurality of destination addresses acquired from each of the plurality of packets received in the reception procedure, and the extracted plurality of bit strings and the array elements constituting the hierarchy are subjected to SIMD calculation. By repeatedly acquiring the information about the next hop and the information about the next layer contained in the matched array element by matching by the longest match using, the information about the next hop of the destination address of the plurality of packets is obtained. The lookup processing procedure to acquire from the array in parallel and
When the destination address is an IPv6 address, an extraction procedure for extracting a bit string from the destination address every 32 bits until the information regarding the next layer acquired in the lookup processing procedure reaches a predetermined value, and an extraction procedure.
A transmission procedure for transmitting each of the plurality of packets received in the reception procedure according to each of the information regarding the plurality of next hops acquired in the lookup processing procedure, and a transmission procedure for transmitting each of the plurality of packets received in the reception procedure.
Let the computer run
The lookup processing procedure is
The bit string extracted in the extraction procedure is regarded as the destination address of the IPv4 address, and the information regarding the next hop of the destination address and the information regarding the next layer are repeatedly acquired from the array in parallel. Program to be.

Images