JP7064633B1 - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of appropriately adjusting an execution cycle of CBR refresh and row hammer refresh within all temperature ranges, obtaining necessary and sufficient data holding capacity, and reducing power consumption. A semiconductor memory device 100 includes a temperature sensor, a plurality of memory blocks, and a refresh controller. The temperature sensor detects the device temperature inside the semiconductor memory device and generates a corresponding temperature signal. Each memory block includes a memory cell array with a plurality of volatile memory cells and a plurality of word lines. The refresh controller monitors access to a plurality of word lines, detects access that appears a predetermined number of times within a predetermined period, and performs a refresh operation corresponding to a refresh operation command as a first refresh operation and a second refresh operation. Distribute. [Selection diagram] Fig. 1

Description

The present invention relates to an electronic device, and more particularly to a refresh control method of a semiconductor memory device having a memory cell that requires a refresh operation for data retention, and a semiconductor memory device to which the method is applied.

In DRAM (Dynamic Random Access Memory), which is a semiconductor memory device, the row hammer phenomenon has become apparent with the miniaturization of process technology. The number of times until an error occurs due to activation / deactivation of the word line, the hammer threshold, is already 100,000 times or less in the 20 nm process generation, and it is a circuit measure in DRAM or Without some measures on the memory system side, it is difficult to maintain normal operation.

As a circuit measure in the DRAM, for example, a row hammer refresh (Row-) that captures a frequently accessed row address (hammer address) and performs an additional refresh operation on the adjacent row address at an appropriate frequency. Hammer Refresh, RHR) is widely used. There are roughly two methods for capturing hammer addresses, one focusing on the number of occurrences (access count) that increases, and the other focusing on the frequency of appearance (probability of appearance) that inevitably increases. This is the method.

However, in order to maintain the required data retention characteristics, the refresh cycle is shortened, the effective refresh cycle is shortened, and the effect of row hammer refresh is likely to be enhanced at the same time, which is refreshed by one refresh operation. This means that the amount of data (number of memory cells) and the number of activated word lines are further increased, that is, the refresh current (idd5) is significantly increased.

As a mitigation measure, a temperature-compensated refresh (TCR) adopted by a recent mobile DRAM (for example, LPDDR4) is known. Focusing on the fact that the refresh cycle can be extended because the dominant cell leak factor decreases significantly as the temperature drops, the control device side that controls the DRAM increases the issuance interval of the auto refresh command, for example, twice or four times. To lengthen. This is a method of reducing the refresh current during actual use.

However, at low temperatures, it will increase the rate at which the auto refresh command is assigned to row hammer refresh. At low temperatures, it becomes difficult to balance row hammer refresh and other normal refresh (CBR refresh), and the risk to data retention increases.

In the 1αnm generation and beyond, most refresh operations must be assigned to row hammer refresh at low temperatures as the hammer threshold drops significantly. With the temperature-compensated refresh adopted by mobile DRAM, it is difficult to maintain both the data retention capacity for the product and the reduction of the refresh current in the future.

The present invention provides a semiconductor memory device capable of appropriately adjusting the execution cycles of CBR refresh and row hammer refresh within the entire temperature range, obtaining necessary and sufficient data retention capacity, and reducing power consumption.

The semiconductor memory device includes a temperature sensor, a plurality of memory blocks, and a refresh controller. The temperature sensor detects the device temperature inside the semiconductor memory device and generates a corresponding temperature signal. Each memory block includes a memory cell array with a plurality of volatile memory cells and a plurality of word lines. The refresh controller monitors the access to a plurality of word lines, detects the access that appears a predetermined number of times within a predetermined period, and performs the refresh operation corresponding to the refresh operation command to the first refresh operation and the second refresh operation. Distribute.

In one embodiment of the invention, the first refresh operation described above is decimated and activated based on the information on the device temperature, and the second refresh operation described above is based on the information on the amount of access to the word line. It is thinned out and activated. When the first refresh operation and the second refresh operation are in the same cycle and two internal refreshes cannot be executed in the same cycle, the refresh controller is used to execute and execute one refresh operation during the cycle. Controls the refresh operation that has not been performed to be executed by shifting to the next cycle.

As described above, the semiconductor memory device of the present invention has a signal for executing the CBR refresh operation (first refresh signal) and a signal for executing the row hammer refresh operation (second), respectively, based on the refresh operation signal. Refresh signal) is generated. Then, in the present invention, the execution cycles of CBR refresh (first refresh) and row hammer refresh (second refresh) are appropriately thinned out on the premise that necessary and sufficient refresh opportunities are provided within the entire temperature range. Can be adjusted. Therefore, the data storage capacity can be secured and the power consumption can be reduced.

The accompanying drawings are included for further understanding of the principles of the invention, are incorporated herein by reference, and constitute a portion thereof. The drawings illustrate embodiments of the invention and serve to explain the principles of the invention as well as the description.

FIG. 1 is a schematic view of a semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a schematic diagram of a memory block according to one embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a refresh controller according to one embodiment of the present invention. 4A to 4C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. 5A to 5C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a refresh controller according to one embodiment of the present invention. 7A to 7C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. FIG. 8 is a schematic circuit diagram of the RHR state control circuit according to one embodiment of the present invention. FIG. 9 is a schematic view of a semiconductor memory device according to one embodiment of the present invention. FIG. 10 is a schematic diagram of a memory block according to one embodiment of the present invention. FIG. 11A is a schematic diagram of a CBR thinning circuit according to one embodiment of the present invention. FIG. 11B is an example of the operation waveform of the CBR thinning circuit according to one embodiment of the present invention. FIG. 12A is a schematic diagram of the RHRSLOT generation circuit according to one embodiment of the present invention. FIG. 12B is an example of the operating waveform of the RHRSLOT generation circuit according to one embodiment of the present invention. FIG. 13A is a schematic diagram of an RHR thinning circuit according to one embodiment of the present invention. FIG. 13B is an example of the operating waveform of the RHR thinning circuit according to one embodiment of the present invention. FIG. 14 is a schematic diagram of an RHR state control circuit according to one embodiment of the present invention. FIG. 15A is a schematic diagram of an RHR thinning circuit according to one embodiment of the present invention. FIG. 15B is an example of the operation waveform of the RHR thinning circuit according to one embodiment of the present invention. FIG. 16A is a schematic diagram of an ACK clock generator according to one embodiment of the present invention. FIG. 16B is an example of the operating waveform of the ACK clock generator according to one embodiment of the present invention.

Hereinafter, with reference to FIG. 1, FIG. 1 is a schematic diagram of a semiconductor memory device 100 according to one embodiment of the present invention. The semiconductor memory device 100 includes a temperature sensor 110, a mode register, an OTP block 120, a refresh controller 130, memory blocks 140_1 to 140_N, and a command decoder 150. N is a positive integer greater than 1. In the present embodiment, a configuration is adopted in which one refresh controller 130 controls the refresh operation of all the memory blocks 140_1 to 140_N.

The temperature sensor 110 is, for example, any kind of sensing element / circuit having a temperature detecting function. The temperature sensor 110 is used to detect the device temperature inside the semiconductor memory device 100 and generate the corresponding temperature signal TS.

The mode register and the OTP (One Time Programmable memory) block 120 are, for example, the burst length (BL) and the CAS latency (CL) according to the READ operation specifications, or the first refresh setting information TMRS and the first refresh setting information TMRS according to the present invention. Second refresh setting information This is a circuit in which a plurality of anti-fuse (Anti-Fuse) storing various operation setting information such as TMRHR and a register group called a mode register are combined. Various operation setting information written in advance in the antifuse is loaded into the mode register when the chip is started, and the setting information stored in each mode register is supplied to each circuit in the chip. Further, after the chip is activated, the operation setting information stored in the mode register is stored in the mode register based on the MRS signal issued from the command decoder 150 and the code information externally input from the address input buffer 161 by the MRS (Mode Register Set) command. Can also be reset.

The refresh controller 130 receives the first refresh setting information TMRS and the second refresh setting information TMRHR from the mode register and the OTP block 120, and receives the temperature signal TS from the temperature sensor 110, and determines the operation specifications related to the refresh control. Then, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT can be output, respectively, based on the refresh operation signal RFIP. The refresh operation signal RFIP is a pulse signal issued from the command decoder 150 when the external command signal COM instructs a refresh command. The refresh controller 130 adjusts the output interval of the first refresh signal CBRSLOT based on the first refresh setting information TMRS and the temperature signal TS, and the second refresh signal RHRSLOT based on the second refresh setting information TMRHR and the temperature signal TS. Output interval can be adjusted. Further, the refresh controller 130 can generate the CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and the second refresh signal RHRSLOT. The first refresh setting information TMRS means, for example, the grade information of the CBR refresh skip rate, and when combined with the temperature information TS, the activation rate of the first refresh signal CBRSLOT is determined, and the temperature compensation of the refresh cycle is realized. .. The second refresh setting information TMRHR includes, for example, the refresh interrupt rate and set information related to the row hammer refresh. The so-called refresh interrupt rate indicates that, for example, the second clock RHRCLK is interrupted and the ratio of the logic level of the second refresh signal RHRSLOT is changed correspondingly. The memory blocks 140_1 to 140_N are connected to the refresh controller 130. The memory blocks 140_1 to 140_N can execute the first refresh operation in response to the first refresh signal CBRSLOT and execute the second refresh operation in response to the second refresh signal RHRSLOT. Among them, the first refresh operation is, for example, a refresh operation for executing a CBR (CAS before RAS) refresh, and the second refresh operation is, for example, for executing a row hammer refresh (RHR). It is a refresh operation. In the present embodiment, the first refresh signal CBRSLOT can display the time zone in which the CBR refresh is executed, and the second refresh signal RHRSLOT can display the time zone in which the row hammer refresh is executed.

As shown in FIG. 1, the semiconductor memory device 100 further includes an address MUX 152, a column address counter and a latch 154, a bank address control logic 156, an address input buffer 161 and an address decoder 162, and a command input buffer 163. , Clock input buffer 164, internal clock generator 165, internal power supply circuit 166, DQ input / output buffer 167, address terminal 171, command terminal 172, clock terminal 173, data terminal 174, and data mask terminal. It includes a power supply terminal 176, a power supply terminal 177, and a GIO and a GIO gate control 180.

The address terminal 171 is a terminal that receives an address signal ADD from the outside. The address signal ADD is provided to the address decoder 162 via the address input buffer 161. After decoding, the address decoder 162 provides the address data XADD to the address MUX152, the low address YADD to the column address counter and the latch 154, and the block address BA to the bank address control logic 156 based on the address signal ADD. Can be provided.

The command terminal 172 is a terminal that receives a command signal COM from the outside. The command signal COM can be provided to the command decoder 150 via the command input buffer 163. The command decoder 150 generates circuits for various internal commands by decoding the command signal COM. Internal commands include, for example, an active signal ACT, a precharge signal PPEC, a read signal RD, a write signal WT, and a refresh operation signal RFIP. The active signal ACT is a pulse signal (active command) that is activated when the command signal COM instructs low access. When activating the active signal ACT, it activates the row decoder at the specified memory block address. The precharge signal PPEC is a pulse signal that is activated when the command signal COM instructs precharge. When activating the precharge signal PPEC, the row decoder of the specified memory block and the row address controlled by this row decoder deactivate the specified word line. Further, when the command signal COM instructs the auto-refresh command, the command decoder 150 can activate the refresh operation signal RFIP.

The address MUX 152 is connected to the refresh controller 130, the command decoder 150, and the address decoder 162. The address MUX152 receives the CBR refresh address RFA and the address data XADD, and selects and outputs the CBR refresh address RFA or the address data XADD as the first row address XADD1 based on the refresh operation signal RFIP. To give an example, when the refresh operation signal RFIP is not activated, the address MUX152 uses the address data XADD (external input address) to indicate that it is a general read operation or write operation. It is provided as the first row address XADD1. When the refresh operation signal RFIP is in the activated state, the address MUX152 provides the address data XADD (external input address) as the first row address XADD1 in order to indicate that it is a row hammer operation or a CBR refresh operation. ..

The column address counter and latch 154 provide column address YADD1 based on column address YADD. The bank address control logic 156 provides block selection signals BS_1 to BS_N based on the block address BA.

The clock terminal 173 is a terminal for inputting external clock signals CK and CKB. The external clock signal CK and the external clock signal CKB are complementary signals, and both are provided in the clock input buffer 164. The clock input buffer 164 is based on the external clock signals CK and CKB and is controlled by the clock enable signal CKE from the command input buffer 163 to generate the internal clock signal ICLK and the internal clock signal ICLK to the command decoder 150 and Provided to the internal clock generator 165. The internal clock generator 165 can generate an internal clock signal LCLK that controls the operation order of the DQ input / output buffer 167 based on the internal clock signal ICLK.

The GIO and the GIO gate control 180 are connected to the DQ input / output buffer 167, and are connected to the memory blocks 140_1 to 140_N, respectively, via the plurality of main input / output lines MIO. The GIO and GIO gate control 180 are used to read data from the memory block specified during the read operation to the DQ input / output buffer 167 and write data from the DQ input / output buffer 167 to the specified memory block during the write operation. ..

The data terminal 174 is a terminal for transmitting input / output data DQ. The data mask terminal 175 is a terminal for receiving the data mask signal DM. When the data mask signal DM is activated, overwriting of the corresponding data is prohibited. The power supply terminal 176 is a terminal for receiving the power supply voltage VDD and VSS, and provides the power supply voltage VDD and VSS to the internal power supply circuit 166. The internal power supply circuit 166 generates various internal potentials VPP, VBB, VBLH, VOD, VINT, etc. based on the power supply voltages VDD and VSS.

The power supply terminal 177 is a terminal for receiving the power supply voltages VDDQ and VSSQ and providing the power supply voltages VDDQ and VSSQ to the DQ input / output buffer 167. The power supply voltages VDDQ and VSSQ have the same potentials as the power supply voltages VDD and VSS supplied to the power supply terminal 176, respectively. However, the dedicated power supply voltages VDDQ and VSSQ are used in the DQ input / output buffer 167 to prevent the power supply noise generated from the DQ input / output buffer 167 from being transmitted to other circuit blocks.

The command decoder 150 is connected to the refresh controller 130. Upon receiving the command signal COM instructing the refresh command, the command decoder 150 can start generating the refresh operation signal RFIP. The command decoder 150 can also transmit the mode signal MRS to the mode register and the OTP block 120 based on the command signal COM. Among them, the mode register, the OTP block 120, and the command decoder 150 can all be realized by a logic circuit familiar to those who have ordinary knowledge in the field of integrated circuits.

Hereinafter, the detailed structure of the memory block in the present embodiment will be described with reference to an example. FIG. 2 is a schematic diagram of the memory block 140_i according to one embodiment of the present invention. As shown in FIG. 2, the memory block 140_i includes an OR gate 210, an AND gate 220, an AND gate 230, a row hammer address (RHA) detection circuit 240, an address MUX 250, a row decoder, and a memory. It includes a block control 260, a column decoder 270, a LIO gate control and DM control logic 272, a sense amplifier 274, a word driver 280, and a memory cell array 290. In this embodiment, i is a positive integer and 1 ≦ i ≦ N.

The first input terminal of the OR gate 210 is connected to the first refresh signal CBRSLOT, and the second input terminal of the OR gate 210 is connected to the second refresh signal RHRSLOT. The first input terminal of the AND gate 220 is connected to the refresh operation signal RFIP, the second input terminal of the AND gate 220 is connected to the output terminal of the OR gate 210, and the output terminal of the AND gate 220 is the effective refresh signal RFEXE. To generate. The effective refresh signal RFEXE can indicate the refresh operation of the actually executed auto refresh (including CBR refresh and row hammer refresh).

The first input terminal of the AND gate 230 is connected to the refresh operation signal RFIP, and the second input terminal of the AND gate 230 is connected to the second refresh signal RHRSLOT. The output terminal of the AND gate 230 generates the enabled (high logic level) row hammer signal RHR when both the refresh operation signal RFIP and the second refresh signal RHRSLOT are enabled (high logic level).

The RHA detection circuit 240 is connected to the output terminal of the AND gate 230. The RHA detection circuit 240 can analyze the second row address XADD2 in response to the active signal ACT, the precharge signal PREC, and the row hammer signal RHR to generate the row hammer refresh address RHA. Specifically, the RHA detection circuit 240 can monitor the memory cell access operation on the previous second row address XADD2 and detect the access that appears a predetermined number of times or more within a predetermined period. When the second row address XADD2 is accessed more than a predetermined number of times, the address adjacent to the second row address XADD2 is calculated and used as the row hammer refresh address RHA.

It should be explained that the number of access to the word line can be obtained by counting the number of times the active signal ACT is enabled. Row hammer refresh address RHA is an address for performing row hammer refresh. In the RHA detection circuit 240, the method of calculating the row hammer refresh address RHA can be realized in the integrated circuit field with a structure applying a memory circuit familiar to a person having ordinary knowledge in this field.

The first input terminal of the address MUX250 is connected to the first row address XADD1 of the address MUX152, the second input terminal of the address MUX250 is connected to the row hammer refresh address RHA, and the first is based on the row hammer signal RHR. Row address XADD1 or row hammer refresh address RHA is selected as the second row address XADD2 and output.

The row decoder and memory block control 260 are connected to the RHA detection circuit 240 and the address MUX 250. The row decoder and the memory block control 260 are driven based on the active signal ACT and the precharge signal PREC, and latch and output the second row address XADD2 as the block access address BADD based on the effective refresh signal RFEXE. Can be done.

Referring to FIG. 2, the address MUX250 sets the first row address XADD1 from the address MUX152 in FIG. 1 to the second row to indicate that it is not a row hammer refresh operation when the row hammer signal RHR is equal to the low logic level. Provided as address XADD2. When the row hammer signal RHR is equal to the high logic level, the address MUX250 sets the row hammer refresh address RHA as the second row address XADD2 in order to indicate that it is a row hammer refresh operation.

When the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are output at the same time as in the circuit arrangement method shown in FIG. 2, the memory block 140_i executes one of the first refresh operation and the second refresh operation. And it is possible to perform operations that have not been performed in the next refresh cycle. To explain by example, when the second refresh signal RHRSLOT is output, regardless of whether the first refresh signal CBRSLOT is also output at the same time, the address MUX250 is all due to the row hammer signal RHR output by the AND gate 230. Since the row hammer refresh address RHA is selected as the second row address XADD2 and output, the second refresh operation can be executed. Further, a first refresh operation that has not been executed in the next refresh cycle is executed.

The memory cell array 290 has a plurality of word line WLs and a plurality of bit line BLs, and has a configuration in which the memory cell MC is arranged at the intersection of the word line WL and the bit line BL. The memory cell array 290 of FIG. 2 shows a structure composed of one word line WL, a bit line BL, and a memory cell MC in the memory cell array 290. In the present embodiment, the word line WL is selected by the row decoder and the memory block control 260, and the bit line BL is selected by the column decoder 270.

The word driver 280 is used to drive the specified word line, and the sense amplifier 274 reads data from the specified memory cell MC or into the specified memory cell MC via the bit line BL. Write data.

The LIO gate control and DM control logic 272 are connected to the sense amplifier 274 via the local input / output line LIO. The LIO gate control and DM control logic 272 accesses the designated memory cell MC via the sense amplifier 274 based on the decoding result of the column decoder 270. Among them, the sense amplifier 274 receives the stored data transmitted from the bit line BL by the memory cell MC, senses the stored data based on the sensing start signal SAEn, acquires the read data, and inputs the read data to the main input. It can be transmitted to the output line MIO. The sense amplifier 274 receives the write data on the main input / output line MIO, senses the write data based on the sensing start signal SAEn, and writes the sensing result to the memory cell MC via the bit line BL. You can also. In this embodiment, the RHA detection circuit 240 can also analyze the spare row address XRED and calculate the row hammer refresh address RHA.

Hereinafter, the detailed structure of the refresh controller in the present embodiment will be described with reference to an example. FIG. 3 is a schematic circuit diagram of the refresh controller 300 according to one embodiment of the present invention. As shown in FIG. 3, the refresh controller 300 includes a CBR thinning circuit 310, an RHR state control circuit 320, and a CBR counter 330.

The CBR thinning circuit 310 outputs the first refresh signal CBRSLOT based on the first clock CBRCLK, and the first refresh based on the temperature signal TS2, the first refresh setting information TMRS, and the CBR refresh address RFA. The output interval of the signal CBRSLOT can be adjusted.

The RHR state control circuit 320 is connected to the CBR thinning circuit 310. The RHR state control circuit 320 outputs the second refresh signal RHRSLOT based on the second clock RHRCLK, and adjusts the output interval of the second refresh signal RHRSLOT based on the temperature signal TS2 and the second refresh setting information TMRHR. be able to.

The CBR counter 330 is, for example, any kind of counting element / circuit having a counting function. The CBR counter 330 is connected to the CBR thinning circuit 310 and the RHR state control circuit 320. The CBR counter 330 counts the number of times the first refresh operation is executed based on the count signal CBRCNT, and generates a CBR refresh address RFA.

In FIG. 3, the CBR thinning circuit 310, the RHR state control circuit 320, and the CBR counter 330 are connected via a buffer gate 340, an AND gate 350, a multiplexer 360, an inverter 370, and an AND gate 380, respectively. The flip-flop 390 reacts to the inverted first refresh signal CBRSLOT and is used to provide the temperature signal TS2 based on the temperature signal TS.

As shown in FIG. 3, the input terminal of the buffer gate 340 is connected to the refresh operation signal RFIP, and the output terminal of the buffer gate 340 can generate the first clock CBRCLK. The first input terminal of the AND gate 350 is connected to the output terminal of the buffer gate 340, the second input terminal of the AND gate 350 is connected to the first refresh signal CBRSLOT, and the count signal CBRCNTP is connected to the output terminal of the AND gate 350. To generate.

The first terminal of the multiplexer 360 is connected to the refresh operation signal RFIP, the second terminal of the multiplexer 360 is connected to the count signal CBRCNTP, and the refresh operation signal RFIP or the count signal CBRCNTP is connected based on the mode switching signal SW. Select as 2 clock RHRCLK and output. The input terminal of the inverter 370 is connected to the second refresh signal RHRSLOT. The first input terminal of the AND gate 380 is connected to the output terminal of the inverter 370, the second input terminal of the AND gate 380 is connected to the count signal CBRCNTP, and the output terminal of the AND gate 380 connects the count signal CBRCNT to the CBR. Output to counter 330. Hereinafter, the operating principle of the refresh controller 300 shown in FIG. 3 of the present application will be further described.

The refresh controller 300 can receive the refresh operation signal RFIP provided by the command decoder 150 when generating a command signal COM instructing a refresh command. The refresh operation signal RFIP passes through the buffer gate 340 and is provided to the CBR thinning circuit 310 and the AND gate 350 as the first clock CBRCLK.

The CBR thinning circuit 310 can generate the first refresh signal CBRSLOT based on the first clock CBRCLK based on the temperature signal TS2 and the first refresh setting information TMRS.

The AND gate 350 is used to gate the first clock CBRCLK. When the first refresh signal CBRSLOT is 1 (high logic level), the first clock CBRCLK is output as a count signal CBRCNTP and transmitted to the AND gate 380. When the second refresh signal RHRSLOT is 0 (low logic level), the count signal CBRCNT is equal to the first clock CBRCLK and is provided to the CBR counter 330 of the next stage as a basis for performing the counting operation.

When the second refresh signal RHRLOT is 1 (high logic level), the refresh operation of CBR refresh is prohibited, and the refresh operation of row hammer refresh is executed. At the same time, since the count signal CBRCNT is held at 0 (low logic level), the CBR counter 330 does not count and corresponds to the prohibition of CBR refresh. That is, the CBR counter 330 counts the number of CBR refreshes for generating the CBR refresh address RFA.

On the other hand, the refresh operation signal RFIP and the count signal CBRCNTP are provided to the multiplexer 360. The multiplexer 360 selects the refresh operation signal RFIP or the count signal CBRCNTP as the second clock RHRCLK based on the mode switching signal SW, and drives the RHR state control circuit 320 of the next stage. The RHR state control circuit 320 is a circuit for generating a second refresh signal RHRSLOT.

The RHR state control circuit 320 can generate a second refresh signal RHRSLOT based on the second clock RHRCLK based on the temperature signal TS2 and the second refresh setting information TMRHR.

It should be mentioned that, in the present embodiment, the purpose of the CBR refresh and the row hammer refresh are different, but the first refresh signal CBRSLOT used for the CBR refresh and the second refresh signal RHRSLOT used for the row hammer refresh are both refresh operation signals. It was generated based on RFIP. However, as shown in FIG. 3, the multiplexer 360 can select the refresh operation signal RFIP or the count signal CBRCNTP as the second clock RHRCLK based on the mode switching signal SW.

The mode switching signal SW is provided by, for example, the command decoder 150. When the mode switching signal SW is equal to the low logic level (mode A), the multiplexer 360 outputs the count signal CBRCNTP as the second clock RHRCLK. In mode A, the second clock RHRCLK is also adjusted according to the temperature signal TS2 by the action of the AND gate 350 (corresponding to the adjustment performed by the CBR thinning circuit 310 with respect to the first refresh signal CBRSLOT based on the temperature signal TS2). ..

Since the refresh skip rate of the CBR thinning circuit 310 increases as the temperature decreases, in order to prevent the second refresh signal RHRSLOT from being affected by the temperature, the RHR state control circuit 320 also corresponds to this, and the refresh interrupt rate is based on the temperature signal TS2. Must be adjusted higher.

4A to 4C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. A refresh operation when the mode switching signal SW is equal to the low logic level (mode A) will be described with reference to FIGS. 3 and 4A to 4C at the same time.

FIG. 4A illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 1x. The multiple of the refresh interval tREFI is determined by the CBR thinning circuit 310 based on the temperature signal TS2 and the first refresh setting information TMRS. Among them, X is, for example, an arbitrary integer, but it is only necessary to know the change in the CBR refresh address RFA.

In the situation of FIG. 4A, the CBR decimation circuit 310 does not skip any first clock CBRCLK, and the refresh interval tREFI of the first refresh operation is equal to the interval of the refresh operation signal RFIP. Therefore, the waveform of the effective refresh signal RFEXE is equal to the refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P40, the RHR state control circuit 320 generates the first second refresh signal RHRSLOT. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-7 at this time. At the same time, the memory block performs a second refresh operation. After that, when the pulse of the refresh operation signal RFIP is P41, the RHR state control circuit 320 again generates a second refresh signal RHRSLOT.

FIG. 4B illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 2x.

In the situation of FIG. 4B, the CBR decimation circuit 310 can skip half the first timing CBRCLK and the refresh interval tREFI of the first refresh operation is equal to the interval of the double refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P40, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT compete with each other (generated at the same time). In the event of a conflict, the refresh controller 300 does not extend or adjust the first refresh signal CBRSLOT or the second refresh signal RHRSLOT to a higher logic level time, so the memory block preferentially executes the second refresh operation. At the same time, the first refresh operation is skipped. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-3 at this time. After that, when the pulse of the refresh operation signal RFIP is P42, the first refresh signal CBRSLOT and the second second refresh signal RHRSLOT compete again, so that the CBR counter 330 pauses the count again.

FIG. 4C illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 4x. In the situation of FIG. 4C, the CBR decimation circuit 310 can skip the 3/4 first timing CBRCLK and the refresh interval tREFI of the first refresh operation is equal to the quadruple refresh operation signal RFIP interval.

When the pulse of the refresh operation signal RFIP is P40, the first refresh signal CBRSLOT and the first second refresh signal RHRSLOT compete with each other. In the event of a conflict, the refresh controller 300 does not extend or adjust the first refresh signal CBRSLOT or the second refresh signal RHRSLOT to a higher logic level time, so the memory block preferentially executes the second refresh operation. At the same time, the first refresh operation is skipped. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-1 at this time. After that, when the pulse of the refresh operation signal RFIP is P43, the first refresh signal CBRSLOT and the second second refresh signal RHRSLOT compete again, so that the CBR counter 330 pauses the count again.

Returning to FIG. 3, when the mode switching signal SW is equal to the high logic level (mode B), the multiplexer 360 directly outputs the refresh operation signal RFIP as the second clock RHRCLK.

5A to 5C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. A refresh operation when the mode switching signal SW is equal to the high logic level (mode B) will be described with reference to FIGS. 3 and 5A to 5C at the same time.

FIG. 5A illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 1x. In the situation of FIG. 5A, the CBR decimation circuit 310 does not skip any first timing CBRCLK, and the refresh interval tREFI of the first refresh operation is equal to the interval of the refresh operation signal RFIP. Therefore, the waveform of the effective refresh signal RFEXE is equal to the refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P50, the RHR state control circuit 320 generates the first second refresh signal RHRSLOT. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-7 at this time. At the same time, the memory block performs a second refresh operation. After that, when the pulse of the refresh operation signal RFIP is P51, the RHR state control circuit 320 again generates a second refresh signal RHRSLOT.

FIG. 5B illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 2x. In the situation of FIG. 5B, the CBR decimation circuit 310 can skip half the first timing CBRCLK and the refresh interval tREFI of the first refresh operation is equal to the interval of the double refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P50, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT compete with each other. In the event of a conflict, the refresh controller 300 does not extend or adjust the first refresh signal CBRSLOT or the second refresh signal RHRSLOT to a higher logic level time, so the memory block preferentially executes the second refresh operation. At the same time, the first refresh operation is skipped. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-3 at this time.

The difference from the situation in FIG. 4B is that it is not necessary to determine the second clock signal RHRCLK in the first refresh signal CBRSLOT. Therefore, when the pulse of the refresh operation signal RFIP is P51, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT Is not in conflict.

FIG. 5C illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 4x. In the situation of FIG. 5C, the CBR decimation circuit 310 can skip the first clock CBRCLK of 3/4, and the refresh interval tREFI of the first refresh operation is equal to the interval of the quadruple refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P50, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT compete with each other. As shown in FIG. 5C, when a conflict occurs, the refresh controller 300 does not extend or adjust the first refresh signal CBRSLOT or the second refresh signal RHRSLOT to a high logic level time, so that the memory block is a second refresh operation. Is executed with priority, and at the same time, the first refresh operation is skipped. Due to the action of the inverter 370 and the AND gate 380, the CBR counter 330 pauses the count and holds the CBR refresh address RFA at X-1 at this time.

The difference from the situation of FIG. 4C is that the second clock RHRCLK does not need to be determined by the first refresh signal CBRSLOT, so that when the pulse of the refresh operation signal RFIP is P51, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT Do not conflict.

Returning to FIG. 3, in the embodiment of FIG. 3, appropriate control cannot be performed for the situation where the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are simultaneously generated. When the mode switching signal SW is equal to the low logic level (mode A), the multiplexer 360 provides the count signal CBRCNTP for the first clock CBRCLK to the RHR state control circuit 320 as the second clock RHRCLK, and the second refresh operation is the original. Since it is limited to the opportunity of the first refresh operation, it is impossible to realize the second refresh operation with high frequency at low temperature. When the mode switching signal SW is equal to the high logic level (mode B), the problem of competition is solved by simply executing the second refresh operation preferentially, but the opportunity of the first refresh operation is reduced, so that the data Occurs the problem of being lost. Hereinafter, FIG. 6 shows a circuit in which the above-mentioned drawbacks are improved.

FIG. 6 is a schematic circuit diagram of the refresh controller 400 according to one embodiment of the present invention. The operation method for the CBR thinning circuit 410, the RHR state control circuit 420, and the CBR counter 430 is the same as or similar to the above-mentioned CBR thinning circuit 310, RHR state control circuit 320, and CBR counter 330, respectively. The explanation is omitted.

The difference from the above-described embodiment is that in the present embodiment, the CBR thinning circuit 410, the RHR state control circuit 420, and the CBR counter 430 pass through the buffer gate 440, the AND gate 450, the AND gate 460, and the NAND gate 470, respectively. Is to be connected. The input terminal of the buffer gate 440 is connected to the refresh operation signal RFIP, and the output terminal of the buffer gate 440 generates the second clock RHRCLK.

The first input terminal of the AND gate 450 is connected to the refresh operation signal RFIP, and the first clock CBRCLK is generated at the output terminal of the AND gate 450. The first input terminal of the AND gate 460 is connected to the first clock CBRCLK, the second input terminal of the AND gate 460 is connected to the first refresh signal CBRSLOT, and the count signal CBRCNT is generated at the output terminal of the AND gate 460. do. The first input terminal of the NAND gate 470 is connected to the second refresh signal RHRSLOT, the second input terminal of the NAND gate 470 is connected to the first refresh signal CBRSLOT, and the output terminal of the NAND gate 470 is the AND gate 450. It is connected to the second input terminal. The flip-flop 480 is used to react to the inverted first refresh signal CBRSLOT and provide the temperature signal TS2 based on the temperature signal TS.

Based on the circuit arrangement method shown in FIG. 6, not only the second refresh operation is not limited to the opportunity of the original first refresh operation, but also the opportunity of the second refresh operation is not reduced, so that the above-mentioned drawbacks of the embodiment are disadvantaged. Can be improved.

7A to 7C are schematic waveforms of a refresh operation of the semiconductor memory device according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 6 and 7A to 7C at the same time.

FIG. 7A illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 1x. In the situation of FIG. 7A, the CBR decimation circuit 410 does not skip any first clock CBRCLK, and the refresh interval tREFI of the first refresh operation is equal to the interval of the refresh operation signal RFIP. Therefore, the waveform of the effective refresh pulse RFEXE is equal to the refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P70, the RHR state control circuit 420 generates the first second refresh signal RHRSLOT. Due to the action of the NAND gate 470, AND gate 450, and AND gate 460, the CBR counter 430 pauses the count and suspends the CBR refresh address RFA at X-7. After that, when the pulse of the refresh operation signal RFIP is P71, the RHR state control circuit 420 generates a second refresh signal RHRSLOT.

FIG. 7B illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 2x. In the situation of FIG. 7B, the CBR decimation circuit 410 can skip half the first clock CBRCLK, and the refresh interval tREFI of the first refresh operation is equal to the interval of the double refresh operation signal RFIP.

In FIG. 7B, when the pulse of the refresh operation signal RFIP is P70, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT compete with each other. Due to the action of the NAND gate 470, AND gate 450, and AND gate 460, the CBR counter 430 pauses the count and suspends the CBR refresh address RFA at X-3. At the same time, the memory block performs a second refresh operation.

However, when a conflict occurs, the refresh controller 400 extends the first refresh signal CBRSLOT to a high logic level time so that the first refresh operation can be performed at the time point of the next refresh operation signal RFIP. Therefore, the opportunity for the first refresh operation does not decrease.

Similarly, when the pulse of the refresh operation signal RFIP is P71, the refresh controller 400 also extends the first refresh signal CBRSLOT to a high logic level time, and the first refresh at the time point of the next refresh operation signal RFIP. Allow the operation to be performed.

FIG. 7C illustrates a signal waveform in which the refresh interval tREFI of the first refresh operation (CBR refresh) is a multiple of 4x. In the situation of FIG. 7C, the CBR decimation circuit 410 can skip the first clock CBRCLK of 3/4, and the refresh interval tREFI of the first refresh operation is equal to the interval of the quadruple refresh operation signal RFIP.

When the pulse of the refresh operation signal RFIP is P70, the first refresh signal CBRSLOT and the second refresh signal RHRSLOT compete with each other. Due to the action of the NAND gate 470, AND gate 450, and AND gate 460, the CBR counter 430 pauses the count and suspends the CBR refresh address RFA at X-1. At the same time, the memory block performs a second refresh operation.

However, when a conflict occurs, as shown in FIG. 7C, the refresh controller 400 extends the first refresh signal CBRSLOT to a high logic level time and performs a first refresh operation at the time point of the next refresh operation signal RFIP. To be able to execute. Therefore, the opportunity for the first refresh operation does not decrease.

Similarly, when the pulse of the refresh operation signal RFIP is P71, the refresh controller 400 extends the first refresh signal CBRSLOT to a high logic level time and performs the first refresh operation at the time point of the next refresh operation signal RFIP. To be able to execute.

It should be explained that, in one embodiment, the RHR state control circuit can further adjust the second refresh signal RHRSLOT based on the number of times the word line is accessed. To give an example, FIG. 8 is a schematic circuit diagram of the RHR state control circuit 500 according to one embodiment of the present invention. The RHR decimation circuit 510 can generate a third clock RHRCLKD based on a second clock RHRCLK, a second refresh signal RHRSLOT, and an active signal ACT corresponding to each memory block 140_1 to 140_N. Among them, the RHR thinning circuit 510 can count the active signal ACTs of the memory blocks 140_1 to 140_N to obtain the number of access of the word line.

The RHRSLOT generation circuit 520 is connected to the RHR thinning circuit 510. The RHRSLOT generation circuit 520 generates a second refresh signal RHRSLOT based on the third clock RHRCLKD, and adjusts the output interval of the second refresh signal RHRSLOT based on the temperature signal TS2 and the second refresh setting information TMRHR. Can be done.

It should be explained that, in one embodiment, the corresponding refresh controller may be further arranged for each memory block. In order for engineers in this field to further understand the present invention, one embodiment will be given and described in detail below.

FIG. 9 is a schematic view of the semiconductor memory device 600 according to one embodiment of the present invention. The semiconductor memory device 600 includes a temperature sensor 610, a mode register and an OTP block 620, memory blocks 640_1 to 640_N, and a command decoder 650. In the present embodiment, each memory block 640_1 to 640_N has one refresh controller, and a structure for controlling is adopted.

Temperature sensor 610, mode register and OTP block 620, column address counter and latch 654, bank address control logic 656, address input buffer 661, address decoder 662, command input buffer 663, clock input buffer 664, internal clock generator 665, internal Power circuit 666, DQ input / output buffer 667, address terminal 671, command terminal 672, clock terminal 673, data terminal 674, data mask terminal 675, power supply terminal 676, power supply terminal 677, and GIO. Since the operation method of the GIO gate control 680 is the same as or similar to the corresponding member in the semiconductor memory device 100 described above, the description of the operation method will be omitted.

The difference from the above-described embodiment is that the command decoder 650 starts generating the refresh operation signals RFIP_1 to RFIP_N when the command signal COM instructing the refresh command is received, and can be provided in the memory blocks 640_1 to 640_N, respectively. be.

Hereinafter, the detailed structure of the memory block in the present embodiment will be described with reference to an example. FIG. 10 is a schematic diagram of a memory block 640_i according to one embodiment of the present invention. As shown in FIG. 10, the memory block 640_i includes a refresh controller 710, an OR gate 720, an AND gate 722, an AND gate 730, an inverter 732, an AND gate 734, an RHA detection circuit 740, and an address MUX750. , Row decoder and memory block control 760, column decoder 770, LIO gate control and DM control logic 772, sense amplifier 774, word driver 780, and memory cell array 790.

The refresh controller 710 can output the first refresh signal CBRSLOT and the second refresh signal RHRSLOT, respectively, based on the refresh operation signal RFIP_i. The refresh controller 710 adjusts the output interval of the first refresh signal CBRSLOT based on the first refresh setting information TMRS and the temperature signal TS, and the second refresh signal RHRSLOT based on the second refresh setting information TMRHR and the temperature signal TS. Can be adjusted. Further, the refresh controller 710 can generate the CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and the second refresh signal RHRSLOT.

The first input terminal of the OR gate 720 is connected to the first refresh signal CBRSLOT, and the second input terminal of the OR gate 720 is connected to the second refresh signal RHRSLOT. The first input terminal of the AND gate 722 is connected to the refresh operation signal RFIP_i, the second input terminal of the AND gate 722 is connected to the output terminal of the OR gate 720, and the output terminal of the AND gate 722 is the effective refresh signal RFEXE. To generate. The effective refresh signal RFEXE can indicate the refresh operation of the actually executed auto refresh (including CBR refresh and row hammer refresh).

The first input terminal of the AND gate 730 is connected to the refresh operation signal RFIP_i, the second input terminal of the AND gate 730 is connected to the second refresh signal RHRSLOT, and the row hammer signal RHR is transmitted at the output terminal of the AND gate 730. Generate.

The input terminal of the inverter 732 is connected to the second refresh signal RHRSLOT. The first input terminal of the AND gate 734 is connected to the output terminal of the inverter 732. The second input terminal of the AND gate 734 is connected to the first refresh signal CBRSLOT. The third input terminal of the AND gate 734 is connected to the refresh operation signal RFIP_i. The output terminal of the AND gate 734 generates a selection signal CBR.

The RHA detection circuit 740 is connected to the output terminal of the AND gate 730. The RHA detection circuit 740 can analyze the second row address XADD2 and generate the row hammer refresh address RHA in response to the active signal ACT, the precharge signal PREC, and the row hammer signal RHR. Specifically, the RHA detection circuit 740 monitors the access to the word line WL in the memory cell array 790 based on the previous second row address XADD2, and detects the access that appears a predetermined number of times within a predetermined period. Then, the address adjacent to the access address that appears a predetermined number of times can be calculated and used as the row hammer refresh address RHA.

The refresh controller 710 in the memory block 640_i can output the first refresh signal CBRSLOT and the second refresh signal RHRSLOT, respectively, based on the refresh operation signal RFIP_i. The refresh controller 710 adjusts the output interval of the first refresh signal CBRSLOT based on the first refresh setting information TMRS and the temperature signal TS, and the second refresh signal RHRSLOT based on the second refresh setting information TMRHR and the temperature signal TS. Can be adjusted. Further, the refresh controller 710 can generate the CBR refresh address RFA based on the adjusted first refresh signal CBRSLOT and the second refresh signal RHRSLOT.

The first input terminal of the address MUX750 is connected to the address data XADD from the address decoder 662, the second input terminal of the address MUX750 is connected to the CBR refresh address RFA from the refresh controller 710, and the third input terminal of the address MUX750. Is connected to the row hammer refresh address RHA. The address MUX750 selects and outputs the address data XADD, the CBR refresh address RFA, or the row hammer refresh address RHA as the second row address XADD2 based on the selection signal CBR and the row hammer signal RHR.

Referring to FIG. 10, when the selection signal CBR is equal to the low logic level and the row hammer signal RHR is equal to the low logic level, the address MUX750 indicates a general read or write operation, so that the address MUX750 is the data address XDADD ( External input address) is provided as a block access address BADD. When the selection signal CBR is equal to the high logic level and the row hammer signal RHR is equal to the low logic level, the address MUX750 blocks access to the CBR refresh address RFA calculated by the refresh controller 710 to indicate a CBR refresh refresh operation. The address is BADD. When the selection signal CBR is equal to the low logic level and the row hammer signal RHR is equal to the high logic level, the address MUX750 sets the row hammer refresh address RHA as the block access address BADD to indicate the row hammer refresh refresh operation. ..

When the first refresh signal CBRSLOT and the second refresh signal RHRSLOT are output at the same time as in the circuit arrangement method shown in FIG. 10, the memory block 640_i executes one of the first refresh operation and the second refresh operation. can do. Specifically, when the second refresh signal RHRSLOT is output, regardless of whether the first refresh signal CBRSLOT is also output at the same time, the address MUX750 is all due to the arrangement of the AND gate 730, the inverter 732, and the AND gate 734. , Row hammer refresh address RHA can be selected and output as the second address XADD2, and the second refresh operation can be executed.

Regarding the operation method of the row decoder and memory block control 760, the column decoder 770, the LIO gate control and DM control logic 772, the sense amplifier 774, the word driver 780, and the memory cell array 790, the corresponding members in the semiconductor memory device 100 described above are described. Since it is the same as or similar to the above, the description of the operation method will be omitted.

In the present embodiment, each of the memory blocks 640_1 to 640_N has one refresh controller and adopts a structure for controlling. However, the operation method of the first refresh signal CBRSLOT and the second refresh signal RHRSLOT is the above-described embodiment. There is no particular difference. Therefore, a person having ordinary knowledge in this field can apply the circuit arrangement method shown in FIGS. 3, 6, and 8 to the semiconductor memory device 600.

We will explain the internal structure of the CBR decimation circuit by giving an example again. FIG. 11A is a schematic diagram of the CBR thinning circuit 800 according to one embodiment of the present invention. As shown in FIG. 11A, the CBR thinning circuit 800 includes a cycle counter 810, a set signal generator 820, a reset signal generator 830, an inverter 840, a NAND gate 850, a flip-flop 860, and an inverter 870. include. As the structure of the CBR decimation circuit 800, the CBR decimation circuit 310 of FIG. 3 and the CBR decimation circuit 410 of FIG. 6 can be applied.

The cycle counter 810 counts the first clock CBRCLK and generates a count value CNT1. Further, the cycle counter 810 is controlled by the reset signal RESET1 and counts again. The set signal generator 820 is connected to the cycle counter 810. The set signal generator 820 can determine the set value D1 based on the temperature signal TS2 and the first refresh setting information TMRS. When the count value CNT1 changes from the set value D1 to another value, the set signal generator 820 generates the set signal SET1. The reset signal generator 830 is connected to the cycle counter 810. The reset signal generator 830 can determine the set value D2 based on the temperature signal TS2 and the first refresh setting information TMRS. When the count value CNT1 changes from the set value D2 to another value, the reset signal generator 830 generates the reset signal RESET2.

The input terminal of the inverter 840 is connected to the reset signal RESET2. The first input terminal of the NAND gate 850 is connected to the output terminal of the inverter 840, the second input terminal of the NAND gate 850 is connected to the start signal PWR, and the reset signal RESET1 is generated at the output terminal of the NAND gate 850. .. The flip-flop 860 is connected to the set signal generator 820 and the NAND gate 850. The flip-flop 860 can change the logic level of the output terminal based on the set signal SET1 and the reset signal SET1. Further, the output terminal of the inverter 870 is connected to the output terminal of the flip-flop 860, and the output terminal of the inverter 870 generates the first refresh signal CBRSLOT.

FIG. 11B is an example of the operation waveform of the CBR thinning circuit according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 11A and 11B at the same time.

As shown in FIG. 11B, when the power is turned on (that is, the time point T1), the power supply voltage VDD increases. In response to this, the signal related to power-on is activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR changes from 0 to 1 (effective). Subsequently, when the activation signal PWR is activated, the initialization period is entered and the reset signal RESET1 changes from 1 to 0. The reset signal RESET1 can be provided not only to the cycle counter 810 and the flip-flop 860, but also to other related circuits to perform the reset operation. During the reset operation, not only the first refresh signal CBRSLOT is set to 1 (valid), but also, for example, the CBR refresh address RFA of the CBR counter is also reset to 0 (count stop).

Subsequently, after the time point T1, the command decoder starts to periodically generate the first clock CBRCLK in order to periodically start providing the command signal COM instructing the refresh command according to its own setting. However, when the count of the cycle counter 810 with respect to the first clock CBRCLK is smaller than the threshold value (for example, the threshold value x = 128), this circuit (CBR thinning circuit 800) remains stopped from the reset state. That is, the refresh operation is not executed for a while (initial operation). In this embodiment, the refresh operation is used not only for data retention but also for resetting each circuit.

When the first clock CBRCLK continues to be generated and the count for the first clock CBRCLK of the cycle counter 810 reaches the threshold value (that is, the time point T2), the cycle counter 810 is released from the stopped state and the generated count value is generated. CNT1 begins to increase. In response to this, when the count value CNT1 increases from 0 (that is, the set value D1) to 1, the set signal generator 820 generates a pulse of the set signal SET1. The logic level of the output terminal of the flip-flop 860 becomes 1, and the first refresh signal CBRSLOT is set to 0 (invalid). As a result, the first clock CBRCLK can be skipped, and the first refresh signal CBRSLOT is held at 0.

However, when the count value CNT1 reaches 3 (that is, the set value D2) and is about to change (that is, the time point T3), the reset signal generator 830 generates the reset signal RESET2. Along with this, the reset signal RESET1 is generated by arranging the inverter 840 and the NAND gate 850. The reset signal RESET1 resets the flip-flop 860. The logic level of the output terminal of the flip-flop 860 becomes 0, and the first refresh signal CBRSLOT is set to 1 (valid). At the same time, before the count value CNT1 becomes 4, the cycle counter 810 is reset by the reset signal RESET1, so that the count value CNT1 is reset to 0. As a result, the refresh interval adjustment is temporarily stopped, so that the first clock CBRCLK at this time is not skipped.

Similarly, if the first clock CBRCLK is continuously generated, the cycle counter 810 increases the count value CNT1 from 0 to 1. In response to this, the set signal generator 820 generates a pulse of the set signal SET1. The logic level of the output terminal of the flip-flop 860 becomes 1, and the first refresh signal CBRSLOT is set to 0 (invalid). As a result, the refresh interval adjustment is restarted, the first clock CBRCLK is skipped, and the first refresh signal CBRSLOT is held at 0.

After that, the above operation is repeatedly executed. In the present embodiment, the refresh cycle is extended four times (refresh skip rate = 3/4).

We will explain the internal structure of the RHRSLOT generation circuit by giving an example again. FIG. 12A is a schematic diagram of the RHRSLOT generation circuit 900 according to one embodiment of the present invention. As the structure of the RHRSLOT generation circuit 900, the RHRSLOT generation circuit 520 of FIG. 8 can be applied.

The cycle counter 910 counts the third clock RHRCLKD and generates a count value CNT2. Further, the cycle counter 910 is controlled by the reset signal RESET3 and counts again. The set signal generator 920 is connected to the cycle counter 910. The set signal generator 920 can determine the set value D3 based on the temperature signal TS2 and the second refresh setting information TMRHR. When the count value CNT2 changes from the set value D3 to another value, the set signal generator 920 generates the set signal SET2. The reset signal generator 930 is connected to the cycle counter 910. The reset signal generator 930 can determine the set value D4 based on the temperature signal TS2 and the second refresh setting information TMRHR. When the count value CNT2 changes from the set value D4 to another value, the reset signal generator 930 generates the reset signal RESET4.

The input terminal of the inverter 940 is connected to the reset signal RESET4. The first input terminal of the NAND gate 950 is connected to the output terminal of the inverter 940, the second input terminal of the NAND gate 950 is connected to the start signal PWR, and the reset signal RESET3 is generated at the output terminal of the NAND gate 950. .. The flip-flop 960 is connected to the set signal generator 920 and the NAND gate 950. The flip-flop 960 can change the logic level of the output terminal based on the set signal SET2 and the reset signal SET3. Further, the input terminal of the buffer gate 970 is connected to the output terminal of the flip-flop 960, and the output terminal of the buffer gate 970 generates a second refresh signal RHRSLOT.

FIG. 12B is an example of the operating waveform of the RHRSLOT generation circuit according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 12A and 12B at the same time.

As shown in FIG. 12B, when the power is turned on (that is, the time point T4), the power supply voltage VDD increases. In response to this, the signal related to power-on is activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR becomes 0 to 1 (effective). Subsequently, when the activation signal PWR is activated, the initialization period is entered, and the reset signal RESET3 changes from 1 to 0 to become a pulse signal for resetting. The reset signal RESET3 can be provided not only to the cycle counter 910 and the flip-flop 960, but also to other related circuits to perform a reset operation at startup.

Subsequently, after the time point T4, the control signal generator starts to periodically generate the third clock RHRCLKD in order to periodically start providing the command signal COM instructing the refresh command according to its own setting.

When the initialization period ends (that is, the time point T5) and the count value CNT2 increases from fe (set value D3) to ff, the set signal generator 920 generates a pulse of the set signal SET2. The logic level of the output terminal of the flip-flop 960 becomes 1, and the second refresh signal RHRSLOT becomes 1 (valid).

However, when the count value CNT1 has reached ff (that is, the set value D4) and is about to change, the reset signal generator 930 generates the reset signal RESET4. Along with this, the reset signal RESET3 is generated by arranging the inverter 940 and the NAND gate 950. The reset signal RESET3 resets the flip-flop 960. The logic level of the output terminal of the flip-flop 960 becomes 0, and the second refresh signal RHRSLOT becomes 0 (invalid).

Similarly, if the third clock RHRCLKD is continuously generated, the cycle counter 910 increases the count value CNT2 from f to 10. In response to this, the set signal generator 920 generates a pulse of the set signal SET2. The logic level of the output terminal of the flip-flop 960 becomes 1, and the second refresh signal RHRSLOT becomes 1 (valid). As a result, the third clock RHRCLKD is interrupted again, and the second refresh signal RHRSLOT is generated. After that, the above operation can be repeatedly executed.

We will explain the internal structure of the RHR thinning circuit by giving an example again. FIG. 13A is a schematic diagram of the RHR thinning circuit 1000 according to one embodiment of the present invention. As the structure of the RHR thinning circuit 1000, the RHR thinning circuit 510 of FIG. 8 can be applied.

The input terminal of the delay circuit (Delay) 1020 is connected to the second clock RHRCLK. The input terminal of the inverter 1030 is connected to the output terminal of the delay circuit 1020. The first input terminal of the NAND gate 1040 is connected to the output terminal of the inverter 1030, and the second input terminal of the NAND gate 1040 is connected to the start signal PWR. The first control terminal of the flip-flop 1050 is connected to the active signal ACT, and the second control terminal of the flip-flop 1050 is connected to the output terminal of the NAND gate 1040. The output terminal of the flip-flop 1050 is used to provide the first enable signal AEn.

The input terminal of the inverter 1060 is connected to the second refresh signal RHRSLOT. The input terminal of the delay circuit 1070 is connected to the second refresh signal RHRSLOT. The first input terminal of the AND gate 1080 is connected to the output terminal of the inverter 1060, and the second input terminal of the AND gate 1080 is connected to the output terminal of the delay circuit 1070. The input terminal of the inverter 1090 is connected to the start signal PWR. The first control terminal of the flip-flop 1100 is connected to the output terminal of the AND gate 1080, and the second control terminal of the flip-flop 1100 is connected to the output terminal of the inverter 1090. The output terminal of the flip-flop 1100 is used to provide a second enable signal PEn.

The input terminal of the inverter 1110 is connected to the output terminal of the flip-flop 1050 and receives the first enable signal AEn. The first input terminal of the NAND gate 1120 is connected to the output terminal of the inverter 1110, and the second input terminal of the NAND gate 1120 is connected to the output terminal of the flip-flop 1100 to receive the second enable signal PEn. The output terminal of the NAND gate 1120 is used to provide the third enable signal En. The first input terminal of the AND gate 1130 is connected to the output terminal of the NAND gate 1120 to receive the third enable signal En, the second input terminal of the AND gate 1130 is connected to the second clock RHRCLK, and the AND gate 1130. The output terminal of is generated a third clock RHRCLKD. Based on the circuit arrangement method shown in FIG. 13, the function of the RHR thinning circuit can be realized.

FIG. 13B is an example of the operating waveform of the RHR thinning circuit 1000 according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 13A and 13B at the same time.

As shown in FIG. 13B, when the power is turned on (that is, the time point T6), the power supply voltage VDD increases. In response to this, the signal related to power-on is activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR becomes 0 to 1 (effective). Subsequently, when the activation signal PWR is activated, the initialization period is entered. In the initial operation, even if the active signal ACT is not activated, the third enable signal En is also fixed at 1, so that the row hammer refresh (RHR) thinning is not yet started at this time.

Subsequently, after the time point T7, the second refresh signal RHRSLOT starts to be generated. At time point T8, the flip-flop 1100 raises the second enable signal PEn to 1. In response to this, the third enable signal En is not fixed to 1, and starts operating in response to the first enable signal AEn. In this way, when the active signal ACT stops activating, the generation of the third clock RHRCLKD also stops, so that the RHR interrupt rate changes (in FIG. 13B, for example, the RHR interrupt rate 1 / (16 + 1). ) To 1 / (18 + 1)).

It should be explained that, in one embodiment, the RHRSLOT generation circuit can also be the first stage in the RHR state control circuit. FIG. 14 is a schematic diagram of the RHR state control circuit 1200 according to one embodiment of the present invention. The RHRSLOT generation circuit 1210 generates a third refresh signal RHRSLOTPre based on the second clock RHRCLK, and adjusts the output interval of the third refresh signal RHRSLOTPre based on the temperature signal TS2 and the second refresh setting information TMRHR.

The RHR thinning circuit 1220 is connected to the RHRSLOT generation circuit 1210. The RHR decimation circuit 1220 generates a second refresh signal RHRSLOT based on the third refresh signal RHRSLOTPre, the working signal ACT of the corresponding memory block, and the precharge signal PREC. It should be explained that the precharge signal PREC is, for example, a pulse signal generated when an attempt is made to start precharging a bit line. When the control signal generator receives the precharge command, it can generate the precharge signal PREC.

We will explain the internal structure of the RHR thinning circuit by giving an example again. FIG. 15A is a schematic circuit diagram of the RHR thinning circuit 1300 according to one embodiment of the present invention. As the structure of the RHR thinning circuit 1300, the RHR thinning circuit 1220 of FIG. 14 can be applied.

The ACK clock generator 1310 can generate an execution signal ACK based on the active signal ACT, the precharge signal PREC, the temperature signal TS2, and the start signal PWR. The WL activity time counter 1320 is connected to the ACK clock generator 1310. The WL activity time counter 1320 counts the execution signal ACK, generates the first enable signal AEn, is controlled by the reset signal RESET5, and counts again.

The input terminal of the inverter 1330 is connected to the third refresh signal RHRSLOTPre. The input terminal of the delay circuit 1340 is connected to the third refresh signal RHRSLOTPre. The first input terminal of the AND gate 1350 is connected to the output terminal of the inverter 1330, the second input terminal of the AND gate 1350 is connected to the output terminal of the delay circuit 1340, and the output terminal of the AND gate 1350 is the reset signal RESET5. To generate.

The input terminal of the inverter 1360 is connected to the start signal PWR. The first control terminal of the flip-flop 1370 is connected to the reset signal RESET5, and the second control terminal of the flip-flop 1370 is connected to the output terminal of the inverter 1360. The output terminal of the flip-flop 1370 is used to provide a second enable signal PEn.

The input terminal of the inverter 1380 is connected to the output terminal of the WL activity time counter 1320 and receives the first enable signal AEn. The first input terminal of the NAND gate 1390 is connected to the output terminal of the inverter 1380, and the second input terminal of the NAND gate 1390 is connected to the output terminal of the flip-flop 1370 to receive the second enable signal PEn. The output terminal of the NAND gate 1390 is used to provide the third enable signal En. The first input terminal of the AND gate 1400 is connected to the output terminal of the NAND gate 1390, the second input terminal of the AND gate 1400 is connected to the third refresh signal RHRSLOTPre, and the output terminal of the AND gate 1400 is the second refresh. Generate the signal RHRSLOT. Based on the circuit arrangement method shown in FIG. 15A, the function of the RHR thinning circuit can be realized.

FIG. 15B is an example of an operating waveform of the RHR thinning circuit 1300 according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 15A and 15B at the same time.

As shown in FIG. 15B, when the power is turned on (that is, the time point T9), the power supply voltage VDD increases. In response to this, the signal related to power-on is activated. For example, when the power supply voltage VDD reaches a predetermined stable potential, the start signal PWR becomes 0 to 1 (effective). Subsequently, when the activation signal PWR is activated, the initialization period is entered. In the initial operation, even if the active signal ACT is not activated, the third enable signal En is also fixed at 1, so that the row hammer refresh (RHR) thinning is not yet started at this time.

Subsequently, after the time point T10, the third refresh signal RHRSLOTPre is started to be generated. At time point T11, flip-flop 1370 raises the second enable signal PEn to 1. In response to this, since the third enable signal En is not fixed to 1, the operation starts in response to the first enable signal AEn. As described above, when the count for the active signal ACT of the WL activity time counter 1320 does not reach the set threshold value, even if the third refresh signal RHRSLOTPre is received, the generation of the second refresh signal RHRSLOT is stopped.

We will once again explain the internal structure of the ACK clock generator with an example. FIG. 16A is a schematic diagram of the ACK clock generator 1500 according to one embodiment of the present invention. As for the structure of the ACK clock generator 1500, the ACK clock generator 1310 of FIG. 15 can be applied.

The input terminal of the inverter 1510 is connected to the precharge signal PREC. The first input terminal of the NAND gate 1520 is connected to the output terminal of the inverter 1510, and the second input terminal of the NAND gate 1520 is connected to the start signal PWR. The first control terminal of the flip-flop 1530 is connected to the active signal ACT, and the second control terminal of the flip-flop 1530 is connected to the output terminal of the NAND gate 1520. The output terminal of the flip-flop 1530 is used to provide the fourth enable signal EnP.

The input terminal of the inverter 1540 is connected to the output terminal of the flip-flop 1530 and receives the fourth enable signal EnP. The first input terminal of the NAND gate 1550 is connected to the output terminal of the inverter 1540, and the second input terminal of the NAND gate 1550 is connected to the output terminal of the inverter 1552. The output terminal of the NAND gate 1550 is used to provide the fifth enable signal EnS. The input terminal of the oscillator 1560 is connected to the output terminal of the NAND gate 1550 to receive the fifth enable signal EnS, the control terminal of the oscillator 1560 is connected to the temperature signal TS2 and the oscillation information TMRHOSC, and the output terminal of the oscillator 1560 is. , Generates an oscillation signal OSC and is connected to the input terminal of the inverter 1552 and the input terminal of the delay circuit 1562. The output terminal of the delay circuit 1562 is used to provide the oscillation signal OSCD.

The input terminal of the delay circuit 1570 is connected to the output terminal of the delay circuit 1562 and receives the oscillation signal OSCD. The input terminal of the inverter 1580 is connected to the output terminal of the delay circuit 1570. The first input terminal of the NAND gate 1590 is connected to the oscillation signal OSCD, the second input terminal of the NAND gate 1590 is connected to the output terminal of the inverter 1580, and the output terminal of the NAND gate 1590 generates the execution signal ACKF. be able to.

The input terminal of the inverter 1600 is connected to the active signal ACT. The first input terminal of the NAND gate 1610 is connected to the output terminal of the inverter 1600, the second input terminal of the NAND gate 1610 is connected to the output terminal of the NAND gate 1590, receives the execution signal ACKF, and receives the execution signal ACKF. The output terminal can generate an execution signal ACK.

FIG. 16B is an example of the operating waveform of the ACK clock generator 1500 according to one embodiment of the present invention. The refresh operation of the present embodiment will be described with reference to FIGS. 16A and 16B at the same time.

As shown in FIG. 16B, in the situation where the command signal COM instructing the activation is received at the time point T12 and the command signal COM instructing the write operation is received at the time point T13, the flip-flop 1530 is an active signal. You can receive ACT. With the circuit arrangement shown in FIG. 16A, the oscillator 1560 generates an oscillation signal OSC so that the NAND gate 1610 can generate the corresponding execution signal ACK.

On the other hand, as shown in FIG. 16B, the flip-flop 1530 does not receive the active signal ACT in the situation where the command signal COM instructing auto-refresh is received at the time point T14. In this way, the oscillator 1560 does not generate the oscillation signal OSC and the NAND gate 1610 also does not generate the execution signal ACK.

Further, as shown in FIG. 16B, the flip-flop 1530 also receives the command signal COM instructing the activation at the time point T15 and the command signal COM instructing the read operation at the time point T16. The active signal ACT can be received. With the circuit arrangement shown in FIG. 16A, the oscillator 1560 generates an oscillation signal OSC so that the NAND gate 1610 can generate the corresponding execution signal ACK.

As described above, the semiconductor memory device of the present invention has a signal for executing the CBR refresh operation (first refresh signal) and a signal for executing the row hammer refresh operation (second), respectively, based on the refresh operation signal. A refresh signal) can be generated. Further, in the present invention, the execution cycles of CBR refresh (first refresh) and row hammer refresh (second refresh) are appropriately thinned out on the premise of providing necessary and sufficient refresh opportunities within the entire temperature range. can do. As a result, the data holding capacity can be secured and the power consumption can be reduced.

100, 600 Semiconductor memory device 110, 610 Temperature sensor 120, 620 Mode register and OTP block 130, 300, 400, 710 Refresh controller 140_i, 140_1 to 140_N, 640_i, 640_1 to 640_N Memory block 150, 650 Command decoder 152, 250, 750 address MUX
154, 654 Column address counter and latch 156, 656 Bank address control logic 161, 661 Address input buffer 162, 662 Address decoder 163, 663 Command input buffer 164, 664 Clock input buffer 165, 665 Internal clock generator 166, 666 Internal power supply Circuit 167, 667 DQ input / output buffer 171, 671 Address terminal 172, 672 Command terminal 173, 673 Clock terminal 174, 674 Data terminal 175, 675 Data mask terminal 176, 177, 676, 677 Power supply terminal 180, 680 GIO and GIO Gate control 210, 720 OR gate 220, 230, 350, 380, 450, 460, 722, 730, 734, 1080, 1130, 1350, 1400 AND gate 240, 740 RHR detection circuit 260, 760 Row decoder and memory block control 270 , 770 Column Decoder 272, 772 LIO Gate Control and DM Control Logic 274, 774 Sense Amplifier 280, 780 Word Driver 290, 790 Memory Array 390, 860, 960, 1050, 1100, 1370, 1530 Flip Flop 310, 410, 800 CBR Thinning circuit 320, 420, 500, 1200 RHR state control circuit 330, 430 CBR counter 340, 440, 970 Buffer gate 370, 840, 870, 940, 1030, 1060, 1090, 1110, 1330, 1360, 1380, 1510, 1540 , 1552, 1580, 1600 Inverter 470, 850, 950, 1040, 1120, 1390, 1520, 1550, 1590, 1610 NAND Gate 510, 1000, 1220, 1300 RHR thinning circuit 520, 900, 1210 RHRSLOT generation circuit 810, 910 cycle Counter 820, 920 Set signal generator 830, 930 Reset signal generator 1020, 1070, 1340, 1563, 1570 Delay circuit 1320 WL Activity time counter 1310, 1500 ACK Clock generator 1560 Oscillator Aen 1st enable signal ACK Execution signal ACT action Medium signal ADD address signal BA block address BS_i, BS_1 to BS_N block selection signal CK, CKB external clock signal COM command signal RFA CBR refresh address BADD block access address CBR selection signal CBRCLK 1st clock CBRCNT, CBRCNTP count signal CBRSLOT 1st refresh signal CNT1, CNT2 count value DQ input / Output data DM data Mask signal En 3rd enable signal EnP 4th enable signal EnS 5th enable signal ICLK, LCLK Internal clock signal MIO Main input / output line MRS mode signal OSC, OSCD oscillation signal P40 to P43, P50, P51, P70, P71 pulse Pen 2nd enable signal RD read signal PREC precharge signal PWR start signal RESET1 to RESET5 reset signal RFEX valid refresh signal RFIP, RFIP_i refresh operation signal RHA low hammer refresh address SET1, SET2 set signal RHRCLK 2nd clock EHECLKD RHRSLOT 2nd refresh signal RHRSLOTPre 3rd refresh signal SAEn detection start signal SW mode switching signal T1 to T17 time point TS, TS2 temperature signal TMRHR 2nd refresh setting information TMRS 1st refresh setting information tREFI refresh interval VDD, VSS, VDDQ, VSSQ Power supply voltage VPP, VBB, VBLH, VOD, VINT Internal potential WT Write signal XADD address data XADD1 1st row address XRED Spare row address YADD, YADD1 Column address

Claims (14)

A temperature sensor for detecting the device temperature inside the semiconductor memory device and generating a corresponding temperature signal,
A memory cell array having a plurality of volatile memory cells and a plurality of word lines, each of which is a plurality of memory blocks connected to the volatile memory cell.
The first refresh operation, which is connected to the temperature sensor and the memory block, monitors the access to the word line, detects the access that appears a predetermined number of times within a predetermined period, and performs the refresh operation corresponding to the refresh operation command. And a refresh controller that distributes to the second refresh operation,
Semiconductor memory device including. The first refresh operation is thinned out and activated based on the information on the device temperature, and the second refresh operation is thinned out and activated based on the information on the amount of access to the word line. When the first refresh operation and the second refresh operation are in the same cycle and two internal refreshes cannot be executed in the same cycle, the refresh controller is used to execute one refresh operation during the cycle. The semiconductor memory device according to claim 1, wherein the refresh operation that has not been executed is controlled to be transferred to the next cycle and executed. The semiconductor memory device according to claim 1, wherein the first refresh operation is a refresh operation for executing a CBR refresh, and the second refresh operation is a refresh operation for executing a row hammer refresh. Further including a mode register and an OTP block connected to the refresh controller and generating a first refresh setting information and a second refresh setting information based on a mode signal.
The refresh controller outputs a first refresh signal and a second refresh signal based on the refresh operation signal, and outputs an output interval of the first refresh signal based on the first refresh setting information and the temperature signal, respectively. The output interval of the second refresh signal is adjusted based on the second refresh setting information and the temperature signal.
The memory block responds to the first refresh signal to execute the first refresh operation, and responds to the second refresh signal to execute the second refresh operation.
When the refresh controller generates a CBR refresh address based on the first refresh signal and the second refresh signal and simultaneously outputs the first refresh signal and the corresponding second refresh signal, each memory. The semiconductor memory device according to claim 1, wherein the block executes one of the first refresh operation and the second refresh operation. A first address that is connected to the refresh controller and the memory block, receives the data address and the CBR refresh address, and selects the data address or the CBR refresh address as the first row address based on the refresh operation signal. The semiconductor memory device according to claim 4, further comprising a MUX. Each of the memory blocks
An AND gate in which the first input terminal is connected to the refresh operation signal, the second input terminal is connected to the second refresh signal, and the output terminal generates a row hammer signal.
An RHA detection circuit connected to the output terminal of the AND gate and generating a row hammer refresh address based on the working signal, the row hammer signal, and the second row address.
The first input terminal is connected to the first row address, the second input terminal is connected to the row hammer refresh address, and the first row address or the row hammer refresh address is assigned based on the row hammer signal. The second address MUX, which is selected as the 2 row address and output, and
A row decoder and memory block control that are connected to the RHA detection circuit and the second address MUX, latch and output the second row address as a block access address based on the active signal, and
The semiconductor memory device according to claim 5. The refresh controller
CBR decimation that outputs the first refresh signal based on the first clock and adjusts the output interval of the first refresh signal based on the temperature signal, the first refresh setting information, and the CBR refresh address. Circuit and
It is connected to the CBR thinning circuit, outputs the second refresh signal based on the second clock, and adjusts the output interval of the second refresh signal based on the temperature signal and the second refresh setting information. RHR state control circuit and
A CBR counter connected to the CBR thinning circuit and the RHR state control circuit, counting the number of executions of the first refresh operation based on the first count signal, and generating the CBR refresh address.
The semiconductor memory device according to claim 4. The RHR state control circuit
An RHR decimation circuit that generates a third clock based on the second clock, the second refresh signal, and the active signal.
It is connected to the RHR thinning circuit, generates the second refresh signal based on the third clock, and adjusts the output interval of the second refresh signal based on the temperature signal and the second refresh setting information. RHRSLOT generation circuit and
The semiconductor memory device according to claim 7. The semiconductor memory device according to claim 1, further comprising a command decoder connected to the refresh controller and starting to generate a refresh operation signal when the refresh operation command is received. A temperature sensor for detecting the device temperature inside the semiconductor memory device and generating a corresponding temperature signal,
A refresh controller, a memory cell array having a plurality of volatile memory cells, and a plurality of word lines connected to the temperature sensor, each of which is connected to a plurality of memory blocks connected to the volatile memory cell. ,
The refresh controller monitors the access to the corresponding word line, detects the access that appears a predetermined number of times within a predetermined period, and performs the refresh operation corresponding to the refresh operation command in the first refresh operation and A semiconductor memory device that distributes to the second refresh operation. It further includes a mode register and an OTP block that are connected to the refresh controller and generate first refresh setting information (TMRS) and second refresh setting information (TMRHR) based on the mode signal.
Each refresh controller outputs the first refresh signal and the second refresh signal based on the refresh operation signal, and outputs the output interval of the first refresh signal based on the first refresh setting information and the temperature signal, respectively. The output interval of the second refresh signal is adjusted based on the second refresh setting information and the temperature signal.
Each memory block performs a first refresh operation in response to the corresponding first refresh signal and performs a second refresh operation in response to the corresponding second refresh signal.
Corresponding to when the refresh controller generates a CBR refresh address based on the corresponding first refresh signal and the second refresh signal, and simultaneously outputs the first refresh signal and the corresponding second refresh signal. The semiconductor memory device according to claim 10, wherein the memory block performs one of the first refresh operation and the second refresh operation. Each of the memory blocks
A first AND gate in which the first input terminal is connected to the refresh operation signal, the second input terminal is connected to the second refresh signal, and a row hammer signal is generated at the output terminal.
An RHA detection circuit connected to the output terminal of the first AND gate and generating a row hammer refresh address based on an active signal, the row hammer signal, and a row address.
An inverter whose input terminal is connected to the second refresh signal,
The first input terminal is connected to the refresh operation signal, the second input terminal is connected to the first refresh signal, the third input terminal is connected to the output terminal of the inverter, and a selection signal is generated at the output terminal. The second AND gate and
The first input terminal is connected to the CBR refresh address, the second input terminal is connected to the data address, the third input terminal is connected to the row hammer refresh address, and based on the row hammer signal and the selection signal. , The address MUX that selects and outputs one of the CBR refresh address, the data address, and the row hammer refresh address as the row address, and
A flip-flop connected to the RHA detection circuit and the address MUX, latching the row address as a block access address based on the active signal, and outputting the flip-flop.
The semiconductor memory device according to claim 11. Each refresh controller
CBR decimation that outputs the first refresh signal based on the first clock and adjusts the output interval of the first refresh signal based on the temperature signal, the first refresh setting information, and the CBR refresh address. Circuit and
It is connected to the CBR thinning circuit, outputs the second refresh signal based on the second clock, and adjusts the output interval of the second refresh signal based on the temperature signal and the second refresh setting information. RHR state control circuit and
A CBR counter connected to the CBR thinning circuit and the RHR state control circuit, counting the number of executions of the first refresh operation based on the first count signal, and generating the CBR refresh address.
The semiconductor memory device according to claim 11. The RHR state control circuit
An RHRSLOT generation circuit that generates a third refresh signal based on the second clock and adjusts the output interval of the third refresh signal based on the temperature signal and the second refresh setting information.
An RHR decimation circuit connected to the RHRSLOT generation circuit and generating the second refresh signal based on the third refresh signal, the corresponding active signal, and the precharge signal.
13. The semiconductor memory device according to claim 13.

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