JP7048650B2 - Memory device and method - Google Patents

Description

The present embodiment relates to a memory device and a method .

The solid state drive (SSD) includes a non-volatile memory such as, for example, a NAND flash memory. The NAND flash memory includes a plurality of blocks (physical blocks). A plurality of blocks include a plurality of memory cells arranged at the intersection of a word line and a bit line.

Japanese Unexamined Patent Publication No. 2012-141944

The present embodiment provides a memory device and a method for efficiently managing address translation data.

According to the present embodiment, the memory device includes a non-volatile memory, a cache memory, and a processor. The processor uses a part of each fragment of the address mapping corresponding to the target logical address of access and a part of the data mapping fragment corresponding to the target logical address as a cache line from the non-volatile memory to the cache memory. It is configured to access the physical address mapped from the target logical address to the non-volatile memory by referencing multiple layers of address mapping that are loaded and loaded as cache lines into the cache memory. Each bit of the data mapping indicates whether the data stored in the physical address of the non-volatile memory is valid. Each of the plurality of layers has a plurality of fragments, and the elements that are a part of the fragments belonging to the upper layer have a hierarchical structure corresponding to the fragments belonging to the lower layer. Each of the multiple fragments belonging to each layer except the bottom layer of the multiple layers is divided into multiple elements corresponding to the multiple fragments belonging to the layer immediately below, and the multiple fragments belonging to the layer directly below are divided into multiple elements. Contains multiple referenced information to indicate. The plurality of fragments belonging to the lowest layer among the plurality of layers indicate the correspondence between each logical address mapped to the lowest layer and the physical address of the non-volatile memory for each logical address. The data mapping fragment has the same size as each of the loaded fragments of multiple layers of address mapping. The cache line of each fragment of the loaded address mapping layer, or the cache line of the loaded data mapping fragment, further includes pointers to the cache lines referenced before and after it.

The block diagram which shows an example of the structure of the information processing system which concerns on 1st Embodiment. A conceptual diagram illustrating a typical look-up table and an active data map. The conceptual diagram which illustrates the structure of the hierarchical look-up table which concerns on 1st Embodiment. The data structure diagram which illustrates the data format of the fragment of the hierarchical look-up table which concerns on 1st Embodiment. The data structure diagram which illustrates the data format of the fragment of the active data map which concerns on 1st Embodiment. The data structure diagram which illustrates the data format used at the time of writing back from the cache memory to the non-volatile memory which concerns on 1st Embodiment. The flowchart which illustrates the search process of the physical address which concerns on 1st Embodiment. The block diagram which illustrates the relationship of the cache line in the search process of the physical address which concerns on 1st Embodiment. The data structure diagram which illustrates the list structure of the cache memory which concerns on 1st Embodiment. The flowchart which illustrates the state change of the cache line in the cache memory which concerns on 1st Embodiment. The block diagram which illustrates the state change of the cache line in the cache memory which concerns on 1st Embodiment. The block diagram which illustrates the relationship between the fragment of the hierarchical look-up table which concerns on 1st Embodiment, and the page of a non-volatile memory.

Hereinafter, each embodiment will be described with reference to the drawings. In the following description, substantially the same functions and components are designated by the same reference numerals, and duplicate explanations are given only when necessary.

[First Embodiment]
This embodiment describes a memory device including a hierarchical look-up table (hereinafter referred to as LUT). A LUT is a type of address translation data used for translation from a physical address to a logical address.

In the present embodiment, the memory device is, for example, an SSD, but various types of memory such as a memory card, a hard disk drive (HDD), a hybrid memory device including an HDD and an SSD, an optical disk, a storage device, and a memory server. It may be a device. When the memory device is an SSD, the memory device has the same communication interface as the HDD.

A memory device that is an SSD includes a non-volatile memory. In this embodiment, a case where the non-volatile memory includes a NAND flash memory will be described. However, the non-volatile memory is a NAND such as a NOR type flash memory, an MRAM (Magnetoresistive Random Access Memory), a PRAM (Phase change Random Access Memory), a ReRAM (Resistive Random Access Memory), or a FeRAM (Ferroelectric Random Access Memory). It may include other types of memory that are not type flash memory. Further, the non-volatile memory may include a flash memory having a three-dimensional structure.

In the non-volatile memory, data is erased collectively for each erase unit area. The erase unit area includes a plurality of write unit areas and a plurality of read unit areas. When the non-volatile memory is a NAND flash memory, the erasing unit area corresponds to a block. The write unit area and the read unit area correspond to pages.

In the present embodiment, the access means both writing or storing data in the memory and reading data from the memory.

In this embodiment, the program is a computer program. In a computer program, the processes that a computer should perform are described in order. By being executed by a computer, the program can realize various functions such as command, data, and issuance and reception of information, data processing, and calculation.

In the present embodiment, the computer is, for example, a machine that executes an operation or a process according to an instruction. For example, a computer includes a memory and a processor. The memory stores the program. A processor is hardware for executing an instruction set (for example, data transfer, calculation, processing, control, management) described in a program stored in a memory. In the present embodiment, the computer should be interpreted in a broad sense, and includes, for example, an information processing device, a controller of a memory device, a personal computer, a large computer, a microcomputer, a server device, and the like. In the present embodiment, instead of the computer, a computer system in which a plurality of computers operate in cooperation with each other may be used.

In this embodiment, the software interface is, for example, a convention and procedure defined for one program to utilize the other program. More specifically, the software interface defines, for example, a procedure and a data format for calling a function of a certain program and data to be managed from another program, and using the called function and the data to be managed. It is a convention. An API (Application Programming Interface) is an example of a software interface.

In this embodiment, the identification information is referred to as an ID.

FIG. 1 is a block diagram showing an example of an information processing system according to the present embodiment.

The information processing system 1 includes an information processing device 2 and a memory device 3. The information processing device 2 can operate as a host device corresponding to the memory device 3.

The memory device 3 may be built in the information processing device 2, and the information processing device 2 and the memory device 3 may be connected to each other so as to be able to transmit and receive data by a network or the like. The memory device 3 may be communicably connected to a plurality of information processing devices 2. Further, a plurality of memory devices 3 may be communicably connected to one or more information processing devices 2.

The memory device 3 includes a controller 4 as an example of a control circuit and a non-volatile memory 5. The controller 4 and the non-volatile memory 5 may be detachable, and the memory capacity of the memory device 3 may be freely expanded. Here, the memory capacity is the maximum amount of data that can be written to the memory.

The controller 4 includes a communication interface control unit 41, a write buffer memory 42, a read buffer memory 43, a processor 44, memories 45A and 45B, and a non-volatile memory controller 46. These are electrically connected by an internal bus IB. Further, the controller 4 is electrically connected to the non-volatile memory 5.

The communication interface control unit 41 includes, for example, a transmission / reception control unit 411 and a command control unit 412. The communication interface control unit 41 communicates between the external device and the memory device 3 according to the communication interface.

The transmission / reception control unit 411 controls the reception of data, information, signals, commands, requests, messages, designations, etc. from an external device such as the information processing device 2, and the data, information, signals to the external device, etc. Controls the sending of commands, requests, messages, specifications, etc.

The transmission / reception control unit 411 transmits / receives data to / from, for example, the information processing apparatus 2. The transmission / reception control unit 411 stores the data received from the information processing apparatus 2 in the write buffer memory 42. The transmission / reception control unit 411 reads the data read from the non-volatile memory 5 from the read buffer memory 43 and transmits the data to the information processing apparatus 2.

More specifically, the transmission / reception control unit 411 transmits / receives data to / from the information processing apparatus 2. The transmission / reception control unit 411 stores the data received from the information processing apparatus 2 in the write buffer memory 42. The transmission / reception control unit 411 reads the data read from the non-volatile memory 5 from the read buffer memory 43 and transmits the data to the information processing apparatus 2.

The command control unit 412 controls, for example, the reception of commands, messages, requests, commands, etc. from an external device, and controls the transmission of commands, messages, requests, commands, etc. to the external device.

More specifically, the command control unit 412 sends and receives commands to and from the information processing device 2. When the command received from the information processing apparatus 2 is a write command, the command control unit 412 sends a write command to the write control unit 441. Further, when the command received from the information processing apparatus 2 is a read command, the command control unit 412 sends a read command to the read control unit 442.

Even if the command sent / received between the information processing device 2 and the command control unit 412 and the command sent / received inside the memory device 3 have the same name, the command formats may be different from each other.

All or part of the functions of the communication interface control unit 41 may be realized by the processor 44, or may be realized by a processor other than the processor 44.

The write buffer memory 42 temporarily stores the write data transmitted from the information processing apparatus 2. Specifically, the write buffer memory 42 temporarily stores the data until the write data has a predetermined data size suitable for the non-volatile memory 5.

The read buffer memory 43 temporarily stores the read data read from the non-volatile memory 5. Specifically, in the read buffer memory 43, the read data are rearranged in an order suitable for the information processing device 2 (order of logical addresses designated by the information processing device 2).

The processor 44 controls the operation of the entire controller 4 via the internal bus IB.

For example, the processor 44 temporarily stores the control program P stored in the memory 45B in the memory 45A, and executes the control program P stored in the memory 45A. Thereby, for example, the processor 44 realizes the functions as a write control unit 441, a read control unit 442, a garbage collection control unit 443, an initialization unit 444, and an address translation unit 445. The write control unit 441, the read control unit 442, the garbage collection control unit 443, the initialization unit 444, and the address translation unit 445 may be freely combined or separated. For example, the initialization unit 444 and the address translation unit 445 may be combined. The write control unit 441, the read control unit 442, the garbage collection control unit 443, the initialization unit 444, and the address translation unit 445 may be realized by hardware.

The processor 44 may be, for example, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), or the like.

The write control unit 441 controls, for example, to send data or the like from the communication interface control unit 41 to the non-volatile memory controller 46 via the write buffer memory 42.

More specifically, the write control unit 441 converts the logical address into a physical address by using the address conversion unit 445 according to the write command from the command control unit 412, and the write command, the write data, and the physical address are non-volatile. Send to the sex memory controller 46.

The read control unit 442 controls, for example, to send data or the like from the non-volatile memory controller 46 to the communication interface control unit 41 via the read buffer memory 43.

More specifically, the read control unit 442 converts the logical address into a physical address by using the address conversion unit 445 according to the read command from the command control unit 412, and the read command and the physical address are converted into a non-volatile memory controller. It is sent to 46, receives read data corresponding to a physical address from the non-volatile memory controller 46, and sends the read data to the information processing apparatus 2 via the read buffer memory 43 and the communication interface control unit 41.

The garbage collection control unit 443 performs garbage collection of the non-volatile memory 5. For example, the garbage collection control unit 443 may perform garbage collection of the non-volatile memory 5 by cooperating with the write control unit 441, the read control unit 442, and the non-volatile memory controller 46. In the present embodiment, the garbage collection is a process of releasing an unnecessary area of the memory. Here, when the non-volatile memory 5 is a NAND flash memory, it is necessary to erase the block in order to release an unnecessary area of the memory. Therefore, valid data that may be available in the block subject to garbage collection is moved to another block. Therefore, when the non-volatile memory 5 is a NAND flash memory, compaction tends to be executed together with garbage collection.

The memory 45A includes, for example, a main storage device used as a working memory of the processor 44 and is subject to control from the processor 44. The memory 45A stores, for example, a program, data, information, and the like to be processed by the processor 44. In the present embodiment, the case where the memory 45A is a DRAM (Dynamic Random Access Memory) will be described, but for example, other volatile memory may be used, or non-volatile memory such as SRAM (Static Random Access Memory) may be used. It may be memory.

The initialization unit 444 generates the hierarchical LUT 51 in the initial state. For example, the initialization unit 444 determines the number of layers in each namespace of the hierarchical LUT 51 and the data capacity corresponding to each layer based on the setting information of the memory device 3 such as the capacity of the non-volatile memory 5 and the capacity of the namespace. , The link relationship between the layers is determined, and the data structure of the hierarchical LUT 51 in the initial state is determined. For example, the initialization unit 444 writes the hierarchical LUT 51 in the initial state to the non-volatile memory 5.

The initialization unit 444 generates an active data map 52 (Active Data Map, hereinafter referred to as ADM) in the initial state. The ADM is data that manages whether the data stored in the non-volatile memory 5 is valid or invalid. For example, the ADM 52 sets “1” when the data of the minimum unit is valid and “0” when the data of the minimum unit is invalid for each minimum unit of the data written in the non-volatile memory 5, and is in the initial state. Write the ADM 52 to the non-volatile memory 5. Details of the ADM 52 will be described later.

The cache memory control unit 447 reads, for example, a part of the hierarchical LUT 51 or a part of the ADM 52 from the non-volatile memory 5 by using the read control unit, and caches a part of the read hierarchical LUT 51 or a part of the ADM 52. It is stored in the memory 451. Further, the cache memory control unit 447 uses, for example, the write control unit 441 to transfer a part of the hierarchical LUT 51 or a part of the ADM 52 stored in the cache memory 451 to the hierarchical LUT 51 or the ADM 52 of the non-volatile memory 5. Controls to write back.

The processing of the cache memory control unit 447 may be realized by the cooperation of the address translation unit 445 and the data map management unit 446. In this case, the cache memory control unit 447 may be omitted.

Further, the cache memory control unit 447 manages whether the cache line stored in the cache memory 451 belongs to a free list, a clean list, or a dirty list. In the present embodiment, the cache line is, for example, unit size data stored in the cache memory 451. A description of the free list, clean list, and dirty list will be described later.

The address translation unit 445 hierarchically describes the translation from the logical address to the physical address for the hierarchical LUT 51 each time data is written. Further, the address translation unit 445 uses the hierarchical LUT 51 to translate a logical address into a physical address. More specifically, the address conversion unit 445 searches for partial data that is a part of the hierarchical LUT 51 to be stored in the cache memory 451 according to the hierarchical structure of the hierarchical LUT 51, and the partial data is stored in the cache memory 451. The logical address is converted into a physical address by storing the data in the cache memory 451 and referring to the cache memory 451. Details of the hierarchical LUT 51 will be described later.

The data map management unit 446 updates the ADM 52 every time data is written. More specifically, the data map management unit 446 writes and reads a part of the ADM 52 stored in the cache memory 451. After that, a part of the ADM 52 stored in the cache memory 451 is written back to the non-volatile memory 5.

The memory 45B includes a non-volatile storage device for storing programs and data used in the controller 4, such as the control program P.

The non-volatile memory controller 46 controls writing data to and from the non-volatile memory 5 and reading data from the non-volatile memory 5.

The non-volatile memory controller 46 preferably includes a DMAC (Direct Memory Access Controller), an error correction unit, a randomizer (or Scrambler), and the like. However, the non-volatile memory controller 46 does not have to include these functions.

The DMAC transfers write data, read data, and the like via the internal bus IB. A plurality of DMACs may be set at various positions in the controller 4, if necessary.

The error correction unit adds an error correction code (for example, Error Correcting Code (ECC)) to the write data transmitted from the write buffer memory 42. The error correction unit uses ECC to correct the read data read from the non-volatile memory 5 as necessary.

When writing data to the non-volatile memory 5, the randomizer distributes the write data so that the write data is not biased toward a specific page or word line direction of the non-volatile memory 5 (referred to as randomization processing). As a result, the number of writes can be leveled, and the life of the memory cell of the non-volatile memory 5 can be extended. Therefore, the reliability of the non-volatile memory 5 can be improved. In addition, the randomizer executes the reverse processing of the randomization processing at the time of writing at the time of the data reading operation, and restores the original data.

The cache memory 451 included in the memory 45A stores the cache data of the hierarchical LUT 51 and the ADM 52 stored in the non-volatile memory 5. More specifically, the cache memory 451 is faster read and write than the non-volatile memory 5, stores partial data that is part of the hierarchical LUT 51, and is part of the ADM 52. Stores map partial data. In this embodiment, the hierarchical LUT 51 and the ADM 52 are written in the non-volatile memory 5. However, at least one of the hierarchical LUT 51 and the ADM 52 may be stored in another non-volatile memory provided in the memory device 3, such as the memory 45B. Further, the non-volatile memory 5 is divided into a memory (or a memory area) for storing user data, a memory (or a memory area) for storing the hierarchical LUT 51, and a memory (or a memory area) for storing the ADM 52. May be good.

When the hierarchical LUT 51 is stored in the non-volatile memory 5, the cache memory control unit 447 reads a part (partial data) or all of the contents of the hierarchical LUT 51 from the non-volatile memory 5 into the cache memory 451. Further, the cache memory control unit 447 reflects the contents of the rewritten cache memory 451 in the hierarchical LUT 51 of the non-volatile memory 5 at an arbitrary timing.

Similarly, when the ADM 52 is stored in the non-volatile memory 5, the cache memory control unit 447 reads a part (map partial data) or the entire contents of the ADM 52 from the non-volatile memory 5 into the cache memory 451. Further, the cache memory control unit 447 reflects the contents of the rewritten cache memory 451 in the ADM 52 of the non-volatile memory 5 at an arbitrary timing.

When the non-volatile memory is a NAND flash memory, the LUT has a logical address of write data or read data (hereinafter referred to as Logical Block Addressing (LBA)) and a physical address (hereinafter referred to as Physical Block Addressing (PBA)). It is the data related to.

The hierarchical LUT 51 is data in which the LUT is hierarchically configured. More specifically, the hierarchical LUT 51 associates an LBA designated as a write destination or a read destination with a PBA indicating the position of the non-volatile memory 5 by a hierarchical structure having a plurality of layers. By using the hierarchical LUT 51, the processor 44 can efficiently search for the PBA corresponding to the LBA or the LBA corresponding to the PBA.

The hierarchical LUT 51 may have a data structure in a table format, or may have another data structure such as a list format. The hierarchical LUT 51 includes a plurality of partial data (eg, a table). In the following, partial data will be referred to as fragments. Fragment is fragmented data. The plurality of fragments are, for example, a predetermined size, that is, the same size. Multiple fragments belong to multiple layers. The first fragment belonging to the first layer of the plurality of layers is a logical address and a plurality of references for referencing the plurality of second fragments belonging to the second layer below the first layer. Includes destination information (hereinafter referred to as pointer). The lowest fragment in a hierarchical structure contains a logical address and a physical address. Each of the top-level fragments belonging to the top-level layer corresponds to each of the plurality of namespaces. The hierarchical LUT 51 has a different number of layers of the plurality of namespaces according to the storage capacity of the plurality of namespaces. For example, the number of layers of a namespace having a small storage capacity is small, and the number of layers of a namespace having a large storage capacity is large. Each predetermined size of the plurality of fragments corresponds to, for example, the unit size of the cache line contained in the cache memory. The details of the hierarchical LUT 51 will be described later.

In this embodiment, the configuration of the controller 4 shown in FIG. 1 is an example, and the controller 4 is not limited to the configuration of FIG.

The cache memory 451 is a cache memory for speeding up access to the hierarchical LUT 51 and the ADM 52, and stores a part of the hierarchical LUT 51 and the ADM 52. Further, the cache memory 451 may be rewritten by the write control unit 441 via the write buffer memory 42, or may be read by the read control unit 442 via the read buffer memory 43.

FIG. 2 is a conceptual diagram illustrating a general LUT and ADM. In FIG. 2 and FIGS. 3 and 8 described later, kilobytes are referred to as KB.

The LUT L relates the LBA and PBA of the data of the NAND flash memory M. In the LUT L of FIG. 2, LBA Y corresponds to PBA X. 4KB of data D is written in the area of the NAND flash memory M represented by PBA X. The amount of data that can be written to the PBA can be changed arbitrarily.

Here, for example, assuming that the size of the PBA stored in each LBA of the LUT L is 32 bits (4 bytes), the LUT L has a data amount of 4 bytes in order to store the PBA X corresponding to the data D of 4 KB. Needs. That is, a LUT having a size 1/1000 of the size of the NAND flash memory M is required.

The LUT L needs to be cached on the DRAM from the NAND flash memory M at the start of use (when energized) of the NAND flash memory M. Therefore, as the size of the LUT L increases in proportion to the capacity of the NAND flash memory M, the time required for caching also increases. For example, in a memory device equipped with a NAND flash memory M of about 1 TB, the size of the LUT L is about 1 Kigabyte (GB), and it takes about several tens of seconds until the LUT L is read out on the DRAM when the power of the memory device 3 is turned on. ..

In this embodiment, the LUTs are layered and the size of the LUTs read out on the DRAM at one time is reduced. This reduces the time required to read the LUT. In addition, the access speed is increased by improving the efficiency of the LUT search.

The ADM A is data for managing whether the data stored in the NAND flash memory M is valid or invalid. In the example of FIG. 2, the ADM A manages whether the data is valid or invalid by using 1-bit flag information for each 4KB of data stored in the NAND flash memory M. For example, since the data D stored in the NAND flash memory M corresponds to the flag information B of the ADM A and the flag information B is “1” indicating that the flag information B is valid, the data D is valid data. be.

FIG. 3 is a conceptual diagram illustrating the configuration of the hierarchical LUT 51 according to the present embodiment. In FIGS. 3 and 8, megabytes are referred to as MB.

The namespace is a memory space obtained by dividing a plurality of blocks included in the non-volatile memory 5. By allocating a namespace for each memory area in a certain range, even if the logical address overlaps in at least two memory areas, the namespace ID and the logical address are used to obtain appropriate data in the appropriate memory area. Can be accessed. By making the namespaces identifiable, LBAs can be assigned independently for each namespace, and even if LBAs are duplicated in a plurality of namespaces, they can be appropriately accessed. Therefore, in the information processing system 1, access to different namespaces is treated in the same way as access to different devices, for example.

In the present embodiment, the hierarchical LUT 51 describes, for example, a LUT in a hierarchical structure having a plurality of layers. In this embodiment, the hierarchical LUT 51 is divided into namespaces NS1 to NSn (n is a natural number of 2 or more). The depth of the hierarchy for each namespace NS1 to NSn in the hierarchical LUT 51 is determined according to the size of the namespace NS1 to NSn.

The first (top) layer L1 of the hierarchical LUT 51 covers the range of the PBA of the non-volatile memory 5 by n fragments (elements) corresponding to the namespaces NS1 to NSn according to the size of the namespaces NS1 to NSn. Group) Assign to Li1. Each of the n fragments Li1 of the first layer L1 further contains a plurality of elements C1.

The second layer L2 further divides each of the ranges of PBA divided into n pieces in the first layer L1 into m pieces of fragments Li2. The m number may be, for example, the number of a plurality of elements C1 contained in the fragment Li1 of the first layer L1. Each of the fragments Li2 of the second layer L2 further contains a plurality of elements C2. Each of the plurality of elements C1 included in the fragment Li1 of the first layer L1 is associated with the fragment Li2 of the second layer L2, and includes, for example, a pointer indicating the corresponding lower fragment Li2.

The third layer L3 further divides each of the ranges of PBA divided into m pieces in the second layer L2 into l fragments Li3. The number of l may be, for example, the number of a plurality of elements C2 contained in the fragment Li2 of the second layer L2. Each of the fragments Li3 of the third layer L3 further contains a plurality of elements C3. Each of the plurality of elements C2 included in the fragment Li2 of the second layer L2 is associated with the fragment Li3 of the third layer L3, and includes, for example, a pointer indicating the corresponding lower fragment Li3.

The fourth layer L4 further divides each of the range of PBA divided into l by the third layer L3 into k fragments Li4. The k number may be, for example, the number of a plurality of elements C3 contained in the fragment Li3 of the third layer L3. Each of the fragments Li4 of the fourth layer L4 further contains a plurality of elements C4. Each of the plurality of elements C3 included in the fragment Li3 of the third layer L3 is associated with the fragment Li4 of the fourth layer L4, and includes, for example, a pointer indicating the corresponding lower fragment Li4.

The hierarchical LUT 51 identifies the PBA corresponding to the LBA by the PBA divided in the lowermost fourth layer L4.

Thus, the element C1 in the first layer L1 shows the fragment Li2 in the second layer L2, the element C2 in the second layer L2 shows the fragment Li3 in the third layer L3, and the third layer L3. The element C3 represents the fragment Li4 in the fourth layer L4 to form a hierarchical LUT 51.

The number of elements contained in one fragment belonging to the first to fourth layers L1 to L4 may be the same, and may be, for example, 32.

FIG. 3 illustrates the case where the number of layers is four. However, the number of layers may be 2 or more.

The size of the PBA used in the hierarchical LUT 51 may be 32 bits as in the example of FIG. 2 above. Further, the size of the PBA used in the hierarchical LUT 51 may be equal to, for example, the width of the address bus of the memory device 3.

For example, each fragment Li1 to Li4 has a PBA (first physical address) corresponding to the corresponding lower layer fragment, a PBA of the corresponding access target data, a corresponding namespace ID (namespace name), and a corresponding logic. Includes address and range of PBA to manage (Grain).

For example, if the range of PBA managed by the elements C1 to C4 of each fragment Li1 to Li4 matches the page unit (for example, 4KB) handled in the NAND flash memory, each element C1 to C4 is to be accessed. The PBA of the data is stored. For example, when a lower layer exists, each element C1 to C4 stores a PBA (for example, the first physical address) corresponding to the fragment of the lower layer. The PBA corresponding to the fragment of the lower layer may be represented by an address in another format.

In the hierarchical LUT 51, the fragment of the upper layer contains a plurality of elements. The range of PBA managed by each element contained in the fragment of the upper layer corresponds to the range of PBA managed by the fragment of the lower layer, and the fragment of this lower layer contains more than one element. .. For example, each element contained in the fragment of the upper layer stores the PBA corresponding to the fragment of the lower layer. As a result, the upper layer and the lower layer are associated with each other.

Similarly, in the lower layer, for example, each element included in each fragment of the lower layer stores the PBA corresponding to the fragment of the lower layer.

When the range of PBA managed by one element is 4KB, the PBA corresponding to the data written in the non-volatile memory 5 is stored in the element.

It should be noted that each of the fragments Li1 to Li4 included in the hierarchical LUT 51 indicates the head of the data of the plurality of reference destinations when the data of the plurality of reference destinations are continuously arranged in the non-volatile memory 5. Other pointers that include the start pointer and are not the start of the data of the plurality of references may be omitted. As a result, the size of the hierarchical LUT 51 can be reduced, and the amount of the cache memory 451 used can be reduced. For example, when a plurality of PBAs referenced by a plurality of elements included in the first fragment belonging to the first layer are continuous, the first element contained in the first fragment is among the plurality of PBAs. Includes leading PBA. Other elements included in the first fragment and the second fragment belonging to the second layer below the first fragment can be omitted. As a result, the amount of data required for the first layer and the second layer in the hierarchical LUT 51 can be reduced. The write control unit 441 or the read control unit 442 may be included in the first fragment belonging to the first layer, for example, when the second fragment belonging to the second layer is omitted. It is determined that the element refers to a plurality of consecutive PBAs. As a result, the write control unit 441 or the read control unit 442 can improve the access speed to the continuous data stored in the non-volatile memory 5 by using, for example, burst transfer.

The example of FIG. 3 will be described in more detail. The first layer L1 is divided into n fragments Li1 corresponding to each of the n namespaces NS1 to NSn. One fragment Li1 corresponds to 4 GB of PBA. One fragment Li1 further contains 32 elements C1. One element C1 corresponds to 128MB of PBA. That is, the range of PBA corresponding to the element C1 of the fragment Li1 is 128MB. The range of PBA managed by the element C1 is larger than the minimum unit of data handled in the NAND flash memory, for example, page unit (for example, 4KB). Therefore, the fragment Li2 of the second layer L2 is generated for each element C1, and the address indicating the head of the corresponding fragment Li2 of the second layer L2 is stored in each element C1.

The second layer L2 is divided into the fragment Li2 corresponding to the element C1 of the first layer L1. One fragment Li2 corresponds to 128 MB of PBA. One fragment Li2 further contains 32 elements C2. One element C2 corresponds to 4MB of PBA. That is, the range of PBA corresponding to the element C2 of the fragment Li2 is 4MB. The range of PBA managed by the element C2 is larger than the page unit 4KB handled in the NAND flash memory. Therefore, the fragment Li3 of the third layer L3 is generated for each element C2, and the address indicating the head of the corresponding fragment Li3 of the third layer L3 is stored in each element C2.

The third layer L3 is divided into fragments Li3 corresponding to the element C2 of the second layer L2. One fragment Li3 corresponds to 4MB of PBA. One fragment Li3 further contains 32 elements C3. One element C3 corresponds to 128KB of PBA. That is, the range of PBA corresponding to the element C3 of the fragment Li3 is 128KB. The range of PBA managed by the element C3 is larger than the page unit 4KB handled in the NAND flash memory. Therefore, the fragment Li4 of the fourth layer L4 is generated for each element C3, and the address indicating the head of the corresponding fragment Li4 of the fourth layer L4 is stored in each element C3.

The fourth layer L4 is divided into fragments Li4 corresponding to the element C3 of the third layer L3. One fragment Li4 corresponds to 128KB of PBA. One fragment Li4 further contains 32 elements C4. One element C4 corresponds to 4KB of PBA. That is, the range of PBA corresponding to the element C4 of the fragment Li4 is 4KB. The range of PBA managed by the element C4 is equivalent to the page unit 4KB handled in the NAND flash memory. Therefore, each element C4 stores a PBA indicating data.

For example, when a plurality of PBAs stored in one fragment Li4 are continuous, the fragment Li4 may be omitted. The element C3 that is the reference source of the fragment Li4 includes the PBA at the beginning of the data for 128 KB, which is the range of the PBA corresponding to the element C3. That is, when data of the same size as the range of PBA corresponding to a plurality of elements contained in a certain fragment is associated with a continuous PBA, the lower fragment of this certain fragment can be omitted and is included in the certain fragment. The element to be included contains the PBA at the beginning of this certain data.

It should be noted that the size of the corresponding PBA range (corresponding memory area size) is different for each namespace NS1 to NSn, and for example, the number of PBAs for each namespace NS1 to NSn managed by the hierarchical LUT 51 is different. May be good. In this case, the number of layers may be different for each of the namespaces NS1 to NSn, for example, depending on the size of the namespaces NS1 to NSn. For example, in the namespace NS1, the PBA corresponding to 128 GB may be managed by the number of layers 5, and in the namespace NS2, the PBA corresponding to 64 GB may be managed by the number of layers 6.

In the present embodiment, it is desirable that the number of elements contained in the fragment is the same in one namespace, but the number of elements contained in the fragment may be different for each layer.

FIG. 4 is a data structure diagram illustrating the data format of the fragment of the hierarchical LUT 51 according to the present embodiment. Specifically, FIG. 4 illustrates one fragment of the hierarchical LUT 51, as shown in FIG. 3, where one fragment of the upper layer corresponds to 32 fragments of the lower layer.

The cache memory 451 stores a part of the hierarchical LUT 51 in units of cache lines. In the following, the fragment of the hierarchical LUT 51 will be referred to as a LUT fragment. The cache line corresponding to the LUT fragment is referred to as a LUT cache line.

The data updated in the cache memory 451 is written back to the non-volatile memory 5 in units of cache lines.

The LUT fragment and the LUT cache line correspond to any of the LUT fragments Li1 to Li4 in each layer L1 to L4. The LUT fragment and the LUT cache line include, for example, PBA storage units C_1 to C_32, LBA storage units C_33, and management data storage units C_34.

The PBA storage units C_1 to C_32 correspond to elements. The PBA storage units C_1 to C_32 store the PBA corresponding to the LUT fragment of the lower layer or the PBA indicating the storage position of the data. As described in FIG. 2 above, one PBA is represented by, for example, 32 bits. For example, 8-bit management data MD1 may be attached to each PBA. In each management data MD1, for example, whether the PBA stored in each of the PBA storage units C_1 to C_32 is a PBA corresponding to the LUT fragment of the lower layer (in this case, in the PBA on the non-volatile memory 5). It may be managed whether it is a PBA on the cache memory 451) or a PBA indicating a storage position of data. The size of each of the PBA storage units C_1 to C_32 may be 40 bits, which is the sum of the size of the PBA and the size of the management data MD1, and the total size of the PBA storage units C_1 to C_32 may be 160 bytes.

The LBA storage unit C_33 stores the LBA corresponding to the PBA storage unit C_1 (that is, the first PBA managed by the LUT fragment).

The management data storage unit C_34 stores the namespace ID to which the LUT fragment belongs and the range of the PBA managed by the LUT fragment.

The management data storage unit C_34 may store other information. For example, the management data storage unit C_34 may store the ID of the layer to which the LUT fragment belongs.

When each LUT fragment is stored, for example, on the cache memory 451 of the memory 45A, each LUT cache line may further include, in addition to the LUT fragment, a pointer indicating a LUT cache line to be associated with each other in the cache memory 451. More specifically, the LUT cache line has a front pointer storage unit C_N-1 indicating a cache line referenced before the LUT cache line and a next pointer indicating a cache line referenced next to the LUT cache line. It may include the storage unit C_N. In this way, by including the pointers to the cache lines before and after the LUT cache line stored in the cache memory 451 to be referred to, the access to the cache memory 451 can be speeded up, and continuous access can be performed. It can be realized. The LUT cache line may include other management data.

For example, when a certain cache line is included in the free list FL described later, the next address storage unit C_N of this cache line may include a pointer indicating another cache line included in the same free list FL. When a certain cache line is included in the dirty list DL described later, the next address storage unit C_N of this cache line may include a pointer indicating another cache line included in the same dirty list DL. When a cache line is included in the clean list CL described later, the next address storage unit C_N of this cache line may include a pointer indicating another cache line included in the same clean list CL.

In the present embodiment, the address of the cache line to be referred to next will be described as being represented by PBA, but may be represented by an address of another form. Further, in the present embodiment, the front pointer storage unit C_N-1 and the next pointer storage unit C_N will be described as storing the PBA, but addresses of other formats may be stored.

It is desirable that the LUT fragment and the LUT cache line are all configured according to the format shown in FIG. In this case, the size of each LUT fragment can be fixed length (eg, 168 bytes). The size of each LUT cache line can be fixed length (eg, 188 bytes). However, each LUT fragment and each LUT cache line may be configured according to a different format for each layer.

FIG. 5 is a data structure diagram illustrating the data format of the fragment of ADM52 according to the present embodiment.

The cache memory 451 stores a part of the ADM 52 in units of cache lines. In the following, the fragment of ADM52 will be referred to as an ADM fragment. The cache line corresponding to the ADM fragment is referred to as an ADM cache line.

The ADM fragment and the ADM cache line include, for example, map storage units D_1 to D_40 and PBA storage units D_42.

The map storage units D_1 to D_40 store bits for managing the validity or invalidity of each data for each of the 4KB data stored in the non-volatile memory 5. For example, assuming that the total size of the map storage units D_1 to D_40 is 160 bytes (= 1280 bits), valid or invalid data for 1280 4KB data stored in the non-volatile memory 5 in one ADM fragment and ADM cache line. Can be managed.

The PBA storage unit D_42 stores the PBA of the map storage unit D_1 (that is, the first PBA managed by this ADM fragment).

The ADM cache line may further include a pointer indicating a cache line to be associated with each other in the cache memory 451 as in the above-mentioned LUT cache line. More specifically, the ADM cache line includes a front pointer storage unit D_N-1 indicating a cache line referenced before the ADM cache line and a next pointer indicating a cache line referenced next to the ADM cache line. It includes a storage unit D_N. The ADM cache line may include other management data.

Further, it is desirable that the ADM fragment and the ADM cache line are all configured according to the format shown in FIG. 5 and have a fixed length of the same size as the LUT fragment and the LUT cache line. That is, it is preferable that the size of the ADM fragment is 168 bytes, which is the same as the LUT fragment, and the size of the ADM cache line is 188 bytes, which is the same as the size of the LUT cache line.

FIG. 6 is a data structure diagram illustrating a data format used at the time of writing back from the cache memory 451 to the non-volatile memory 5 according to the present embodiment.

As described above, when the LUT cache line or the ADM cache line is updated in the cache memory 451 the LUT fragment contained in the updated LUT cache line or the ADM fragment contained in the updated ADM cache line becomes a non-volatile memory. Written back to 5.

In the present embodiment, since the sizes of the LUT fragment and the ADM fragment are all the same, the write control unit 441 can efficiently write the LUT fragment and the ADM fragment back to the non-volatile memory 5.

Specifically, for example, as shown in FIGS. 4 and 5, the size of the LUT fragment written back onto the non-volatile memory 5 is 168 bytes, regardless of the layer. Also, the size of the ADM fragment is 168 bytes, which is the same as the size of the LUT fragment. Here, for example, assuming that the data unit for writing back from the cache memory 451 to the non-volatile memory 5 (hereinafter referred to as the write-back unit) is 512 bytes as shown in FIG. 6, one write-back unit is the cache memory. Any three fragments FG_1 to FG_3 selected from the LUT fragment and the ADM fragment stored in 451 can be included. The remainder size excluding the fragments FG_1 to FG_3 from the write-back unit is 8 bytes. 8 bytes is a sufficiently small value for the write-back unit (512 bytes). Further, for example, the page size of the NAND flash memory is generally an integral multiple of 512 bytes, so that the size is sufficiently smaller than the page size. Therefore, by using the data format of FIG. 6, it is possible to suppress waste of the capacity of the page written to the non-volatile memory 5 at the time of writing back, and to efficiently write back the cache line.

In addition, one write-back unit may include the management data MD2 using the remainder size (8 bytes) of the write-back unit. For example, the management data MD2 may represent the types of three fragments stored in one write-back unit.

Further, the write-back unit is not limited to 512 bytes. The write-back unit may be, for example, 1 KB or 2 KB. However, the write-back unit is preferably a multiple of 512 bytes.

Further, when transmitting and receiving a fragment that is either a LUT fragment or an ADM fragment between the non-volatile memory controller 46 and the non-volatile memory 5, a fragment including ECC (Error-Correcting Code) is transmitted and received. You may. In this case, for example, by adjusting the number of fragments included in one write-back unit and the size of the fragments, ECC can be attached to a plurality of fragments without waste, and the transmission / reception of fragments is efficient. Can be done.

FIG. 7 is a flowchart illustrating the PBA search process according to the present embodiment.

Specifically, the PBA search process is a process in which the address conversion unit 445 of the processor 44 converts the designated LBA into the PBA by using the hierarchical LUT 51.

The hierarchical LUT 51 is generated in advance by the initialization unit 444 of the processor 44, the address translation unit 445 in the write process, and the like, and is stored in the non-volatile memory 5.

In step S701, the cache memory control unit 447 reads the LUT fragment Li1 of the first layer L1 of the hierarchical LUT 51 stored in the non-volatile memory 5 via the non-volatile memory controller 46, and stores the LUT fragment Li1 in the memory. It is stored in the cache memory 451 in 45A. The reading of the LUT fragment Li1 may be performed, for example, at the time of starting the memory device 3. Further, the reading of the LUT fragment Li1 may be performed based on the namespace ID specified by the information processing apparatus 2.

In step S702, the address translation unit 445 searches for the PBA storage unit corresponding to the designated LBA for the read LUT fragment Li1, and reads out the PBA stored in the corresponding PBA storage unit.

In step S703, the address translation unit 445 determines whether or not the PBA read in step S702 is a PBA indicating a LUT fragment of a lower layer.

If the read PBA is not a PBA indicating a LUT fragment of a lower layer, the address translation unit 445 assumes that the read PBA is an address corresponding to the designated LBA in step S705, and ends the search process.

When the read PBA is a PBA indicating a LUT fragment of a lower layer, the cache memory control unit 447 reads the LUT fragment of the lower layer corresponding to the read PBA in step S704. The cache memory control unit 447 stores a pointer indicating the LUT cache line corresponding to the LUT fragment of the lower layer stored in the cache memory 451 in the next pointer storage unit C_N of any cache line belonging to the clean list CL. This indicates that the LUT cache line corresponding to the LUT fragment of the lower layer belongs to the clean list CL. The cache memory control unit 447 stores a pointer indicating a cache line belonging to the clean list CL in the front pointer storage unit C_N-1 of the LUT cache line corresponding to the LUT fragment of the lower layer. After that, the process returns to step S702.

In step S704, when the reference destination of the fragment of the lower layer read in step S703 points to the PBA in the non-volatile memory 5, the cache memory control unit 447 is referred to by the hierarchical LUT 51 of the non-volatile memory 5. The lower fragment is read, and the read lower fragment is stored in the cache memory 451 in the memory 45A. When the reference destination of the fragment of the lower layer read in step S703 points to the PBA in the cache memory 451 from the hierarchical LUT 51 of the non-volatile memory 5 by the cache memory control unit 447 to the cache memory 451 in the memory 45A. No read processing is required.

FIG. 8 is a block diagram illustrating the relationship between cache lines in the PBA search process according to the present embodiment. The configuration of the hierarchical LUT 51 of FIG. 8 is the same as the configuration of the hierarchical LUT 51 shown in FIG.

FIG. 8 illustrates a state in which the LUT cache lines CLi1, CLi2 (1), CLi3 (2), and CLi4 (20) are read from the first layer L1 to the fourth layer L4.

In the first layer L1, the LUT cache line CLi1 corresponding to the LUT fragment Li1 includes PBA storage units C1_1 to C1_32. Each of the PBA storage units C1-1 to C1_32 corresponds to a range of 128 MB of PBA. The PBA storage units C1-1 to C1_32 each store the PBA corresponding to the 32 LUT fragments Li2 of the second layer L2. In FIG. 8, the PBA storage units C1-1 to C1_32 include PBAs corresponding to the LUT cache lines CLi2 (1) to CLi2 (32) in the second layer L2, respectively.

In the second layer L2, the LUT cache line CLi2 (1) corresponding to the LUT fragment Li2 includes PBA storage units C2 (1) _1 to C2 (1) _32. Each of the PBA storage units C2 (1) _1 to C2 (1) _32 corresponds to a PBA range of 4 MB. The PBA storage units C2 (1) _1 to C2 (1) _32 each store the PBA corresponding to the 32 LUT fragments Li3 of the third layer L3. In FIG. 8, the PBA storage units C2 (1) _1 to C2 (1) _32 each include a PBA corresponding to the LUT cache lines CLi3 (1) to CLi3 (32) in the third layer L3.

In the third layer L3, the LUT cache line CLi3 (2) corresponding to the LUT fragment Li3 includes PBA storage units C3 (2) _1 to C3 (2) _32. Each of the PBA storage units C3 (2) _1 to C3 (2) _32 corresponds to a PBA range of 128 KB. The PBA storage units C3 (2) _1 to C3 (2) _32 each store the PBA corresponding to the 32 LUT fragments Li4 of the fourth layer L4. In FIG. 8, the PBA storage units C3 (2) _1 to C3 (2) _32 include PBAs corresponding to the LUT cache lines CLi4 (1) to CLi4 (32) in the fourth layer L4, respectively.

In the fourth layer L4, the LUT cache line CLi4 (20) corresponding to the LUT fragment Li4 includes PBA storage units C4 (20) _1 to C4 (20) _32. Each of the PBA storage units C4 (20) _1 to C4 (20) _32 corresponds to the range of PBA of 4KB. Each of the PBA storage units C4 (20) _1 to C4 (20) _32 stores the PBA corresponding to the data.

First, the cache memory control unit 447 reads the LUT fragment Li1 of the first layer L1 from the non-volatile memory 5 based on, for example, the namespace ID, the LBA Y, the start address, and the offset value, and corresponds to the LUT fragment Li1. The LUT cache line CLi1 is stored in the cache memory 451.

The address translation unit 445 reads, for example, the PBA stored in the corresponding PBA storage unit C1-1 from the LUT cache line CLi1 corresponding to the LUT fragment Li1 based on the LBA Y, the start address, and the offset value.

Since the value stored in the PBA storage unit C1-1 is the PBA indicating the LUT fragment Li2 of the second layer L2, the cache memory control unit 447 reads the LUT fragment Li2 from the non-volatile memory 5 and corresponds to the LUT fragment Li2. The LUT cache line CLi2 (1) to be cached is stored in the cache memory 451.

The address translation unit 445 searches for the PBA storage unit C2 (1) _2 to which the range of the LBA including the LBA Y is assigned, and reads out the PBA stored in the PBA storage unit C2 (1) _2.

Since the value stored in the PBA storage unit C2 (1) _2 is the PBA indicating the LUT fragment Li3 of the third layer L3, the cache memory control unit 447 reads the LUT fragment Li3 from the non-volatile memory 5 and LUTs. The LUT cache line CLi3 (2) corresponding to the fragment Li3 is stored in the cache memory 451.

The address translation unit 445 searches the PBA storage unit C3 (2) _20 to which the range of the LBA including the LBA Y is assigned from the LUT cache line CLi3 (2), and stores the PBA storage unit C3 (2) _20. Read the PBA.

Since the value stored in the PBA storage unit C3 (2) _20 is the PBA indicating the LUT fragment Li4 of the fourth layer L4, the cache memory control unit 447 reads the LUT fragment Li4 from the non-volatile memory 5 and LUTs. The LUT cache line CLi4 (20) corresponding to the fragment Li4 is stored in the cache memory 451.

The address translation unit 445 searches the PBA storage unit C4 (20) _31 to which the range of the LBA including the LBA Y is assigned from the LUT cache line CLi4 (20), and stores the PBA storage unit C4 (20) _31. Read PBA X. The PBA X stored in the PBA storage unit C4 (20) _31 indicates data, not a LUT cache line. Therefore, the address translation unit 445 can specify the PBA X corresponding to the LBA Y.

FIG. 9 is a data structure diagram illustrating the list structure of the cache memory 451 according to the present embodiment.

In the present embodiment, the cache line may be a LUT cache line or an ADM cache line.

When the cache memory control unit 447 stores the LUT fragment of the hierarchical LUT 51 on the cache memory 451 as a LUT cache line, or when the ADM fragment of the ADM 52 is stored on the cache memory 451 as an ADM cache line, FIG. 4 above. And as described with reference to FIG. 5, the cache lines stored in the cache memory 451 are concatenated to generate a list structure.

In the present embodiment, the cache memory 451 includes a free list FL, a dirty list DL, and a clean list CL. It is desirable that the LUT cache line and the ADM cache line are managed by different lists. In this case, it is desirable that the list that manages the LUT cache line and the list that manages the ADM cache line have the same format.

In FIG. 9, the next pointer storage unit C_N of the cache line belonging to the free list FL, the dirty list DL, and the clean list CL stores the address of the cache line belonging to the same list and concatenated next. If there is no cache line to be concatenated next, the next pointer storage unit C_N may be omitted. The front pointer storage unit C_N-1 of the cache line is. Stores the addresses of previously concatenated cache lines that belong to the same list. If there is no cache line to be concatenated before, the front pointer storage unit C_N may be omitted.

The free list FL includes, for example, rewrite candidate cache lines FL1 to FL3 that do not belong to the clean list CL or the dirty list DL. The cache line immediately after being stored in the cache memory 451 from the hierarchical LUT 51 or the ADM 52 belongs to the free list FL. The order of the cache lines FL1 to FL3 belonging to the free list FL may be random. The next pointer storage unit C_N of the cache line FL1 and the front pointer storage unit C_N-1 of the cache line FL3 store the PBA of the cache line FL2. The next pointer storage unit C_N of the cache line FL2 stores the PBA of the cache line FL3. The front pointer storage unit C_N-1 of the cache line FL2 stores the PBA of the cache line FL1.

The dirty list DL includes, for example, cache lines DL1 and DL2 in which the cache line is rewritten in the cache memory 451 but the content of the rewritten cache line is not reflected in the hierarchical LUT 51 of the non-volatile memory 5. The order of the cache lines DL1 and DL2 belonging to the dirty list DL may be random. The next pointer storage unit C_N of the cache line DL1 stores the PBA of the cache line DL2. The front pointer C_N-1 of the cache line DL2 stores the PBA of the cache line DL1.

For example, when the communication interface control unit 41 receives a write command from the information processing device 2 or the like, the cache memory control unit 447 switches the LUT cache line corresponding to the write destination LBA from the free list FL to the dirty list DL.

The contents of the cache lines DL1 and DL2 belonging to the dirty list DL need to be reflected (written) in the hierarchical LUT 51 or ADM 52 of the non-volatile memory 5. Since the cache memory control unit 447 does not need to manage the cache lines DL1 and DL2 by the dirty list DL after the cache lines DL1 and DL2 in the dirty list DL are written to the non-volatile memory 5, the cache memory control unit 447 does not need to manage the cache lines DL1 and DL2 by the dirty list DL. Connect DL2 from dirty list DL to clean list CL. Therefore, it is desirable that the cache lines DL1 and DL2 belonging to the dirty list DL are written to the non-volatile memory 5 by a first-in first-out (Fast In Fast Out: FIFO) method and converted into a cache line belonging to the clean list CL.

For example, the dirty list DL is used to speed up the writing process to the non-volatile memory 5.

The clean list CL includes cache lines CL1 to CL4 having the same contents in the hierarchical LUT 51 or ADM 52 of the cache memory 451 and the non-volatile memory 5. The cache lines CL1 to CL4 are, for example, cache lines rewritten in the cache memory 451 and reflected in the hierarchical LUT 51 of the non-volatile memory 5. The order of the cache lines CL1 to CL4 belonging to the clean list CL may be random. The next pointer storage unit C_N of the cache line CL1 and the front pointer storage unit C_N-1 of the cache line CL3 store the PBA of the cache line CL2. The next pointer storage unit C_N of the cache line CL2 and the front pointer storage unit C_N-1 of the cache line CL4 store the PBA of the cache line CL3. The front pointer storage unit C_N-1 of the cache line CL2 stores the PBA of the cache line CL1. The next pointer storage unit C_N of the cache line CL3 stores the PBA of the cache line CL4.

For example, when the communication interface control unit 41 receives a read command from the information processing device 2 or the like, the cache memory control unit 447 switches the cache line corresponding to the read destination LBA from the free list FL to the clean list CL.

Since the cache lines CL1 to CL4 belonging to the clean list CL have the same contents as a part of the hierarchical LUT 51 of the non-volatile memory 5, even if the cache lines CL1 to CL4 belonging to the clean list CL are lost, even if the cache lines CL1 to CL4 belonging to the clean list CL are lost. No inconsistency occurs between the cache lines CL1 to CL4 of the cache memory 451 and the data of the hierarchical LUT 51 or ADM 52 stored in the non-volatile memory 5. Therefore, for example, the cache memory control unit 447 may move the cache line of the clean list CL to the free list FL when the total size of the free list FL decreases to a certain threshold value or less. The clean list CL may be managed by a first-in first-out method. The increase or decrease of clean list CL may not be controlled. That is, the number of lists may be increased or decreased randomly.

Hereinafter, the details of the state change of the cache memory 451 when the memory device 3 receives the read command and the write command will be described.

FIG. 10 is a flowchart illustrating a change in the state of the cache line in the cache memory 451 according to the present embodiment.

FIG. 11 is a block diagram illustrating a change in the state of the cache line in the cache memory 451 according to the present embodiment. FIG. 11 illustrates the process shown in the flowchart of FIG.

In step S1001, the cache memory control unit 447 reads a part of the hierarchical LUT 51 from the non-volatile memory 5 and stores it in the cache memory 451 as cache lines FL1 to FLx belonging to the free list FL. For example, in step S1001, the cache line CLi1 corresponding to the fragment Li1 of the first layer L1 at the highest level of the hierarchical LUT 51 is stored in the cache memory 451 as in step S701 of FIG.

In step S1002, the cache memory control unit 447 determines whether or not an access command to the non-volatile memory 5 has been received from the information processing device 2 via the communication interface control unit 41. When the write command is received, the process proceeds to step S1003, when the read command is received, the process proceeds to step S1007, and when the access command is not received, the process proceeds to step S1008.

In step S1003, the address translation unit 445 searches the cache lines FL1 to FLx of the free list FL for the PBA corresponding to the write destination LBA. Here, the search process for the hierarchical LUT 51 or the cache memory 451 is the same as the search process described with reference to FIGS. 7 and 8.

The cache memory control unit 447 reads a LUT fragment not stored in the cache memory 451 among the hierarchical LUT 51 searched by the address conversion unit 445, and reads the read LUT fragment to any of the cache lines FL1 to FLx belonging to the free list FL. It is stored in the cache memory 451 as a result. Further, the cache memory control unit 447 reads an ADM fragment containing the ADM corresponding to the PBA to be written in the ADM 52, and sets the read ADM fragment as one of the cache lines FL1 to FLx belonging to the free list FL to the cache memory 451. Store. Further, when the LUT cache line among the cache lines FL1 to FLx of the free list FL is rewritten by the address conversion unit 445, the cache memory control unit 447 uses the rewritten LUT cache line as a dirty corresponding to the hierarchical LUT 51. Move to the list LDL. Similarly, when the ADM cache line among the cache lines FL1 to FLx of the free list FL is rewritten by the data map management unit 446, the cache memory control unit 447 uses the rewritten ADM cache line as the dirty corresponding to the ADM 52. Move to the list ADL.

In step S1004, the cache memory control unit 447 satisfies certain conditions for reflecting the cache lines DL1 to DLy-1 and DLy to DLx of the dirtylists LDL and ADL to the hierarchical LUT 51 and ADL 52 of the non-volatile memory 5. Judge whether or not. The condition may be satisfied, for example, when the sizes of dirtylists LDL and ADL exceed a certain threshold value. If the condition is not satisfied, the process returns to step S1002. When the condition is satisfied, in step S1005, the cache memory control unit 447 reflects the cache lines DL1 to DLy-1, DLy to DLx of the dirtylists LDL and ADL to the hierarchical LUT 51 and ADM 52 of the non-volatile memory 5. Let (write).

The determination in step S1004 may be periodically performed by the cache memory control unit 447 even when there is no write command in step S1002.

In step S1006, the cache memory control unit 447 moves the cache line of the dirty list LDL that has been reflected in the hierarchical LUT 51 to the clean list LCL corresponding to the hierarchical LUT 51. The cache memory control unit 447 moves the cache line of the dirty list ADL that has been reflected in the ADM 52 to the clean list ACL corresponding to the ADM 52. After that, the process returns to step S1002.

In step S1007, the address translation unit 445 searches the cache lines FL1 to FLx of the free list FL for the PBA corresponding to the read destination LBA. The cache memory control unit 447 stores the LUT fragment not stored in the cache memory 451 among the hierarchical LUTs 51 searched in this search process as one of the cache lines FL1 to FLx belonging to the free list FL in the cache memory 451. Then move to the clean list LCL. Further, the cache memory control unit 447 reads an ADM fragment containing an ADM corresponding to the PBA to be read from the ADM 52, and stores the read ADM fragment in the cache memory 451 as one of the cache lines FL1 to FLx belonging to the free list FL. Then move to the clean list ACL. After that, the process returns to step S1002.

In step S1008, the cache memory control unit 447 checks the size of the free list FL. If the free list is not insufficient, the process returns to step S1002. When the free list FL is insufficient, in step S1009, the cache memory control unit 447 moves the cache lines of the clean list LCL and ACL to the free list FL. After that, the process returns to step S1002.

In the above description of FIG. 10, an example in which the cache line moves from the free list FL to the dirty list LDL and ADL has been described, but the cache line rewritten in the clean list LCL and ACL also moves to the dirty list LDL and ADL. It may be possible. Further, in the above example, the LUT fragment or the ADM fragment read from the hierarchical LUT 51 or the ADM 52 of the non-volatile memory 51 is stored in the cache memory 451 as belonging to the free list FL, but instead of this, it is clean. It may be stored in the cache memory 451 as belonging to the list LCL and ACL.

The cache lines DL1 to DLy-1 and DLy to DLx of the dirtylists LDL and ADL are reflected in the hierarchical LUT 51 or ADM 52 in the non-volatile memory 5 at a specific timing regardless of the determination in step S1004 described above. May be good. For example, the memory device 3 supplies power for the time required to write the cache lines DL1 to DLy-1, DLy to DLx of the dirtylists LDL and ADL to the hierarchical LUT 51 or ADM 52 when the power supply of the memory device 3 is lost. A separate power supply may be secured. In this case, power is supplied from the other power source to the memory device 3 at the timing when the power supply of the memory device 3 is lost, and the cache lines DL1 to DLy-1 and DLy to DLx of the dirtylists LDL and ADL are the non-volatile memory 5. It is written to the hierarchical LUT 51 or ADM 52. In this case, by reducing the sizes of the dirtylists LDL and ADL, the capacity of the separate power supply to be secured can be reduced, and the cost required for the memory device 3 can be suppressed. Further, by reducing the size of the dirtylists LDL and ADL, the time for reflecting the cache lines DL1 to DLy-1 and DLy to DLx of the dirtylists LDL and ADL to the hierarchical LUT51 or ADM52 when the power is supplied from another power source is increased. It can be shortened and safety can be improved.

Since the sizes of dirtylists LDL and ADL can be adjusted by threshold values, etc., the frequency of reflecting the cache lines DL1 to DLy-1 and DLy to DLx of dirtylists LDL and ADL to the hierarchical LUT51 and ADM52 should be adjusted. Can be done. Thereby, the access frequency to the non-volatile memory 5, the processing speed of the memory device 3, and the life of the non-volatile memory 5 can be adjusted. Since the memory device 3 manages the sizes of the dirtylists LDL and ADL and can change the sizes of the dirtylists LDL and ADL by commands from the information processing device 2 and the like, the cost, safety, and performance of the memory device 3 can be determined. You can keep the balance of life.

FIG. 12 is a block diagram illustrating the relationship between the LUT fragment according to the present embodiment and the page of the non-volatile memory 5. Hereinafter, the LUT fragment and the LUT cache line will be described, but the same applies to the ADM fragment and the ADM cache line. FIG. 12 illustrates the case where all the fragments contained in the page are LUT fragments. However, the fragment contained in the page may be an ADM fragment. The page may be a mixture of LUT fragments and ADM fragments.

In this embodiment, when the hierarchical LUT 51 is generated, the LUT fragments include the same number of elements in all layers as described above. In this case, the size of each LUT fragment is the same, and the size of each LUT cache line is the same. By making the size of the LUT fragment the same and the size of the LUT cache line the same, the hierarchical LUT 51 can be efficiently stored on the non-volatile memory 5.

Specifically, for example, when the LUT fragment and LUT cache line formats shown in FIG. 4 are used, the size of each LUT fragment of the hierarchical LUT 51 arranged on the non-volatile memory 5 depends on the layer. No, all are 168 bytes.

Here, for example, assuming that the page size of the non-volatile memory 5 is 1024 bytes as shown in FIG. 12, one page contains six LUT fragments LiA to LiF. In this case, the remainder size of the page is 16 bytes, which is sufficiently small for the capacity of one page (1024 bytes). Therefore, it is possible to efficiently manage LUT fragments while suppressing waste of page capacity.

When transmitting and receiving a LUT fragment between the non-volatile memory controller 46 and the non-volatile memory 5, a LUT fragment including ECC (Error-Correcting Code) may be transmitted and received. In this case, for example, by adjusting the number of LUT fragments contained in one page and the size of the LUT fragments, ECC can be attached to a plurality of LUT fragments without waste, and the LUT fragments can be transmitted and received. Can be done efficiently.

In the present embodiment described above, by hierarchically describing the address translation data that translates the logical address into the physical address, a part of the data in the hierarchical LUT 51 is efficiently stored in the cache memory 451. Can be managed.

In this embodiment, the plurality of fragments contained in the hierarchical LUT 51 have the same size. Therefore, it is possible to efficiently perform the process of reading the fragment from the non-volatile memory 5 and storing it in the cache memory 451 and the process of reading the fragment from the cache memory 451 and storing it in the non-volatile memory 5.

In the present embodiment, the hierarchical LUT 51 has a hierarchical structure for converting a logical address into a physical address for each namespace. Therefore, when the address translations of the same namespace are continuous, the possibility that the fragment required for the address translation is stored in the cache memory 451 can be increased, and the speed of the address translation can be improved. The amount of processing such as cash-in and cash-out can be reduced.

In the hierarchical LUT 51 according to the present embodiment, the number of layers of the namespace having a small storage capacity can be reduced, the number of layers of the namespace having a large storage capacity can be increased, and the number of layers can be increased according to the storage capacity of the namespace. It is possible to realize a data structure with less waste.

In the present embodiment, the size of each fragment included in the hierarchical LUT 51 is set to be substantially the same as the unit size of the cache line included in the cache memory 451 so that the cache-in and cache-out are performed, for example, in fragment units or an integral multiple of the fragment. And can efficiently manage the cache memory 451.

In the present embodiment, since the cache line stored in the cache memory 451 belongs to any of the dirty list DL, the clean list CL, and the free list FL, the state of the fragment corresponding to the cache line can be easily grasped. be able to.

In the present embodiment, by generating the hierarchical LUT 51 by the initialization unit 444 and the address translation unit 445, the size of the LUT that is read out to the cache memory 451 of the memory 45A at one time can be reduced. As a result, the time required for reading the LUT can be shortened. Further, since only the cache line of the first layer L1 is read when the memory device 3 is started, the start of the memory device 3 can be speeded up. Therefore, the convenience of the memory device 3 can be enhanced.

In the present embodiment, the memory device 3 may manage the size of the dirty list DL included in the cache memory 451 and change the size of the dirty list DL by a command from the information processing device 2 or the like. As a result, it is possible to control the frequency of occurrence of the process of writing back the cache line from the cache memory 451 to the hierarchical LUT 51, and it is possible to maintain a balance between cost, safety, performance, and life of the memory device 3.

In the present embodiment, the hierarchical LUT 51 is efficiently stored on the non-volatile memory 5 by, for example, keeping the number of elements included in the fragment constant among the layers in one namespace of the hierarchical LUT 51. be able to. Further, the cache line can be efficiently transmitted and received between the non-volatile memory controller 46 and the non-volatile memory 5.

In the present embodiment, the sizes of the ADM fragment and the LUT fragment are the same size, and the sizes of the ADM cache line and the LUT cache line are the same size. As a result, the cache memory control unit 447 can efficiently manage the ADM cache line and the LUT cache line by the free list FL, the clean list CL, and the dirty list DL in the same format. For example, by sharing the free list of the ADM cache line and the LUT cache line, the capacity of the cache memory 451 can be efficiently used. Further, the write control unit 441 mixes the ADM fragment and the LUT fragment into one write-back unit and page to the non-volatile memory 5 without distinguishing whether the ADM fragment or the LUT fragment is used. Can be written back. This makes it possible to efficiently write back the cache line while suppressing waste of page capacity.

The embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. This embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. The present embodiment and its modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Information processing system, 2 ... Information processing device, 3 ... Memory device, 4 ... Controller, 5 ... Non-volatile memory, 41 ... Communication interface control unit, 42 ... Write buffer memory, 43 ... Read buffer memory, 44 ... Processor, 45A, 45B ... Memory, 46 ... Non-volatile memory controller, 51 ... Hierarchical LUT, 411 ... Transmission / reception control unit, 412 ... Command control unit, 441 ... Write control unit, 442 ... Read control unit, 443 ... Garbage collection control unit, 444 ... Initialization unit, 445 ... Address conversion unit, 446 ... Data map management unit, 447 ... Cache memory control unit, 451 ... Cache memory, P ... Control program.

Claims (11)

With non-volatile memory
Cache memory and
With the processor
Equipped with
The processor
From the non-volatile memory to the cache memory, each fragment of the plurality of layers of the address mapping corresponding to the target logical address of access and a part of the fragment of the data mapping corresponding to the target logical address are used as a cache line. Configured to load,
Configured to access the physical address mapped from the target logical address to the non-volatile memory with reference to the fragments of the plurality of layers of the address mapping loaded into the cache memory as the cache line. Being done
Each bit of the data mapping indicates whether or not the data stored in the physical address of the non-volatile memory is valid.
Each of the plurality of layers has a plurality of fragments, and an element that is a part of the fragment belonging to the upper layer has a hierarchical structure corresponding to the fragment belonging to the lower layer.
Each of the plurality of fragments belonging to each layer other than the lowest layer among the plurality of layers is divided into a plurality of elements corresponding to the plurality of fragments belonging to the layer immediately below, and the plurality of fragments belonging to the layer immediately below the plurality of layers. Contains multiple referenced information indicating a fragment
The plurality of fragments belonging to the lowest layer among the plurality of layers indicate the correspondence between each logical address mapped to the lowest layer and the physical address of the non-volatile memory for each logical address.
The fragment of the data mapping has the same size as each of the loaded fragments of the plurality of layers of the address mapping.
The cache line of the fragment of each of the plurality of layers of the loaded address mapping, or the cache line of the fragment of the loaded data mapping, points to a pointer indicating a cache line referenced before and after the cache line. Including ,
Memory device. The processor updates the loaded fragments of the plurality of layers of the address mapping into the non-volatile memory as it writes data about the target logical address from the target logical address to the mapped physical address. The memory device of claim 1, further configured to rewrite the stored address mapping to the updated fragment. The memory of claim 2, wherein the processor is further configured to write the updated fragments back from the cache memory to the non-volatile memory when the size of the list of updated fragments exceeds a threshold. Device. The processor is further configured to maintain the loaded fragment in the cache memory after reading data about the target logical address from the physical address mapped from the target logical address. Memory device. Each of the layers of the address mapping comprises a plurality of fragments, each of the plurality of fragments in each of the layers corresponds to a different logical address range, and the plurality of fragments in the plurality of layers having different address mappings are the same. The memory device of claim 1 having a size. When the processor writes data about the target logical address from the target logical address to the mapped physical address, the loaded fragment of the plurality of layers of the address mapping and the loaded fragment of the data mapping. The fragment is updated, and the updated fragment of the address mapping and the updated fragment of the data mapping are combined with respect to the address mapping and the data mapping stored in the non-volatile memory. The memory device according to claim 1, further configured to be rewritten. The processor manages whether the cache line stored in the cache memory belongs to a clean list, a dirty list, or a free list.
The clean list includes a cache line that is rewritten in the cache memory and the rewritten contents are reflected in the non-volatile memory.
The dirty list includes a cache line that has been rewritten in the cache memory, but the rewritten content is not reflected in the non -volatile memory.
The free list includes cache lines that do not belong to the clean list or the dirty list.
The memory device of claim 1. In a method of controlling a memory device including non-volatile memory and cache memory.
From the non-volatile memory to the cache memory, each fragment of the plurality of layers of the address mapping corresponding to the target logical address of access and a part of the fragment of the data mapping corresponding to the target logical address are used as a cache line. To load and
To access the physical address mapped from the target logical address to the non-volatile memory by referring to the fragments of the plurality of layers of the address mapping loaded into the cache memory as the cache line.
Equipped with
Each bit of the data mapping indicates whether or not the data stored in the physical address of the non-volatile memory is valid.
Each of the plurality of layers has a plurality of fragments, and an element that is a part of the fragment belonging to the upper layer has a hierarchical structure corresponding to the fragment belonging to the lower layer.
Each of the plurality of fragments belonging to each layer other than the lowest layer among the plurality of layers is divided into a plurality of elements corresponding to the plurality of fragments belonging to the layer immediately below, and the plurality of fragments belonging to the layer immediately below the plurality of layers. Contains multiple referenced information indicating a fragment
The plurality of fragments belonging to the lowest layer among the plurality of layers indicate the correspondence between each logical address mapped to the lowest layer and the physical address of the non-volatile memory for each logical address.
The fragment of the data mapping has the same size as each of the loaded fragments of the plurality of layers of the address mapping.
The cache line of the fragment of each of the plurality of layers of the loaded address mapping, or the cache line of the fragment of the loaded data mapping, points to a pointer indicating a cache line referenced before and after the cache line. Including ,
Method. It further comprises managing whether the cache line stored in the cache memory belongs to a clean list, a dirty list, or a free list.
The clean list includes a cache line that is rewritten in the cache memory and the rewritten contents are reflected in the non-volatile memory.
The dirty list includes a cache line that has been rewritten in the cache memory, but the rewritten content is not reflected in the non -volatile memory.
The free list includes cache lines that do not belong to the clean list or the dirty list.
The method of claim 8 . In the method of controlling non-volatile memory
Load each fragment of the plurality of layers of the address mapping corresponding to the target logical address of access and a part of the fragment of the data mapping corresponding to the target logical address as a cache line from the non-volatile memory to the cache memory. To do and
To access the physical address mapped from the target logical address to the non-volatile memory by referring to the fragments of the plurality of layers of the address mapping loaded into the cache memory as the cache line.
Equipped with
Each bit of the data mapping indicates whether or not the data stored in the physical address of the non-volatile memory is valid.
Each of the plurality of layers has a plurality of fragments, and an element that is a part of the fragment belonging to the upper layer has a hierarchical structure corresponding to the fragment belonging to the lower layer.
Each of the plurality of fragments belonging to each layer other than the lowest layer among the plurality of layers is divided into a plurality of elements corresponding to the plurality of fragments belonging to the layer immediately below, and the plurality of fragments belonging to the layer immediately below the plurality of layers. Contains multiple referenced information indicating a fragment
The plurality of fragments belonging to the lowest layer among the plurality of layers indicate the correspondence between each logical address mapped to the lowest layer and the physical address of the non-volatile memory for each logical address.
The fragment of the data mapping has the same size as each of the loaded fragments of the plurality of layers of the address mapping.
The cache line of the fragment of each of the plurality of layers of the loaded address mapping, or the cache line of the fragment of the loaded data mapping, points to a pointer indicating a cache line referenced before and after the cache line. Including ,
Method. It further comprises managing whether the cache line stored in the cache memory belongs to a clean list, a dirty list, or a free list.
The clean list includes a cache line that is rewritten in the cache memory and the rewritten contents are reflected in the non-volatile memory.
The dirty list includes a cache line that has been rewritten in the cache memory, but the rewritten content is not reflected in the non -volatile memory.
The free list includes cache lines that do not belong to the clean list or the dirty list.
The method of claim 10.

Images