JP7040187B2 - compiler - Google Patents

Description

The present invention relates to a compiler, a computer, and a computer code generation method.

Generally, in a vector computer (vector processing device) for the purpose of speeding up instruction processing, overtaking control of a memory access instruction is performed. The overtaking control of the memory access instruction is performed when the access area of the memory load instruction issued subsequently does not overlap with the area accessed by the memory store instruction preceding by the memory access instruction, the subsequent memory load system. It is realized by executing the memory access of the instruction first. This makes it possible to improve the memory access performance. In addition to the vector load instruction and the vector store instruction, the target memory access type instructions include a list vector instruction such as a vector scatter instruction and a vector gather instruction. The list vector instruction specifies the access destination address by the list address that indirectly refers to the addresses of a plurality of access destinations by an array or the like.

For example, in Patent Document 1, when compiling a source program including a loop control statement that repeatedly processes a list vector, the start address and end address of an array accessed by a list vector instruction are set as command words of the list vector instruction. Then, the vector computer uses the start address and the end address set in the instruction word of the list vector instruction to determine whether or not there is an overlap with the address range of the memory accessed by another memory access instruction, and overtaking control is performed. Controls the execution of. Patent Document 2 also describes the same technique as Patent Document 1.

Japanese Patent No. 3698027 Japanese Patent No. 3789320

As described above, in Patent Document 1, the start address and the end address of the array accessed by the list vector instruction are set as the instruction words of the list vector instruction. That is, the list vector instruction is supposed to access the entire range of the array to be accessed. However, the list vector instruction may access only part of the array. Therefore, in the configuration in which the start address and the end address of the array accessed by the list vector instruction are set as the instruction words of the list vector instruction, the address range of the memory accessed by the list vector instruction may be wider than the actual one. Then, when other memory access type instructions access the same array as the array accessed by the list vector instruction, the address range of the memory to be accessed even if different parts of the same array are actually accessing each other. Are determined to overlap each other. As a result, even if it is actually possible to overtake, it may be determined that overtaking is not possible.

An object of the present invention is to provide a compiler that solves the above-mentioned problem, that is, the problem that appropriate overtaking control of a memory access instruction is difficult.

The compiler according to one embodiment of the present invention is
To a computer that generates an object program for a vector computer from a source program,
The source program is analyzed, and the loop control statement that repeatedly processes the list vector is translated into a series of instruction lists including the list vector instruction.
In the process, the start address and the end address of the memory accessed by the list vector instruction are calculated every time the loop of the loop control statement is repeated, and the start address and the end address are set as the command words of the list vector instruction. do.

Further, the computer according to another embodiment of the present invention is
A computer that generates an object program for a vector computer from a source program.
A loop analysis unit that analyzes the source program and recognizes a loop control statement that repeatedly processes the list vector.
Includes a code generator that translates the loop control statement into a series of instruction lists, including list vector instructions.
The code generation unit calculates the start address and the end address of the memory accessed by the list vector instruction for each loop repetition of the loop control statement, and the start address and the end address are the command words of the list vector instruction. Set to.

Further, the computer code generation method according to another embodiment of the present invention is described.
It is a code generation method executed by a computer that generates an object program for a vector computer from a source program.
Analyzing the source program, recognizing the loop control statement that iterates over the list vector,
The loop control statement is translated into a series of instruction lists including list vector instructions.
In the translation, the start address and the end address of the memory accessed by the list vector instruction are calculated for each loop repetition of the loop control statement, and the start address and the end address are set as the command words of the list vector instruction. do.

By having the above-mentioned configuration, the present invention enables appropriate overtaking control of the memory access instruction.

It is a block diagram of the compiler which concerns on 1st Embodiment of this invention. It is a figure which shows a part of the instruction word of the list vector instruction generated by the compiler which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the source program to be translated. It is a figure which shows a part example of the object program of a translation result. It is a figure which shows the memory image of the array A. It is a block diagram of the computer which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the DO loop for demonstrating the problem which the present invention tries to solve. It is a figure which shows the example of the instruction sequence and the data arrangement of the array A when the DO loop is J = 2, 3 for explaining the problem to be solved by this invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
First, the first embodiment of the present invention will be described.

<Background of this embodiment>
In general, the gap between high-speed processor performance and low-speed memory performance has a great influence on the effective performance of a computer. For memory performance, the latency of memory load instructions is a particularly important factor.

Further, in the vector processing method for the purpose of speeding up the instruction processing, the overtaking control of the memory access instruction is performed. The overtaking control of the memory access instruction is performed when the access area of the memory load instruction issued subsequently does not overlap with the area accessed by the memory store instruction preceding by the memory access instruction, the subsequent memory load system. It is realized by executing the memory access of the instruction first. This makes it possible to improve the memory access performance. However, the vector gather instruction and the vector scatter instruction with random access by the list vector have a problem that the memory access is not regular and the address dependence analysis is difficult, and the effective overtaking control is difficult.

In Patent Document 1, the start address of the memory accessed by the vector gather instruction and the vector scatter instruction is a value assigned to the memory in an array to which a list address is specified, and the end address is set to the start address. It is the value obtained by adding the size of the array. That is, whether or not the instruction can be overtaken is determined as the range for accessing the entire array regardless of the contents of the list address. Therefore, when loads and stores to the same array are mixed in the loop, overtaking is never performed. On the other hand, in the present embodiment, the list address is set as the range of memory accessed by the vector gather instruction and the vector scatter instruction from the start address to the end address for each iteration of the loop of the specified dimension. In the instruction to access the area that does not overlap with the range accessed by the list address, the instruction can be overtaken, the number of instructions that can be overtaken increases as compared with the invention described in Patent Document 1, and the processing time of the memory access system is further increased. It is expected to improve and speed up the program.

<Characteristics of this embodiment>
The present embodiment has a function of analyzing an address area accessed by a vector gather instruction or a vector scatter instruction and determining a range overlapping with an area accessed by another memory access system instruction in the same loop. Provides a compiler. By adding a range of information that overlaps the memory access determined by this compiler to the vector gather instruction and vector scatter instruction, it is easy to control the overtaking of the vector gather instruction and vector scatter instruction in hardware. At the same time, increase the number of commands that can be overtaken. This can improve the processing time of memory access and speed up the program.

<Problems to be solved by this embodiment>
In the vector gather instruction and the vector scatter instruction, since each element of the vector register is used as the execution address to access the memory, there is no regularity in the memory access and it is difficult to analyze the address dependence. In order to solve this problem, for example, in the case of the overtaking control function proposed in Patent Document 1, the access range of the instruction is from the start address to the end address of the array accessed by the vector gather instruction or the vector scatter instruction. If there is, if this access range does not overlap with the access range of other memory access system instructions, the hardware determines that overtaking is possible and performs overtaking control. However, in this method, the address range of the memory accessed by the vector gather instruction or the vector scatter instruction becomes wider than it actually is, and even if it is actually possible to overtake, it may be determined that it cannot be overtaken. Occur.

For example, in the equation (1) of the code example shown in FIG. 7, there is no dependency between the array A and the array B, and it can be determined that the vector gather instruction of the array B may overtake the vector scatter instruction of the array A. .. However, in the technique of Patent Document 1, it is determined that overtaking cannot be performed because there is a dependency relationship of the reference definition of the sequence A between (1) and (2).

FIG. 8 shows the instruction sequence when J = 2 and J = 3 in the code of the above example, and the data sequence of the array A. When J = 2, the area accessed by the store instruction of the array A is the area 5-2 of FIG. 8, and the area accessed by the load instruction of the array A is the area 5-1 of FIG. There is no overlap and there is no dependency between the store instruction and the load instruction. Further, when J = 3, the area accessed by the store instruction is the area 5-3, the area accessed by the load instruction is the area 5-2, and the area accessed by the store instruction and the load instruction does not overlap. That is, when J is M (2 ≦ M ≦ N), the elements of the array A (I, M-1) loaded in (2) are the array A (L (I), which is the store destination of (1). Since there is no memory overlap with M), the load instruction of (2) can overtake (1). However, in Patent Document 1, since the access range is set from the start address to the end address of the array A as described above, the areas accessed by (1) and (2) are regarded as overlapping in the same array A and cannot be overtaken. Was determined to be.

<Solution by the present embodiment>
First, the hardware required by this embodiment and the requirements of the compiler will be described. In this embodiment, a vector gather instruction for loading the data pointed to by the address on the memory stored in each element of the vector register specified by the list vector into the vector register to be loaded, and the vector register specified by the list vector. The target is hardware (vector computer) having a CPU equipped with a vector scatter instruction for storing data on a vector register at a store destination address on the memory stored in each element of the instruction set. It is assumed that this hardware has an overtaking control function that enables overtaking of instructions if there is no overlap of memory access of vector load / store instructions. Further, it is assumed that the compiler has a function of statically acquiring information such as the number of dimensions, the number of elements, and the size of the array from the declaration information of the array. The above are the requirements of the hardware and the compiler required by this embodiment. These are also used in the prior art.

In this embodiment, an array accessed by a list vector, a list vector analysis unit that analyzes information about the list vector, and a start address and an end address of a memory area that performs list access obtained by the analysis are used as commands. It is determined whether or not the memory area to be accessed between the means for generating the vector gather instruction and the vector scatter instruction and the address set in the instruction term overlaps with other memory access system instructions. By providing a compiler having a list address overlap determination unit, the overtaking control of the vector instruction for list access can be made simple and effective, thereby speeding up the program.

<Structure of this embodiment>
FIG. 1 is a block diagram of a compiler 100 according to a first embodiment of the present invention. The compiler 100 translates the source program 101 to generate the instruction word 102. The instruction word 102 is also called an object code. The instruction word 102 is executed by a vector computer. In this way, the compiler 100 generates an object program for the vector computer.

The compiler 100 includes an in-loop instruction generation processing unit 110 and a list vector analysis unit 120. Further, the in-loop instruction generation processing unit 110 includes a preceding instruction generation unit 111, a vector gather / scatter instruction generation unit 112, a subsequent instruction generation unit 113, and a list address overlap determination unit 114.

When the compiler 100 recognizes the loop control statement that analyzes the source program 101 and repeatedly processes the list vector, the in-loop instruction generation processing unit 110 and the list vector analysis unit 120 are applied to the loop control statement. It is configured.

The list vector analysis unit 120 is configured to calculate the start address and the end address of the addresses that can be accessed by the list vector for each loop repetition of the loop control statement.

The in-loop instruction generation processing unit 110 is configured to translate the loop control statement into a series of instruction lists 130 including a list vector instruction (vector gather instruction or vector scatter instruction). At that time, the preceding instruction generation unit 111 generates an instruction preceding the vector gather instruction or the vector scatter instruction. Further, the vector gather / scatter instruction generation unit 112 generates a vector gather instruction or a vector scatter instruction. Further, the vector gather / scatter instruction generation unit 112 sets a register storing the start address and the end address calculated by the list vector analysis unit 120 in the command word of the generated vector gather instruction or vector scatter instruction. Further, the subsequent instruction generation unit 113 generates a subsequent instruction of the vector gather instruction or the vector scatter instruction. Further, the list address overlap determination unit 114 sets the range from the beginning to the end of the list address calculated by the list vector analysis unit 120 as the memory access range of the list vector instruction (vector gather instruction and vector scatter instruction). In the case of a vector gather instruction, it is determined whether or not there is an overlap with the memory area accessed by the preceding store instruction, and in the case of a vector scatter instruction, the subsequent load instruction. Then, the list address overlap determination unit 114 sets a predetermined value in the instruction word of the list vector instruction according to the presence or absence of overlap in the program of the address area of the memory access based on the determination result. To set.

FIG. 2 shows an example of the structure of a part of the instruction word of the list vector instruction. The instruction words in this example are the opcode OP, the overtaking bit V, the field VR that specifies the vector register that stores the address that accesses the memory, and the field that specifies the register that stores the start address calculated by the list vector analysis unit 120. It is configured to include Smin and a field Smax that specifies a register that stores the terminal address calculated by the list vector analysis unit 120. In the case of a list vector instruction in which it is certain that there is no overlap at compile time, the overtaking bit V is "1", and otherwise it is "0".

Therefore, in the hardware (vector computer) that executes the above command word, when the overtaking bit V of the command word is "1", the overtaking control is unconditionally performed. When the overtaking bit V of the instruction word is "0", the hardware (vector computer) acquires the start address and end address of the overlap range from the registers specified by the instruction words Smin and Smax, and gives an instruction. Recognize the range that prohibits overtaking. Therefore, it is possible to control the overtaking of instructions without analyzing the list address on the hardware (vector computer).

<Operation of this embodiment>
Next, the operation of this embodiment will be described by taking the source program shown in FIG. 3 as an example.

The source program shown in FIG. 3 is an example of a DO loop of Fortran source code. In the array A on the left side of Equation 3-1 the first-dimensional element is designated by the list vector L. The compiler 100 translates the source program shown in FIG. 3 into a machine language (instruction language) level.

FIG. 4 shows a part of the translation result of the source program of FIG. Equation 3-1 in FIG. 3 is translated as 4-1 to 4-5 in FIG. 4, and Equation 3-2 in FIG. 3 is translated as 4-6 to 4-7 in FIG. ..

In Patent Document 1, when the vector scatter instruction 4-5 is generated for the equation 3-1 to set the entire array A in the access range, the array A generated for the subsequent equation 3-2 is set. There is an overlap between the load instruction 4-6 and the memory access area, and it is determined that overtaking is not possible. In the present embodiment, when the vector scatter instruction 4-5 is generated for the equation 3-1 the list vector analysis unit 120 performs the following analysis processing on the array A.

First, the list vector analysis unit 120 acquires the following information from the declaration information of the array.
(A) Base address of the array (b) Size of one element of the array (c) Number of dimensions of the array (d) Information of each dimension (number of elements, distance between elements, lower limit)

Next, the list vector analysis unit 120 obtains the first-dimensional start address and end address for each loop iteration using the acquired information as follows.
Start address = base address + ((number of elements in the first dimension x size of elements) x (index in the second dimension-1))
End address = start address + (number of elements in the first dimension x element size)

The vector gather / scatter instruction generation unit 112 sets the start address and the end address calculated by the list vector analysis unit 120 to the command words of the vector scatter instruction 4-5 generated for the array A.

FIG. 5 shows a memory image of the array A when J = 3 in the outer loop of FIG. The memory area for list access by repeating J = 3 in the outer loop is within the range of the diagonal line indicated by A (L (I), 3) in FIG. Therefore, the start address and the end address calculated by the list vector analysis unit 120 are the start and end addresses in the shaded area of FIG. The load instruction 4-6 of A (I, J-1) is generated for the equation 3-2 of FIG. 3, but when J = 3, the load instruction 4-6 is the A (I) of FIG. , 2) Access the area surrounded by the dotted line. The load instruction 4-6 of A (I, 2) overtakes the preceding vector scatter instruction 4-5 of A (L (I), 3) because it does not overlap with the range of diagonal lines accessed in the list. It turns out that is possible.

As described above, the list vector analysis unit 120 finds the start and end of the address to access the list every time the loop is repeated, and the vector gather / scatter instruction generation unit 112 uses it as the command word of the vector scatter instruction 4-5. set.

The list address overlap determination unit 114 acquires the set start address and end address from the instruction word of the vector scatter instruction 4-5, and between the range and the range accessed by the subsequent load instruction 4-6. It is judged whether or not there is an overlap. In the case of the loop of FIG. 3, as shown in FIG. 5, the access range of the load instruction 4-6 of the array A corresponding to the equation 3-2 is the range of the J-1 in the second dimension of the array A, and the equation 3 In the vector scatter instruction 4-5 corresponding to -1, the second dimension of the array A is the range of J. Therefore, the list address overlap determination unit 114 has no dependency on the definition reference of the array A in this loop, and the load instruction 4-6 corresponding to the equation 3-2 is the vector scatter instruction corresponding to the equation 3-1. Judge that it is possible to overtake 4-5. When the overlap of the memory area to be accessed is not found between the list address overlap determination unit 114 and the subsequent load instruction, the overtaking bit V of the instruction word of the vector scatter instruction 4-5 is set to “1”. .. The list address overlap determination unit 114 sets the overtaking bit V of the instruction word to “0” when it is not possible to determine whether or not the access areas overlap from the array information that can be statically acquired at compile time.

The hardware (vector computer) performs overtaking control using the information of the instruction word of the list vector instruction generated by the above method. In the hardware, first, the overtaking bit V set by the compiler in the instruction word is confirmed, and if the value of the overtaking bit V is "1", the overtaking control is unconditionally performed for the instruction. When the value of the overtaking bit V is "0", the hardware obtains the start address and the end address of the access range from the register set in the instruction field fields Smin and Smax, and the address of the overlap range of the vector scatter instruction. By comparing with the address accessed by the subsequent load instruction, it is judged whether or not overtaking is possible, and overtaking control is performed when overtaking is possible.

The case of the vector scatter instruction has been described by taking the source program shown in FIG. 3 as an example. However, the present invention also executes the processing for the vector gather instruction, and whether or not it is possible to overtake the preceding memory store instruction. Can be determined by the compiler 100, and the information necessary for the determination by the hardware can be set in the instruction word.

<Effect of this embodiment>
In Patent Document 1, in the case of the source program shown in FIG. 3, the vector scatter instruction 4-5 corresponding to the equation 3-1 sets the access range from the start address to the end address of the array A. The area accessed by the cutter instruction 4-5 and the load instruction 4-6 was regarded as overlapping in the same array A, and it was determined that overtaking was not possible. That is, it was determined that overtaking was not possible even though the area where the addresses were not duplicated was actually accessed. On the other hand, in the present embodiment, the memory access range analysis function in the loop repetition unit enables overtaking control even for an instruction determined to be impossible to overtake in Patent Document 1. This alleviates the performance degradation of memory access caused by the load instruction waiting for the store instruction, and speeds up the execution of the program. In addition, by determining the overlap of addresses with the compiler, the resources consumed by the hardware can be saved compared to the case where the same processing is performed by the hardware, and the advantages of not being physically restricted by the hardware resources. There is. Further, there is an effect that the application of optimization accompanied by the change of the order of instructions such as the rearrangement of instructions is promoted.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.

In the first embodiment, the list vector analysis unit 120 acquires the information necessary for calculating the start address and the end address of the memory accessed by the list vector instruction from the declaration information of the array. However, array information such as Fortran shape inheritance arrays is unknown at compile time, and may not be known until execution time. In the present embodiment, when the necessary information cannot be obtained, the compiler 100 generates an instruction (machine language) for calculating the values at the time of execution instead of calculating the address of the access area by the list vector analysis unit 120. , Performs the process of adding to the object code. Further, since the address value is not fixed at the time of compilation, the overtaking bit V is set to "0" in the list address overlap determination unit 114. Further, the contents of the registers pointed to by Smin and Smax are set to, for example, NULL values. Specifically, (a) the base address of the array, (b) the size of one element of the array, (c) the number of dimensions of the array, and (d) the information (elements) of each dimension described in paragraph [0033]. Information about the composition of an array, such as the number of elements, the distance between elements, and the lower limit), is stored in a data structure called an array descriptor at run time. Therefore, the list vector analysis unit 120 of the compiler 100 acquires the information necessary for calculating the start address and the end address of the memory accessed by the list vector instruction from the array descriptor, and describes, for example, the calculation described in paragraph [0033]. Calculate the start address and end address of the memory accessed by the list vector instruction using the same calculation formula as the formula, and generate the instruction to be stored in the register indicated by the instruction words Smin and Smax of the list vector instruction. It is configured.

The instruction generated by the compiler 100 in the list vector analysis unit 120 calculates the start address and end address of the memory accessed by the list vector instruction when the object program is executed in the vector computer, and stores the start address and the end address in the register. The vector computer acquires the range of the memory access of the list vector instruction by referring to the register in the overtaking control device, and performs the overtaking control of the instruction. This makes it possible to control the overtaking of instructions in the same way as when the address of the access area is statically calculated at compile time.

[Third Embodiment]
Next, a third embodiment of the present invention will be described.

FIG. 6 is a block diagram of a computer according to the present embodiment. The computer 200 according to the present embodiment is configured to generate the object code 202 for the vector computer from the source program 201. The computer 200 includes a loop analysis unit 210 and a code generation unit 220.

The loop analysis unit 210 is configured to analyze the source program 201 and recognize a loop control statement that repeatedly processes the list vector.

The code generation unit 220 is configured to translate the loop control statement recognized by the loop analysis unit 210 into a series of instruction lists including a list vector instruction. Further, the code generation unit 220 calculates the start address and the end address of the memory accessed by the list vector instruction every time the loop of the loop control statement is repeated, and sets the start address and the end address as the instruction words of the list vector instruction. It is configured in.

The computer 200 has a processor such as a CPU and a memory, and realizes the loop analysis unit 210 and the code generation unit 220 on the computer by executing a program recorded on the hard disk or the like.

The computer 200 according to the present embodiment configured in this way functions as follows. That is, when the source program 201 is input to the computer 200, the loop analysis unit 210 first analyzes the source program 201 and recognizes a loop control statement that repeatedly processes the list vector. Next, the code generation unit 220 translates the loop control statement recognized by the loop analysis unit 210 into a series of instruction lists including the list vector instruction. At that time, the code generation unit 220 calculates the start address and the end address of the memory to be accessed by the list vector instruction every time the loop of the loop control statement is repeated, and sets the start address and the end address as the command words of the list vector instruction. do.

As described above, according to the present embodiment, appropriate overtaking control is possible. The reason is that the start address and the end address of the memory accessed by the list vector instruction are calculated every time the loop of the loop control statement is repeated, and the start address and the end address are set as the command words of the list vector instruction.

The present invention can be applied to a compiler, and can be particularly used for a compiler that translates a source program to generate an object program for a vector computer.

100 ... Compiler 101 ... Source program 102 ... Instruction word 110 ... In-loop instruction generation processing unit 111 ... Preceding instruction generation unit 112 ... Vector gather / scatter instruction generation unit 113 ... Subsequent instruction generation unit 114 ... List address overlap determination unit 120 ... List Vector analysis unit 130 ... Instruction list 200 ... Computer 201 ... Source program 202 ... Object code 210 ... Loop analysis unit 220 ... Code generation unit OP ... Operation code V ... Overtaking bit VR ... Field that specifies the vector register that stores the address Smin ... Top Field that specifies the register that stores the address Smax ... Field that specifies the register that stores the terminal address

Claims (10)

To a computer that generates an object program for a vector computer from a source program,
The source program is analyzed, and the loop control statement that repeatedly processes the list vector is translated into a series of instruction lists including the list vector instruction.
In the process, the start address and the end address of the memory accessed by the list vector instruction are calculated every time the loop of the loop control statement is repeated, and the start address and the end address are set as the command words of the list vector instruction. do,
compiler. In the calculation, when an element of a specific dimension of the array is specified by the list vector, the base address, the size of one element of the array, and the dimension of the array are obtained from the declaration information of the array of the source program. The number and the information of each dimension of the array are acquired, and the start address and the end address are calculated based on the acquired information.
The compiler according to claim 1. In the process, further, an address range from the start address set in the instruction word of the list vector instruction to the end address and an address range of the memory accessed by another memory access system instruction included in the instruction list. The presence or absence of duplication is determined, and based on the determination result, an overtaking bit in which a predetermined value is set according to the presence or absence of overlap in the program of the address area of the memory access is set in the instruction word.
The compiler according to claim 1 or 2. In the determination, when the list vector instruction is a vector gather instruction, the other memory access system instruction is a store instruction preceding the list vector instruction.
The compiler according to claim 3. In the determination, when the list vector instruction is a vector scatter instruction, the other memory access system instruction is a load instruction following the list vector instruction.
The compiler according to claim 3. In the process, if the information required for the calculation cannot be acquired at compile time, the information required for the calculation is acquired at the time of executing the object program, the start address and the end address are calculated, and stored in a predetermined register. Generate instructions,
The compiler according to any one of claims 1 to 5. A computer that generates an object program for a vector computer from a source program.
A loop analysis unit that analyzes the source program and recognizes a loop control statement that repeatedly processes the list vector.
Includes a code generator that translates the loop control statement into a series of instruction lists, including list vector instructions.
The code generation unit calculates the start address and the end address of the memory accessed by the list vector instruction for each loop repetition of the loop control statement, and the start address and the end address are the command words of the list vector instruction. Set to,
Computer. When the element of a specific dimension of the array is specified by the list vector, the code generator can obtain the base address, the size of one element of the array, and the array from the declaration information of the array of the source program. The number of dimensions and the information of each dimension of the array are acquired, and the start address and the end address are calculated based on the acquired information.
The computer according to claim 7. The code generation unit further includes an address range from the start address set in the instruction word of the list vector instruction to the end address and the address of the memory accessed by another memory access system instruction included in the instruction list. The presence or absence of overlap with the range is determined, and based on the determination result, an overtaking bit is set in the instruction word in which a predetermined value is set according to the presence or absence of overlap in the program of the address area of the memory access. do,
The computer according to claim 7 or 8. It is a code generation method executed by a computer that generates an object program for a vector computer from a source program.
Analyzing the source program, recognizing the loop control statement that iterates over the list vector,
The loop control statement is translated into a series of instruction lists including list vector instructions.
In the translation, the start address and the end address of the memory accessed by the list vector instruction are calculated for each loop repetition of the loop control statement, and the start address and the end address are set as the command words of the list vector instruction. do,
How to generate code for your computer.

Images