JP7038648B2 - Control device - Google Patents

Description

The present invention relates to a control device having a logic circuit between a control line and a controlled object.

Conventionally, a control device for controlling equipment installed in a facility such as a power plant or a substation needs to continue control without erroneous output even if a partial failure occurs. Multiplex architectures of triple or higher may be used.

For example, Patent Document 1 has a logic circuit that receives output signals from each of the three systems and takes a majority decision on the received three output signals, and the output signal selected by the logic circuit is controlled as a system output signal. A control device that outputs to is disclosed. In such a control device, a main output circuit and a sub output circuit are provided in the output unit of each system, and each of the three output signal lines is controlled by the main output circuit and the sub output circuit in different output units. As a result, even if a double failure occurs in the output unit, an output signal having a large number of normal outputs can be supplied to the logic circuit.

Japanese Unexamined Patent Publication No. 2017-0217112

In the control device described in Patent Document 1, an output signal having a large number of normal outputs can be supplied to the logic circuit even when a double failure occurs in the output unit, but when an abnormality occurs in the logic circuit, It may not be possible to output a normal output signal to the control target.

The present invention has been made in view of the above, and an object of the present invention is to obtain a control device capable of detecting an abnormality in a logic circuit.

In order to solve the above-mentioned problems and achieve the object, the control device of the present invention has three or more multiplexed control units, three or more control lines to which a voltage is supplied from a control power supply, and logic. It includes a circuit, three or more current detection units, and an abnormality detection unit. A logic circuit is connected between three or more control lines and a controlled object, and controls two or more switches controlled by two or more control units having different combinations of the three or more control units. Have for each line. The three or more current detection units each detect the current difference between two control lines having different combinations of the three or more control lines. The abnormality detection unit detects an abnormality in a logic circuit based on three or more current differences detected by the three or more current detection units. Each of the three or more control units shifts at least one of the timing of turning off the corresponding switch and the timing of turning on the corresponding switch among the two or more switches for each control line between the three or more control units. Switch the order of shifting at least one timing.

According to the present invention, there is an effect that an abnormality in a logic circuit can be detected.

The figure which shows an example of the structure of the control apparatus which concerns on Embodiment 1 of this invention. The figure which shows the structure of the logic circuit of the control device which concerns on Embodiment 1. The figure which shows the relationship between the logic circuit and the control part which concerns on Embodiment 1. The figure which shows the relationship between the current flowing through the control line, and the detection signal of a current detection part in the case where the control signal of the control part which concerns on Embodiment 1 is a 1st shift order. The figure which shows the relationship between the current flowing through the control line, and the detection signal of a current detection part in the case where the control signal of the control part which concerns on Embodiment 1 is a 2nd shift order. The figure which shows the relationship between the current flowing through the control line, and the detection signal of a current detection part in the case where the control signal of the control part which concerns on Embodiment 1 has a third shift order. The figure which shows the structural example of the abnormality detection part which concerns on Embodiment 1. The figure which shows the other example of the relationship between the control signal of the control part which concerns on Embodiment 1, the current flowing through a control line, and the detection signal of a current detection part. The figure which shows the state of the detection signal of the current detection part at the time of the open failure of one of the plurality of switches constituting the logic circuit which concerns on Embodiment 1. The figure which shows the state of the detection signal of the current detection part at the time of a short circuit failure of one of the plurality of switches constituting the logic circuit which concerns on Embodiment 1. The figure which shows the relationship between the turn-off timing of the switch which concerns on Embodiment 1 and the detectable short-circuit failure. The figure which shows the characteristic of the current detection part which concerns on Embodiment 1. The figure which shows an example of the hardware composition of the 1st system unit which concerns on Embodiment 1. The figure which shows an example of the hardware composition of the logic circuit which concerns on Embodiment 1. The figure which shows the structural example of the control apparatus which concerns on Embodiment 2 of this invention. The figure which shows the relationship between the current flowing through the control line, and the detection signal of a current detection part in the case of the switch of the logic circuit which concerns on Embodiment 2 is an open failure. The figure which shows the relationship between the current flowing through the control line, and the detection signal of a current detection part in the case of a short circuit failure of the switch of the logic circuit which concerns on Embodiment 2. The figure which shows the structural example of the control apparatus which concerns on Embodiment 3 of this invention. The figure which shows the structural example of the abnormality detection part which concerns on Embodiment 3. The figure which shows an example of the relationship between the control device arranged in the substation of the railway which concerns on Embodiment 4 of this invention, and a substation equipment.

Hereinafter, the control device according to the embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to this embodiment.

Embodiment 1.
FIG. 1 is a diagram showing an example of the configuration of the control device according to the first embodiment of the present invention. As shown in FIG. 1, the control device 1 is provided between the control power supply ₂ and the control target 3 ₁ , 32, ..., 3 _m , 4 ₁ , ..., 4 _m , and the control target 3 is provided. It controls ₁ , 3 ₂ , ..., 3 _m , 4 ₁ , ..., 4 _m .

The control power supply 2 is, for example, an AC power supply that outputs an AC voltage or a DC power supply that outputs a DC voltage. The controlled objects 3 ₁ , 32, ..., _{3 m} , 4 ₁ , ..., 4 _m are equipment or devices installed in facilities such as substations, power plants, or factories. In addition, m is an integer of 3 or more, for example. In the following, when each of the controlled objects 3 ₁ , 32, ..., _{3 m} is shown without distinction, it is described as the controlled object 3, and each of the controlled objects 4 ₁ , ..., 4 _m is distinguished. If it is shown without, it may be described as the control target 4.

The control device 1 includes a first system unit 10 ₁ , a _second system unit 102, a third system unit 10 ₃ , control lines ₂₀ , 24, switch groups 30 ₁ , 302, and resistors 31, 32, 33, current detectors 40 ₁ , 40 ₂ , 40 ₃ , and logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n , 52 ₁ , 52 ₂ , ..., It includes 52 _n-1 and 52 _n . Note that n is, for example, an integer of 6 or more. Logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , 51 _n and logic circuits 52 ₁ , 52 ₂ , ..., 52 _n-1 , 52 _n are separate switchboards from each other. Is placed in.

The first system unit 10 ₁ , the second system unit 10 ₂ , and the third system unit 10 ₃ are each configured by, for example, a PLC (Programmable Logic Controller) or the like. The first system unit 10 ₁ includes a control unit 11 ₁ and an abnormality detection unit 12 ₁ . Similarly, the _second system unit 10 ₂ includes a control unit ₁₁₂ and an abnormality detection unit 122. The third system unit 10 ₃ includes a control unit 11 ₃ and an abnormality detection unit ₁₂₃ .

The control device 1 is _tripled by these _three control units 11 ₁ , 112, and 113. The control unit 11 ₁ is a control unit of the first system, the control unit 11 ₂ is a control unit of the second system, and the control unit 11 ₃ is a control unit of the third system. In addition, the abnormality detection units 12 ₁ , 12 ₂ , ₁₂₃ include logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n , 52 ₁ , 52 ₂ , ..., 52. Each abnormality of _{n -1} , 52n is detected. Hereinafter, when _each of the control units 11 ₁ , ₁₁₂ , and 113 is shown without distinction, it may be referred to as the control unit 11, and _each of the abnormality detection units 12 ₁ , ₁₂₂ , and 123 is not distinguished. When indicated, it may be described as an abnormality detection unit 12.

The control lines 20 and 24 are connected to the control power supply 2, and the voltage supplied from the control power supply 2 is applied. For example, the control line 20 is connected to the positive electrode of the control power supply 2, and the control line 24 is connected to the negative electrode of the control power supply 2. The control line 20 is branched into control lines 21, 22, and 23. Further, the control line 21 is branched into the control lines 21 ₁ and ₂₁₁ , the control line 22 is branched into the control lines 22 ₁ and 222, and the control line 23 is _branched into the control lines 23 ₁ and ₂₃₂ . .. The control line 24 is branched into control lines 24 ₁ and ₂₄₂ .

The switch group 30 ₁ is connected between the control lines 21, 22, 23, 24 and the control lines 21 ₁ , 22 ₁ , 23 ₁ , 24 ₁ , and the control lines 21, 22, 23, 24 and the control lines 21 ₁ . , 22 ₁ , 23 ₁ , 24 ₁ Make connections and disconnections. _The switch group 30 ₂ is connected between the control lines 21, 22, 23, 24 and the control lines ₂₁₁ , 222, ₂₃₂ , 242, and the control lines 21, 22, 23, 24 and the control line _{211 2 .} , ₂₂₂ , 23 ₂ , ₂₄₂ to connect and disconnect. The switch group 30 ₁ , 30 ₂ is controlled by, for example, the control unit 11 ₁ , _{112, 11 3 or} an external device.

The resistor 31 is arranged in the middle of the control line 21, the resistor 32 is arranged in the middle of the control line 22, and the resistor 33 is arranged in the middle of the control line 23. The resistance values of the resistors 31, 32, and 33 are set so that, for example, the currents flowing from each of the control lines 21, 22, and 23 to the control targets 3 and 4 are equal.

The current detection units 40 ₁ , 40 ₂ , 403 detect the current difference between _two control lines of the control lines 21, 22, 23, which are different combinations from each other. Such current detection units 40 ₁ , 40 ₂ , ₄₀₃ are, for example, non-contact sensors.

Specifically, the current detection unit 40 ₁ detects the current difference ΔI ₂₁ which is the difference between the current I2 of the control line 22 and the current I1 of the control line 21. The current detection unit 402 detects a current difference ΔI ₃₂ which is a difference between the current I3 of the control line 23 and the current _I2 of the control line 22. The current detection unit 40 ₃ detects the current difference ΔI ₁₃ which is the difference between the current I1 of the control line 21 and the current I3 of the control line 23. It should be noted that ΔI ₂₁ = I2-I1, ΔI ₃₂ = I3-I2, and ΔI ₁₃ = I1-I3.

Each of the current detectors 40 _{1 , 402} , and 403 includes, for example, a penetrating CT (Current Transformer). The control line 21 is attached to the CT of the current detection unit 401 in _a direction opposite to the direction from the control power supply 2 to the control target 3, and the control line 22 is in the direction from the control power supply 2 to the control target 3. It can be installed in the state. As a result, the current detection unit 40 ₁ can output a detection signal Sd1 having a magnitude corresponding to the current difference ΔI ₂₁ .

The control line 22 is attached to the CT of the current detection unit 402 in a direction opposite to the direction from the control power supply ₂ to the control target 3, and the control line 23 is in the direction from the control power supply 2 to the control target 3. It can be installed in the state. As a result, the current detection unit 402 can output a detection signal _Sd2 having a magnitude corresponding to the current difference ΔI ₃₂ .

The control line 23 is attached to the CT of the current detection unit 403 in a state opposite to the direction from the control power supply 2 to the control target ₃ , and the control line 21 is in the direction from the control power supply 2 to the control target 3. It can be installed in the state. As a result, the current detection unit 403 can output the detection signal _Sd3 having a magnitude corresponding to the current difference ΔI ₁₃ .

As described above, the current detectors 40 ₁ , 40 ₂ , 403 attach the _two control lines of the control lines 21, 22, 23, which are different combinations from each other, to the CT, so that the current difference ΔI ₂₁ , ΔI ₃₂ , ΔI ₁₃ is detected, but is not limited to such an example. For example, each of the current detection units 40 ₁ , 40 ₂ , and 403 calculates the difference between the CT attached to _each of the two control lines of the control lines 21, 22, and 23 and the output of these CTs to generate a current. The configuration may include a calculation unit for detecting the differences ΔI ₂₁ , ΔI ₃₂ , and ΔI ₁₃ .

Hereinafter, when _each of the current detection units 40 ₁ , 40 ₂ , and 403 is shown without distinction, it may be referred to as the current detection unit 40. Further, when each of the current difference ΔI ₂₁ , ΔI ₃₂ , and ΔI ₁₃ is shown without distinction, it may be described as the current difference ΔI.

Logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n , 52 ₁ , 52 ₂ , ..., 52 _n-1 , 52 _n are the first system, the second system. , And a majority logic circuit capable of performing normal output if at least two of the third systems are normal, and have the same configuration as each other.

Each of the logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n has at least one of the control lines 21 ₁ , 22 ₁ , 23 ₁ , 24 ₁ and the control target 3 ₁ , It is connected to the corresponding control target 3 out of 3 ₂ , ..., 3 _m . For example, the logic circuit 51 ₁ is connected between the control line 24 ₁ and the control target ₃₁ . The logic circuits 51 ₂ and 51 ₃ are connected between the control lines 21 ₁ , 22 ₁ and 23 ₁ and the control target 3 ₁ .

Further, the logic circuit ₅₄₁ is connected between the control line 24 ₁ and the control target 32 ₂ . The logic circuit ₅₁₅ is connected between the control lines 21 ₁ , 22 ₁ , 23 ₁ and the control target 3 ₂ . Hereinafter, when each of the logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n is shown without distinction, it may be described as the logic circuit 51.

The logic circuits 52 ₁ , 52 ₂ , ..., 52 _n-1 , 52 _n include at _least one of the control lines ₂₁₁ , 222, ₂₃₂ , ₂₄₂ and the control target 4 ₁ , ..., 4 _m . Of these, it is connected to the corresponding control target 4. For example, the logic circuit 52 ₁ is connected between the control line ₂₄₂ and the control target ₄₁ . The logic circuit 52 ₂ is connected between the control lines ₂₁₁ , 222, ₂₃₂ and the control target _{4 1 .}

Further, the logic circuit 52 _n-1 is connected between the control line 242 and the control target _{4 m} . The logic circuit 52 _n is connected between the control lines ₂₁₁ , 222, ₂₃₂ and the control target _{4 m} . Hereinafter, when each of the logic circuits 52 ₁ , 52 ₂ , ..., 52 _n-1 , 52 _n is shown without distinction, it may be described as the logic circuit 52.

The control units 11 ₁ , 11 ₂ , 113 _send the control signals S11 ₁ to S11 _n , S21 ₁ to S21 _n to the logic circuits 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n . , S31 ₁ to S31 _n are output to control the controlled objects 3 ₁ , 32, ..., _{3 m} . Further, the control units 11 ₁ , _{112, 113 to the logic circuits 52 1 , 52 2 , ...} , 52 _n-1 , 52 _n , control signals S12 ₁ to S12 _n , S22 ₁ to S22 _n , S32. By outputting ₁ to S32 _n , the control target 4 ₁ , ..., 4 _m is controlled.

For example, the control units _{11 1} , 112, and _{113 output the control signals S11 1, S21 1, and S31 1 to the logic circuit 51 1 , and output the} control signals S11 ₂ , S21 ₂ , and S31 ₂ to the logic circuit ₅₁₂ . Then, the control target 3 ₁ is controlled by outputting the control signals S11 ₃ , S21 ₃ , and S31 ₃ to the logic circuit 51 ₃ . The control units _{11 1} , 112, and 113 output the control signals S11 ₄ , S21 ₄ , and S3 _{1 4 to} the logic circuit ₅₁₄ , and output the control signals S11 ₅ , S21 ₅ , and S3 ₁₅ to the logic circuit ₅₁₅ . Then, the control target 3 ₂ is controlled.

Further, the control units _{11 1} , 112, and _{113 output the control signals S12 1, S22 1, and S32 1 to the logic circuit 52 1 , and output the} control signals S12 ₂ , S22 ₂ , and S32 ₂ to the logic circuit 52 ₂ . By doing so, the control target ₄₁ is controlled. The control units _{11 1 ,} 112, and 113 output the control signals S12 _n-1 , S22 _n-1 , and S32 _n-1 to the logic circuit 52 _n-1 , and output the control signals S12 _n , S22 _n , and S32 _n . By outputting to the logic circuit 52 _n , the controlled object 4 _m is controlled.

FIG. 2 is a diagram showing a configuration of a logic circuit of the control device according to the first embodiment, and shows the configuration of the logic circuits 51 _{1 ,} 51 ₂ , 513. As shown in FIG. 2, the logic circuit 51 ₁ is connected between the control line 24 ₁ and the control line 89. The logic circuit _{512 is connected between the control lines 21 1, 22 1, 23 1 and the control} line 80. The logic circuit 51 ₃ is connected between the control lines 21 ₁ , 22 ₁ , 23 ₁ and the control line 81. _{The control lines 80, 81, 89 are connected to the control target 31, and the control target 3 1 is controlled} by the output from the logic circuits 51 ₁ , 51 ₂ , 513 to the control lines 80, 81, 89. As described above, the logic circuits 51 ₁ , 51 ₂ , 51 ₃ have the same configuration as each other, and the configuration and operation of the logic circuit ₅₁₂ will be specifically described below.

As shown in FIG. ₂ , the logic circuit 521 includes switches 61 ₁ , ₆₁₂ , 62 ₁ , 62 ₂ , 63 ₁ , ₆₃₂ and connection lines 70 ₁ , 70 ₂ , 70 ₃ , 71 ₁ , ₇₁₂ , It is equipped with 71 ₃ , 72 ₁ , 72 ₂ , and 72 ₃ . The switches 61 ₁ and 62 ₁ are connected between the control line 21 ₁ and the control target 3 ₁ , and the switches 62 ₂ and 63 ₁ are connected between the control line 22 ₁ and the control target 3 ₁ . ₂ , 63 ₂ are connected between the control line 23 ₁ and the control target 3 ₁ .

Specifically, a connection line 70 ₁ , a switch 61 ₁ , a connection line 71 ₁ , a switch 62 ₁ , and a connection line 72 ₁ are connected in series between the control line 21 ₁ and the control target 3 ₁ . A connection line 702, a switch 622, a connection line ₇₁₂ , _{a switch 63 1 ,} and a connection line _{722 are} connected in series between the control line 22 ₁ and the control target 3 ₁ . _A connection line 703, a switch ₆₁₂ , a connection line 713 _, a switch ₆₃₂ , and a connection line 732 _are connected in series between the control line 231 and the control target _{3 1} .

FIG. 3 is a diagram showing the relationship between the logic circuit and the control unit according to the first embodiment. As shown in FIG. 3, the switches 61 ₁ and 612 are controlled to be turned on and off by the control signal S11 ₂ output from the control unit ₁₁₁ , and the switches 62 ₁ and 62 ₂ are _output from the control unit ₁₁₂₂ . _On and off are controlled by the control signal S221. Further, the switches 63 ₁ and 63 ₂ are controlled to be turned on and off by the control signal S31 ₂ output from the control unit ₁₁₃ .

The switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ , 63 ₂ are, for example, electromagnetic relays such as latching relays, but may also be semiconductor relays. Hereinafter, when each of the switches 61 ₁ and 62 ₂ is shown without distinction, it is described as a switch 61, and when each of the switches 62 ₁ and 62 ₂ is shown without distinction, it is described as a switch 62 and the switch 63 ₁ and When each of 63 ₂ is shown without distinction, it may be described as switch 63.

Since the logic circuits 51 and 52 operate normally even if one of the plurality of switches 61, 62, 63 fails, the failure does not become apparent. However, for example, in the logic circuits 51 and 52, if a failure occurs in a switch controlled by a control system different from the one switch after one switch fails, the logic circuits 51 and 52 do not operate normally. There is.

Therefore, the control device 1 includes an abnormality detection unit 12 in addition to the control unit 11, and the abnormality detection unit 12 causes one of the plurality of switches 61, 62, 63 constituting the logic circuits 51, 52 to be switched. The failure is detected as an abnormality of the logic circuits 51 and 52. Hereinafter, the operation of the control unit 11 for detecting the abnormality of the logic circuits 51 and 52 by the abnormality detection unit 12 and the abnormality detection method of the logic circuits 51 and 52 by the abnormality detection unit 12 will be specifically described.

FIG. 4 is a diagram showing the relationship between the current flowing through the control line and the detection signal of the current detection unit when the control signal of the control unit according to the first embodiment has the _first deviation order, and is a diagram showing the relationship between the detection signal and the detection signal of the current detection unit. Here is an example when is normal. As shown in FIG. 4, _each of the control signals S11 ₂ , S21 ₂ , and S312 _output from the control units _{11 1} , 112, and 113 each has a timing to turn on the corresponding switch among the switches 61, 62, and 63. Is the same at time t10, but the timing at which the corresponding switches are turned off is different from each other.

Here, it is assumed that the magnitudes of the currents I1, I2, and I3 when _each of the control lines 21, 22, and 23 and the control target 31 are connected are the same, and the currents I1, I2, and I3 in this case are assumed to be the same. The current value of is described as "Ia". Further, for convenience of explanation, the current value when _one or two of the control lines 21, 22, and 23 are connected to the control target 31, is also described as “Ia”. The size of "Ia" may differ depending on the number of control lines connected to the control target 31 _among the control lines 21, 22, 23. For example, "Ia" is a case where only _{one of the control lines 21 and 22 and 23 is connected to the control target 31 and a case where all the control lines 21 and 22 and 23 are connected to the control target 3 1 .} And, the size may be different.

As shown in _FIG . 4, between the times t10 and t11, the switches 61, 62, and 63 _are turned on by the control signals _S112 , S221, and S312. Therefore, the currents are in equilibrium between the two control lines attached to the current detection units 40 _{1 ,} 40 ₂ , and 403, and the current differences ΔI ₂₁ , ΔI ₃₂ , and ΔI ₁₃ are “0”. Therefore, the detection signals Sd1, Sd2, and _{Sd3 output} from the current detection units 40 ₁ , 402, and 403 are analog signals having a magnitude of "0".

In the example shown in FIG. 4, the switches are turned off in the order of the first system → the second system → the third system, that is, the switches 61, 62, 63. Specifically, at time t11, the switch 61, which is a switch of the _first system, is turned from on to off by the control signal S112. Further, at time t12, the switch 62, which is a switch of the _second system, is turned from on to off by the control signal S221. Further, at time t13, the switch 63, which is a switch of the _third system, is turned from on to off by the control signal S312. In this way, the control units 11 ₁ , ₁₁₂ , and _{113 make logic circuits for the control signals S112, S221, and S31 2 so that} the switches are turned off in the order of the first system, the second system, and the _third system. It can be _output to 512.

During the period from time t11 to t12, since _only the current I2 flows through the control target 31, ΔI ₂₁ = Ia, ΔI ₃₂ = −Ia, and ΔI ₁₃ = 0. That is, the current becomes unbalanced between the _two control lines attached to the current detection units 40 ₁ and 402, and the current becomes equilibrium between the _two control lines attached to the current detection units 403. _In this case, the detection signal Sd1 of the current detection unit 401 is an analog signal having a magnitude of "Ia", and the detection signal _Sd2 of the current detection unit 402 is an analog signal having a magnitude of "-Ia". The detection signal _Sd3 of the current detection unit 403 is an analog signal having a magnitude of “0”.

FIG. 5 is a diagram showing the relationship between the current flowing through the control line and the detection signal of the current detection unit when the control signal of the control unit according to the first embodiment has the _second deviation order, and is a diagram showing the relationship between the detection signal and the detection signal of the current detection unit. Here is an example when is normal. In the example shown in FIG. 5, the switches are turned off in the order of the second system → the third system → the first system, that is, the switches 62, 63, 61. Specifically, at time t11, the switch 62 is turned from on to off by the control signal _S221 . Further, at _time t12, the switch 63 is turned on and off by the control signal S312. Further, at _time t13, the switch 61 is turned from on to off by the control signal S112.

In this case, since _only the current I3 flows through the control target 31 during the period from time t11 to t12, ΔI ₂₁ = 0, ΔI ₃₂ = Ia, and ΔI ₁₃ = −Ia. That is, the current becomes equilibrium between the two control lines attached to the current detection unit 401, and the current becomes unbalanced between the _{two control lines attached to the current detection units 40 2 and 403} . Therefore, the detection signal Sd1 is an analog signal having a magnitude of "0", the detection signal Sd2 is an analog signal having a magnitude of "Ia", and the detection signal Sd3 has a magnitude of "-Ia". Is an analog signal.

FIG. 6 is a diagram showing the relationship between the current flowing through the control line and the detection signal of the current detection unit when the control signal of the control unit according to the first embodiment has the _third deviation order, and is a diagram showing the relationship between the detection signal and the detection signal of the current detection unit. Here is an example when is normal. In the example shown in FIG. 6, the switches are turned off in the order of the third system → the first system → the second system, that is, the switches 63, 61, 62. Specifically, at time t11, the switch 63 is turned from on to off by the control signal _S312 . Further, at time t12, the switch 61 is turned on and off by the control signal _S112 . Further, at _time t13, the switch 62 is turned from on to off by the control signal S221.

In this case, since _only the current I1 flows through the control target 31 during the period from time t11 to t12, ΔI ₂₁ = −Ia, ΔI ₃₂ = 0, and ΔI ₁₃ = Ia. That is, the current becomes unbalanced between the _two control lines attached to the current detection units 40 ₁ and 403, and the current becomes equilibrium between the _two control lines attached to the current detection units 402. Therefore, the detection signal Sd1 is an analog signal having a magnitude of "-Ia", the detection signal Sd2 is an analog signal having a magnitude of "0", and the detection signal Sd3 has a magnitude of "Ia". Is an analog signal.

In this way, the control units _{11 1 ,} 112, and 113 can shift the timing of turning off the corresponding switch among the switches 61, 62, and 63. When the control signals S11 ₂ , S21 ₂ , and S31 ₂ shown in FIG. 4, FIG. 5, or FIG. 6 are _output to the logic circuit 512, the abnormality detection unit 12 is a current detection unit 40 ₁ , 40 ₂ , 40 ₃ . Based on whether or not the detection signals Sd1, Sd2, and Sd3 output from are in the state shown in _FIG . 4, FIG. 5, or FIG. 6, it can be determined whether or not there is an abnormality in the logic circuit 521. .. Hereinafter, when each of the detection signals Sd1, Sd2, and Sd3 is shown without distinction, it may be described as the detection signal Sd.

When detecting an abnormality in the logic circuit 512, the abnormality detection unit ₁₂ can classify the detection signal Sd into three stages of plus level, zero level, and minus level. FIG. 7 is a diagram showing a configuration example of the abnormality detection unit according to the first embodiment. The abnormality detection unit 12 shown in FIG. 7 includes an analog-digital converter 41, a processing unit 42, and a determination unit 43. The analog-to-digital converter 41 converts the detection signal Sd, which is an analog signal, into a digital signal. The processing unit 42 classifies the detection signal Sd into three stages of plus level, zero level, and minus level based on the digital signal converted by the analog-to-digital converter 41.

For example, the processing unit 42 determines that the detection signal Sd showing the current difference ΔI having the threshold value Is1 or more is a plus level, and determines that the detection signal Sd showing the current difference ΔI having the threshold value Is2 or more and less than the threshold value Is1 is a zero level. judge. Further, the processing unit 42 determines that the detection signal Sd indicating the current difference ΔI less than the threshold value Is2 is a minus level. The determination unit 43 can detect whether or not there is an abnormality in the logic circuits 51 and 52 based on the level state of the detection signal Sd determined by the processing unit 42. It should be noted that Is1> 0 and Is2 <0.

In the above-mentioned example, when each of the control lines 21, 22 and 23 and the control target 31 are connected, _an example in which the magnitudes of the currents I1, I2 and I3 are the same as each other has been described, but the current I1 has been described. , I2, I3 may be currents of different magnitudes from each other. FIG. 8 is a diagram showing another example of the relationship between the control signal of the control unit according to the first embodiment, the current flowing through the control line, and the detection signal of the current detection unit.

The processing unit 42 of the abnormality detection unit 12 corrects the detection signals Sd1, Sd2, Sd3 based on the detection signals Sd1, _Sd2 , _Sd3 output from the current detection units 40 ₁ , 402, and 403. Specifically, the processing unit 42 corrects the detection signals Sd1, Sd2, Sd3 so that Sd1 = Sd2 = Sd3 = 0 in the period from time t10 to t11 when the logic circuits 51 and 52 are normal. The values ΔSd1, ΔSd2, ΔSd3 are determined.

Here, the magnitude of the current I1 flowing from the control line 21 to the control target 31 is "Ib", and the magnitude of the currents _I2 and _I3 flowing from the control lines 22 and 23 to the control target 31 is "Ia". And. In this case, Sd1 = Ia-Ib, Sd2 = 0, and Sd3 = Ib-Ia in the period from time t10 to t11. Therefore, in this case, the processing unit 42 sets ΔSd1 = Ib-Ia, ΔSd2 = 0, and ΔSd3 = Ia-Ib.

Then, in the period from time t10 to t11 thereafter, the processing unit 42 generates a new detection signal Sd1 by adding the correction value ΔSd1 to the detection signal Sd1, and adds the correction value ΔSd2 to the detection signal Sd2. The detection signal Sd2 is generated, and a new detection signal Sd3 is generated by adding the correction value ΔSd3 to the detection signal Sd3. As a result, the processing unit 42 can accurately classify each detection signal Sd into three stages of plus level, zero level, and minus level in the period from time t10 to t11.

Further, the processing unit 42 can calculate the magnitudes of the currents I1, I2, I3 from the detection signals Sd1, Sd2, Sd3 during the period from time t11 to t12, and the correction value ΔSd1 is based on the calculation result. It is also possible to determine ΔSd2 and ΔSd3. Also with this, the processing unit 42 can accurately classify each detection signal Sd into three stages of plus level, zero level, and minus level. The method for determining the correction values ΔSd1, ΔSd2, ΔSd3 is not limited to the above-mentioned example.

Further, as shown in FIG. 8, the determination unit 43 may change the detection signals Sd1, Sd2, Sd3 for a short period of time at time t10, which is the timing of the change of the currents I1, I2, and I3. , Such changes can be ignored. That is, the determination unit 43 uses the detection signal Sd whose same level continues for a certain period of time Tc or _more for detecting an abnormality in the logic circuit 512, and uses the detection signal Sd whose same level is less than Tc for a certain period of time in the logic circuit ₅₁₂ . Not used for anomaly detection. As a result, the determination unit 43 can improve the accuracy of abnormality detection of the logic circuit ₅₁₂ . The abnormality detection unit 12 may be configured such that the processing unit 42 only corrects the detection signals Sd1, Sd2, Sd3, and the determination unit 43 determines the level of the detection signals Sd1, Sd2, Sd3.

Next, the abnormality detection of the logic circuit 512 by the abnormality detection unit ₁₂ will be specifically described. First, a case where one of the switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ , 63 ₂ of the logic circuit ₅₁₂ has an open failure will be described. An open failure is a failure in which the switch is not short-circuited, and is caused by, for example, a contact failure.

FIG. 9 is a diagram showing a state of a detection signal of the current detection unit when one of the plurality of switches constituting the logic circuit according to the first embodiment fails to open. FIG. 9 shows an example in which the switches 61, 62, 63 are turned off in the order of the first system → the second system → the third system, that is, the switches 61 ₁ are in the open failure. When the switch 61 ₁ is _an open failure, the control signal S11 ₂ does not turn on the switch 61 ₁ , so that the current I1 does not flow from the control line 21 ₁ to the control target 31 via the control line 80.

Therefore, as shown in FIG. 9, when the switch 611 has an open failure, the detection signal Sd1 has a positive level and the detection signal _Sd3 has a negative level during the period from time t10 to t11. This also applies when the switch 621 has _an open failure. Therefore, in the determination unit 43 of the abnormality detection unit 12, at least one of the switches 61 ₁ and 62 ₁ is set when the detection signal Sd1 is at a positive level and the detection signal Sd3 is at a negative level during the period from time t10 to t11. It can be determined that the failure is open.

The determination unit 43 can determine whether each of the switches 62 ₂ , 63 ₁ , 61 ₂ , 63 ₂ has an open failure, as in the case of the switches 61 ₁ , 62 ₁ . For example, in the determination unit 43, when the detection signal Sd1 is at a negative level and the detection signal _Sd2 is at a positive level during the period from time t10 to t11, at least _one of the switches 622 and 631 is an open failure. Can be determined.

Further, in the determination unit 43, when the detection signal Sd2 is at a negative level and the detection signal Sd3 is at a positive level during the period from time t10 to t11, at least one of the switches 61 ₂ and 63 ₂ is an open failure. Can be determined. The abnormality detection unit 12 can detect an open failure of the switches 61, 62, 63 even if the timing at which the switches 61, 62, 63 are turned off is not different from each other.

Next, a case where some of the switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ , 63 ₂ of the logic circuit ₅₁₂ has a short-circuit failure will be described. A short-circuit failure is a failure in which the switch remains in a short-circuited state, and is caused by, for example, welding between contacts.

FIG. 10 is a diagram showing a state of a detection signal of the current detection unit when one of the plurality of switches constituting the logic circuit according to the _first embodiment fails in a short circuit, and the switch 611 is short-circuited. An example of a failure is shown. When the switch 61 ₁ is short _- circuited, the control signal S112 does not turn off the switch 61 ₁ .

As shown in FIG. 10, when the first system → the second system → the third system are turned off in the order of the switches 61, 62, 63, the detection signal Sd1 is at the zero level during the period from time t11 to t12. Yes, the detection signal Sd3 is at a negative level. In this case, the abnormality detection unit 12 determines that the switch 611 is _a short-circuit failure when the detection signal Sd1 is at the zero level and the detection signal Sd3 is at the minus level during the period from time t11 to t12. can.

On the other hand, when the switches are turned off in the order of the second system → the third system → the first system, that is, the switches 62, 63, 61, the detection signals Sd1, Sd2, Sd3 are shown in the figure during the period from time t11 to t12. It is the same state as in the case of 4. Therefore, when the determination unit 43 of the abnormality detection unit 12 is turned off in the order of the second system → the third system → the first system, that is, in the order of the switches 63, 61, 62 during the period from time t11 to t12, the switch 61 The short failure of ₁ cannot be detected.

As described above, the abnormality detection unit 12 may or may not be able to detect a short failure depending on the order in which the switches 61, 62, and 63 are turned off. FIG. 11 is a diagram showing the relationship between the switch off timing according to the first embodiment and the detectable short failure. As shown in FIG. 11, when the determination unit 43 of the abnormality detection unit 12 is turned off in the order of the first system → the second system → the third system, that is, the switches 61, 62, 63, the switches 61 ₁ , 62 It is possible to detect short faults of ₂ , 63 ₂ .

Further, as shown in FIG. 11, when the determination unit 43 of the abnormality detection unit 12 is turned off in the order of the third system → the first system → the second system, that is, in the order of the switches 63, 61, 62, the switch 61 ₁ , 63 ₁ and ₆₁₂ short faults can be detected. Further, as shown in FIG. 11, when the determination unit 43 of the abnormality detection unit 12 is turned off in the order of the second system → the third system → the _first system, that is, in the order of the switches 62, 63, 61, the switch 621 , 62 ₂ and ₆₁₂ short faults can be detected.

The control units _{11 1 ,} 112, and 113 switch the order in which the switches 61, 62, and 63 are turned off. For example, the control units 11 ₁ , ₁₁₂ , and 113 have the first switch control that turns off the switch in the order of the first system → the second system → the _third system, and the second system → the third system → the first system. The second switch control that turns off the switch and the third switch control that turns off the switch in the order of the third system → the first system → the second system are switched by rotation. For example, the control units 11 ₁ , ₁₁₂ , and 113 repeat the process of sequentially performing the first switch control, the second switch control, and the _third switch control.

As a result, the abnormality detection unit 12 can detect all short _- circuit failures of the switches 61 ₁ , 62 ₁ , 62 ₂ , 63 ₁ , 61 ₂ , 632. The control units _{11 1 ,} 112, and 113 can detect abnormalities in all logic circuits 51 by switching the order in which the switches 61, 62, and 63 are turned off for each logic circuit 51. ..

The control units 11 ₁ , ₁₁₂ , and 113 can switch the switch control order each time the control target ₃ is controlled. Further _, the control units 11 ₁ , ₁₁₂ , and 113 can also switch the order of switch control every unit time. The unit time is, for example, one hour, several hours, or one day.

Further, the control unit 11 can acquire the detection result from the abnormality detection unit 12. The control unit 11 can stop the control of the logic circuit 51 for which an abnormality is detected by the abnormality detection unit 12. Further, the control unit 11 can also output a control signal to the logic circuit 51 so that the operation of the control target 3 connected to the logic circuit 51 where the abnormality detection unit 12 has detected an abnormality is stopped. ..

FIG. 12 is a diagram showing the characteristics of the current detection unit according to the first embodiment. As shown in FIG. 12, in the current detection unit 40, the region where the current difference ΔI is relatively small is a high-precision region in which the change in the detection signal Sd with respect to the change in the current difference ΔI is relatively large. Further, in the current detection unit 40, the region where the current difference ΔI is relatively large is a low-precision region where the change in the detection signal Sd with respect to the change in the current difference ΔI is relatively small.

As described above, in the current detection unit 40, the region where the current difference ΔI is relatively small is the high-precision region. Therefore, the abnormality detection unit 12 accurately determines the correction values ΔSd1, ΔSd2, ΔSd3 for correcting the detection signals Sd1, Sd2, Sd3 when the current difference ΔI is not “0” in the period from time t10 to t11. can do.

Further, in the unbalanced time such as the period from time t11 to t12 shown in FIG. 4, a large current flows, but the region where the magnitude of the current difference ΔI is large in the current detection unit 40 is the low accuracy region. Since the detection range is large due to the detection in such a low accuracy region, it is not saturated and the presence or absence of imbalance can be detected with high accuracy.

As described above, since the current detection unit 40 has a high-precision region and a low-precision region, the processing unit 42 of the abnormality detection unit 12 sets each detection signal Sd in three stages of plus level, zero level, and minus level. Can be classified accurately. Therefore, it is possible to prevent the abnormality detection unit 12 from erroneously detecting an abnormality in the logic circuits 51 and 52.

FIG. 13 is a diagram showing an example of the hardware configuration of the first system unit according to the first embodiment. The configurations of the second system unit 10 ₂ and the third system unit 10 ₃ are the same as the configurations of the first system unit 10 ₁ . As shown in FIG. 13, the _first system unit 101 includes a computer including a processor 101, a memory 102, an input / output circuit 103, and a communication circuit 104.

The processor 101, the memory 102, the input / output circuit 103, and the communication circuit 104 can send and receive data to and from each other by the bus 105. The processor 101 executes the functions of the control unit 11 and the abnormality detection unit 12 by reading and executing the program stored in the memory 102. The processor 101 is an example of a processing circuit, and includes one or more of a CPU (Central Processing Unit), a DSP (Digital Signal Processer), and a system LSI (Large Scale Integration).

The memory 102 includes one or more of RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), and EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory). include. Further, the memory 102 includes a recording medium in which a computer-readable program is recorded. Such recording media include one or more of non-volatile or volatile semiconductor memories, magnetic disks, flexible memories, optical discs, compact discs, and DVDs (Digital Versatile Discs). The _first system unit 101 may include integrated circuits such as an ASIC (Application Specific Integrated Circuit) and an FPGA (Field Programmable Gate Array). The input / output circuit 103 includes, for example, the analog-to-digital converter 41 described above, an input / output port, and the like. Further, the communication circuit 104 constitutes a part of the control unit 11 and outputs control signals to the logic circuits 51 and 52.

FIG. 14 is a diagram showing an example of the hardware configuration of the logic circuit according to the first embodiment. Although the logic circuit 51 is shown in FIG. 14, the configuration of the logic circuit 52 is the same as that of the logic circuit 51. As shown in FIG. 14, the logic circuit 51 includes a switch unit 53, a communication circuit 54, and a switch drive circuit 55.

The switch unit 53 includes the above-mentioned switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ , ₆₃₂ . The communication circuit 54 communicates with the control unit 11 and receives a control signal transmitted from the control unit 11. The switch drive circuit 55 controls the on / off of the switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ , 63 ₂ based on the control signal acquired by the communication circuit 54. The logic circuits 51 and 52 may be configured to be capable of controlling the switches 61 ₁ , 61 ₂ , 62 ₁ , 62 ₂ , 63 ₁ and ₆₃₂ based on the control signal transmitted from the control unit 11. FIG. It is not limited to the configuration shown in.

In the first embodiment described above, the logic circuits 51 and 52, which are the majority logic circuits provided between the three control lines 21 and 22, 23 and the control targets 3 and 4, are the three control units 11 ₁ and 11 ₂ . , 113 has been described _, but the number of control lines connected to the logic circuits 51 and 52, the number of control units 11, and the configuration of the logic circuits 51 and 52 are not limited to the above-mentioned examples. For example, the number of control lines connected to the logic circuits 51 and 52 and the number of control units 11 may be 4 or more. Further, the logic circuits 51 and 52 may have a configuration in which two or more switches controlled by different control units 11 are provided between each of the four or more control lines and each of the control targets 3 and 4. In this way, the control device 1 may be quadrupled.

As described above, the control device 1 according to the first embodiment includes three or more multiplexed control units 11, three or more control lines 21, 22, 23, and one or more logic circuits 51. A 52, three or more current detection units 40, and an abnormality detection unit 12 are provided. A voltage is supplied to the control lines 21, 22, and 23 from the control power supply 2. The logic circuits 51 and 52 are connected between the control lines 21 and 22, 23 and each of the control targets 3 and 4, respectively, and the control unit 11 of three or more of the three or more switches 61, 62, 63 is connected. Of these, each control line 21, 22, 23 has two or more switches controlled by two control units 11 having different combinations. The three or more current detection units 40 detect the current difference ΔI between two control lines in different combinations of the three or more control lines 21, 22, 23, respectively. The abnormality detection unit 12 detects an abnormality in the logic circuits 51 and 52 based on the three or more current differences ΔI detected by the three or more current detection units 40. As a result, the control device 1 can detect an abnormality in the logic circuits 51 and 52.

In each of the three or more control units 11, the timing of turning off the corresponding switch among the two or more switches for each of the control lines 21, 22, and 23 is different from each other. As a result, not only when an open failure occurs in the switches 61, 62, 63 constituting the logic circuits 51, 52, but also when a short failure occurs in the switches 61, 62, 63 constituting the logic circuits 51, 52. Even if there is, the abnormality of the logic circuits 51 and 52 can be detected.

Further, the three or more control units 11 switch the order of shifting the timing of turning off the corresponding switches. As a result, even if a short-circuit failure occurs in any of the switches 61, 62, 63 constituting the logic circuits 51 and 52, the abnormality of the logic circuits 51 and 52 can be detected.

Further, one or more logic circuits 51 and 52 are provided corresponding to each of the plurality of control targets 3 and 4, and the three or more current detection units 40 are provided with three or more control lines 21 and 22.23. It is an intermediate portion and is arranged between the control power supply 2 and the plurality of logic circuits 51 and 52. Then, the abnormality detecting unit 12 detects the abnormality of the logic circuits 51 and 52 based on the three or more current differences ΔI detected by the three or more current detecting units 40. As described above, in the control device 1, since the current detection unit 40 is provided on the upstream side of the control lines 21, 22, 23, for example, as compared with the case where the current detection unit is provided for each logic circuit 51, 52 or for each switchboard, for example. It is possible to reduce the size and cost of the control device 1.

Further, a corresponding resistance among the resistances 31, 32, 33 is provided between the control power supply 2 and the plurality of logic circuits 51, 52 in the middle of each of the three or more control lines 21, 22, 23. Be done. As a result, the current flowing through the control lines 21 and 22 and 23 can be reduced, and the current flowing through the control lines 21 and 22 and 23 can be adjusted to be uniform.

Further, each of the three or more current detection units 40 has two control lines corresponding to each other in a state where the currents flowing through the two control lines of the three or more control lines 21, 22, 23 are opposite to each other. It is attached and outputs a detection signal Sd having a magnitude corresponding to the current difference ΔI. As a result, when the magnitudes of the currents flowing through the two corresponding control lines are the same, the current detection unit 40 sets the detection signal Sd to “0”. Therefore, for example, the abnormality detection unit 12 detects. When the signal Sd is not substantially "0", it can be detected that the logic circuits 51 and 52 have an abnormality.

Further, the abnormality detection unit 12 includes an analog-digital converter 41, a processing unit 42, and a determination unit 43. The analog-to-digital converter 41 converts the detection signal Sd, which is an analog signal output from each of the three or more current detection units 40, into a digital signal. The processing unit 42 corrects the current difference ΔI based on the digital signal output from the analog-digital converter 41. The determination unit 43 determines whether or not there is an abnormality in the logic circuits 51 and 52 based on the correction result of the processing unit 42. In this way, the abnormality detection unit 12 can accurately determine whether or not there is an abnormality in the logic circuits 51 and 52.

Further, the abnormality detection unit 12 is provided corresponding to each of the three or more control units 11. As a result, each of the three or more control units 11 outputs a control signal to the logic circuits 51 and 52 based on the abnormality detection result by the corresponding abnormality detection unit 12 among the three or more abnormality detection units 12. be able to. Therefore, it is possible to quickly perform processing when there is an abnormality in the logic circuits 51 and 52.

Embodiment 2.
The control unit of the control device according to the second embodiment is different from the control unit 11 of the control device 1 according to the first embodiment in that the timing of turning off the switch of the logic circuit is shifted at the point of shifting the timing of turning on the switch of the logic circuit. different. In the following, the components having the same functions as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted, and the differences from the control device 1 of the first embodiment will be mainly described.

FIG. 15 is a diagram showing a configuration example of the control device according to the second embodiment of the present invention. As shown in FIG. 15, the control device 1A according to the second embodiment is a first system instead of the first system unit 10 ₁ , the second system unit 10 ₂ , and the third system unit 10 ₃ shown in FIG. It differs from the control device 1 according to the first embodiment in that the unit 10A ₁ , the second system unit 10A ₂ , and the third system unit 10A ₃ are provided.

The first system unit 10A ₁ includes a control unit 11A ₁ and an abnormality detection unit 12A ₁ . The second system unit 10A ₂ includes a control unit 11A ₂ and an abnormality detection unit 12A ₂ . The third system unit 10A ₃ includes a control unit 11A ₃ and an abnormality detection unit 12A ₃ . The control device 1A is tripled by these three control units 11A ₁ , 11A ₂ , and 11A ₃ .

Further, the abnormality detection units 12A ₁ , 12A ₂ , 12A ₃ detect each abnormality of the logic circuits 51 and 52. Hereinafter, when each of the control units 11A ₁ , 11A ₂ , and 11A ₃ is shown without distinction, it may be described as the control unit 11A, and each of the abnormality detection units 12A ₁ , 12A ₂ , and 12A ₃ is not distinguished. When indicated, it may be described as an abnormality detection unit 12A.

_The control units 11A ₁ , 11A ₂ , 11A ₃ shift the timing of turning off the switches 61, 62, 63 at the point of shifting the timing of turning on the switches 61, 62, 63. It is different from 11 ₂ and 11 ₃ .

FIG. 16 is a diagram showing the relationship between the current flowing through the control line and the detection signal of the current detection unit when the switch of the logic circuit according to the second embodiment has an open failure. _{FIG. 16 shows the relationship between the control signals S112, S221, and S31 2 to} the logic circuit 512, the currents I1, _I2 , and I3, and the detection signals Sd1, _Sd2 , and Sd3, as in FIG.

In the example shown in _FIG . 16, the control signals S112, S221, and S312 output from the control units 11A ₁ , 11A ₂ , and 11A ₃ are used in the order of the _second system, the third system, and the _first system, that is, the switch 62. , 63, 61 are turned on in this order. Specifically, at time t20, the switch 62 is turned from off to _on by the control signal S221. Further, at time t21, the switch 63 is turned from off to on by the control signal S31 ₂ . Further, at time t22, the switch 61 is turned from off to _on by the control signal S112.

Therefore, when the logic circuit 521 is normal, the detection signal Sd1 becomes a plus level, the detection signal _Sd2 becomes a minus level, and the detection signal Sd3 becomes a zero level at times t21 to t22. Further, at time t23, the switches 61, 62, and 63 _are turned from _on to off by the control signals S112, _S221 , and S312. Therefore, when the logic circuit 521 is normal, the detection signals Sd1, _Sd2 , and Sd3 become zero levels during the period from time t22 to t23.

Further, when the switch 61 ₁ of the logic circuit 512 has _an open failure, the detection signal Sd1 becomes a positive level and the detection signal Sd3 becomes a negative level during the period from time t22 to t23. The abnormality detection unit 12A may detect _an open failure of the switch 611 of the logic circuit 521 when the detection signal Sd1 is at a positive level and the detection signal _Sd3 is at a negative level during the period from time t22 to t23. can. The abnormality detection unit 12A can detect an open failure of switches _other than the switch 611 in the logic circuit 512 based on the detection signals Sd1, _Sd2 , _Sd3 as in the case of the switch 611.

FIG. 17 is a diagram showing the relationship between the current flowing through the control line and the detection signal of the current detection unit when the switch of the logic circuit according to the second embodiment has a short circuit failure. _{FIG. 17 shows the relationship between the control signals S112, S221, and S31 2 to} the logic circuit 512, the currents I1, _I2 , and I3, and the detection signals Sd1, _Sd2 , and Sd3, as in FIG. In the example shown in FIG. 17, similarly to the example shown in FIG. 16, the control signals S11 ₁ , S21 ₁ , and S31 ₁ output from the control units 11A ₁ , 11A ₂ , and 11A ₃ are used to control the second system → the third system →. The first system is turned on, that is, the switches 62, 63, and 61 are turned on in this order.

When the switch 61 ₁ of the logic circuit 512 has _a short-circuit failure, the detection signal Sd1 becomes a negative level in the period from time t20 to t21, and the detection signal Sd3 becomes a positive level in the period from time t21 to t22. The abnormality detection unit 12A has _{a switch 61 1 of} the logic circuit 512 when the detection signal Sd1 is at a negative level during the period from time t20 to t21 and the detection signal Sd3 is at a positive level during the period from time t21 to t22. Short circuit failure can be detected. The abnormality detection unit 12A can detect a short circuit failure based on the detection signals Sd1, _Sd2 , _Sd3 for the switches _other than the switch 611 in the logic circuit 512 as in the case of the switch 611.

The control units 11A ₁ , 11A ₂ , 11A ₃ switch the order of shifting the timing of turning on the switches 61, 62, 63. For example, the control units 11A ₁ , 11A ₂ , 11A ₃ are the first switch control that turns the switch on in the order of the first system → the second system → the third system, the second system → the third system → the first system. The second switch control that turns the switch from off to on in the order of, and the third switch control that turns the switch from off to on in the order of the third system → the first system → the second system are switched by rotation. For example, the control units 11A ₁ , 11A ₂ , 11A ₃ repeat the process of sequentially performing the first switch control, the second switch control, and the third switch control.

In addition, the control units 11A ₁ , 11A _{2 ,} 11A ₃ perform the same switching processing as the control units 11 ₁ , ₁₁₂ , 113 in addition to the processing of shifting the timing of turning off the switches 61, 62, 63, so that the switches 61, It is also possible to shift the timing of turning on 62 and 63. As a result, it is possible to perform a process of detecting a short-circuit failure of the switches constituting the logic circuits 51 and 52 before and after the timing when all the switches 61, 62, and 63 are turned on. Therefore, the accuracy of detecting a short-circuit failure of the switches constituting the logic circuits 51 and 52 can be further improved.

Further, the control device 1A according to the second embodiment has the same number of control lines connected to the logic circuits 51 and 52, the number of control units 11A, and the logic circuit 51, as in the control device 1 according to the first embodiment. , 52 is not limited to the above-mentioned example. For example, the number of control lines connected to the logic circuits 51 and 52 and the number of control units 11A may be 4 or more.

The hardware configuration example of the first system unit 10A ₁ , the second system unit 10A ₂ , and the third system unit 10A ₃ according to the second embodiment is the first system unit 10 ₁ and the second system according to the first embodiment. It is the same as the unit 10 ₂ and the third system unit 10 ₃ . For example, the first system unit 10A ₁ , the second system unit 10A ₂ , and the third system unit 10A ₃ according to the second embodiment can have the same configuration as the hardware configuration shown in FIG. The processor 101 can execute the functions of the control unit 11A and the abnormality detection unit 12A by reading and executing the program stored in the memory 102.

As described above, the three or more control units 11A ₁ , 11A ₂ , 11A ₃ in the control device 1A according to the second embodiment are the corresponding switches among the two or more switches for each control line 21, 22, 23. Shift the timing of turning on each other. As a result, it is possible to detect a short-circuit failure of the switches 61, 62, 63 constituting the logic circuits 51, 52.

Further, the three or more control units 11A ₁ , 11A ₂ , 11A ₃ switch the order of shifting the timing of turning on the switches 61, 62, 63 constituting the logic circuits 51, 52. As a result, the control device 1A can detect a short-circuit failure of all the switches 61, 62, 63 constituting the logic circuits 51, 52.

Embodiment 3.
The abnormality detection unit of the control device according to the third embodiment has a comparator that compares the detection signal of the current detection unit with the threshold value, instead of the analog-to-digital converter that digitizes the detection signal of the current detection unit. It is different from the abnormality detection unit 12 of the control device 1 according to the first embodiment. In the following, the components having the same functions as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted, and the differences from the control device 1 of the first embodiment will be mainly described.

FIG. 18 is a diagram showing a configuration example of the control device according to the third embodiment of the present invention. As shown in FIG. 18, the control device 1B according to the third embodiment is a first system instead of the first system unit 10 ₁ , the second system unit 10 ₂ , and the third system unit 10 ₃ shown in FIG. It differs from the control device 1 according to the first embodiment in that the unit 10B ₁ , the second system unit 10B ₂ , and the third system unit 10B ₃ are provided.

The first system unit 10B ₁ includes a control unit 11 ₁ and an abnormality detection unit 12B ₁ . The _second system unit 10B ₂ includes a control unit 112 and an abnormality detection unit 12B ₂ . The third system unit 10B ₃ includes a control unit 11 ₃ and an abnormality detection unit 12B ₃ . The abnormality detection unit 12B ₁ , 12B ₂ , 12B ₃ detects an abnormality in each of the logic circuits 51 and 52. Hereinafter, when each of the abnormality detection units 12B ₁ , 12B ₂ , and 12B ₃ is shown without distinction, it may be referred to as an abnormality detection unit 12B. The control device 1B may be configured to include control units 11A ₁ , 11A ₂ , 11A ₃ instead of the control units 11 ₁ , ₁₁₂ , and ₁₁₃ .

FIG. 19 is a diagram showing a configuration example of the abnormality detection unit according to the third embodiment. As shown in FIG. 19, the abnormality detection unit 12B according to the third embodiment includes the comparators 44 and 45 and the determination unit 43B. The comparator 44 compares the detection signal Sd with the threshold value Is1, and outputs the comparison result. The comparator 45 compares the detection signal Sd with the threshold value Is2 and outputs the comparison result. The comparators 44 and 45 may be configured to be included in the input port.

When the detection signal Sd is equal to or higher than the threshold value Is1, the detection signal Sd is the above-mentioned plus level. When the detection signal Sd is less than the threshold value Is1 and greater than or equal to the threshold value Is2, the detection signal Sd is the above-mentioned zero level. When the detection signal Sd is less than the threshold value Is2, the detection signal Sd is the above-mentioned negative level. The determination unit 43B can detect whether or not the logic circuits 51 and 52 are abnormal based on the comparison results of the comparators 44 and 45 by using the same determination method as the determination unit 43.

The hardware configuration example of the first system unit 10B ₁ , the second system unit 10B ₂ , and the third system unit 10B ₃ according to the third embodiment is the first system unit 10 ₁ , the second system according to the first embodiment. It is the same as the unit 10 ₂ and the third system unit 10 ₃ . For example, the first system unit 10B ₁ , the second system unit 10B ₂ , and the third system unit 10B ₃ according to the third embodiment can have the same configuration as the hardware configuration shown in FIG. The processor 101 can execute the functions of the control unit 11 and the abnormality detection unit 12B by reading and executing the program stored in the memory 102.

As described above, the abnormality detection unit 12B of the control device 1B according to the third embodiment includes the comparators 44 and 45 and the determination unit 43B. The comparators 44 and 45 compare the detection signals Sd output from each of the three or more current detection units 40 with the threshold values Is1 and It2. The determination unit 43B determines whether or not there is an abnormality in the logic circuits 51 and 52 based on the comparison results of the comparators 44 and 45. As a result, the abnormality detection unit 12B does not need to be provided with the analog-digital converter 41 unlike the abnormality detection unit 12, so that the cost can be reduced.

Embodiment 4.
The fourth embodiment shows an example in which the control device 1 according to the first embodiment is applied to a substation of a railway. Instead of the control device 1 according to the first embodiment, the control device 1A according to the second embodiment or the control device 1B according to the third embodiment can be applied to a substation of a railway.

FIG. 20 is a diagram showing an example of the relationship between the control device arranged in the substation of the railway and the substation equipment according to the fourth embodiment of the present invention. As shown in FIG. 20, the railway substation 100 is provided with a plurality of substation facilities 3A ₁ , 3A ₂ , 3A ₃ , 3A ₄ , 3A ₅ , ..., _3An as the control target 3 described above. The substation equipment 3A ₁ , 3A ₂ , 3A ₃ , 3A ₄ , 3A ₅ , ..., _3An is controlled by the control device 1.

The substation equipment 3A ₁ , 3A ₂ , 3A ₃ , 3A ₄ , 3A ₅ , ..., _3An is, for example, a circuit breaker or a disconnector. For example, when the substation equipment 3A ₁ is the control target 31 ₁ described above and is a circuit breaker, the control lines 80, 81, 89 shown in FIG. 2 are connected to the substation equipment 3A ₁ . Then, when the control line 80 is connected to the control line 20 and the control line 89 is connected to the control line 24, the substation equipment 3A ₁ connects the electric circuit between the power transmission network of the electric power company and the substation equipment 3A ₂ . To. Further, in the substation equipment 3A ₁ , when the control line 81 is connected to the control line 20 and the control line 89 is connected to the control line 24, the electric circuit between the power transmission network of the electric power company and the substation equipment 3A ₂ is cut off. To.

Although the control device 1 is used in the substation 100 shown in FIG. 20, the substation 100 may have a configuration in which the control device 1A or the control device 1B is used instead of the control device 1. Further, the control devices 1, 1A and 1B may be provided in a power plant, another facility such as a factory, or the like instead of the substation of the railway.

The configuration shown in the above-described embodiment shows an example of the content of the present invention, can be combined with another known technique, and is one of the configurations as long as it does not deviate from the gist of the present invention. It is also possible to omit or change the part.

1,1A, 1B control device, 2 control power supply, 3,3 1,3 ₂ , ..., _{3 m} , 4,4 ₁ , ..., 4 _m Control target, 3A ₁ , 3A ₂ , 3A ₃ , 3A ₄ , 3A ₅ , ..., _3An substation equipment, 10 ₁ , 10A ₁ , 10B ₁ 1st system unit, 10 ₂ , 10A ₂ , 10B ₂ 2nd system unit, 10 ₃ , 10A ₃ , 10B _3rd 3 system unit, 11, 11 ₁ , 11 ₂ , 11 ₃ , 11A, 11A ₁ , 11A ₂ , 11A ₃ Control unit, 12, 12 ₁ , 12 ₂ , 12 ₃ , 12A, 12A ₁ , 12A ₂ , 12A ₃ , _12B , 12B ₁ , _{12B 2} , 12B _{3 Abnormality} detector, _{20,21,21 1,221,22,22 1,222,23,23 1,232,24,24 1,242,80} , 81, 89 control line, 30 ₁ , 30 ₂ switch group, 31, 32, 33 resistance, 40, 40 ₁ , 40 ₂ , 40 ₃ current detector, 41 analog digital converter, 42 processing unit, 43, 43B judgment unit , 44, 45 Comparator, 51, 51 ₁ , 51 ₂ , 51 ₃ , 51 ₄ , 51 ₅ , ..., 51 _n , 52, 52 ₁ , 52 ₂ , ..., 52 _n-1 , 52 _n Logic circuit, 53 switch section, 54 communication circuit, 55 switch drive circuit, 61, 61 ₁ , 621, 62, 62 ₁ , 62 ₂ , 63, 63 ₁ , 63 ₂ switch, 70 ₁ , 70 _{2 , 703} , 71 ₁ , 7 _{12 2} , 71 ₃ , 72 ₁ , 72 ₂ , 72 ₃ Connection line, 100 Substation, I1, I2, I3 Current, S11 ₁ to S11 _n , S21 ₁ to S21 _n , S31 ₁ to S31 _n , S12 ₁ to S12 _n , S22 ₁ to S22 _n , S32 ₁ to S32 _n Control signal, Sd, Sd1, Sd2, Sd3 detection signal, ΔI, ΔI ₂₁ , ΔI ₃₂ , ΔI ₁₃ current difference, ΔSd1, ΔSd2, ΔSd3 correction value.

Claims (7)

With three or more multiplexed controls,
Three or more control lines to which voltage is supplied from the control power supply,
The control line is a switch having two or more switches connected between the three or more control lines and a controlled object and controlled by two or more control units having different combinations of the three or more control units. The logic circuit that each has,
Three or more current detectors that detect the current difference between two control lines of different combinations of the three or more control lines, respectively.
An abnormality detection unit for detecting an abnormality in the logic circuit based on the three or more current differences detected by the three or more current detection units is provided .
Each of the three or more control units
At least one of the timing of turning off the corresponding switch and the timing of turning on the corresponding switch among the two or more switches for each control line is shifted from each other between the three or more control units, and the timing of at least one of the switches is shifted. Switch the order
A control device characterized by that. One or more of the logic circuits are provided corresponding to each of the plurality of controlled objects.
The three or more current detection units are arranged in the middle of the three or more control lines between the control power supply and the plurality of logic circuits.
The abnormality detection unit is
The control device according to claim 1, wherein an abnormality of a plurality of the logic circuits is detected based on the current detected by the three or more current detection units. The control device according to claim 1 or 2 , wherein a resistor is provided between the control power supply and the plurality of logic circuits in the middle of each of the three or more control lines. Each of the three or more current detectors
Any of claims 1 to 3 , wherein the currents flowing through the two control lines are attached to the two control lines in opposite directions, and a detection signal having a magnitude corresponding to the current difference is output. The control device described in one. The abnormality detection unit is
An analog-to-digital converter that converts the detection signals output from each of the three or more current detection units into digital signals.
A processing unit that corrects the current difference based on the digital signal output from the analog-digital converter, and a processing unit.
The control device according to any one of claims 1 to 4 , further comprising a determination unit for determining whether or not there is an abnormality in the logic circuit based on a correction result by the processing unit. The abnormality detection unit is
A comparator that compares the magnitude and threshold of the detection signal output from each of the three or more current detection units, and
The control device according to any one of claims 1 to 4 , further comprising a determination unit for determining whether or not there is an abnormality in the logic circuit based on the comparison result by the comparator. The abnormality detection unit is
The control device according to any one of claims 1 to 6 , wherein the control device is provided corresponding to each of the three or more control units.

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