JP7027970B2 - Semiconductor light receiving device, infrared detector - Google Patents

Description

The present invention relates to a semiconductor light receiving device and an infrared detecting device.

Non-Patent Document 1 discloses an infrared detector having a type II superlattice.

"Band engineered HOT mid wave infrared detectors based on type-II InAs / GaSb strained layer superlattices", Infrared Physics & Technology, ElSEVIER, 2013.

Infrared detectors with a Type II superlattice light absorption layer are used at low operating temperatures where dark currents can be reduced, such as 77 Kelvin. An infrared detector capable of operating at temperatures above 77 Kelvin reduces the cooling burden during operation.

One aspect of the present invention is to provide an infrared light receiving device capable of reducing the carrier level (dark current) detected during operation without light incident. Another aspect of the present invention is to provide an infrared detection device including an infrared light receiving device.

The semiconductor light receiving device according to one aspect of the present invention includes a support including an n-type semiconductor region, a barrier structure providing an electron barrier, a light absorbing layer containing a III-V compound semiconductor having a band gap sensitive to infrared rays, and a light absorbing layer. A mesa structure including a p-type semiconductor region and having an arrangement of semiconductor mesa provided on the support is provided, and the barrier structure includes a first spacer semiconductor layer, a first barrier layer, and a second spacer semiconductor layer. The p-type semiconductor region, the light absorption layer, the first spacer semiconductor layer, the first barrier layer, the second spacer semiconductor layer, and the n-type semiconductor region are arranged in the direction of the first axis. To.

The infrared detection device according to another aspect of the present invention includes a semiconductor light receiving device and a readout semiconductor device connected to the semiconductor light receiving device via a bump electrode.

The above object and other objects, features, and advantages of the invention will be more easily apparent from the following detailed description of preferred embodiments of the invention, which are advanced with reference to the accompanying drawings.

As described above, according to one aspect of the present invention, it is possible to provide a semiconductor light receiving device capable of reducing the carrier level (dark current) detected during operation without light incident. According to another aspect of the present invention, an infrared detection device including an infrared detection device can be provided.

Part (a) of FIG. 1 is a perspective view showing an infrared detection device according to the present embodiment. Part (b) of FIG. 1 is a plan view showing a semiconductor light receiving device according to the present embodiment. Part (a) of FIG. 2 shows the structure of the semiconductor light receiving device according to the present embodiment, and part (b) of FIG. 2 is a band diagram associated with the structure shown in part (a) of FIG. It is a drawing which shows. Part (c) of FIG. 2 is a drawing showing a semiconductor mesa of the semiconductor light receiving device shown in part (a) of FIG. FIG. 3 shows a band diagram provided by the semiconductor light receiving device according to the present embodiment. FIG. 4 is a drawing schematically showing a cross section taken along the IV-IV line shown in the part (a) of FIG. FIG. 5 is a drawing schematically showing a cross section taken along the VV line shown in the part (a) of FIG. FIG. 6 is a drawing schematically showing a cross section taken along the VI-VI line shown in the part (a) of FIG. 1. FIG. 7 is a drawing schematically showing a cross section taken along the line VII-VII shown in the part (a) of FIG. FIG. 8 is a drawing schematically showing the relationship between the electron barrier EB1 in the barrier structure in the semiconductor mesa and the voltage on the control electrode. Part (a) and part (b) of FIG. 9 are drawings schematically showing a semiconductor mesa and a band diagram in the mesa structure of the semiconductor light receiving device according to the experimental example. FIG. 10 is a drawing showing the dark current characteristics of the semiconductor light receiving device C and the semiconductor light receiving device D according to the experimental example. FIG. 11 is a drawing showing a dark current characteristic DC and an optical response characteristic PC of the semiconductor light receiving device D according to the experimental example. FIG. 12 is a drawing showing the time change of the applied voltage to the control electrode of the semiconductor light receiving device D and the applied voltage between the anode and the cathode in the measurement of FIG. 11. FIG. 13 is a drawing schematically showing a main step in the method for manufacturing the semiconductor light receiving device according to the present embodiment. FIG. 14 is a drawing schematically showing a main step in the method for manufacturing the semiconductor light receiving device according to the present embodiment. FIG. 15 is a drawing schematically showing a main step in the method for manufacturing the semiconductor light receiving device according to the present embodiment.

Some concrete examples will be described.

The semiconductor light receiving device according to the specific example is a light absorption including (a) a support including an n-type semiconductor region, (b) a barrier structure providing an electron barrier, and a III-V compound semiconductor having a band gap sensitive to infrared rays. The barrier structure includes a layer and a mesa structure including a p-type semiconductor region and having an arrangement of semiconductor mesa provided on the support, and the barrier structure includes a first spacer semiconductor layer, a first barrier layer, and a second barrier structure. The p-type semiconductor region, the light absorption layer, the first spacer semiconductor layer, the first barrier layer, the second spacer semiconductor layer, and the n-type semiconductor region include a spacer semiconductor layer in the direction of the first axis. Arranged in.

According to the semiconductor light receiving device, the narrow bandgap semiconductor in the semiconductor light receiving device generates electron-hole pairs by thermal excitation depending on the operating temperature. The electrons in the electron-hole pair go to the n-type semiconductor region. The first barrier layer is provided between the light absorption layer and the n-type semiconductor region, and provides a barrier against electrons toward the n-type semiconductor region. A certain amount of thermally excited electrons cannot overcome the electron barrier. This results in a reduction in dark current. The light absorption layer also produces photocarriers in the pn junction depletion layer in response to incident light. A certain amount of electrons in the optical carrier crosses the electron barrier of the first barrier layer to become a photocurrent and drifts to the n-type semiconductor region.

In the semiconductor light receiving device according to the specific example, the first spacer semiconductor layer and the second spacer semiconductor layer have p-conductivity and n-conductivity, respectively.

According to the semiconductor light receiving device, the first spacer semiconductor layer and the second spacer semiconductor layer having p-conductivity and n-conductivity, respectively, can provide a pn junction in the barrier structure. The first spacer semiconductor layer having a conductive type opposite to that of the conductive type of the second spacer semiconductor layer facilitates electron recombination that does not get over the first barrier layer.

In the semiconductor light receiving device according to the specific example, each of the semiconductor mesas includes the p-type semiconductor region, the light absorption layer, the first spacer semiconductor layer, and the first barrier layer.

According to the semiconductor light receiving device, the barrier structure can adjust the height of the electron barrier of the first barrier layer between the first spacer semiconductor layer and the second spacer semiconductor layer separately from the anode electrode and the cathode electrode. No electrodes are used.

The semiconductor light receiving device according to the specific example further includes a control electrode connected to the first spacer semiconductor layer, each of the semiconductor mesas includes the p-type semiconductor region and the light absorption layer, and each semiconductor mesa includes the p-type semiconductor region and the light absorption layer. It has a side surface that reaches the first spacer semiconductor layer.

According to the semiconductor light receiving device, a control electrode different from the anode electrode and the cathode electrode can be provided in the barrier structure. The control electrode is connected to the first spacer semiconductor layer, and an electric field corresponding to the potential difference between the control electrode and the cathode electrode can be applied to the barrier structure. By applying this electric field, the height of the electron barrier of the first barrier layer between the first spacer semiconductor layer and the second spacer semiconductor layer can be adjusted.

In the semiconductor light receiving device according to the specific example, the mesa structure has a groove defining the arrangement of the semiconductor mesa, and the semiconductor mesa has a side surface reaching the first spacer semiconductor layer. The control electrode makes contact with the first spacer semiconductor layer at the bottom of the groove.

According to the semiconductor light receiving device, the control electrode is connected to the first spacer semiconductor layer at the bottom of the groove.

The infrared detection device according to a specific example includes (a) a semiconductor light receiving device and (b) a readout semiconductor device connected to the semiconductor light receiving device via a bump electrode.

According to the infrared detection device, the carrier level detected during operation without light incident can be reduced.

The findings of the present invention can be readily understood by reference to the accompanying drawings shown as examples and taking into account the following detailed description. Subsequently, an embodiment relating to the infrared detection device, the semiconductor light receiving device, and the method for manufacturing the semiconductor light receiving device of the present invention will be described with reference to the accompanying drawings. When possible, the same parts are designated by the same reference numerals.

Part (a) of FIG. 1 is a perspective view showing an infrared detection device according to the present embodiment. Part (b) of FIG. 1 is a plan view showing a main part of the semiconductor light receiving device according to the present embodiment. The infrared detection device 10 includes a semiconductor light receiving device 11 and a read semiconductor device 12, and the read semiconductor device 12 is connected to the semiconductor light receiving device 11. The infrared detector 10 further includes an underfill 14 that fills the space between the semiconductor light receiving device 11 and the readout semiconductor device 12. The underfill 14 includes a resin body such as an epoxy resin.

The semiconductor light receiving device 11 includes a support 13 and a mesa structure 15. The mesa structure 15 includes an array ARY of semiconductor mesas 35 provided on the support 13. The support 13 includes a first region 13a and a second region 13b. The second region 13b is located outside the first region 13a. The first region 13a mounts the array ARY of the mesa structure 15, specifically the semiconductor mesa 35. With reference to the part (b) of FIG. 1, the positions of the individual semiconductor mesas 35 are represented by “P”.

Part (a) of FIG. 2 shows the structure of the semiconductor light receiving device according to the present embodiment, and part (b) of FIG. 2 is a band diagram associated with the structure shown in part (a) of FIG. It is a drawing which shows, and the part (c) of FIG. 2 is a drawing which shows the single semiconductor mesa in the semiconductor light receiving device shown in the part (a) of FIG.

As shown in parts (a), (b) and (c) of FIG. 2, the mesa structure 15, specifically the semiconductor mesa 35, is a barrier structure 19 that provides an electron barrier EB1 and is sensitive to infrared rays. It includes a light absorption layer 21 containing a III-V compound semiconductor having a bandgap, and a p-type semiconductor region 23. The light absorption layer 21 includes a III-V compound semiconductor capable of providing a bandgap capable of sensitive to infrared rays. The light absorption layer 21 can include a superlattice structure and / or a bulk semiconductor. The mesa structure 15 has a groove GV that defines the array ARY of the semiconductor mesa 35, and the groove GV is shown by a broken line in the portion (b) of FIG.

The barrier structure 19 provides an electron barrier EB1. The barrier structure 19 includes a first spacer semiconductor layer 25, a first barrier layer 27, and a second spacer semiconductor layer 29. In the semiconductor light receiving device 11, the p-type semiconductor region 23, the light absorption layer 21, the first spacer semiconductor layer 25, the first barrier layer 27, the second spacer semiconductor layer 29, and the n-type semiconductor region 17 are the first axis Ax1. Arranged in the direction.

According to the semiconductor light receiving device 11, the semiconductor with a narrow bandgap generates electron-hole pairs by thermal excitation depending on the operating temperature. The electrons in the electron-hole pair go to the n-type semiconductor region 17. The first barrier layer 27 is provided between the light absorption layer 21 and the n-type semiconductor region 17 and provides a barrier (EB1) for electrons toward the n-type semiconductor region 17. A certain amount of thermally excited electrons cannot overcome the electron barrier EB1. This results in a reduction in dark current. Further, the light absorption layer 21 generates optical carriers (E, H) in the depletion layer of the pn junction in response to the incident light LIN. A certain amount of electrons in the optical carrier crosses the electron barrier EB1 of the first barrier layer 27 to become a photocurrent and drifts to the n-type semiconductor region 17. The electronic barrier EB1 can be, for example, 100 to 300 meV.

The light absorption layer 21 includes a type II superlattice structure, and the type II superlattice structure includes a first semiconductor layer 21a and a second semiconductor layer 21b arranged alternately. Specifically, the light absorption layer 21 can have an InAs / GaSb superlattice. According to the InAs / GaSb superlattice of the light absorption layer 21, it can be provided that the semiconductor light receiving device 11 can exhibit the light detection ability in the infrared wavelength region (3 to 15 micrometers).

In this embodiment, the first spacer semiconductor layer 25 and the second spacer semiconductor layer 29 can have p-conductivity and n-conductivity, respectively. According to the semiconductor light receiving device 11, the first spacer semiconductor layer 25 and the second spacer semiconductor layer 29 having p-conductivity and n-conductivity, respectively, can provide a pn junction to the barrier structure 19, and the barrier structure 19 is a pn junction. Has a built-in potential associated with. The first spacer semiconductor layer 25, which has a conductive type opposite to that of the conductive type of the second spacer semiconductor layer 29, facilitates electron recombination that does not get over the first barrier layer 27.

The first barrier layer 27 includes a type II first superlattice structure SL1, which has an energy level BL27C in the conduction band higher than the energy level BL21C in the conduction band of the light absorption layer 21. The first spacer semiconductor layer 25 and the second spacer semiconductor layer 29 each have an energy level BL25C and an energy level BL29C in the conduction band. The energy level BL27C of the first barrier layer 27 is higher than the energy level BL25C and the energy level BL29C. The difference between the energy level BL27V in the valence band of the first barrier layer 27 and the energy level BL25V in the valence band of the first spacer semiconductor layer 25 is the energy level BL27C in the conduction band of the first barrier layer 27 and the first spacer semiconductor. It is smaller than the difference between the energy level of the conduction band of layer 25 and BL25C. The difference between the energy level BL27V of the valence band of the first barrier layer 27 and the energy level BL29V of the valence band of the second spacer semiconductor layer 29 is the energy level BL27C of the conduction band of the first barrier layer 27 and the second. It is smaller than the difference between the energy level of the conduction band of the spacer semiconductor layer 29 and the energy level BL29C.

Such band alignment is provided by the first spacer semiconductor layer 25, the first barrier layer 27, and the second spacer semiconductor layer 29, respectively, which have a superlattice structure. The first spacer semiconductor layer 25 can have a type II superlattice structure, and the superlattice structure of the first spacer semiconductor layer 25 includes an alternately arranged first semiconductor layer 25a and a second semiconductor layer 25b. .. Specifically, the first spacer semiconductor layer 25 can include, for example, a p-type InAs / GaSb superlattice structure, and the first barrier layer 27 can have a type II superlattice structure. The superlattice structure of the first barrier layer 27 includes a first semiconductor layer 27a and a second semiconductor layer 27b arranged alternately. Specifically, the superlattice structure of the first barrier layer 27 can include an InAs / GaSb superlattice. The InAs / GaSb superlattice can provide an electron barrier to the conduction band of the first barrier layer 27, and can provide a band structure to the first barrier layer 27 having substantially no potential barrier in the valence band. The second spacer semiconductor layer 29 can include a type II superlattice structure. The superlattice structure of the second spacer semiconductor layer 29 includes a first semiconductor layer 29a and a second semiconductor layer 29b arranged alternately. Specifically, the second spacer semiconductor layer 29 can include, for example, an n-type InAs / GaSb superlattice structure.

The semiconductor light receiving device 11 includes an anode electrode 31 and a cathode electrode 33. In this embodiment, the anode electrode 31 is connected to the p-type semiconductor region 23 in the semiconductor mesa 35 in the mesa structure 15. The cathode electrode 33 is connected to the n-type II superlattice structure of the mesa structure 15 or the n-type bulk layer of the support 13.

In this embodiment, the p-type semiconductor region 23 includes a p-type II superlattice structure 45 and a p-type cap layer 47. The superlattice structure of the p-type type II superlattice structure 45 includes a first semiconductor layer 45a and a second semiconductor layer 45b arranged alternately, and in this embodiment, the p-type cap layer 47 is made of a bulk semiconductor. The anode electrode 31 makes contact with the p-type cap layer 47 of the p-type semiconductor region 23.

Further, the semiconductor light receiving device 11 can include an n-type type II superlattice structure 49, and the superlattice structure of the n-type type II superlattice structure 49 includes a first semiconductor layer 49a and a second semiconductor arranged alternately. Includes layer 49b. The n-type semiconductor region 17 can include an n-type bulk layer, and the n-type bulk layer makes contact with the n-type type II superlattice structure 49. The cathode electrode 33 can be provided in either the n-type type II superlattice structure 49 or the n-type semiconductor region 17 of the support 13.

If necessary, the semiconductor light receiving device 11 may further include a control electrode 37 different from the anode electrode 31 and the cathode electrode 33. The control electrode 37 is connected to the first spacer semiconductor layer 25. The control electrode 37 provided to the barrier structure 19 is connected to the first spacer semiconductor layer 25, and an electric field corresponding to the potential difference between the control electrode 37 and the cathode electrode 33 can be applied to the barrier structure 19. By applying this electric field, the height of the electron barrier of the first barrier layer 27 between the first spacer semiconductor layer 25 and the second spacer semiconductor layer 29 can be adjusted. In this embodiment, the control electrode 37 is connected to the first spacer semiconductor layer 25 at the bottom of the groove GV.

Alternatively, the semiconductor light receiving device 11 may not include the control electrode 37 connected to the first spacer semiconductor layer 25. In the barrier structure 19, the band offset determined by the semiconductor material and the semiconductor structure of the first spacer semiconductor layer 25, the second spacer semiconductor layer 29, and the first barrier layer 27 is set with the first spacer semiconductor layer 25 and the second spacer semiconductor layer 29. It can be provided at each interface with the first barrier layer 27.

In this structure, the groove GV can have a bottom that reaches the first spacer semiconductor layer 25, the first barrier layer 27, the second spacer semiconductor layer 29, or the n-type type II superlattice structure 49. For example, each of the semiconductor mesas 35 includes a p-type semiconductor region 23, a light absorption layer 21, a first spacer semiconductor layer 25, and a first barrier layer 27, and includes a part or all of the second spacer semiconductor layer 29. Can be done.

If necessary, the semiconductor light receiving device 11 is a barrier layer provided between the light absorption layer 21 and the p-type semiconductor region 23 and at least one of the n-type semiconductor region 17 and the light absorption layer 21. Can be included. In this embodiment, the semiconductor light receiving device 11 can include a second barrier layer 41 and a third barrier layer 43. Specifically, the second barrier layer 41 is provided between the light absorption layer 21 and the p-type semiconductor region 23 to provide the electron barrier EB2. The third barrier layer 43 is provided between the n-type semiconductor region 17 and the barrier structure 19 and the light absorption layer 21 to provide a barrier against holes. The electron barrier EB1 of the first barrier layer 27 is lower than the electron barrier EB2 of the second barrier layer 41. The third barrier layer 43 has a hole barrier HB larger than the size of the electron barrier EB1 of the first barrier layer 27. The superlattice structure of the second barrier layer 41 includes a first semiconductor layer 41a and a second semiconductor layer 41b arranged alternately. The superlattice structure of the third barrier layer 43 includes a first semiconductor layer 43a and a second semiconductor layer 43b arranged alternately.

According to the semiconductor light receiving device 11, the second barrier layer 41 is provided with an electron barrier having an offset higher than that of the electron barrier EB1 of the first barrier layer 27. The low electron barrier EB17 of the first barrier layer 27 allows the photocurrent from the light absorption layer 21 to overcome the first barrier layer 27, while the high electron barrier EB2 of the second barrier layer 41 is p-type. The generation of dark current can be suppressed by preventing electrons, which are minority carriers diffused from the type II superlattice structure 45, from reaching the light absorption layer 21. Further, according to the semiconductor light receiving device 11, a hole barrier having an offset larger than the size of the electron barrier EB 17 of the first barrier layer 27 is provided to the third barrier layer 43. The high hole barrier HB of the third barrier layer 43 is dark by preventing holes, which are minority carriers diffused from the n-type type II superlattice structure 49 and the second spacer semiconductor layer 29, from reaching the light absorption layer 21. The generation of current can be suppressed.

The first spacer semiconductor layer 25 of the barrier structure 19 can have a thickness smaller than that of the light absorption layer 21. According to the semiconductor light receiving device 11, the first spacer semiconductor layer 25 can provide a region having a thin p-conductivity between the light absorption layer 21 and the n-type semiconductor region 17. The thin regions of p-conductivity can provide additional pn junctions to the barrier structure 19.

The first spacer semiconductor layer 25 of the barrier structure 19 can have a bandgap smaller than that of the light absorption layer 21. The bandgap first spacer semiconductor layer 25, which is smaller than the light absorption layer, facilitates the recombination of electrons accumulated in the first spacer semiconductor layer 25 without being able to overcome the first barrier layer 28.

Referring to the part (c) of FIG. 2, the support 13 includes a main surface 13c and a back surface 13d. The mesa structure 15 has an array ARY of semiconductor mesas 35 provided on the main surface 13c of the support 13. The support 13 and the semiconductor mesa 35 are arranged along the direction of the first axis Ax1. Each semiconductor mesa 35 includes a light absorption layer 21 and a p-type semiconductor region 23, and in this embodiment, includes a part of the first spacer semiconductor layer 25 of the barrier structure 19. Specifically, the semiconductor mesa 35 includes a second barrier layer 41 and a third barrier layer 43 in addition to the light absorption layer 21 and the p-type semiconductor region 23. In this embodiment, the p-type semiconductor region 23, the second barrier layer 41, the light absorption layer 21, and the third barrier layer 43 are arranged along the direction of the first axis Ax1.

The mesa structure 15 can have a terrace 53 in the semiconductor laminate, and the terrace 53 mounts the semiconductor mesa 35. The semiconductor mesa 35 has an upper surface 38a and a side surface 38b, and the side surface 38b extends from the upper surface 38a of the semiconductor mesa 35 to the bottom 38c of the semiconductor mesa 35 in the direction of the first axis Ax1.

The barrier structure 19 is provided on the semiconductor mesa 35 or the terrace 53. In this embodiment, the semiconductor mesa 35 may include a portion of the barrier structure 19 and the terrace 53 may include the rest of the barrier structure 19.

Specifically, the semiconductor mesa 35 may include a part of the first spacer semiconductor layer 25, and the terrace 53 may include the rest of the first spacer semiconductor layer 25, the first barrier layer 27, and the second spacer semiconductor layer 29. The control electrode 37 can be provided on the terrace 53 and can make contact with the first spacer semiconductor layer 25. The cathode electrode 33 can be provided outside the array ARY of the semiconductor mesas 35.

Alternatively, the semiconductor mesa 35 can include a part of the first spacer semiconductor layer 25, the first barrier layer 27, and the second spacer semiconductor layer 29 of the barrier structure 19, and the terrace 53 is the second spacer semiconductor layer 29. Can include the rest. The control electrode 37 is not provided on the semiconductor light receiving device 11. The cathode electrode 33 can be provided on the terrace 53 and can make contact with the second spacer semiconductor layer 29.

If necessary, the terrace 53 may not be provided on the semiconductor light receiving device 11. The semiconductor mesa 35 includes all of the barrier structure 19, and the control electrode 37 is not provided on the semiconductor light receiving device 11.

The semiconductor light receiving device 11 may include a protective film 48 that covers the semiconductor mesa 35. The protective film 48 can cover the terrace 53. The anode electrode 31, the cathode electrode 33 and the control electrode 37 make contact with the semiconductor through the opening of the protective film 48.

As described above, the first barrier layer 27, the first spacer semiconductor layer 25, and the second spacer semiconductor layer 29 can have a type II superlattice structure. The superlattice structure of the first spacer semiconductor layer 25 has an energy difference smaller than the energy difference between the conduction band and the valence band related to carrier conduction in the light absorption layer, and the band structure (conduction band and valence band) of the first spacer semiconductor layer 25. Can be provided to the band). According to the semiconductor light receiving device 11, the bandgap first spacer semiconductor layer smaller than the light absorption layer 21 facilitates the recombination of electrons accumulating the first barrier layer 27.

The superlattice structure of the second spacer semiconductor layer 29 has an energy difference larger than the energy difference between the conduction band and the valence band related to carrier conduction in the superlattice structure of the first spacer semiconductor layer 25, and the band of the second spacer semiconductor layer 29. It can be provided to the structure (conduction band and valence band). According to the semiconductor light receiving device 11, the superlattice structure of the first spacer semiconductor layer 25 can form a band gap smaller than that of the light absorption layer. The second spacer semiconductor layer 29, which has a band gap larger than that of the first spacer semiconductor layer 25, facilitates adjustment of the width of the depletion layer in the barrier structure 19.

The energy difference between the conduction band and the valence band related to carrier conduction in the superlattice structure of the second spacer semiconductor layer 29 is based on the energy difference between the conduction band and the valence band related to carrier conduction in the superlattice structure of the first barrier layer 27. It may be small and larger than the energy difference larger than the energy difference between the conduction band and the valence band related to carrier conduction in the superlattice structure of the first spacer semiconductor layer 25. Further, the first spacer semiconductor layer 25 can have a carrier concentration larger than the carrier concentration of the second spacer semiconductor layer 29, and this concentration difference makes it possible to spread the depletion layer to the second spacer semiconductor layer 29. ..

An example of the semiconductor light receiving device 11.
Base BS of support 13: n-type GaSb substrate.
N-type semiconductor region 17 of the support 13: n-type GaSb epitaxial layer (500 nm thickness, 1 to 3 × 10 ¹⁸ cm ^-3 ).
Semiconductor mesa 35 of the mesa structure 15.
n-type type II superlattice structure 49: n-type InAs / GaSb superlattice (350 nm thickness, 1 × 10 ¹⁸ cm ^-3 ).
Barrier structure 19.
First spacer semiconductor layer 25: p-type InAs / GaSb superlattice (300 nm thickness, 1-2 × 10 ¹⁸ cm ^-3 ).
First barrier layer 27: p-type InAs / GaSb superlattice (60 nm thickness, 0.1 to 1 × 10 ¹⁶ cm ^-3 ).
Second spacer semiconductor layer 29: n-type InAs / GaSb superlattice (160 nm thickness, 0.1 to 1 × 10 ¹⁶ cm ^-3 ).
Third barrier layer 43 (hole barrier layer): n-type InAs / GaSb superlattice (300 nm thickness, 1-2 × 10 ¹⁶ cm ^-3 ).
Light absorption layer 21: p-type InAs / GaSb superlattice (1000 nm thickness, 0.1 to 1 × 10 ¹⁶ cm ^-3 ).
Second barrier layer 41 (electron barrier layer): undoped InAs / GaSb superlattice (thickness of 300 nm).
P-type semiconductor region 23.
p-type type II superlattice structure 45: p-type InAs / GaSb superlattice (250 nm thickness, 1-2 × 10 ¹⁷ cm ^-3 ).
p-type cap layer 47: p-type GaSb bulk (200 nm thickness, 1-3 × 10 ¹⁸ cm ^-3 ).
Protective film 48; Silicon-based inorganic insulating film (SiO ₂ , 100 to 300 nm thick).

FIG. 3 shows a band diagram provided by a semiconductor light receiving device. FIG. 3 shows the conduction band CB, the valence band VD, and the Fermi level EF in the semiconductor mesa 35 and the support 13 of the mesa structure 15. The conduction band CB and the valence band VD are the electron level and the hole level provided by the superlattice structure, respectively, except for the bulk layer (n-type semiconductor region 17 and p-type cap layer 47 in this embodiment). Is shown.

The light absorption layer 21 is located between the second barrier layer 41 (electron barrier layer) and the third barrier layer 43 (hole barrier layer). The light absorption layer 21 and the third barrier layer 43 (hole barrier layer) are located between the second barrier layer 41 (electron barrier layer) and the barrier structure 19. The electron barrier EB1 of the first barrier layer 27 of the barrier structure 19 can be about 300 meV. The electron barrier of the second barrier layer 41 (electron barrier layer) is larger than the electron barrier EB1 and can be about 100 to 200 meV. The hole barrier of the third barrier layer 43 (hole barrier layer) is larger than the electron barrier EB1 and can be about 100 to 200 meV.

FIG. 4 is a drawing schematically showing a cross section taken along the IV-IV line shown in the part (a) of FIG. FIG. 5 is a drawing schematically showing a cross section taken along the VV line shown in the part (a) of FIG. FIG. 6 is a drawing schematically showing a cross section taken along the VI-VI line shown in the part (a) of FIG. 1. FIG. 7 is a drawing schematically showing a cross section taken along the line VII-VII shown in the part (a) of FIG. Referring to FIGS. 4 to 7, the readout semiconductor device 12 is connected to the semiconductor light receiving device 11 via the bump electrode 16. The read semiconductor device 12 includes a read circuit 12a, an anode / cathode power supply circuit 12b, and a control voltage power supply circuit 12c corresponding to each semiconductor mesa 35. The read circuit 12a is connected to the anode electrode 31 via the bump electrode 16. The anode / cathode power supply circuit 12b is connected to the cathode electrode 33 via the bump electrode 16. The control voltage power supply circuit 12c is connected to the control electrode 37 via the bump electrode 16.

Referring to FIGS. 4, 5, 6 and 7, the anode electrode 31 is provided on the upper surface of each semiconductor mesa 35. In the mesa structure 15, the arrangement of the semiconductor mesas 35 is defined by the groove GV. The spacing between the semiconductor mesas 35, eg, the width of the groove GV, can be, for example, 2-4 micrometers. In this embodiment, the groove GV has a bottom in the first spacer semiconductor layer 25. The groove GV may reach the first spacer semiconductor layer 25, the first barrier layer 27, the second spacer semiconductor layer 29, or the n-type type II superlattice structure 49.

Referring to part (b) of FIG. 1 and FIG. 4, the mesa structure 15 can have a semiconductor structure 55 such as a semiconductor wall or a semiconductor column. The semiconductor structure 55 is provided outside the array ARY of the semiconductor mesas 35, and protrudes in the direction of the first axis Ax1. The control electrode 37 is connected to the first spacer semiconductor layer 25 at the bottom of the groove GV and extends so as to reach the upper surface of the semiconductor structure 55. In this embodiment, the semiconductor structure 55 includes a semiconductor mesa 35, and the upper surface and side surfaces of the semiconductor structure 55 are covered with a protective film 48.

Referring to part (b) of FIG. 1 and FIG. 5, the mesa structure 15 can have another semiconductor structure 57 such as a semiconductor wall or a semiconductor column. The semiconductor structure 57 is provided outside the array ARY of the semiconductor mesas 35, and protrudes in the direction of the first axis Ax1. The upper surface and the side surface of the semiconductor structure 57 are covered with the protective film 48. The control electrode 37 is connected to the first spacer semiconductor layer 25 at the bottom of the groove GV and extends so as to reach the upper surface of the semiconductor structure 57.

Referring to part (b) of FIG. 1, FIGS. 4, 5, 6 and 7, the semiconductor light receiving device 11 can include an outer semiconductor structure 59 separated from the mesa structure 15. The outer semiconductor structure 59 is provided on the outside of the mesa structure 15 and projects in the direction of the first axis Ax1. The upper surface and the side surface of the outer semiconductor structure 59 are covered with the protective film 48. In this embodiment, the semiconductor light receiving device 11 further includes an outer groove 61, which can separate the outer semiconductor structure 59 from the mesa structure 15 and reach the n-type type II superlattice structure 49. .. The cathode electrode 33 makes contact with the bottom surface of the outer groove 61 in the second region 13b. Specifically, the cathode electrode 33 can make contact with the second region 13b outside the outer semiconductor structure 59, or the cathode electrode 33 contacts the second spacer semiconductor layer 29 at the bottom of the outer groove 61. The cathode electrode 33 can extend so as to reach the upper surface of at least one of the semiconductor structure 57 and the outer semiconductor structure 59. The width of the outer groove 61 can be, for example, 100 micrometers. The outer groove 61 is, for example, 0.5 to 1.0 micrometer deeper than the groove GV.

FIG. 8 schematically shows the relationship between the electron barrier EB1 in the barrier structure 19 and the voltage on the control electrode in each semiconductor mesa 35. The first spacer semiconductor layer 25 receives a negative voltage with respect to the potential of the n-type type II superlattice structure 49. The electron barrier EB1 of the first barrier layer 27 becomes lower as the applied voltage increases.
Characteristic line, voltage applied to the control electrode 37 (V).
C1, zero.
C2, 150 mV (this bias can be changed in the range of 50-150 mV on demand).
C3, 300 mV (this bias can be changed in the range of 150-300 mV on demand).
"BVin" represents the built-in potential.

The parts (a) and (b) of FIG. 9 are drawings schematically showing the semiconductor mesa and the band diagram in the mesa structure of the experimental example. With reference to the parts (a) and (b) of FIG. 9, the semiconductor light receiving device C and the semiconductor light receiving device D are shown. The main power supply PS1 is connected between the anode and the cathode. The additional power supply PS2 is connected between the cathode electrode 33 and the control electrode 37. The additional power supply PS2 can change the electronic barrier of the first barrier layer 27.

The structure of the semiconductor light receiving device C shown in the part (a) of FIG.
Mesa structure 1.
n-type type II superlattice structure 2: n-type InAs / GaSb superlattice (350 nm thickness, 1 × 10 ¹⁸ cm ^-3 ).
Hole barrier layer 3: n-type InAs / GaSb superlattice (300 nm thickness, 1-2 × 10 ¹⁶ cm ^-3 ).
Light absorption layer 4: p-type InAs / GaSb superlattice (1000 nm thickness, 0.1 to 1 × 10 ¹⁶ cm ^-3 ).
Electronic barrier layer 5: Undoped InAs / GaSb superlattice (300 nm thickness).
P-type semiconductor region.
p-type type II superlattice structure 6: p-type InAs / GaSb superlattice (250 nm thickness, 1-2 × 10 ¹⁷ cm ^-3 ).
p-type cap layer 7: p-type GaSb bulk (200 nm thickness, 1 to 3 × 10 ¹⁸ cm ^-3 ).

The structure of the semiconductor light receiving device D shown in the part (b) of FIG.
Mesa structure 15.
n-type type II superlattice structure 49: n-type InAs / GaSb superlattice (350 nm thickness, 1 × 10 ¹⁸ cm ^-3 ).
Barrier structure 19.
First spacer semiconductor layer 25: p-type InAs / GaSb superlattice (300 nm thickness, 1 × 10 ¹⁸ cm ^-3 ).
First barrier layer 27: p-type InAs / GaSb superlattice (60 nm thickness, 0.1 to 1 × 10 ¹⁶ cm ^-3 ).
Second spacer semiconductor layer 29: n-type InAs / GaSb superlattice (160 nm thickness, 1 × 10 ¹⁶ cm ^-3 ).
Third barrier layer 43: n-type InAs / GaSb superlattice (300 nm thickness, 1 × 10 ¹⁶ cm ^-3 ).
Light absorption layer 21: p-type InAs / GaSb superlattice (1000 nm thickness, 0.1 × 10 ¹⁶ cm ^-3 ).
Second barrier layer 41: undoped InAs / GaSb superlattice (300 nm thickness).
P-type semiconductor region 23.
p-type type II superlattice structure 45: p-type InAs / GaSb superlattice (250 nm thickness, 1-2 × 10 ¹⁷ cm ^-3 ).
p-type cap layer 47: p-type GaSb bulk (200 nm thickness, 1-3 × 10 ¹⁸ cm ^-3 ).

FIG. 10 shows the dark current characteristics of the semiconductor light receiving device C and the semiconductor light receiving device D. The horizontal axis shows the voltage between the anode and the cathode, and the vertical axis shows the current density of the measured current. Further, in the semiconductor light receiving device D, the voltage applied to the control electrode is zero (zero bias condition in the additional power supply PS2). In FIG. 10, “C77” indicates the dark current characteristic of the semiconductor light receiving device C at an absolute temperature of 77 Kelvin. “D77”, “D150” and “D210” indicate the dark current characteristics of the semiconductor light receiving device D at absolute temperatures of 77 Kelvin, 150 Kelvin and 210 Kelvin, respectively. The dark current characteristic of the semiconductor light receiving device D is superior to the dark current characteristic (absolute temperature 77 Kelvin) of the semiconductor light receiving device C in the temperature range of 77 to 210 Kelvin.

FIG. 11 shows the dark current characteristic DC and the optical response characteristic PC of the semiconductor light receiving device D. The horizontal axis shows the voltage between the anode and the cathode, and the vertical axis shows the current density of the measured current. In FIG. 11, dark current characteristics and optical response characteristics are measured at an absolute temperature of 77 Kelvin. Further, "GF", "GH" and "GC" indicate dark current characteristic DC and optical response characteristic PC at applied voltages of −0.5, −0.3 and 0.0V to the control electrode, respectively. The semiconductor light receiving device D can reduce the level of dark commutation according to the voltage applied to the control electrode. Further, the semiconductor light receiving device D can output a photocurrent in response to an optical input at a reduced dark current level (voltage applied to the control electrode).

FIG. 12 shows the time change of the applied voltage (VCNT) to the control electrode of the semiconductor light receiving device D and the applied voltage (VOUT) between the anode and the cathode in the measurement of FIG.
Voltage applied between the anode and cathode by the main power supply PS1 (VOUT): -1.0 volt (continuous application).
Voltage applied to the control electrode 37 by the additional power supply PS2 (VCNT): -0.3 volts (pulse applied).
High duration of pulse (TH): 1 microsecond to 1 millisecond.
Pulse Row Period (TL): 1 nanosecond to 1 microsecond.

As described above, according to the present embodiment, the barrier structure 19 can reduce the dark current detected during operation without light incident in the semiconductor light receiving device depending on the presence / absence and magnitude of the control voltage.

A method of manufacturing the semiconductor light receiving device 11 will be described with reference to FIGS. 13, 14 and 15. Where possible, reference numerals used in the description of the semiconductor light receiving device 11 are used for ease of understanding.

As shown in part (a) of FIG. 13, an epitaxial film for the mesa structure 15 is grown on the GaSb wafer 71 by the molecular beam epitaxy method to prepare an epitaxial substrate EP. Specifically, a semiconductor laminate 73 including the following semiconductor film is formed on a GaSb wafer 71: an n-type InAs / GaSb superlattice 73a for an n-type type II superlattice structure 49, a second spacer semiconductor layer 29. N-type InAs / GaSb superlattice 73b for the first barrier layer 27, p-type InAs / GaSb superlattice 73c for the first barrier layer 27, p-type InAs / GaSb superlattice 73d for the first spacer semiconductor layer 25, third barrier layer. N-type InAs / GaSb superlattice 73e for 43, p-type InAs / GaSb superlattice 73f for light absorption layer 21, undoped InAs / GaSb superlattice 73g for second barrier layer 41, p-type type II superlattice A p-type InAs / GaSb superlattice 73h for the lattice structure 45 and a p-type GaSb film 73i for the p-type cap layer 47. If necessary, the GaSb bulk layer can be grown on the GaSb wafer 71 prior to the above growth.

As shown in the portion (a) of FIG. 13, the insulating film mask M1 that defines the mesa is formed on the semiconductor laminate 73. As shown in the portion (b) of FIG. 13, the semiconductor laminate is etched using the insulating film mask M1 to form an array ARY of the semiconductor mesas 35. After etching, the insulating film mask M1 is removed.

As shown in the part (a) of FIG. 14, the insulating film mask M2 formed so as to cover the semiconductor mesa 35 is formed. As shown in the portion (b) of FIG. 14, the semiconductor laminate 73 is etched with the insulating film mask M2 to form the terrace 53.

As shown in part (a) of FIG. 15, a silicon-based inorganic insulating film 75 (for example, a SiN film by a chemical vapor deposition method) is deposited on the semiconductor mesa 35 and the terrace 53. As shown in part (b) of FIG. 15, an opening for the anode electrode 31 and the cathode electrode 33 (control electrode 37 if necessary) is formed in the silicon-based inorganic insulating film 75 by photolithography and etching. At the same time, the metal film for metallization is deposited on the silicon-based inorganic insulating film 75 to form the anode electrode 31, the cathode electrode 33 and the control electrode 37. By these steps, the semiconductor light receiving device 11 can be manufactured.

Although the principles of the invention have been illustrated and demonstrated in preferred embodiments, it will be appreciated by those skilled in the art that the invention may be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in this embodiment. Therefore, we claim all amendments and changes that come from the scope of the claims and their spirit.

As described above, according to the present embodiment, it is possible to provide an infrared detection device capable of reducing the carrier level (dark current) detected during operation without light incident.

11 ... semiconductor light receiving device, 13 ... support, 15 ... mesa structure, 17 ... n-type semiconductor region, 19 ... barrier structure, 21 ... light absorption layer, 23 ... p-type semiconductor region, 25 ... first spacer semiconductor layer, 27 ... 1st barrier layer, 29 ... 2nd spacer semiconductor layer, Ax1 ... 1st axis.

Claims (5)

It is a semiconductor light receiving device
A support containing an n-type semiconductor region and
A mesa comprising a barrier structure providing an electron barrier, a light absorbing layer containing a III-V compound semiconductor having a bandgap sensitive to infrared rays, and a p-type semiconductor region, and comprising an array of semiconductor mesa provided on the support. Structure and
Equipped with
The barrier structure includes a first spacer semiconductor layer, a first barrier layer and a second spacer semiconductor layer.
The p-type semiconductor region, the light absorption layer, the first spacer semiconductor layer, the first barrier layer, the second spacer semiconductor layer, and the n-type semiconductor region are arranged in the direction of the first axis.
The semiconductor light receiving device further includes a control electrode connected to the first spacer semiconductor layer.
Each of the semiconductor mesas includes the p-type semiconductor region and the light absorption layer, and each semiconductor mesa is a semiconductor light receiving device having a side surface reaching the first spacer semiconductor layer . The semiconductor light-receiving device according to claim 1, wherein the first spacer semiconductor layer and the second spacer semiconductor layer have p-conductivity and n-conductivity, respectively. The semiconductor light-receiving device according to claim 1 or 2, wherein each of the semiconductor mesas includes the p-type semiconductor region, the light absorption layer, the first spacer semiconductor layer, and the first barrier layer. The mesa structure has a groove that defines the arrangement of the semiconductor mesas.
The semiconductor mesa has a side surface that reaches the first spacer semiconductor layer.
The semiconductor light-receiving device according to claim 1 or 2 , wherein the control electrode makes contact with the first spacer semiconductor layer at the bottom of the groove. It ’s an infrared detector,
The semiconductor light receiving device according to any one of claims 1 to 4 .
A read semiconductor device connected to the semiconductor light receiving device via a bump electrode,
Infrared detector.

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