JP7004937B2 - Optimization device, optimization device control method, and optimization device control program - Google Patents

Description

The present invention relates to an optimization device, a control method of the optimization device, and a control program of the optimization device.

As a method of solving a multivariable optimization problem that Neumann computers are not good at, there is an optimization device using an Ising-type energy function (sometimes called an Ising machine or a Boltzmann machine). The optimizer replaces the problem to be calculated with the Ising model, which is a model representing the spin behavior of a magnetic material, and calculates.

The optimizer can also be modeled using, for example, a neural network. In that case, each of the multiple bits (spin bits) corresponding to the multiple spins included in the Ising model has a weighting coefficient (also called a coupling coefficient) indicating the magnitude of the interaction between the other bit and its own bit. Functions as a neuron that outputs 0 or 1 depending on the. The optimizer obtains the minimum value (called energy) of the energy function (also called cost function or objective function) as described above by a stochastic search method such as simulated annealing for each bit. Find the combination of values as a solution.

For example, there is a proposal of a semiconductor system for searching the ground state of the Ising model using a semiconductor chip equipped with a plurality of unit elements corresponding to spins. In the proposed semiconductor system, in order to realize a semiconductor chip capable of dealing with a large-scale problem, a plurality of semiconductor chips equipped with a certain number of unit elements are used for construction.

International Publication No. 2017/037903

In the optimizer, the number of spin bits used (corresponding to the scale of the problem) and the number of bits of the weighting factor (corresponding to the accuracy of the conditional expression in the problem) may change depending on the problem to be solved. For example, in a problem in a certain field, the number of spin bits may be relatively large, and the number of bits of the weighting factor may be relatively small. On the other hand, in problems in other fields, the number of spin bits may be relatively small, but the number of weight coefficient bits may be relatively large. However, it is inefficient to manufacture an optimization device having the number of spin bits and the number of weighting coefficient bits suitable for each problem individually for each problem.

In one aspect, it is an object of the present invention to provide an optimizer, a control method for the optimizer, and a control program for the optimizer, which can vary in scale and accuracy.

In one aspect, an optimization device is provided. The optimization device has a storage unit, a plurality of bit operation circuits, a selection circuit unit, and a setting change unit. The storage unit stores a coefficient indicating the magnitude of the interaction between the bits in the bit string representing the state of the Ising model. In each of the plurality of bit arithmetic circuits, when any bit in the bit string is inverted, the energy change of the Ising model is calculated using the coefficient corresponding to the inverted bit read from the storage unit and its own bit. A signal indicating whether or not the own bit can be inverted is output according to the above. The selection circuit unit outputs a signal indicating the bit to be inverted among the selected bit strings based on the signal indicating whether or not the inversion is possible output from each of the bit operation circuits having the first number of bits of the bit string among the plurality of bit operation circuits. It is output to each of the bit operation circuits having the first number of bits. The setting change unit changes the number of first bits for the selection circuit unit and changes the number of second bits of the coefficient for each of the bit operation circuits having the first number of bits.

Also, in one aspect, an optimization device is provided. The optimization device has an input unit, a conversion unit, a control unit, and a display unit. The input unit inputs the problem to be solved and the operating conditions. The conversion unit converts the input problem into a search problem in the base state of the search problem, scale information indicating the scale of the search problem, accuracy information indicating the accuracy of the expression of the search problem, and the initial value of the energy of the search problem. The energy information representing the above and the scale accuracy mode information according to the scale and accuracy are generated. The control unit inputs scale information, accuracy information, energy information, operating conditions, and scale accuracy mode information, executes an operation for searching the ground state, and outputs a solution. The display unit displays the solution obtained as a result of the search for the ground state by the control unit.

Also, in one aspect, a method of controlling the optimizer is provided.
Also, in one aspect, a control program for the optimizer is provided.

On one side, scale and accuracy can be variable.
The above and other objects, features and advantages of the invention will be apparent by the following description in connection with the accompanying drawings representing preferred embodiments of the invention.

It is a figure which shows the optimization apparatus of 1st Embodiment. It is a figure which shows the example of the information processing system of the 2nd Embodiment. It is a block diagram which shows the hardware example of an information processing apparatus. It is a figure which shows the example of the relationship of hardware in an information processing system. It is a block diagram which shows the hardware example of a control part. It is a figure which shows the example of the combinatorial optimization problem. It is a figure which shows the search example of the binary value which becomes the minimum energy. It is a figure which shows the circuit configuration example of the optimization apparatus. It is a figure which shows the circuit configuration example of a random selector part. It is a figure which shows the example of the trade-off relationship between scale and accuracy. It is a figure which shows the storage example (the 1) of the weighting coefficient. It is a figure which shows the storage example (the 2) of the weighting coefficient. It is a figure which shows the storage example (the 3) of the weighting coefficient. It is a figure which shows the storage example (the 4) of the weighting coefficient. It is a flowchart which shows the example of the initialization process. It is a flowchart which shows the example of the arithmetic processing. It is a figure which shows the storage example (the 5) of the coupling coefficient. It is a figure which shows the example of the optimization apparatus of the 3rd Embodiment. It is a figure which shows the circuit configuration example of LFB. It is a figure which shows the circuit structure example of the scale coupling circuit. It is a figure which shows the example of the required range of scale / accuracy for each problem. It is a figure which shows the example of the selectable range of scale accuracy. It is a figure which shows the example of the use pattern of LFE. It is a figure which shows the example of the utilization flow of the optimization apparatus.

Hereinafter, the present embodiment will be described with reference to the drawings.
[First Embodiment]
The first embodiment will be described.

FIG. 1 is a diagram showing an optimization device according to the first embodiment.
In the optimization device 1, the energy function is the minimum value among the combinations (states) of the values of the plurality of bits (spin bits) corresponding to the plurality of spins included in the Ising model obtained by transforming the problem to be calculated. Search for the value (ground state) of each bit at the time.

The Ising-type energy function E (x) is defined by, for example, the following equation (1).

The first term on the right-hand side is the sum of the products of the two bit values (0 or 1) and the coupling coefficient for all combinations of the two bits that can be selected from all the bits included in the Ising model, without omission or duplication. Is. The total number of bits included in the Ising model is K (K is an integer of 2 or more). Further, each of i and j is an integer of 0 or more and K-1 or less. x _i is a variable (also called a state variable) representing the value of the i-th bit. x _j is a variable representing the value of the jth bit. W _ij is a weighting coefficient indicating the magnitude of the interaction between the i-th and j-th bits. In addition, _Wii = 0. In addition, W _ij = W _ji in many cases (that is, the coefficient matrix based on the weighting coefficient is often a symmetric matrix).

The second term on the right-hand side is the sum of the products of the bias coefficients of all the bits and the values of the bits. b _i indicates the bias coefficient of the i-th bit.
Further, when the value of the variable x _i changes to 1-x _i , the increase of the variable x _i can be expressed as Δx _i = (1-x _i ) −x _i = 1-2x _i . Therefore, the energy change ΔE _i accompanying the spin inversion (change in value) is expressed by the following equation (2).

_hi is called a local field and is expressed by the equation (3).

The energy change ΔE _i is obtained by multiplying the local field h _i by a code (+1 or -1) according to Δx _i . The change Δh _i of the local field h _i is expressed by the equation (4).

The process of updating the local field h _i when a certain variable x _j changes is performed in parallel.
The optimization device 1 is, for example, a one-chip semiconductor integrated circuit, and is realized by using an FPGA (Field Programmable Gate Array) or the like. The optimization device 1 includes bit operation circuits 1a1, ..., 1aK, ..., 1aN (a plurality of bit operation circuits), a selection circuit unit 2, a threshold value generation unit 3, a random number generation unit 4, a setting change unit 5, and a control unit 6. Have. Here, N is the total number of bit operation circuits included in the optimization device 1. N is an integer greater than or equal to K. Identification information (index = 0, ..., K-1, ..., N-1) is associated with each of the bit operation circuits 1a1, ..., 1aK, ..., 1aN.

The bit operation circuits 1a1, ..., 1aK, ..., 1aN are unit elements that provide one bit included in a bit string representing the state of the Ising model. The bit string may be called a spin bit string, a state vector, or the like. Each of the bit operation circuits 1a1, ..., 1aK, ..., 1aN stores the weighting coefficient between the own bit and the other bit, and determines whether or not the own bit can be inverted according to the inversion of the other bit based on the weighting coefficient. , A signal indicating whether or not the own bit can be inverted is output to the selection circuit unit 2.

The selection circuit unit 2 selects a bit (inverted bit) to be inverted from the spin bit strings. Specifically, the selection circuit unit 2 outputs from each of the bit operation circuits 1a1, ..., 1aK, ..., 1aN used for searching the ground state of the Ising model among the bit operation circuits 1a1, ..., 1aK, ..., 1aN. Accepts the inversion enable / disable signal. The selection circuit unit 2 preferentially selects one bit corresponding to the bit operation circuit that outputs the inverting signal from the bit operation circuits 1a1, ..., 1aK, and uses it as an inversion bit. For example, the selection circuit unit 2 selects the inverting bit based on the random number bit output by the random number generation unit 4. The selection circuit unit 2 outputs a signal indicating the selected inverting bit to the bit calculation circuits 1a1, ..., 1aK. The signal indicating the inversion bit includes the identification information of the inversion bit (index = j), the flag indicating whether or not the inversion is possible (flg _j = 1), and the current value q _j of the inversion bit (the value before the inversion this time). Includes the indicated signal. However, none of the bits may be inverted. If neither bit is inverted, the selection circuit unit 2 outputs flg _j = 0.

The threshold value generation unit 3 generates a threshold value used for determining whether or not the bit can be inverted for each of the bit calculation circuits 1a1, ..., 1aK, ..., 1aN. A signal indicating the threshold value is output to each of the bit operation circuits 1a1, ..., 1aK, ..., 1aN. As will be described later, the threshold value generation unit 3 uses a parameter (temperature parameter) T indicating a temperature and a random number to generate the threshold value. The threshold value generation unit 3 has a random number generator that generates the random number. It is preferable that the threshold value generation unit 3 has a random number generator individually for each of the bit calculation circuits 1a1, ..., 1aK, ..., 1aN, and individually generates and supplies the threshold value. However, the threshold generation unit 3 may share a random number generator with a predetermined number of bit operation circuits.

The random number generation unit 4 generates random number bits and outputs them to the selection circuit unit 2. The random number bits generated by the random number generation unit 4 are used for selection of the inverting bit by the selection circuit unit 2.
The setting changing unit 5 changes the first bit number (spin bit number) of the bit string (spin bit string) representing the state of the Ising model to be calculated among the bit calculation circuits 1a1, ..., 1aK, ..., 1aN. .. Further, the setting changing unit 5 changes the number of second bits of the weighting coefficient for each of the bit arithmetic circuits having the first number of bits.

The control unit 6 sets the weighting coefficient for each storage unit of the temperature parameter T and the bit calculation circuits 1a1, ..., 1aN, and controls the start and end of the calculation by the bit calculation circuits 1a1, ..., 1aN. The control unit 6 outputs the calculation result. For example, when the operation using the bit operation circuits 1a1, ..., 1aK is completed, the control unit 6 reads out and outputs the spin bit strings held in the bit operation circuits 1a1, ..., 1aK.

Next, the circuit configuration of the bit operation circuit will be described. The bit operation circuit 1a1 (index = 0) will be mainly described, but other bit operation circuits can be realized by the same circuit configuration (for example, in the Xth (X is an integer of 1 or more and N or less) bit operation circuit). On the other hand, index = X-1 may be set).

The bit calculation circuit 1a1 includes a storage unit 11, an accuracy switching circuit 12, an inversion determination unit 13, a bit holding unit 14, an energy change calculation unit 15, and a state transition determination unit 16.
The storage unit 11 is, for example, a register, a SRAM (Static Random Access Memory), or the like. The storage unit 11 stores a coefficient indicating the magnitude of the interaction between the bits in the spin bit string. More specifically, the storage unit 11 stores the weighting coefficient between the own bit (here, the bit of index = 0) and the other bit. Here, the total number of weighting coefficients is K2 with respect to the number of spin bits (the number of ^first bits) K. The storage unit 11 stores K weight coefficients W ₀₀ , W ₀₁ , ..., W _{0, K-1} for bits of index = 0. Here, the weighting coefficient is represented by the second bit number L. Therefore, in the storage unit 11, K × L bits are required to store the weighting coefficient. The storage unit 11 may be provided outside the bit operation circuit 1a1 and inside the optimization device 1 (the same applies to the storage unit of other bit operation circuits).

When any bit of the spin bit string is inverted, the precision switching circuit 12 reads out the weighting coefficient for the inverted bit from its own storage unit 11 (of the bit operation circuit 1a1), and reads out the weighting coefficient in the energy change calculation unit. Output to 15. That is, the accuracy switching circuit 12 receives the identification information of the inverting bit from the selection circuit unit 2, reads the weighting coefficient corresponding to the pair of the inverting bit and the own bit from the storage unit 11, and outputs the weighting coefficient to the energy change calculation unit 15. ..

At this time, the precision switching circuit 12 reads out the weighting coefficient represented by the second number of bits set by the setting changing unit 5. The precision switching circuit 12 changes the number of second bits of the coefficient read from the storage unit 11 according to the change of the number of second bits by the setting changing unit 5.

For example, the precision switching circuit 12 has a selector that reads out a bit string having a predetermined number of bits from the storage unit 11. When the predetermined number of bits read by the selector is larger than the number of second bits, the precision switching circuit 12 reads the unit bit string including the weighting coefficient corresponding to the inverting bit by the selector, and the second bit from the read unit bit string. Extract the weighting factor represented by a number. Alternatively, when the predetermined number of bits read by the selector is smaller than the number of second bits, the precision switching circuit 12 is represented by the number of second bits by combining a plurality of bit strings read by the selector. The weighting coefficient may be extracted from the storage unit 11.

The inversion determination unit 13 receives the signals indicating index = j and flg _j output by the selection circuit unit 2, and determines whether or not the own bit is selected as the inversion bit based on the signals. When the own bit is selected as the inversion bit (that is, when index = j indicates the own bit and flg _j indicates inversion possible), the inversion determination unit 13 inverts the bit stored in the bit holding unit 14. .. That is, when the bit held in the bit holding unit 14 is 0, the bit is changed to 1. Further, when the bit held in the bit holding unit 14 is 1, the bit is changed to 0.

The bit holding unit 14 is a register that holds one bit. The bit holding unit 14 outputs the held bits to the energy change calculation unit 15 and the selection circuit unit 2.
The energy change calculation unit 15 calculates the energy change value ΔE ₀ of the rising model using the weighting coefficient read from the storage unit 11, and outputs the energy change value ΔE 0 to the state transition determination unit 16. Specifically, the energy change calculation unit 15 receives the value of the inversion bit (the value before the inversion this time) from the selection circuit unit 2, and the inversion bit is inverted from 1 to 0 or from 0 to 1. According to the equation (4), Δh ₀ is calculated. Then, the energy change calculation unit 15 updates h ₀ by adding Δh ₀ to the previous h ₀ . The energy change calculation unit 15 has a register that holds h ₀ , and holds h ₀ after being updated by the register.

Further, the energy change calculation unit 15 receives the current own bit from the bit holding unit 14, and if the own bit is 0, it is inverted from 0 to 1, and if the own bit is 1, it is inverted from 1 to 0. The energy change value ΔE ₀ of the model is calculated by the equation (2). The energy change calculation unit 15 outputs the calculated energy change value ΔE ₀ to the state transition determination unit 16.

The state transition determination unit 16 outputs a signal flg ₀ indicating whether or not the own bit can be inverted to the selection circuit unit 2 in response to the calculation of the energy change by the energy change calculation unit 15. Specifically, the state transition determination unit 16 receives the energy change value ΔE ₀ calculated by the energy change calculation unit 15, and whether or not the own bit can be inverted according to the comparison with the threshold value generated by the threshold value generation unit 3. It is a comparator that determines. Here, the determination by the state transition determination unit 16 will be described.

In simulated annealing, if the permissible probability p (ΔE, T) of the state transition that causes a certain energy change ΔE is determined by the following equation (5), the state is the optimum solution at the limit of the time (number of iterations) infinity. It is known to reach (ground state).

In equation (5), T is the temperature parameter T described above. Here, the equation (6) (Metropolis method) or the equation (7) (Gibbs method) is used as the function f.

The temperature parameter T is represented by, for example, the equation (8). That is, the temperature parameter T is given by a function that decreases logarithmically with respect to the number of iterations t. For example, the constant c is determined according to the problem.

Here, T ₀ is an initial temperature value, and it is desirable to take it sufficiently large depending on the problem.
When the permissible probability p (ΔE, T) expressed by the equation (5) is used and the steady state is reached after sufficient repetition of the state transition at a certain temperature, the state is generated according to the Boltzmann distribution. That is, the occupancy probability of each state follows the Boltzmann distribution for the thermal equilibrium state in thermodynamics. Therefore, a state according to the Boltzmann distribution is generated at a certain temperature, and then a state according to the Boltzmann distribution is generated at a temperature lower than the temperature, and so on, by gradually lowering the temperature, at each temperature. It will be possible to follow the state according to the Boltzmann distribution. Then, when the temperature is 0, the state of the lowest energy (ground state) is realized with high probability by the Boltzmann distribution at the temperature of 0. This method is called simulated annealing because this is very similar to the state change when the material is annealed. At this time, the probabilistic state transition in which the energy rises corresponds to thermal excitation in physics.

For example, a circuit that outputs a flag (flg = 1) indicating that a state transition that causes an energy change ΔE with an allowable probability p (ΔE, T) is allowed has f (−ΔE / T) and an interval [0,1]. ) Can be realized by a comparator that outputs a value corresponding to the comparison with a uniform random number u.

However, the same function can be realized by making the following modifications. Even if the same monotonically increasing function is applied to two numbers, the magnitude relationship does not change. Therefore, even if the same monotonically increasing function is applied to the two inputs of the comparator, the output of the comparator does not change. For example, the inverse function f ^-1 (-ΔE / T) of f (-ΔE / T) as a monotonic increase function acting on f (-ΔE / T), and f ^-1 as a monotonic increase function acting on a uniform random number u. It is possible to use f ^-1 (u) in which −ΔE / T of (−ΔE / T) is u. In that case, the circuit having the same function as the above-mentioned comparator may be a circuit that outputs 1 when −ΔE / T is larger than f ^-1 (u). Further, since the temperature parameter T is positive, the state transition determination unit 16 determines that −ΔE is larger than T · f ^-1 (u) (or ΔE is − (T · f ^-1 (u))). (When small), a circuit that outputs flg ₀ = 1 may be used.

The threshold value generation unit 3 outputs the value of f ^-1 (u) by using the conversion table that generates a uniform random number u and converts it into the value of f ^-1 (u) described above. When the metropolis method is applied, f ^-1 (u) is given by equation (9). Further, when the Gibbs method is applied, f ^-1 (u) is given by the equation (10).

The conversion table is stored in, for example, a memory (not shown) such as a RAM (Random Access Memory) or a flash memory connected to the threshold generation unit 3. The threshold value generation unit 3 outputs the product (T · f ^-1 (u)) of the temperature parameter T and f ^-1 (u) as a threshold value. Here, T. f ^-1 (u) corresponds to the thermal excitation energy.

When flg _j is input from the selection circuit unit 2 to the state transition determination unit 16 and the flg _j indicates that the state transition is not allowed (that is, when the state transition does not occur), the state transition determination unit 16 determines. After adding the offset value to −ΔE ₀ , the comparison with the threshold value may be performed. Further, the state transition determination unit 16 may increase the offset value to be added when the state transition does not continue to occur. On the other hand, the state transition determination unit 16 sets the offset value to 0 when flg _j indicates that the state transition is allowed (that is, when the state transition occurs). -Addition of the offset value to ΔE ₀ and increase of the offset value make it easier to tolerate the state transition, and when the current state is in the local solution, escape from the local solution is promoted.

In this way, the temperature parameter T is gradually set to be smaller, and for example, the spin bit string when the value of the temperature parameter T is reduced a predetermined number of times (or when the temperature parameter T reaches the minimum value) is the bit operation circuit 1a1, ..., held at 1aK. The optimization device 1 outputs a spin bit string as a solution when the value of the temperature parameter T is reduced a predetermined number of times (or when the temperature parameter T reaches the minimum value).

In the optimization device 1, the number of spin bits (number of first bits) of the rising model and the number of bits of the weighting coefficient between bits (number of second bits) can be changed by the setting change unit 5 described above. .. Here, the number of spin bits corresponds to the scale of the circuit (the scale of the problem) that realizes the Ising model. The larger the scale, the more the optimization device 1 can be applied to the combination optimization problem having a large number of combination candidates. Further, the number of bits of the weighting coefficient corresponds to the accuracy of the expression of the mutual relationship between the bits (the accuracy of the conditional expression in the problem). The higher the accuracy, the more detailed the conditions for the energy change ΔE at the time of spin inversion can be set. In some problems, the number of spin bits is large and the number of bits representing the weighting factor is small. Alternatively, another problem is that the number of spin bits is small and the number of bits representing the weighting factor is large. On the other hand, it is inefficient to individually manufacture an optimization device suitable for each problem according to the problem.

Therefore, in the optimization device 1, the scale and accuracy can be changed by enabling the setting change unit 5 to set the number of spin bits representing the state of the Ising model and the number of bits of the weighting coefficient. As a result, one optimization device 1 can realize the scale and accuracy suitable for the problem.

More specifically, each of the bit operation circuits 1a1, ..., 1aK, ..., 1aN has a precision switching circuit, and the precision switching circuit can be used from its own storage unit according to the setting of the setting changing unit 5. Switch the bit length of the weighting factor to be read. Further, the selection circuit unit 2 inputs a signal indicating an inverting bit to a bit operation circuit having a number (for example, K) corresponding to the number of spin bits set by the setting change unit 5, and the number (K). Select the inverting bit from the bits corresponding to the bit operation circuit. As a result, the Ising model can be realized with the scale and accuracy according to the problem by one optimization device 1 without individually manufacturing the optimization device having the scale and accuracy according to the problem.

Here, as described above, the storage unit included in each of the bit operation circuits 1a1, ..., 1aN is realized by a storage device having a relatively small capacity such as SRAM. Therefore, as the number of spin bits increases, the capacity of the storage unit may be insufficient depending on the number of bits of the weighting coefficient. On the other hand, according to the optimization device 1, the setting changing unit 5 can also set the scale and accuracy so as to satisfy the limitation of the capacity of the storage unit. Specifically, it is conceivable that the setting changing unit 5 is set to reduce the number of bits of the weighting coefficient as the number of spin bits increases. Further, it is conceivable that the setting changing unit 5 is set to reduce the number of spin bits as the number of bits of the weighting coefficient increases.

Further, in the above example, K of the N bit operation circuits are used for the Ising model. The optimization device 1 may not use the remaining NK bit operation circuits. In that case, the selection circuit unit 2 forcibly sets all the flags flag output by the remaining NK bit operation circuits to 0, and the bits corresponding to the remaining NK bit operation circuits. May not be selected as an inversion candidate.

Alternatively, when NK ≧ K, the optimizing device 1 realizes the same Ising model as the above-mentioned Ising model by the K bit operation circuit of the remaining NK bit operation circuits, and both. The Ising model may be used to increase the degree of parallelism in processing the same problem to speed up the calculation.

Further, the optimization device 1 realizes another Ising model corresponding to another problem by using a part of the remaining NK bit arithmetic circuits, and the problem represented by the above-mentioned Ising model. In parallel with, the operation of the other problem may be performed.

In the following, an information processing system using the optimization device 1 will be illustrated, and the functions of the optimization device 1 will be described in more detail.
[Second Embodiment]
Next, a second embodiment will be described.

FIG. 2 is a diagram showing an example of an information processing system according to a second embodiment.
The information processing system of the second embodiment includes an information processing device 20 and a client 30. The information processing device 20 and the client 30 are connected to the network 40. The network 40 may be, for example, a LAN (Local Area Network), a WAN (Wide Area Network), the Internet, or the like.

The information processing apparatus 20 provides a function of replacing a combinatorial optimization problem with an Ising model and solving the combinatorial optimization problem at high speed by searching for the ground state of the Ising model.
The client 30 is a client computer used by the user and is used to input a problem to be solved by the user to the information processing apparatus 20.

FIG. 3 is a block diagram showing a hardware example of the information processing apparatus.
The information processing device 20 includes a CPU (Central Processing Unit) 21, a DRAM (Dynamic Random Access Memory) 22, a storage device 23, a NIC (Network Interface Card) 24, an optimization device 25, and a medium reader 28.

The CPU 21, DRAM 22, the storage device 23, the NIC 24, the optimization device 25, and the medium reader 28 are connected to the bus 29 of the information processing device 20. The bus 29 is, for example, a PCIe (Peripheral Component Interconnect Express) bus.

The CPU 21 is a processor that executes a program instruction stored in the DRAM 22. The CPU 21 loads at least a part of the programs and data stored in the storage device 23 into the DRAM 22 and executes the program. The CPU 21 controls the setting and operation of the optimization device 25 by the function exhibited by executing the program.

The DRAM 22 is the main storage device of the information processing device 20, and temporarily stores programs executed by the CPU 21 and data set in the optimization device 25.
The storage device 23 is an auxiliary storage device of the information processing device 20, and stores programs executed by the CPU 21 and data set in the optimization device 25. The storage device 23 is, for example, an SSD (Solid State Drive) or an HDD (Hard Disk Drive).

The NIC 24 is a communication interface that is connected to the network 40 and communicates with the client 30 via the network 40. The NIC 24 is connected to, for example, a communication device such as a switch or a router belonging to the network 40 by a cable.

The optimization device 25 searches for the ground state of the Ising model under the control of the CPU 21. The optimization device 25 is, for example, a one-chip semiconductor integrated circuit, and is realized by an FPGA or the like. The optimization device 25 is an example of the optimization device 1 of the first embodiment.

The medium reader 28 is a reading device that reads programs and data recorded on the recording medium 41. As the recording medium 41, for example, a magnetic disk, an optical disk, a magneto-optical disk (MO: Magneto-Optical disk), a semiconductor memory, or the like can be used. The magnetic disk includes a flexible disk (FD) and an HDD. Optical discs include CDs (Compact Discs) and DVDs (Digital Versatile Discs).

The medium reader 28 copies, for example, a program or data read from the recording medium 41 to another recording medium such as the DRAM 22 or the storage device 23. The read program is executed by, for example, the CPU 21. The recording medium 41 may be a portable recording medium and may be used for distribution of programs and data. Further, the recording medium 41 and the storage device 23 may be referred to as a computer-readable recording medium.

The client 30 has a CPU, a main storage device, an auxiliary storage device, an NIC, an input device such as a mouse and a keyboard, and a display.
FIG. 4 is a diagram showing an example of the relationship between hardware in an information processing system.

The client 30 executes the user program 31. The user program 31 inputs various data (for example, operating conditions such as the content of the problem to be solved and the usage schedule of the optimization device 25) to the information processing device 20, and displays the calculation result by the optimization device 25. conduct. The client 30 and the NIC 24 notify the input unit for inputting various data to the information processing apparatus 20 and the solution obtained as a result of the base state search as they are, or result information that is easy for the user to understand (for example, for example). A display unit that displays the result as information on the display screen visualized as a graph is realized.

The CPU 21 is a processor (arithmetic unit) that executes the library 21a and the driver 21b. The program of the library 21a and the program of the driver 21b are stored in the storage device 23, and are loaded into the DRAM 22 at the time of execution by the CPU 21.

The library 21a receives various data input by the user program 31 and converts the problem to be solved by the user into a problem of searching for the lowest energy state of the Ising model. The library 21a provides the driver 21b with information about the problem after conversion (eg, the number of spin bits, the number of bits representing the weighting factor, the value of the weighting factor, the initial value of the temperature parameter, and the like). Further, the library 21a acquires the search result of the solution by the optimization device 25 from the driver 21b, converts the search result into result information that is easy for the user to understand, and provides the search result to the user program 31.

The driver 21b supplies the information provided by the library 21a to the optimization device 25. Further, the driver 21b acquires the search result of the solution by the Ising model from the optimization device 25 and provides it to the library 21a.

The optimization device 25 has a control unit 25a and an LFB (Local Field Block) 50 as hardware.
The control unit 25a has a RAM for storing the operating conditions of the LFB50 received from the driver 21b, and controls the calculation by the LFB50 based on the operating conditions. Further, the control unit 25a sets initial values in various registers provided in the LFB 50, stores the weighting coefficient in the SRAM, reads out the spin bit string (search result) after the calculation is completed, and the like. The control unit 25a is realized by, for example, a circuit in FPGA.

The LFB 50 has a plurality of LFEs (Local Field Elements). The LFE is a unit element corresponding to a spin bit. One LFE corresponds to one spin bit. As will be described later, the optimization device 25 may have a plurality of LFBs.

FIG. 5 is a block diagram showing a hardware example of the control unit.
The control unit 25a includes a CPU input / output unit 25a1, a control register 25a2, an LFB transmission unit 25a3, and an LFB reception unit 25a4.

The CPU input / output unit 25a1 inputs the data received from the CPU 21 to the control register 25a2 or the LFB 50. For example, the CPU input / output unit 25a1 inputs setting data such as the scale and accuracy input by the CPU 21, initial values of each parameter, coupling constants, and operating condition data of the LFB 50 to the LFB 50 via the control register 25a 2. It can also be input to each register or RAM in the LFB50.

The control register 25a2 holds various setting data for the LFB 50 by the CPU input / output unit 25a1 and outputs the setting data to the LFB transmission unit 25a3. Further, the control register 25a2 holds the data received from the LFB 50 by the LFB receiving unit 25a4 and outputs the data to the CPU input / output unit 25a1.

The LFB transmission unit 25a3 transmits the setting data held in the control register 25a2 to the LFB 50.
The LFB receiving unit 25a4 receives data (data such as a calculation result) from the LFB 50 and stores it in the control register 25a2.

FIG. 6 is a diagram showing an example of a combinatorial optimization problem.
As an example of the combinatorial optimization problem, consider the traveling salesman problem. Here, for the sake of simplicity, it is assumed that a route that goes around the five cities of A city, B city, C city, D city, and E city at the minimum cost (distance, fare, etc.) is found. Graph 201 shows one route with a city as a node and movement between cities as an edge. This route is represented by, for example, a matrix 202 in which the order of going around the rows and the columns are associated with the cities. The matrix 202 indicates to go around the city in which the bit "1" is set, in ascending order of rows. Further, the matrix 202 can be converted into a binary value 203 corresponding to a spin bit string. In the example of the matrix 202, the binary value 203 is 5 × 5 = 25 bits. The number of bits of the binary value 203 (spin bit string) increases as the number of cities to be visited increases. That is, as the scale of the combinatorial optimization problem increases, more spin bits are required, and the number of bits (scale) of the spin bit string increases.

Next, an example of searching for a binary value that is the minimum energy will be described.
FIG. 7 is a diagram showing an example of searching for a binary value that is the minimum energy.
First, the energy before inverting one bit of the binary value 221 (before spin inverting) is defined as E _init .

The optimization device 25 calculates the energy change amount ΔE when inverting any one bit of the binary value 221. Graph 211 illustrates an energy change with respect to 1-bit inversion according to an energy function, where the horizontal axis is a binary value and the vertical axis is energy. The optimization device 25 obtains ΔE by the equation (2).

The optimization device 25 applies the above calculation to all the bits of the binary value 221 and calculates the energy change amount ΔE for the inversion of each bit. For example, when the number of bits of the binary value 221 is N, the number of inversion patterns 222 is N. Graph 212 exemplifies the state of energy change for each inversion pattern.

The optimization device 25 randomly selects one of the inversion patterns 222 that satisfy the inversion conditions (predetermined determination conditions of the threshold value and ΔE) based on ΔE for each inversion pattern. The optimization device 25 adds / subtracts ΔE corresponding to the selected inversion pattern to the E _init before the spin inversion, and calculates the energy value E after the spin inversion. The optimization device repeats the above procedure using the obtained energy value E as E _init and the binary value 223 after spin inversion.

Here, as described above, one element of W used in the equations (2) and (3) is a spin inversion weighting coefficient indicating the magnitude of the interaction between the bits. The number of bits representing the weighting factor is called precision. The higher the accuracy, the more detailed the conditions for the energy change amount ΔE at the time of spin inversion can be set. For example, the total size of W is "precision x number of spin bits x number of spin bits" for the total coupling of two bits included in the spin bit string. As an example, when the number of spin bits is 8k (= 8192), the total size of W is “precision × 8k × 8k” bits.

Next, the circuit configuration of the optimization device 25 that performs the search illustrated in FIG. 7 will be described.
FIG. 8 is a diagram showing a circuit configuration example of the optimization device.
The optimization device 25 (or LFB50 of the optimization device 25) includes LFE51a1, 51a2, ..., 51an, a random selector unit 52, a threshold value generation unit 53, a random number generation unit 54, a mode setting register 55, an adder 56, and E storage. It has a register 57.

Each of LFE51a1, 51a2, ..., 51an is used as one bit of the spin bit. n is an integer of 2 or more and indicates the number of LFEs included in the LFB 50. LFE identification information (index) is associated with each of LFE51a1, 51a2, ..., 51an. For each of LFE51a1, 51a2, ..., 51an, index = 0,1, ..., N-1. LFE51a1, 51a2, ..., 51an are examples of the bit operation circuits 1a1, ..., 1aN of the first embodiment.

Hereinafter, the circuit configuration of the LFE51a1 will be described. LFE51a2, ..., 51an are also realized by the same circuit configuration as LFE51a1. Regarding the description of the circuit configuration of LFE51a2, ..., 51an, the "a1" part at the end of the code of each element in the following description is replaced with each of "a2", ..., "An" (for example, "an". The code of "60a1" may be replaced with "60an"). Further, the subscripts of each value such as h, q, ΔE, and W may be replaced with the subscripts corresponding to each of "a2", ..., And "an".

The LFE51a1 has an SRAM 60a1, an accuracy switching circuit 61a1, a Δh generation unit 62a1, an adder 63a1, an h storage register 64a1, an inversion determination unit 65a1, a bit storage register 66a1, a ΔE generation unit 67a1, and a determination unit 68a1.

SRAM 60a1 stores the weighting factor W. The SRAM 60a1 corresponds to the storage unit 11 of the first embodiment. The SRAM 60a1 stores only the weight coefficient W of all spin bits used in the LFE51a1. Therefore, assuming that the number of spin bits is K (K is an integer of 2 or more and n or less), the size of the total weighting factor stored in the SRAM 60a1 is “precision × K” bits. In FIG. 8, as an example, the case where the number of spin bits K = n is illustrated. In this case, the weight coefficients W ₀₀ , W ₀₁ , ..., W _{0, n-1} are stored in the SRAM 60a1.

The precision switching circuit 61a1 acquires the index, which is the identification information of the inverting bit, and the flag F indicating inversion possible from the random selector unit 52, and extracts the weighting coefficient corresponding to the inverting bit from the SRAM 60a1. The precision switching circuit 61a1 outputs the extracted weighting factor to the Δh generation unit 62a1. For example, the precision switching circuit 61a1 may acquire the index and the flag F stored in the SRAM 60a1 by the random selector unit 52 from the SRAM 60a1. Alternatively, the precision switching circuit 61a1 may have a signal line to be supplied with the index and the flag F from the random selector unit 52 (not shown).

Here, the precision switching circuit 61a1 accepts the setting of the number of bits (precision) of the weighting coefficient set in the mode setting register 55, and switches the number of bits of the weighting coefficient read from the SRAM 60a1 according to the setting.

Specifically, the precision switching circuit 61a1 has a selector for reading a bit string (unit bit string) having a predetermined number of unit bits from the SRAM 60a1. The precision switching circuit 61a1 reads out a unit bit string of the number of bits r including the weighting coefficient corresponding to the inverting bit by the selector. For example, when the number of unit bits r read by the selector is larger than the number of bits z of the weighting coefficient, the precision switching circuit 12 sets the bit portion indicating the weighting coefficient corresponding to the inverting bit to the read bit string as LSB. By shifting to the Least Significant Bit) side and substituting 0 for the other bit parts, the weighting coefficient is read out. Alternatively, it is conceivable that the unit bit number r is smaller than the bit number z set by the mode setting register 55. In this case, the precision switching circuit 61a1 may extract the weighting coefficient at the set number of bits z by combining a plurality of unit bit strings read by the selector.

The precision switching circuit 61a1 is also connected to the SRAM 60a2 included in the LFE51a2. As will be described later, the precision switching circuit 61a1 can also read the weighting factor from the SRAM 60a2.

The Δh generation unit 62a1 receives the current bit value of the inversion bit (the bit value before the inversion this time) from the random selector unit 52, and uses the weighting coefficient acquired from the precision switching circuit 61a1 to localize according to the equation (4). The amount of change Δh ₀ in the field h ₀ is calculated. The Δh generation unit 62a1 outputs Δh ₀ to the adder 63a1.

The adder 63a1 adds Δh ₀ to the local field h ₀ stored in the h storage register 64a1 and outputs it to the h storage register 64a1.
The storage register 64a1 captures a value (local field h ₀ ) output by the adder 63a1 in synchronization with a clock signal (not shown). h The storage register 64a1 is, for example, a flip-flop. The initial value of the local field h ₀ stored in the h storage register 64a1 is the bias coefficient b ₀ . The initial value is set by the control unit 25a.

The inversion determination unit 65a1 receives the inversion bit index = _j and the flag Fj indicating whether or not the inversion is possible from the random selector unit 52, and determines whether or not the own bit is selected as the inversion bit. When the own bit is selected as the inverting bit, the inverting determination unit 65a1 inverts the spin bit stored in the bit storage register 66a1.

The bit storage register 66a1 holds a spin bit corresponding to LFE51a1. The bit storage register 66a1 is, for example, a flip-flop. The spin bits stored in the bit storage register 66a1 are inverted by the inversion determination unit 65a1. The bit storage register 66a1 outputs spin bits to the ΔE generation unit 67a1 and the random selector unit 52.

The ΔE generation unit 67a1 calculates the energy change amount ΔE ₀ of the Ising model according to the inversion of its own bit by the equation (2) based on the local field h ₀ of the h storage register 64a1 and the spin bit of the bit storage register 66a1. do. The ΔE generation unit 67a1 outputs the energy change amount ΔE ₀ to the determination unit 68a1 and the random selector unit 52.

The determination unit 68a1 indicates whether or not to allow inversion of the own bit by comparing the energy change amount ΔE ₀ output by the ΔE generation unit 67a1 with the threshold value generated by the threshold value generation unit 53 (of the own bit). The flag _F0 (indicating whether or not inversion is possible) is output to the random selector unit 52. Specifically, the determination unit 68a1 outputs F ₀ = 1 (reversible) when ΔE ₀ is smaller than the threshold value − (T · f ^-1 (u)), and ΔE ₀ is the threshold value − (T · f ⁻ ). When ¹ (u)) or more, F ₀ = 0 (non-reversible) is output. Here, f ^-1 (u) is a function given by any of the equations (9) and (10) according to the applicable law. Further, u is a uniform random number in the interval [0,1).

The random selector unit 52 receives from each of LFE51a1, 51a2, ..., 51an an energy change amount, a flag indicating whether or not the spin bit can be inverted, and a spin bit, and among the invertable spin bits, the bit (inverted bit) to be inverted. Select.

The random selector unit 52 supplies the current bit value (bit qj) of the selected inverted bit to the Δh generation unit _62a1 , 62a2, ..., 62an included in the LFE 51a1, 51a2, ..., 51an. The random selector unit 52 is an example of the selection circuit unit 2 of the first embodiment.

The random selector unit 52 outputs the index = j of the inversion bit and the flag F _j indicating whether or not the inversion is possible to the SRAMs 60a1, 60a2, ..., 60an included in the LFE 51a1, 51a2, ..., 51an. As described above, the random selector unit 52 includes the inversion bit index = j and the flag F _j indicating whether or not the inversion is possible in the precision switching circuits 61a1, 61a2, ..., 61an provided in the LFE 51a1, 51a2, ..., 51an. It may be output to.

Further, the random selector unit 52 supplies the inversion bit index = j and the flag F _j indicating whether or not the inversion is possible to the inversion determination units 65a1, 65a2, ..., 65an provided in the LFE 51a1, 51a2, ..., 51an.

Further, the random selector unit 52 supplies _ΔEj corresponding to the selected inversion bit to the adder 56.
Here, the random selector unit 52 accepts the setting of the number of spin bits (that is, the number of LFEs to be used) in a certain Ising model from the mode setting register 55. For example, the random selector unit 52 makes it possible to search for a solution by using a number of LFEs corresponding to the set number of spin bits in order from the smallest index. For example, when using K LFEs out of n LFEs, the random selector unit 52 selects inversion bits from the spin bit strings corresponding to the LFEs of LFE51a1, ..., LFE51aK. At this time, it is conceivable that the random selector unit 52 forcibly sets the flags F output from each of the unused n—K LFE51a (K-1), ..., 51an to 0.

The threshold value generation unit 53 generates and supplies a threshold value used for comparison with the energy change amount ΔE to the determination units 68a1, 68a2, ..., 68an included in the LFE 51a1, 51a2, ..., 51an. As described above, the threshold generation unit 53 uses the temperature parameter T, the uniform random number u in the interval [0, 1), and f ^-1 (u) represented by the equation (9) or the equation (10). To generate a threshold. The threshold value generation unit 53 has, for example, a random number generator for each LFE individually, and generates a threshold value using the random number u for each LFE. However, the random number generator may be shared by some LFEs. The initial value of the temperature parameter T, the decrease cycle and the decrease amount of the temperature parameter T in simulated annealing, and the like are controlled by the control unit 25a.

The random number generation unit 54 generates random number bits used for selecting the inversion bit in the random selector unit 52, and supplies the random number bits to the random selector unit 52.
The mode setting register 55 supplies a signal indicating the number of bits of the weighting factor (that is, accuracy) to the accuracy switching circuits 61a1, 61a2, 61an included in the LFE 51a1, 51a2, ..., 51an. Further, the mode setting register 55 supplies a signal indicating the number of spin bits (that is, scale) to the random selector unit 52. The control unit 25a sets the number of spin bits and the number of weight coefficient bits for the mode setting register 55. The mode setting register 55 is an example of the setting changing unit 5 of the first embodiment.

The adder 56 adds the energy change amount _ΔEj output by the random selector unit 52 to the energy value E stored in the E storage register 57, and outputs the energy value to the E storage register 57.

The E storage register 57 takes in the energy value E output by the adder 56 in synchronization with a clock signal (not shown). The E storage register 57 is, for example, a flip-flop. The initial value of the energy value E is calculated by the control unit 25a using the equation (1) and set in the E storage register 57.

For example, when K LFEs are used to search for a solution, the control unit 25a obtains a spin bit string by reading each spin bit of the bit storage registers 66a1, ..., 66aK.
FIG. 9 is a diagram showing a circuit configuration example of the random selector unit.

The random selector unit 52 has a flag control unit 52a and a plurality of selection circuits connected in a tree shape over a plurality of stages.
The flag control unit 52a controls the value of the flag input to each of the selection circuits 52a1, 52a2, 52a3, 52a4, ..., 52aq of the first stage according to the setting of the number of spin bits of the mode setting register 55. FIG. 9 illustrates a partial circuit 52xn that controls the value of the flag for one input of the selection circuit 52aq (corresponding to the output of the LFE51an). The flag setting unit 52yn of the partial circuit 52xn is a switch that forcibly sets the flag Fn output from the unused LFE51an to 0.

Two sets of variables q _i , Fi and ΔE _i output by each of the LFE 51a 1, 51a 2, ..., _51an are input to each of the selection circuits 52a1, 52a2, 52a3, 52a4, ..., 52aq in the first stage. .. For example, a set of variables q ₀ , F ₀ , and ΔE ₀ output by LFE 51a 1 and a set of variables q ₁ , F ₁ , and ΔE ₁ output by LFE 51a 2 are input to the selection circuit 52a 1. Further, a set of variables q ₂ and F ₂ and ΔE ₂ and a set of variables q ₃ and F ₃ and ΔE ₃ are input to the selection circuit 52a 2, and the variables q ₄ and F ₄ and ΔE ₄ are input to the selection circuit 52a 3. And the set of variables q ₅ and F ₅ and ΔE ₅ are input. Further, a set of variables q ₆ and F ₆ and ΔE ₆ and a set of variables q ₇ and F ₇ and ΔE ₇ are input to the selection circuit 52a 4, and the variables q _n-2 and F _n − are input to the selection circuit 52 aq. The set of ₂ and ΔE _n-2 and the set of variables q _n-1 and F _n-1 and ΔE _n-1 are input.

Then, each of the selection circuits 52a1, ..., 52aq is based on two sets of input variables q _i , _{Fi and ΔE i ,} and a one-bit random number output by the random number generation unit 54, and one set of variables q. Select _i , _{Fi, and ΔE i .} At this time, each of the selection circuits 52a1, ..., _52aq preferentially selects the set in which Fi is 1, and when both sets are 1, one of the sets is selected based on the 1-bit random number. (Same for other selection circuits). Here, the random number generation unit 54 individually generates a 1-bit random number for each selection circuit and supplies it to each selection circuit. Further, each of the selection circuits _{52a1, ..., 52aq generates a 1-bit identification value indicating which set of variables qi, Fi and ΔE i is selected} , and the selected variables _qi and _Fi A signal (referred to as a state signal) including _ΔEi and an identification value is output. The number of selection circuits 52a1 to 52aq in the first stage is ½ of the numbers of LFE51a1, ..., 51an, that is, n / 2.

Two state signals output by the selection circuits 52a1, ..., 52aq are input to each of the selection circuits 52b1, 52b2, ..., 52br in the second stage. For example, a state signal output by the selection circuits 52a1 and 52a2 is input to the selection circuit 52b1, and a state signal output by the selection circuits 52a3 and 52a4 is input to the selection circuit 52b2.

Then, each of the selection circuits 52b1, ..., 52br selects one of the two state signals based on the two state signals and the 1-bit random number output by the random number generation unit 54. Further, each of the selection circuits 52b1, ..., 52br is updated by adding 1 bit so as to indicate which state signal is selected for the identification value included in the selected state signal, and the selected state signal is output. do.

The same processing is performed in the selection circuit of the third and subsequent stages, the bit width of the identification value is increased by 1 bit in the selection circuit of each stage, and the output of the random selector unit 52 is output from the selection circuit 52p of the last stage. A certain state signal is output. The identification value included in the state signal output by the random selector unit 52 is an index represented by a binary number indicating an inverted bit.

However, the random selector unit 52 accepts the index corresponding to the LFE together with the flag F from each LFE, and selects the index by each selection circuit in the same manner as the variables q _i , _{Fi, and ΔE i ,} so that the inverting bit is used. The index corresponding to may be output. In this case, each LFE has a register for storing index, and outputs index from the register to the random selector unit 52.

In this way, the random selector unit 52 determines whether or not the inversion output is possible by the LFE51a (K + 1), ..., 51an other than the LFE51a1, ..., 51aK having the set spin bit number K among the LFE51a1, ..., 51an. Forcibly set the indicated signal so that it cannot be inverted. The random selector unit 52 selects an inversion bit based on the signal output by LFE51a1, ..., 51aK indicating whether or not inversion is possible and the signal indicating non-inversion set for LFE51a (K + 1), ..., 51an. The random selector unit 52 outputs a signal indicating an inverting bit to LFE51a (K + 1), ..., 51an in addition to LFE51a1, ..., 51aK.

In this way, the flag F of the unused LFE is forcibly set to 0 by the control of the flag control unit 52a, so that the bit corresponding to the LFE not used in the spin bit string can be excluded from the inversion candidates.

Next, an example of storing weighting coefficients for SRAMs 60a1, 60a2, ..., 60an of LFE51a1, ..., 51an will be described. First, the trade-off relationship between scale and accuracy with respect to SRAM capacity will be described.

FIG. 10 is a diagram showing an example of a trade-off relationship between scale and accuracy.
As mentioned above, the traveling salesman problem is an example of the combinatorial optimization problem. The traveling salesman problem is a low-precision problem if the number of cities to be visited is large and the traveling conditions (travel time, travel distance, travel cost, etc.) are small, and if there are many traveling conditions, high accuracy is required. Other optimization problems with relatively low accuracy include problems with certain conditions, such as the eight queens problem and the four-color problem. On the other hand, the portfolio optimization problem requires high accuracy because there are many conditions such as amount and period.

If there is a limit to the capacity of SRAM for each LFE, there is a trade-off relationship between scale and accuracy. Graph 300 shows a trade-off relationship between scale and accuracy when the upper limit of the capacity for storing the weighting factor is 128 k (kilo) bits in the SRAM for each LFE. Here, 1k (kilo) = 1024. The horizontal axis of the graph 300 is the scale (k bits), and the vertical axis is the accuracy (bits). As an example, it is assumed that n = 8192.

In this case, the maximum accuracy is 128 bits for a scale of 1 kbit. The maximum accuracy is 64 bits for a scale of 2 kbits. The maximum accuracy is 32 bits for a scale of 4 kbits. The accuracy is up to 16 bits for a scale of 8 kbits.

Therefore, in the optimization device 25, for example, the following four modes are made available. The first mode is a mode with a scale of 1 kbit / precision of 128 bits. The second mode is a mode with a scale of 2 kbits and a precision of 64 bits. The third mode is a mode having a scale of 4 kbits and a precision of 32 bits. The fourth mode is a mode with a scale of 8 kbits and a precision of 16 bits. Next, an example of storing the weighting coefficient corresponding to each of these four modes will be described. The weighting coefficient is stored in each of the SRAMs 60a1, 60a2, ..., 60an by the control unit 25a. The number of unit bits read from the SRAMs 60a1, 60a2, ..., 60an by the selectors of the precision switching circuits 61a1, 61a2, ..., 61an is assumed to be 128 bits as an example.

FIG. 11 is a diagram showing an example of storing the weighting factor (No. 1).
When the above-mentioned first mode (scale 1 kbit / precision 128 bits) is used, the weighting coefficient W is expressed by the equation (11).

Data 1d1, 1d2, ..., 1ds show an example of storing weighting coefficients for SRAMs 60a1, 60a2, ..., 60as when the above-mentioned first mode (scale 1 kbit / precision 128 bits) is used. Here, s = 1024. The data 1d1, 1d2, ..., 1ds are stored in the SRAMs 60a1, 60a2, ..., 60as, respectively. In this mode, 1k (= 1024) LFEs are used. In the figure, LFE51a1, ..., 51as may be expressed as LFE0, ..., LFE1023 by using their respective identification numbers (the same applies to the following figures).

The data 1d1 indicates _W0,0 to _W0,1023 stored in the SRAM 60a1 of the LFE51a1 (LFE0). The data 1d2 show W _1,0 to W _1,1023 stored in the SRAM 60a2 of the LFE51a2 (LFE1). The data _1ds indicate W 1023, 0 to W ₁₀₂₃ , 1023 stored in the SRAM 60as of the LFE 51as (LFE 1023). The number of bits of one weighting coefficient _Wij is 128 bits.

FIG. 12 is a diagram showing an example of storing the weighting factor (No. 2).
When the above-mentioned second mode (scale 2 kbit / precision 64 bits) is used, the weighting coefficient W is expressed by the equation (12).

The data 2d1, 2d2, ..., 2dt show an example of storing weighting coefficients for SRAMs 60a1, 60a2, ..., 60at when the above-mentioned second mode (scale 2 kbit / precision 64 bits) is used. Here, t = 2048. The data 2d1, 2d2, ..., 2dt are stored in the SRAMs 60a1, 60a2, ..., 60at, respectively. In this mode, 2k (= 2048) LFEs are used.

The data _2d1 indicates _W0,0 to W0,2047 stored in the SRAM 60a1 of the LFE51a1 (LFE0). The data 2d2 show W _1,0 to W _1,2047 stored in the SRAM 60a2 of the LFE51a2 (LFE1). The data _2dt indicates W 2047, 0 to W ₂₀₄₇ , 2047 stored in the SRAM 60 at of the LFE 51at (LFE 2047). The number of bits of one weighting coefficient _Wij is 64 bits.

FIG. 13 is a diagram showing an example of storing the weighting factor (No. 3).
When the above-mentioned third mode (scale 4 kbits / precision 32 bits) is used, the weighting coefficient W is expressed by the equation (13).

The data 3d1, 3d2, ..., 3du show an example of storing weighting coefficients for SRAMs 60a1, 60a2, ..., 60au when the above-mentioned third mode (scale 4 kbit / precision 32 bits) is used. Here, u = 4096. The data 3d1, 3d2, ..., 3du are stored in the SRAMs 60a1, 60a2, ..., 60au, respectively. In this mode, 4k (= 4096) LFEs are used.

The data _3d1 indicates _W0,0 to W0,4095 stored in the SRAM 60a1 of the LFE51a1 (LFE0). The data 3d2 show W _1,0 to W _1,4095 stored in the SRAM 60a2 of the LFE51a2 (LFE1). The data _3du indicates W 4095, 0 to W ₄₀₉₅ , 4095 stored in the SRAM 60au of the LFE51au (LFE4095). The number of bits of one weighting coefficient _Wij is 32 bits.

FIG. 14 is a diagram showing an example of storing the weighting factor (No. 4).
When the above-mentioned fourth mode (scale 8 kbits / precision 16 bits) is used, the weighting coefficient W is expressed by the equation (14).

The data 4d1, 4d2, ..., 4dn show an example of storing the weighting coefficient for the SRAMs 60a1, 60a2, ..., 60an when the above-mentioned fourth mode (scale 8 kbit / precision 16 bit) is used. Here, n = 8192. The data 4d1, 4d2, ..., 4dn are stored in the SRAMs 60a1, 60a2, ..., 60an, respectively. In this mode, 8k (= 8192) LFEs are used.

The data _4d1 indicates _W0,0 to W0.8191 stored in the SRAM 60a1 of the LFE51a1 (LFE0). The data 4d2 show W _1,0 to W _1,8911 stored in the SRAM 60a2 of the LFE51a2 (LFE1). The data 4dn shows W _8191,0 to W ₈₁₉₁ , 8191 stored in the SRAM 60an of the LFE51an (LFE8911). The number of bits of one weighting coefficient _Wij is 16 bits.

Next, the processing procedure of the optimization device 25 will be described. First, an example of the initialization process of the optimization device 25 will be described.
FIG. 15 is a flowchart showing an example of the initialization process.

(S10) The CPU 21 inputs the initial value and the operating condition according to the problem to the optimization device 25. The initial value includes, for example, an energy value E, a local field hi, a spin bit _qi , an initial value of the temperature parameter T, a _weighting coefficient W, and the like. Further, the operating conditions include the number of times the state is updated N1 with one temperature parameter, the number of times the temperature parameter is changed N2, the amount of decrease in the temperature parameter, and the like. The control unit 25a sets the input initial value and the weighting coefficient in the register and SRAM of each of the above-mentioned LFEs. If there is an unused LFE, the control unit 25a sets, for example, all 0s as W in the SRAM of the LFE. The weighting coefficient W between the spin bits is represented by the number of bits corresponding to the accuracy according to the problem.

(S11) The CPU 21 inputs the number of spin bits (scale) and the number of weight coefficient bits (precision) according to the problem to the optimization device 25. The control unit 25a receives the number of spin bits and the number of weight coefficient bits from the CPU 21 and inputs them to the mode setting register 55. The number of bits of the weighting coefficient input to the mode setting register 55 is input to the accuracy switching circuit of each LFE. Further, the number of spin bits input to the mode setting register 55 is input to the random selector unit 52.

(S12) The CPU 21 inputs a calculation start flag (for example, a calculation start flag = 1) to the optimization device 25. The control unit 25a accepts the input of the calculation start flag and starts the calculation by the LFB 50. In this way, the initialization process is completed.

FIG. 16 is a flowchart showing an example of arithmetic processing.
Here, in the description of FIG. 16, the LFE corresponding to index = i is referred to as LFE51ax (the first LFE is LFE51a1 and the nth LFE is 51an). Each part included in the LFE51ax is also described by adding "x" to the end of the reference numeral, for example, SRAM 60ax. The operations by each of LFE51a1, ..., LFE51an are executed in parallel.

(S20) The ΔE generation unit 67ax is the amount of energy change when the bit q _i is inverted based on the local field h _i stored in the h storage register 64 ax and the bit q _i stored in the bit storage register 66 ax. Generate ΔE _i . Equation (2) is used to generate ΔE _i .

(S21) The determination unit 68ax compares the energy change amount ΔE _i generated by the ΔE generation unit 67ax with the threshold value (= − (T · f ^-1 (u))) generated by the threshold value generation unit 53. , It is determined whether or not the threshold value> ΔE _i . When the threshold value> ΔE _i , the process proceeds to step S22. When the threshold value ≤ ΔE _i , the process proceeds to step S23.

(S22) The determination unit _68ax outputs an inversion candidate signal (Fi = 1) to the random selector unit 52. Then, the process proceeds to step S24.
(S23) The determination unit _68ax outputs a non-inverting signal (Fi = 0) to the random selector unit 52. Then, the process proceeds to step S24.

(S24) The random selector unit 52 selects one inversion bit from all inversion candidates (bits corresponding to LFE with Fi = 1) output from each of _LFE51a1 , ..., LFE51an. The random selector unit 52 outputs index = j, F _j , q _j corresponding to the selected inversion bit to LFE51a1, ..., LFE51an. Further, the random selector unit 52 outputs _ΔEj corresponding to the selected inversion bit to the adder 56. Then, the next steps S25 (energy update process) and S26 (state update process) are started in parallel.

(S25) The adder 56 updates the energy value E stored in the E storage register 57 by adding the energy change amount ΔE corresponding to the inverting bit to the energy value E. That is, E = E + ΔE. Then, the energy update process is completed.

(S26) The precision switching circuit 61ax acquires index = _j corresponding to the inverting bit and the flag Fj, and reads a unit bit string including a weighting coefficient corresponding to the inverting bit from the SRAM 60ax. The unit bit string is a unit of a bit string read from the SRAM 60ax at a time by the selector of the precision switching circuit 61ax. The number of bits (number of unit bits) of the unit bit string is 128 bits in one example (other values may be used). In this case, in step S26, a 128-bit unit bit string is read from the SRAM 60ax.

For example, when 128 / a (a = 1, 2, 4, 8) bits are selected as the precision, the precision switching circuit 61ax counts from the unit bit string at the beginning of the SRAM 60ax (the beginning is the 0th). Read the "Integer (j / a)" th unit bit string. Here, Integer (j / a) is a function that extracts an integer part from the value of (j / a).

(S27) The precision switching circuit 61ax has a weight coefficient (weight coefficient corresponding to the inverted bit q _j ) W of the number of bits corresponding to the mode selection set by the mode setting register 55 from the unit bit string read in step S26. Extract _ij . For example, when the precision switching circuit 61ax extracts a z-bit bit string from a 128-bit unit bit string, the precision switching circuit 61ax shifts the z-bit bit range corresponding to the inverting bit to the LSB side as described above, and shifts the z-bit bit range to the other high-order bits. By setting 0, the weighting coefficient of the z-bit is extracted.

In the accuracy switching circuit 61ax, when the unit bit string read in step S26 is divided into bit length sections corresponding to the accuracy from the beginning, the bit range corresponding to the inverting bit is the number from the beginning (0th). The bit range is specified depending on whether it corresponds to a partition.

According to the examples of FIGS. 12 to 14, in the case of a precision of 64 bits, when j is an even number, it is the 0th partition, and when j is an odd number, it is the 1st partition. In the case of a precision of 32 bits, the 0th partition when mod (j, 4) th = 0, the 1st partition when mod (j, 4) = 1, and mod (j, 4) = 2. Sometimes it is the second section, and when mod (j, 4) = 3, it is the third section. Here, mod (u, v) is a function indicating the remainder when u is divided by v. Further, in the case of a precision of 16 bits, similarly, the "mod (j, 8)" th section from the beginning of the read 128-bit unit bit string is the bit range corresponding to the inverting bit. In the case of a precision of 128 bits, the precision switching circuit 61ax uses the 128-bit unit bit string read in step S26 as a weighting coefficient corresponding to the inverting bit as it is.

In the above example, for the accuracy of 128 / a (a = 1, 2, 4, 8) bits, the 128-bit unit bit string read in step S26 is the "mod (j, a)" th from the beginning. The partition (the size of one partition is 128 / a bit) is a bit range indicating the weighting factor corresponding to the inverting bit.

(S28) The Δh generation unit 62ax generates Δh _i based on the inversion direction of the inversion bit and the weighting coefficient _Wij extracted by the accuracy switching circuit 61ax. Equation (4) is used to generate Δh _i . Further, the inversion direction of the inversion bit is determined by the inversion bit q _j (bit before the inversion this time) output by the random selector unit 52.

(S29) The adder 63ax adds the Δh _i generated by the Δh generation unit 62ax to the local field h _i stored in the h storage register 64ax, so that the local field h _i stored in the h storage register 64ax. To update. Further, the inversion determination unit 65ax determines whether or not the own bit is selected as the inversion bit based on the index = j and the flag F _j output by the random selector unit 52. The inverting determination unit 65ax inverts the spin bit stored in the bit storage register 66ax when the own bit is selected as the inverting bit, and when the own bit is not selected as the inverting bit, the spin bit of the bit storage register 66ax. To maintain. Here, the case where the own bit is selected as the inverting bit is the case where the signal output by the random selector unit 52 has index = j = i and F _j = 1.

(S30) The control unit 25a determines whether or not the number of update processes of each spin bit held in the LFE51a1, ..., LFE51an has reached N1 (the number of update processes = N1) in the current temperature parameter T. judge. When the number of update processes reaches N1, the process proceeds to step S31. If the number of update processes has not reached N1, the control unit 25a adds 1 to the number of update processes and proceeds to step S20.

(S31) The control unit 25a determines whether or not the number of changes in the temperature parameter T has reached N2 (whether the number of temperature changes = N2). When the number of temperature changes reaches N2, the process proceeds to step S33. If the number of temperature changes has not reached N2, the control unit 25a adds 1 to the number of temperature changes and proceeds to step S32.

(S32) The control unit 25a changes the temperature parameter T. Specifically, the control unit 25a reduces the value of the temperature parameter T (corresponding to lowering the temperature) by a lowering width according to the operating conditions. Then, the process proceeds to step S20.

(S33) The control unit 25a reads out the spin bits stored in the bit storage register 66ax and outputs them as an operation result. Specifically, the control unit 25a reads out the spin bits stored in each of the bit storage registers 66a1, ..., 66aK corresponding to the number of spin bits K set by the mode setting register 55, and outputs the spin bits to the CPU 21. That is, the control unit 25a supplies the read spin bit string to the CPU 21. Then, the arithmetic processing is completed.

In step S24, the random selector unit 52 forcibly sets the value of F output by the unused LFE to 0 according to the setting of the mode setting register 55, thereby bit-inverting the unused LFE. Can be excluded from the candidates.

According to the optimization device 25, the mode setting register 55 enables setting of the number of spin bits representing the state of the Ising model and the number of bits of the weighting factor, and in the one-chip optimization device 25, the scale and the scale suitable for the problem are set. Achieve accuracy.

More specifically, the precision switching circuit 61ax switches the bit length of the weighting coefficient read from the SRAM 60ax according to the setting of the mode setting register 55. By using the precision switching circuit 61ax, as shown in step S27, various precisions can be realized without changing the number of unit bits read from the SRAM 60ax by the selector of the precision switching circuit 61ax. For example, the accuracy can be made variable without the need to remake the signal line for reading from the SRAM 60ax by the selector of the accuracy switching circuit 61ax for the number of unit bits.

Further, the random selector unit 52 inputs a signal indicating an inverting bit to a number (for example, K) of LFEs corresponding to the number of spin bits set by the mode setting register 55, and the number (K). Select the inverting bit from the bits corresponding to the LFE of. The random selector unit 52 inputs a signal indicating an inverting bit to the unused n—K LFEs, but forcibly sets the flag F output from the n—K LFEs to 0 (non-invertable). By doing so, unused LFEs are excluded from the selection candidates of the inversion bit.

As a result, the Ising model can be realized with the scale and accuracy according to the problem by one optimization device 25 without individually manufacturing the optimization device having the scale and accuracy according to the problem.

Next, another example of mode setting will be described. For example, the optimization device 25 provides a fifth mode having a scale of 4 kbits / precision of 64 bits in addition to the above-mentioned four modes by storing weighting coefficients in SRAMs 60a1, ..., 60an as follows. You can also do it.

FIG. 17 is a diagram showing an example of storing the coupling coefficient (No. 5).
The data 5d1, 5d2, ..., 5dn show an example of storing weighting coefficients for SRAMs 60a1, 60a2, ..., 60an when the above-mentioned fifth mode (scale 4 kbit / precision 64 bits) is used. Here, n = 8192. The data 5d1, 5d2, ..., 5dn are stored in the SRAMs 60a1, 60a2, ..., 60an, respectively. In this mode, 4k (= 4096) LFEs are used as spin bit strings, and an additional 4k (= 4096) LFEs are used only for storing weighting factors.

The data _5d1 indicates _W0,0 to W0,2047 stored in the SRAM 60a1 of the LFE51a1 (LFE0). The data 5d2 show _W0,2048 to _W0,4095 stored in the SRAM 60a2 of the LFE51a2 (LFE1). The data _5dn shows W 4095, ₂₀₄₈ to W 4095, 4095 stored in SRAM 60an of LFE51an (LFE8911). The number of bits of one weighting coefficient _Wij is 64 bits.

Here, as described above, the accuracy switching circuit 61a1 of the LFE51a1 can also acquire the weighting coefficient from the SRAM 60a2 of the LFE51a2. That is, the precision switching circuit 61a1 can, for example, use a read path from the SRAM 60a2 of the adjacent LFE51a2 to stop the functions of the LFE51a2 other than the SRAM 60a2 and lend the capacity of the SRAM 60a2 to the LFE51a1. For example, the odd-numbered (first is the first) LFE enables the even-numbered LFE SRAM (or, if the first is the 0th, the even-numbered LFE uses the odd-numbered LFE SRAM. It can be said that it is possible).

As described above, in the precision switching circuits 61a1, ..., 61an, in response to the change in the number of bits of the weighting coefficient, a part of the weighting coefficient relating to the own bit and the other bit is used by another LFE that is not used as a spin bit. Read from the SRAM that has. In this case, the random selector unit 52 inverts the bits corresponding to the other LFE by forcibly setting the flag F output from another LFE that is not used as a spin bit to 0 (non-invertable). It may be excluded from the bit selection candidates.

This makes it possible to realize a fifth mode having a scale of 4 kbits and an accuracy of 64 bits. Similarly, by reducing the scale, even greater accuracy can be achieved. Thus, according to the optimizer 25, the scale and accuracy can be changed more flexibly according to the problem.

[Third Embodiment]
Next, a third embodiment will be described. The matters different from the second embodiment described above will be mainly described, and the description of common matters will be omitted.

The third embodiment provides a function of efficiently using LFE in addition to the function of the second embodiment.
Here, since the device configuration of the information processing system and the hardware configuration of the information processing device 20 according to the third embodiment are the same as those in FIGS. 2 and 3, the description thereof will be omitted. The optimization device of the third embodiment is partially different from the optimization device 25 of the second embodiment in the circuit configuration.

FIG. 18 is a diagram showing an example of an optimization device according to a third embodiment.
The optimization device 26 is, for example, a one-chip semiconductor integrated circuit, and is realized by an FPGA or the like. The optimization device 26 is an example of the optimization device 1 of the first embodiment. The optimization device 26 has a plurality of LFBs. The optimization device 26 has a control unit 25a that controls the plurality of LFBs (not shown).

In the third embodiment, as an example, the number of LFEs belonging to one LFB is m (m is an integer of 2 or more), and the optimizer 26 has LFB70a, 70b, 70c, 70d, 70e, 70f, It shall have 70 g and 70 h. In this case, the optimization device 26 has a total of 8 m LFEs and can realize a maximum scale of 8 m bits. However, the number of LFBs included in the optimization device 26 is not limited to eight, and may be another number.

The plurality of LFEs included in the LFB 70a, ..., 70h are examples of the bit operation circuits 1a1, ..., 1aN of the first embodiment. It can be said that each of LFB70a, ..., 70h is one group of LFEs including a predetermined number (m pieces) of LFEs as elements. Further, identification numbers # 0 to # 7 are assigned to each of the LFB 70a, ..., 70h.

The optimization device 26 further includes a scale coupling circuit 91, a mode setting register 92, adders 93a, 93b, 93c, 93d, 93e, 93f, 93g, 93h and E storage registers 94a, 94b, 94c, 94d, 94e, 94f. , 94 g, 94 h.

Here, the LFB 70a has LFE71a1, ..., LFE71am, a random selector unit 72, a threshold value generation unit 73, a random number generation unit 74, and a mode setting register 75. The LFE71a1, ..., LFE71am, the random selector unit 72, the threshold value generation unit 73, the random number generation unit 74, and the mode setting register 75 correspond to the hardware of the same name in the second embodiment described with reference to FIG. Omit. However, the random selector unit 72 outputs a set of state signals (flag F _x0 , spin bit q _x0 , and energy change amount ΔE _x0 ) for the selected inversion bit to the scale coupling circuit 91. Further, the random selector unit 72 does not have to have (but may have) the flag control unit 52a. For example, in the random selector unit 72, two state signals from each LFE are input to each selection circuit in the first stage of the random selector unit 72 without going through the flag control unit 52a. The LFB70b, ..., 70h also have the same circuit configuration as the LFB70a.

The scale coupling circuit 91 receives a state signal from each of the LFB 70a, ..., 70h, and selects an inverting bit based on the state signal. The scale coupling circuit 91 supplies a signal relating to the inverting bit to each LFE of LFB70a, ..., 70h.

Specifically, the scale coupling circuit 91 outputs the flag F _y0 , the bit q _y0 , and index = y0 indicating the inverting bit to the LFE71a1, ..., 71am of the LFB70a1. Here, in the following figures, the notation such as “index = x0” output by the random selector unit 72 and the scale coupling circuit 91 may be abbreviated as “x0”. The scale coupling circuit 91 outputs the energy change amount ΔE _y0 to the adder 93a.

Further, the scale coupling circuit 91 supplies the flag F _y1 , the bit q _y1 , and the index = y1 indicating the inverting bit to each LFE of the LFB 70b. The energy change amount ΔE _y1 is output to the adder 93b.

The scale coupling circuit 91 outputs the flag F _y2 , the bit q _y2 , and index = y2 indicating the inverting bit to each LFE of the LFB 70c. The scale coupling circuit 91 outputs the energy change amount _ΔEy2 to the adder 93c.

The scale coupling circuit 91 outputs the flag F _y3 , the bit q _y3 , and index = y3 indicating the inverting bit to each LFE of the LFB 70d. The scale coupling circuit 91 outputs the energy change amount _ΔEy3 to the adder 93d.

The scale coupling circuit 91 outputs the flag F _y4 , the bit q _y4 , and index = y4 indicating the inverting bit to each LFE of the LFB 70e. The scale coupling circuit 91 outputs the energy change amount ΔE _y4 to the adder 93e.

The scale coupling circuit 91 outputs the flag F _y5 , the bit q _y5 , and index = y5 indicating the inverting bit to each LFE of the LFB 70f. The scale coupling circuit 91 outputs the energy change amount ΔE _y5 to the adder 93f.

The scale coupling circuit 91 outputs the flag F _y6 , the bit q _y6 , and index = y6 indicating the inverting bit to each LFE of the LFB 70 g. The scale coupling circuit 91 outputs the energy change amount ΔE _y6 to the adder 93 g.

The scale coupling circuit 91 outputs the flag F _y7 , the bit q _y7 , and index = y7 indicating the inverting bit to each LFE of the LFB 70h. The scale coupling circuit 91 outputs the energy change amount ΔE _y7 to the adder 93h.

The random selector unit (including the random selector unit 72) and the scale coupling circuit 91 of each of the LFB 70a, ..., 70h are examples of the selection circuit unit 2 of the first embodiment.
The mode setting register 92 sets the operation mode for the scale coupling circuit 91. The mode setting register 92 sets the same operation mode as the operation mode set in the LFE71a1, ..., 71am and the random selector unit 72 by the mode setting register 75 in the scale coupling circuit 91. Details of the mode setting by the mode setting registers 75 and 92 will be described later. The mode setting register (including the mode setting register 75) and the mode setting register 92 of each of the LFB 70a, ..., 70h are examples of the setting change unit 5 of the first embodiment.

The adder 93a updates the energy value E ₀ by adding ΔE _y0 to the energy value E ₀ stored in the E storage register 94a. The E storage register 94a takes in the energy value E ₀ calculated by the adder 93a, for example, in synchronization with a clock signal (not shown) (as well as other E storage registers).

The adder 93b updates the energy value E ₁ by adding ΔE _y1 to the energy value E ₁ stored in the E storage register 94b. _The E storage register 94b takes in the energy value E1 calculated by the adder 93b.

The adder 93c updates the energy value E ₂ by adding ΔE _y2 to the energy value E ₂ stored in the E storage register 94c. The E storage register 94c takes in the energy value E ₂ calculated by the adder 93c.

The adder 93d updates the energy value E ₃ by adding ΔE _y3 to the energy value E ₃ stored in the E storage register 94d. The E storage register _94d takes in the energy value E3 calculated by the adder 93d.

The adder 93e updates the energy value E ₄ by adding ΔE _y4 to the energy value E ₄ stored in the E storage register 94e. The E storage register 94e takes in the energy value E4 calculated by the adder _93e .

The adder 93f updates the energy value E ₅ by adding ΔE _y5 to the energy value E ₅ stored in the E storage register 94f. The E storage register 94f takes in the energy value E5 calculated by the adder _93f .

The adder 93g updates the energy value E ₆ by adding ΔE _y6 to the energy value E ₆ stored in the E storage register 94g. The E storage register 94 g takes in the energy value E ₆ calculated by the adder 93 g.

The adder 93h updates the energy value E ₇ by adding ΔE _y7 to the energy value E ₇ stored in the E storage register 94h. The E storage register 94h takes in the energy value E7 calculated by the adder _93h .

Each of the E storage registers 94a, ..., 94h is, for example, a flip-flop.
Next, a circuit configuration example of the LFB 70a will be described. The LFB70b, ..., 70h also have the same circuit configuration as the LFB70a.

FIG. 19 is a diagram showing an example of an LFB circuit configuration.
Each of LFE71a1, 71a2, ..., 71am is used as one bit of the spin bit. m is an integer of 2 or more, and indicates the number of LFEs included in the LFB70a. In FIG. 19, m = 1024 is set as an example. However, m may be another value.

Identification information (index) is associated with each of LFE71a1, 71a2, ..., 71am. For each of LFE71a1, 71a2, ..., 71am, index = 0,1, ..., 1023.

Hereinafter, the circuit configuration of the LFE71a1 will be described. LFE71a2, ..., 71am are also realized by the same circuit configuration as LFE71a1. Regarding the description of the circuit configuration of LFE71a2, ..., 71am, the "a1" part at the end of the code of each element in the following description is replaced with each of "a2", ..., "Am" (for example, "a2", ..., "am". The code of "80a1" may be replaced with "80am").

The LFE71a1 has an SRAM 80a1, an accuracy switching circuit 81a1, a Δh generation unit 82a1, an adder 83a1, an h storage register 84a1, an inversion determination unit 85a1, a bit storage register 86a1, a ΔE generation unit 87a1, and a determination unit 88a1.

Here, the SRAM 80a1, the precision switching circuit 81a1, the Δh generation unit 82a1, the adder 83a1, the h storage register 84a1, the inversion determination unit 85a1, the bit storage register 86a1, the ΔE generation unit 87a1, and the determination unit 88a1 are described with reference to FIG. 8, respectively. It has the same function as the hardware of the same name. However, the SRAM 80a1 (or the precision switching circuit 81a1) and the inversion determination unit 85a1 are supplied with index = _y0 output by the scale coupling circuit 91 and a flag Fy0 indicating whether or not inversion is possible. Further, the inverting bit q _y0 output by the scale coupling circuit 91 is supplied to the Δh generation unit 82a1.

The mode setting register 75 sets the number of bits (precision) of the weighting coefficient for the precision switching circuits 81a1, 81a2, ..., 81am. The mode setting register 75 does not have a signal line for setting the random selector unit 72 (however, the mode setting register 75 may have the signal line). In the third embodiment, as an example, the following five types of modes shown in the second embodiment can be used.

The first mode is a mode with a scale of 1 kbit / precision of 128 bits. The 1 kbit scale / 128 bit precision mode uses one LFB. The mode can be realized with only one of LFB70a, ..., 70h.

The second mode is a mode with a scale of 2 kbits and a precision of 64 bits. The 2 kbit scale / 64 bit precision mode uses two LFBs. For example, the mode can be realized by any one of a combination of LFB70a and 70b, a combination of LFB70c and 70d, a combination of LFB70e and 70f, and a combination of LFB70g and 70h.

The third mode is a mode having a scale of 4 kbits and a precision of 32 bits. The 4 kbit scale / 32 bit precision mode uses four LFBs. For example, the mode can be realized by any one combination of LFB70a, 70b, 70c, 70d and LFB70e, 70f, 70g, 70h.

The fourth mode is a mode having a scale of 4 kbits and a precision of 64 bits. The 4 kbit scale / 64 bit precision mode uses eight LFBs. The mode can be realized by using a combination of LFB70a, ..., 70h. However, as described with reference to FIG. 17, the number of LFEs used in one LFB is half the number of LFEs included in one LFB.

The fifth mode is a mode with a scale of 8 kbits and a precision of 16 bits. The 8 kbit scale / 16 bit precision mode uses eight LFBs. The mode can be realized by using a combination of LFB70a, ..., 70h.

Further, the optimization device 26 of the third embodiment combines the above-mentioned scale 1 kbit / precision 128 bit mode, scale 2 kbit / precision 64 bit mode, and scale 4 kbit / precision 32 bit mode. Allows operations on the same or other problems to be performed in parallel.

Therefore, the scale coupling circuit 91 combines a plurality of LFBs (combination of LFBs) so as to include a number of LFEs corresponding to the number of spin bits according to the change of the number of spin bits by the mode setting register 92. Select the number (number of groups to combine). The scale coupling circuit 91 has, for example, the following circuit configuration.

FIG. 20 is a diagram showing a circuit configuration example of a scale coupling circuit.
The scale coupling circuit 91 includes a selection circuit 91a1, 91a2, 91a3, 91a4, 91b1, 91b2, 91c1 connected in a tree shape over a plurality of stages, a random number generation unit 91d, and a mode selection circuit 91e1, 91e2, 91e3, 91e4, 91e5. , 91e6, 91e7, 91e8.

Two sets (state signals) of variables qi, Fi, ΔE _i , and index _{= i} output by each of the LFB70a, ..., 70h are input to each of the selection circuits 91a1, ..., 91a4 in the first stage. .. For example, the selection circuit 91a1 has a set of (q _x0 , F _x0 , ΔE _x0 , index = x0) output by LFB70a (# 0) and a set (q _x1 , F _x1 , ΔE) output by LFB70b (# 1). The set of _x1 , index = x1) is input. Further, in the selection circuit 91a2, a set of (q _x2 , F _x2 , ΔE _x2 , index = x2) output by LFB70c (# 2) and a set (q _x3 , F _x3 , ΔE _x3 ) output by LFB70d (# 3) are output. , Index = x3) is input. The selection circuit 91a3 has a set of (q _x4 , F _x4 , ΔE _x4 , index = x4) output by LFB70e (# 4) and a set (q _x5 , F _x5 , ΔE _x5 , index) output by LFB70f (# 5). = The set of x5) is input. In the selection circuit 91a4, a set of (q _x6 , F _x6 , ΔE _x6 , index = x6) output by LFB70g (# 6) and a set (q _x7 , F _x7 , ΔE _x7 , index) output by LFB70h (# 7) = The set of x7) is input.

Then, each of the selection circuits 91a1, ..., 91a4 is one of the two sets (x _i , Fi, ΔE _i , index = _i ) based on the 1-bit random number output by the random number generation unit 91d. Select. At this time, each of the selection circuits 91a1, ..., _91a4 preferentially selects the set in which Fi is 1, and when both sets are 1, one of the sets is selected based on the 1-bit random number. (The same applies to the selection circuits 91b1, 91b2, 91c1). Here, the random number generation unit 91d individually generates a 1-bit random number for each selection circuit and supplies it to each selection circuit. Further, each of the selection circuits 91a1, ..., 91a4 generates an identification value indicating which set is selected based on the index included in both sets, and the selected variables q _i , _{Fi and ΔE i are} used. Outputs a status signal including the identification value. The identification value output by each of the selection circuits 91a1, ..., 91a4 is increased by 1 bit from the input index.

Two state signals output by the selection circuits 91a1, ..., 91a4 are input to each of the selection circuits 91b1 and 91b2 in the second stage. For example, a state signal output by the selection circuits 91a1 and 91a2 is input to the selection circuit 91b1, and a state signal output by the selection circuits 91a3 and 91a4 is input to the selection circuit 91b2.

Then, each of the selection circuits 91b1 and 91b2 selects one of the two state signals based on the two state signals and the 1-bit random number output by the random number generation unit 91d. Further, each of the selection circuits 91b1 and 91b2 updates the identification value included in the selected state signal by adding 1 bit so as to indicate which state signal is selected, and outputs the selected state signal. ..

Two state signals output by the selection circuits 91b1 and 91b2 are input to the selection circuit 91c1 in the final stage. The selection circuit 91c1 selects one of the two state signals based on the two state signals and the 1-bit random number output by the random number generation unit 91d. Further, the selection circuit 91c1 updates the identification value included in the selected state signal by adding 1 bit so as to indicate which state signal is selected, and outputs the selected state signal.

As mentioned above, the identification value corresponds to index. The scale coupling circuit 91 outputs the index corresponding to the inverting bit by selecting the index input from each random selector unit by each selection circuit in the same manner as the variables q _i , _{Fi, and ΔE i .} You may. In this case, each random selector unit receives an index from each LFE together with the variable q and the flag F. It is conceivable that the control unit 25a sets the index according to the combination of LFB for the predetermined index storage register of each LFE.

Each of the mode selection circuits 91e1, ..., 91e8 has an input terminal according to the scale (that is, 1 kbit, 2 kbit, 4 k bit, and 8 kbit). In the figure, "1" represented in each of the mode selection circuits 91e1, ..., 91e8 indicates an input terminal corresponding to a scale of 1 kbit. The “2” indicates an input terminal corresponding to a scale of 2 kbits. The “4” indicates an input terminal corresponding to a scale of 4 kbits (however, an accuracy of 32 bits). The “8” indicates an input terminal corresponding to a scale of 8 kbits (or a scale of 4 kbits / precision of 64 bits).

A status signal output by LFB70a (# 0) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e1. A status signal output by LFB70b (# 1) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e2. A status signal output by LFB70c (# 2) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e3. A status signal output by LFB70d (# 3) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e4. A status signal output by the LFB70e (# 4) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e5. A status signal output by LFB70f (# 5) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e6. A status signal output by LFB70g (# 6) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e7. A status signal output by LFB70h (# 7) is input to the input terminal of the scale 1 kbit of the mode selection circuit 91e8.

The status signal output by the selection circuit 91a1 is input to the input terminal of each scale 2 kbit of the mode selection circuits 91e1 and 91e2. The status signal output by the selection circuit 91a2 is input to the input terminal of each scale 2 kbit of the mode selection circuits 91e3 and 91e4. The status signal output by the selection circuit 91a3 is input to the input terminal of each scale 2 kbit of the mode selection circuits 91e5 and 91e6. The status signal output by the selection circuit 91a4 is input to the input terminal of each scale 2 kbit of the mode selection circuits 91e7 and 91e8.

The status signal output by the selection circuit 91b1 is input to the input terminals of each of the scale 4 kbits of the mode selection circuits 91e1, 91e2, 91e3, 91e4. The status signal output by the selection circuit 91b2 is input to the input terminals of each of the mode selection circuits 91e5, 91e6, 91e7, 91e8 with a scale of 4 kbits.

The status signal output by the selection circuit 91c1 is input to the input terminals of the mode selection circuits 91e1, ..., 91e8 having a scale of 8 kbits.
Each of the mode selection circuits 91e1, ..., 91e8 accepts the setting of the scale (number of spin bits) by the mode setting register 92. However, in FIG. 20, the signal lines for each of the mode selection circuits 91e2, ..., 91e8 from the mode setting register 92 are abbreviated by the notation of "...". Each of the mode selection circuits 91e1, ..., 91e8 selects the state signal input to the input terminal according to the set scale, and shifts (x _j , F _j , index = j) to LFB70a, ..., 70h. Output and output ΔE _j to the adders 93a, ..., 93h.

For example, the mode selection circuit 91e1 outputs (x _y0 , F _y0 , index = y0) to the LFB70a and outputs ΔE _y0 to the adder 93a. The adder 93a updates E ₀ based on ΔE _y0 . The mode selection circuit 91e2 outputs (x _y1 , F _y1 , index = y1) to the LFB 70b and outputs ΔE _y1 to the adder 93b. The adder 93b updates E ₁ based on ΔE _y1 . The mode selection circuit 91e3 outputs (x _y2 , F _y2 , index = y2) to the LFB 70c and outputs ΔE _y2 to the adder 93c. The adder 93c updates E ₂ based on ΔE _y2 . The mode selection circuit 91e4 outputs (x _y3 , F _y3 , index = _y3 ) to the LFB70d, and outputs ΔEy3 to the adder 93d. The adder 93d updates E ₃ based on ΔE _y3 . The mode selection circuit 91e5 outputs (x _y4 , F _y4 , index = y4) to the LFB 70e and outputs ΔE _y4 to the adder 93e. The adder _93e updates E4 based on ΔE _y4 . The mode selection circuit 91e6 outputs (x _y5 , F _y5 , index = _y5 ) to the LFB70f and outputs ΔEy5 to the adder 93f. The adder _93f updates E5 based on ΔE _y5 . The mode selection circuit 91e7 outputs (x _y6 , F _y6 , index = y6) to the LFB 70 g, and outputs ΔE _y6 to the adder 93 g. The adder 93g updates E6 based _on ΔE _y6 . The mode selection circuit 91e8 outputs (x _y7 , F _y7 , index = y7) to the LFB 70h and outputs ΔE _y7 to the adder 93h. The adder _93h updates E ₇ based on ΔE y 7.

That is, the optimization device 26 of the third embodiment selects any bit based on the signal indicating whether or not inversion is possible output from each LFE belonging to a certain LFB (group), and the signal indicating the selected bit. A random selector unit is provided for each LFB to output to the scale coupling circuit 91. The scale coupling circuit 91 combines one or more LFBs according to a change in the number of spin bits, and selects a bit to be inverted based on a signal indicating a bit selected by a random selector unit corresponding to each of the one or more LFBs. do. The scale coupling circuit 91 outputs a signal indicating the bit to be inverted to each LFE belonging to the one or more LFBs.

Here, the mode setting register 92 individually sets the scale for the mode selection circuits 91e1, ..., 91e8. However, in a mode of a certain scale, a common scale is set for the mode selection circuits corresponding to the LFB used in combination.

For example, the mode setting register 92 sets the same number of bits as the number of spin bits in the first spin bit string corresponding to the first combination of LFB and the number of spin bits in the second spin bit string corresponding to the second combination of LFB. It may be set to a number or a different number of bits. Further, the mode setting register of each LFB including the mode setting register 75 sets the number of bits of the weighting factor for the LFE belonging to the first combination of LFB and the number of bits of the weighting factor for the LFE belonging to the second combination of LFB. It may be set to the same number of bits or different number of bits.

For example, when a mode of scale 2 kbit is used by using LFB 70a and 70b in combination, a selection signal for selecting a mode of scale 2 kbit is supplied from the mode setting register 92 to the mode selection circuits 91e1 and 91e2. At this time, for example, the optimization device 26 can execute the same problem as the operation by the LFB 70a and 70b or another problem in parallel by using the remaining 6 LFBs by setting the mode setting register 92. Is. For example, the scale coupling circuit 91 may realize six modes of scale 1 kbit in each of the six LFBs for the remaining six LFBs. Further, the scale coupling circuit 91 may realize three modes having a scale of 2 kbit by combining two of the six LFBs. Further, the scale coupling circuit 91 may realize a scale 2 kbit mode by combining two LFBs out of six LFBs, and may realize a scale 4 kbit mode by combining the other four LFBs.

The combinations of modes realized in parallel are not limited to the above combinations, for example, 8 combinations of scale 1 kbit modes, 4 combinations of scale 2 kbit modes, 4 scale 1 kbit modes and scale 2 kbit. Various combinations are conceivable, such as a combination of two modes.

In this way, the scale coupling circuit 91 accepts the setting of the number of spin bits for each of the plurality of spin bit strings by the mode setting register 92, and the number of LFBs (group) to be combined with respect to the number of spin bits for each of the plurality of spin bit strings. Number) is selected and the LFB is combined. As a result, a plurality of Ising models can be realized on one optimization device 26.

In addition, common energy is stored in the set of E storage registers corresponding to the set of LFB used in combination. For example, when used in combination with LFB 70a and 70b, E ₀ and E ₁ stored in the E storage registers 94a and 94b have the same value. In this case, when reading the energy value for the set of the LFB 70a and 70b, the control unit 25a inputs the energy value stored in one of the E storage registers 94a and 94b (for example, the E storage register 94a corresponding to the LFB 70a). It should be read out. The control unit 25a reads out the energy value for other combinations of LFB in the same manner.

In the third embodiment, the control unit 25a receives inputs from the CPU 21 of initial values and operating conditions for each problem to be calculated in parallel as step S10 in FIG. Then, in step S11, the control unit 25a sets the scale / accuracy corresponding to each problem in the mode setting register and the mode setting register 92 of the LFB for each group of LFB used for one problem.

For example, regarding the first problem, the control unit 25a sets the scale 2 kbit / precision 64 bits in the mode setting registers of the LFB 70a and 70b, and sets the mode so that the mode selection circuits 91e1 and 91e2 output the scale 2 kbit. Set to register 92. Further, regarding the second problem, the control unit 25a sets the scale 2 kbit / precision 64 bits in the mode setting register of the LFB 70c and 70d, and sets the mode so that the mode selection circuits 91e3 and 91e4 output to the scale 2 kbit. Set to register 92.

In this case, the optimization device 26 can calculate two problems (or both problems may be the same problem) in parallel. Specifically, the control unit 25a controls each LFB so as to perform the procedure of the flowchart shown in FIG. 16 for the combination of LFBs corresponding to each problem. For example, the control unit 25a individually accepts the initial values of various parameters such as the temperature parameter T, the weighting factor, the number of bit updates and the number of temperature changes in a certain temperature parameter for each problem, and the corresponding problem. Input to each LFB belonging to the combination of LFB to perform the calculation, and execute the calculation in parallel by each combination of LFB.

After the calculation is completed, the control unit 25a reads out the spin bit string for the first problem from each LFE of the LFB 70a and 70b to solve the first problem. Further, the control unit 25a reads out the spin bit string for the second problem from each LFE of the LFB 70c and 70d after the calculation is completed, and uses it as a solution to the second problem. Problems of 3 or more can be calculated in parallel in the same manner. This makes it possible to efficiently execute operations for a plurality of problems.

Further, when solving the same problem in parallel by a plurality of sets of LFBs, it is conceivable that the control unit 25a speeds up the calculation by, for example, a method called a replica exchange method. In the replica exchange method, the spin bit strings are updated with different temperature parameters in each set of LFB (each replica), and after a predetermined number of updates, the temperature parameters are exchanged between the sets of LFB (that is, between replicas) with a predetermined probability. This speeds up the search for a solution.

Alternatively, as a method of searching for a solution, a method of repeating the procedure from the start to the end of FIG. 16 and finding the spin bit string of the minimum energy from a plurality of calculation results as a solution can be considered. In this case, the control unit 25a can reduce the number of repetitions and speed up the calculation by solving the same problem in parallel using a plurality of sets of LFBs.

By the way, problems in various fields can be considered as the optimization problem that can be calculated by using the optimization devices 25 and 26 exemplified in the second and third embodiments. For example, the scale of the required problem and the accuracy of the expression of the problem may change depending on the field such as academics and industry.

FIG. 21 is a diagram showing an example of the required range of scale / accuracy for each problem.
In the graph 400, the horizontal axis is the scale ratio (degree of indicating the magnitude of scale) and the vertical axis is the accuracy ratio (degree of indicating the magnitude of accuracy), and the range of scale accuracy required for problems in three types of fields. Is illustrated. The scale ratio is the ratio of the scale value (number of spin bits) actually required to the scale reference value that is the standard of scale. The accuracy ratio is the ratio of the actually required accuracy value (the number of bits of the coupling coefficient) to the accuracy reference value that is the reference of accuracy.

Region 401 shows the range of scale ratio / accuracy ratio required for problems in the power field. Area 402 shows the range of scale / accuracy ratios required for problems in the financial sector. Area 403 shows the range of scale / accuracy ratios required for problems in the field of life sciences.

For example, according to region 401, problems in the power field often require a relatively high accuracy ratio. Further, according to the area 402, in the problem of the financial field, the scale ratio may be relatively small, but a relatively high accuracy ratio may be required. Further, in the field of life science, the accuracy ratio may be relatively low, but a relatively large scale ratio may be required. However, the scale ratio / accuracy ratio required in each field illustrated here is an example, and the range of the required scale ratio / accuracy ratio may change depending on the problems dealt with in each field in the future.

On the other hand, it is conceivable to manufacture an optimization device suitable for the scale and accuracy of each problem, but it is not efficient.
Therefore, in the second and third embodiments, the combinatorial optimization problems in various fields can be dealt with by making it possible to realize modes of various scales / accuracy by the optimization devices 25 and 26 of one chip. become.

FIG. 22 is a diagram showing an example of a selectable range of scale accuracy.
Graph 500 shows an example of the selectable range of scale accuracy that can be achieved by the optimizers 25 and 26. Here, it is assumed that the upper limit of the capacity reserved for storing the weighting coefficient in the SRAM for each LFE is 128 kbits, and the number of LFEs in each of the optimization devices 25 and 26 is n = 8192. As described above, the optimizers 25 and 26 can realize, for example, five types of modes. However, other scale / accuracy modes may be available within the range indicated by the hatched area of graph 500. By increasing the capacity of the SRAM for each LFE, a larger scale / accuracy mode can be realized.

In the optimization devices 25 and 26, various usage patterns of each LFE are realized after making the scale / accuracy mode variable.
FIG. 23 is a diagram showing an example of an LFE usage pattern.

FIG. 23 (A) shows an example (No. 1) of the use pattern of n LFEs that can be realized in the second and third embodiments. For example, the optimization device 26 realizes the first Ising model X by using the LFE group 710 (that is, the first combination of LFBs) including α LFEs out of n LFEs. Further, the optimization device 26 does not use the LFE group 720 including the remaining β LFEs. Similarly, the optimization device 25 may realize the first Ising model X by the LFE group 710 and may not use the LFE group 720.

FIG. 23B shows an example of the use pattern of n LFEs (No. 2) that can be realized in the third embodiment. For example, the optimization device 26 realizes the first Ising model X by using the LFE group 710 (that is, the first combination of LFBs) including α LFEs out of n LFEs. Further, the optimization device 26 realizes the first Ising model X by using the LFE group 730 (that is, the second combination of LFB) including α LFEs among the remaining LFEs. By increasing the degree of parallelism of operations for the same problem, the convergence of the solution can be accelerated and the operations can be speeded up.

FIG. 23C shows an example of the use pattern of n LFEs (No. 3) that can be realized in the third embodiment. For example, the optimization device 26 realizes the first Ising model X by using the LFE group 710 (that is, the first combination of LFBs) including α LFEs out of n LFEs. Further, the optimizing device 26 uses an LFE group 740 (that is, a second combination of LFBs) containing γ (may be γ = α or γ ≠ α) LFEs among the remaining LFEs. , The second Ising model Y is realized. This makes it possible to calculate different problems in parallel.

Next, an example of the usage flow of the optimization device 26 by the user will be described. In the following, the optimization device 26 is mainly illustrated, but the same usage flow is also applied to the optimization device 25.
FIG. 24 is a diagram showing an example of a usage flow of the optimization device.

(S101) The CPU 21 receives data 601 indicating a problem that the user wants to solve from the client 30 via the NIC 24. The client 30 and the NIC 24 realize an input unit for inputting various data to the information processing device 20 and a notification unit for notifying the user of the solution obtained as a result of the ground state search as result information that is easy for the user to understand. .. The CPU 21 converts the data 601 into a search problem of the ground state of the Ising model by the function of the library 21a. As a result, the CPU 21 includes scale data 611 indicating the scale (number of spin bits) of the problem, accuracy data 612 indicating the accuracy of expressing the problem, energy data 613 indicating the initial value of energy, and a scale accuracy mode according to the scale / accuracy. Generate data 614. The scale data 611 may be binary data indicating a spin bit string. The accuracy data 612 may include a weighting factor between spin bits represented by the accuracy. The CPU 21 determines an appropriate scale accuracy mode from the problem and generates scale accuracy mode data 614.

(S102) The CPU 21 inputs the scale data 611, the accuracy data 612, and the energy data 613 to the control unit 25a as initial values.
(S103) The CPU 21 accepts the input of the user-specified operating condition 602. The user-specified operating condition 602 includes, for example, the number of state updates in a certain temperature parameter, the number of times the temperature parameter is updated, the amount of decrease in the temperature parameter, the initial value of the temperature parameter, and the like. Further, the user-specified operating condition 602 may include the number of LFBs to be combined. The CPU 21 includes the number of LFBs to be combined in the scale accuracy mode data 614. The CPU 21 inputs the scale accuracy mode data 614 and the user-specified operating condition 602 to the control unit 25a as operating conditions. The scale accuracy mode data 614 is set in the mode setting register and the mode setting register 92 of each LFE including the mode setting register 75.

(S104) When the steps S102 and S103 are completed, the CPU 21 instructs the control unit 25a to start executing the operation for searching the ground state.
(S105) When the calculation by the optimization device 26 is completed, the CPU 21 acquires the calculation result 615 from the optimization device 26 and converts it into result information (for example, information on the result display screen) that is easy for the user to understand. The CPU 21 transmits the converted result information to the client 30 as a solution 616 of the problem that the user wants to solve.

In this way, the CPU 21 determines the number of spin bits and the number of bits of the weighting factor according to the problem input by the user. The control unit 25a receives information indicating the number of spin bits, the number of bits of the weighting coefficient, and the weighting coefficient from the CPU 21. The control unit 25a sets the number of spin bits and the number of bits of the weighting factor in the mode setting register 55 (or the mode setting registers 75 and 92). The control unit 25a stores in each SRAM of the number of LFEs corresponding to the number of spin bits.

In this way, the user can execute the calculation by the optimization devices 25 and 26 with the scale / accuracy according to the problem he / she wants to solve. For example, the optimization device 26 can calculate the same problem or different problems by the same user in parallel. In addition, the optimization device 26 can calculate different problems by different users in parallel. That is, by making it possible to calculate with an appropriate scale / accuracy according to the problem to be solved, it becomes possible to calculate other problems in parallel using the free LFB (or free LFE). Further, the optimization devices 25 and 26 of one chip can be shared by a plurality of users. Further, the optimization devices 25 and 26 of one chip can be shared due to a plurality of problems.

Further, an optimization device (or an optimization system) having the functions exemplified above can be considered. The optimization device (or optimization system) has an input unit, a conversion unit, a control unit, and a display unit.

The input unit inputs the problem to be solved and the operating conditions. The input unit may be, for example, an input device such as a mouse or a keyboard, or may be realized by a NIC (for example, NIC 24) and a client terminal (for example, a client 30).

The conversion unit converts the input problem into a search problem in the base state of the search problem, scale information indicating the scale of the search problem, accuracy information indicating the accuracy of the expression of the search problem, and the initial value of the energy of the search problem. The energy information representing the above and the scale accuracy mode information according to the scale and accuracy are generated. The conversion unit may be, for example, a processor such as a CPU (for example, CPU 21) that exerts the functions of the library 21a and the driver 21b. The conversion unit may be realized by a semiconductor integrated circuit such as FPGA.

The control unit inputs the scale information, the accuracy information, and the energy information (or the initial value of the spin bit string, the coupling coefficient, and the initial value of the energy according to the scale information, the accuracy information, and the energy information), and also sets the operating conditions. The scale accuracy mode information is input, the operation for searching the base state is executed, and the solution is output. For example, the control unit sets the initial value of the spin bit string according to the scale information, the accuracy information, and the energy information (or the scale information, the accuracy information, and the energy information) for the LFB50 (or LFB70a, ..., 70h). It may be a control unit 25a that inputs (initial values of coupling coefficient and energy), inputs operating conditions and scale accuracy mode information, executes an operation to search for a base state using LFB, and outputs a solution. The control unit may be, for example, a semiconductor chip including the control unit 25a and the LFB50 (or LFB70a, ..., 70h), and may be a semiconductor chip that searches for the ground state of the Ising model. That is, the control unit has scale information, accuracy information, energy information (or a spin bit string of the number of bits according to the scale information, a coupling coefficient of the number of bits according to the accuracy information, and an initial value of energy according to the energy information. ), And a semiconductor chip that outputs a solution by executing an operation for searching the base state of the rising model based on the operating conditions and the scale accuracy mode information. The scale information may be represented by a scale ratio to a scale reference value that serves as a scale reference. The accuracy information may be represented by an accuracy ratio to an accuracy reference value that is an accuracy reference.

The display unit displays the solution obtained as a result of the search for the ground state by the control unit. The display unit may be a display, or may be realized by a NIC and a client terminal. For example, the conversion unit converts the solution obtained as a result of the search for the ground state into the visualized display information. The display unit displays the visualized display information.

The scale / accuracy can be varied by the optimized device illustrated. The user can execute the calculation by the optimization device according to the scale / accuracy according to the problem to be solved.
The control of the optimization device 1 according to the first embodiment may be realized by executing a program by a processor included in the computer that controls the optimization device 1. For example, the program is stored in the RAM of the computer. The control of the optimization devices 25 and 26 according to the second and third embodiments may be realized by causing the CPU 21 to execute a program. The program can be recorded on a computer-readable recording medium 41.

For example, the program can be distributed by distributing the recording medium 41 on which the program is recorded. Alternatively, the program may be stored in another computer and distributed via the network. For example, the computer may store (install) a program recorded on the recording medium 41 or a program received from another computer in the DRAM 22 or the storage device 23, read the program from the DRAM 22 or the storage device 23, and execute the program. good.

The above merely indicates the principle of the present invention. Further, numerous modifications and modifications are possible to those skilled in the art, and the invention is not limited to the exact configurations and applications described and described above, and all corresponding modifications and equivalents are attached. It is considered to be the scope of the present invention according to the claims and their equivalents.

1 Optimizer 1a1, ..., 1aK, ..., 1aN Bit calculation circuit 2 Selection circuit part 3 Threshold generation part 4 Random number generation part 5 Setting change part 6 Control part 11 Storage part 12 Precision switching circuit 13 Inversion judgment part 14 Bit holding part 15 Energy change calculation unit 16 State transition determination unit

Claims (18)

A storage unit that stores a coefficient indicating the magnitude of interaction between bits in a bit string representing the state of the Ising model, and a storage unit.
When any bit in the bit string is inverted, the energy change of the Ising model is calculated using the coefficient corresponding to the inverted bit read from the storage unit and its own bit. Multiple bit operation circuits that output a signal indicating whether or not the local bit can be inverted, and
The signal indicating the bit to be inverted among the bit strings selected based on the signal indicating whether or not the inversion is possible output from each of the bit operation circuits having the first number of bits of the bit string among the plurality of bit operation circuits is referred to as the first signal. A selection circuit unit that outputs to each of the bit operation circuits with a bit number of 1 and
A setting change unit for changing the number of the first bit for the selection circuit unit and changing the second bit number of the coefficient for each of the bit operation circuits with the first bit number.
Optimizer with. Each of the plurality of bit operation circuits has an accuracy switching circuit that changes the number of second bits of the coefficient read from the storage unit in response to the change of the number of second bits by the setting change unit.
The optimization device according to claim 1. The storage unit is provided in each of the plurality of bit operation circuits.
The precision switching circuit uses a part of the coefficients related to the own bit and the other bit in response to the change of the second number of bits by the setting change unit, and the bit string of the plurality of bit calculation circuits. Read from the storage unit of another bit operation circuit that is not used for
The optimization device according to claim 2. The plurality of bit operation circuits are divided into a plurality of groups, and the plurality of bit operation circuits are divided into a plurality of groups.
The selection circuit unit is one or more so as to include the bit operation circuit having the first bit number among the plurality of bit operation circuits in response to the change of the first bit number by the setting change unit. Has a scale coupling circuit that combines groups,
The optimization device according to claim 1. The selection circuit unit has a plurality of selector units that output a signal indicating a selected bit based on a signal indicating whether or not inversion is possible, which is output from each bit operation circuit belonging to one group, to the scale coupling circuit. Have for each of the groups
Each of the scale coupling circuits belongs to the one or more groups of signals indicating the bits to be inverted selected based on the signal indicating the bits selected by the selector unit corresponding to each of the one or more groups. Output to the bit operation circuit,
The optimization device according to claim 4. The scale coupling circuit accepts the setting of the first bit number for each of the plurality of bit strings by the setting change unit, and combines the one or more groups for each of the plurality of bit strings.
The optimization device according to claim 4. A control unit that executes an operation on the Ising model by the first combination and an operation on the Ising model or another Ising model by the second combination in parallel among a plurality of combinations of groups.
6. The optimization device according to claim 6. The setting change unit is the first bit of the first bit number corresponding to the first combination and the first bit of the second bit string corresponding to the second combination among the plurality of combinations of the group. Set the number to the same number of bits or a different number of bits,
The optimization device according to claim 6. The setting changing unit determines the number of the second bit for the bit operation circuit belonging to the first combination and the number of the second bit for the bit operation circuit belonging to the second combination among the plurality of combinations of the group. Set to the same number of bits or different number of bits,
The optimization device according to claim 6. The selection circuit unit forcibly sets a signal indicating whether or not inversion is possible, which is output by a bit operation circuit other than the bit operation circuit having the first number of bits, among the plurality of bit operation circuits. A signal indicating whether or not the bit can be inverted, which is output by the bit operation circuit having the first number of bits, and a signal indicating the bit to be inverted selected based on the signal indicating non-inversion set for the other bit operation circuit. Is output not only to the bit operation circuit having the first number of bits but also to the other bit operation circuit.
The optimization device according to claim 1. The arithmetic unit that determines the number of the first bit and the number of the second bit according to the input problem accepts the input of information indicating the number of the first bit and the number of the second bit. A control unit that inputs the first bit number and the second bit number to the setting change unit.
The optimization device according to claim 1, further comprising. In the control method of the optimizer
When any bit of the bit string representing the state of the Ising model is inverted in the plurality of bit arithmetic circuits of the optimizer, the magnitude of the interaction between the own bit in the bit string and the other bit. A signal indicating whether or not the own bit can be inverted is output according to the calculation of the energy change of the Ising model using the coefficient corresponding to the inverted bit read from the storage unit that stores the coefficient indicating the above.
The selection circuit unit of the optimizer selects the bit string of the plurality of bit operation circuits based on a signal indicating whether or not inversion is possible, which is output from each of the bit operation circuits having the first number of bits of the bit string. A signal indicating the bit to be inverted is output to each of the bit operation circuits having the first number of bits.
The setting change unit of the optimizer changes the number of the first bits with respect to the selection circuit unit and changes the number of second bits of the coefficient with respect to each of the bit operation circuits having the first number of bits. I do,
How to control the optimizer. In the control program of the optimizer
When any bit of the bit string representing the state of the Ising model is inverted in the plurality of bit arithmetic circuits of the optimizer, the magnitude of the interaction between the own bit in the bit string and the other bit. A signal indicating whether or not the own bit can be inverted is output according to the calculation of the energy change of the Ising model using the coefficient corresponding to the inverted bit read from the storage unit that stores the coefficient indicating the above.
The bit string selected in the selection circuit unit of the optimizer based on a signal indicating whether or not inversion is possible, which is output from each of the bit operation circuits having the first number of bits of the bit string among the plurality of bit operation circuits. A signal indicating the bit to be inverted is output to each of the bit operation circuits having the first number of bits.
In the setting change unit of the optimizer, the change of the first bit number for the selection circuit unit and the change of the second bit number of the coefficient for each of the bit operation circuits of the first bit number. To do,
Optimizer control program. An input section for inputting the problem to be solved and operating conditions,
The input problem is converted into a search problem in the base state of the rising model, scale information indicating the scale of the search problem, accuracy information indicating the accuracy of the expression of the search problem, and the initial value of the energy of the search problem. A conversion unit that generates energy information representing the above and scale accuracy mode information according to the scale and accuracy.
A control unit that inputs the scale information, the accuracy information, the energy information, the operating conditions, and the scale accuracy mode information, executes an operation for searching the ground state, and outputs a solution.
A display unit that displays the solution obtained as a result of the search for the ground state by the control unit, and a display unit.
Optimizer with. The conversion unit converts the solution obtained as a result of the search for the ground state into visualized display information.
The display unit is the optimization device according to claim 14, which displays the visualized display information. The scale information is represented by a scale ratio to a scale reference value that serves as a scale reference.
The accuracy information is represented by an accuracy ratio to an accuracy reference value that is an accuracy reference.
The optimization device according to claim 14 or 15. In the control method of the optimizer
The input unit of the optimizer inputs the problem to be solved and the operating conditions, and then
The conversion unit of the optimizer converts the input problem into a search problem in the base state of the rising model, scale information indicating the scale of the search problem, and accuracy information indicating the accuracy of the expression of the search problem. And energy information representing the initial value of the energy of the search problem, and scale accuracy mode information according to the scale and accuracy are generated.
The control unit of the optimizer inputs the scale information, the accuracy information, the energy information, the operating conditions, and the scale accuracy mode information, and executes a calculation for searching the ground state. And output the solution,
The display unit of the optimizer displays the solution obtained as a result of the search for the ground state by the control unit.
How to control the optimizer. In the control program of the optimizer
The problem to be solved and the operating conditions are input from the input unit of the optimizer.
The conversion unit of the optimizer converts the input problem into a search problem in the base state of the rising model, scale information indicating the scale of the search problem, and accuracy information indicating the accuracy of the expression of the search problem. And energy information representing the initial value of the energy of the search problem, and scale accuracy mode information according to the scale and accuracy are generated.
The scale information, the accuracy information, and the energy information are input to the control unit of the optimization device, and the operating conditions and the scale accuracy mode information are input to execute a calculation for searching the ground state. And output the solution,
The display unit of the optimizer displays the solution obtained as a result of the search for the ground state by the control unit.
Optimizer control program.

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