JP7000892B2 - Memory management program, memory management method, and memory management device - Google Patents

Description

The present invention relates to a memory management program, a memory management method, and a memory management device.

When the size of the data to be written to the memory exceeds the size of the memory area secured in advance due to a program design error or the like, a memory overrun (hereinafter referred to as an overrun) occurs. Then, when the Operating System (OS) detects an overrun, as an exception handling, for example, the application that caused the overrun is forcibly terminated.

As a related technique, a technique has been proposed in which the issuance of an instruction for executing an algorithm for allocating dynamic memory is hooked and the contents in the area of the address secured by executing the algorithm for allocating dynamic memory are inspected. (See, for example, Patent Document 1).

Further, as a related technique, a technique has been proposed in which a file I / O issuance request of the file server application unit is hooked and information of a file to be accessed is acquired from the hooked file I / O issuance request (for example). See Patent Document 2).

Further, as a related technology, a technology has been proposed in which the management table is updated at the time of file update and the file area is expanded when it is determined from the contents of the management table that there is a possibility of overflow in the next processing (for example). See Patent Document 3).

Japanese Unexamined Patent Publication No. 2016-42318 Japanese Unexamined Patent Publication No. 2013-196066 Japanese Unexamined Patent Publication No. 5-233391

If the application is forcibly terminated due to an overrun, it may hinder the business of the user who uses the application.

In order to prevent overrun, for example, it is conceivable that the application secures a memory area obtained by adding a marginal size to the size required for allocating memory. However, it is difficult to determine how much size can be secured to prevent overrun when securing memory. Further, when there is no margin in the memory capacity, it is difficult to secure the spare memory.

As one aspect, it is an object of the present invention to suppress forced termination of an application in the event of an overrun.

In one embodiment, when the memory management program detects in the computer an instruction to secure the first area in the memory, it records information indicating the first area and issues an instruction to write data to the first area. When detected, it is determined whether the data can be written in the first area based on the write command and the information indicating the first area, and the data cannot be written in the first area. When it is determined, a second area different from the first area is secured in the memory, a part of the data is written to the first area, and an instruction to write the remaining part of the data to the second area is output. To execute the process to be performed.

According to one aspect, it is possible to suppress the forced termination of the application in the event of an overrun.

An example of the overall configuration of the system in the embodiment is shown. It is a figure which shows an example of a memory management part. It is a figure which shows an example of the 1st area management table. It is a figure which shows an example of the 2nd area management table. It is a figure which shows an example of the 2nd area management table when expansion is performed a plurality of times. It is a figure which shows the expansion method of the memory area. It is a figure which shows an example of a trace table. It is a figure which shows an example of the information about the writing of data to a 2nd area. It is a figure which shows an example of the information about reading of data from a 2nd area. It is a flowchart which shows an example of the setting process of an embodiment. It is a flowchart which shows an example of the process of a memory management part. It is a flowchart which shows an example of the memory allocation monitoring process in step S203 of FIG. It is a flowchart which shows an example of the memory write monitoring process in step S205 of FIG. FIG. 1 is a flowchart (No. 1) showing an example of the memory read monitoring process in S207 of FIG. FIG. 2 is a flowchart (No. 2) showing an example of the memory read monitoring process in S207 of FIG. This is the source code used for the monitored application in the embodiment. It is a figure which shows the assembler code about the memory allocation processing in an Example. It is a figure which shows the trace table in the memory allocation processing of an Example. It is a figure which shows the 1st area management table in an Example. It is a figure which shows the reserved memory area in an Example. It is a figure which shows the assembler code about the memory write processing in an Example. It is a figure which shows the trace table in the memory write processing of an Example. It is a figure which shows the 2nd area management table and the 1st area management table after the writing process in an Example. It is a figure which shows the expansion method of the memory area in an Example. It is an assembler code about the memory read processing in an Example. It is a figure which shows the trace table in the memory read process of an Example. It is a figure which shows the memory area in the read process of an Example. It is a figure which shows an example of the hardware composition of an information processing apparatus.

Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows an example of the overall configuration of the system in the embodiment. The system in the embodiment includes an information processing device 1 and a display device 2. The information processing device 1 is an example of a computer.

The information processing apparatus 1 includes an OS 11, a memory management unit 12, a management information storage unit 13, a setting unit 14, and applications 15-1 to 15-n. Hereinafter, when application 15-1 to application 15-n are not distinguished, they are referred to as application 15.

The OS 11 performs processing such as allocating memory, writing data to the memory, and reading data from the memory in response to an instruction from the application 15. Further, the OS 11 performs processing according to an instruction from the memory management unit 12.

The memory management unit 12 manages the memory usage status by the application 15. Further, the memory management unit 12 hooks an instruction regarding memory access from the application 15 to the OS 11, and outputs an instruction different from the hooked instruction to the OS 11 according to a predetermined condition.

The memory management unit 12 hooks an instruction from the application 15 to the OS 11 by, for example, acquiring an assembler code from an executable file of the application 15 and performing analysis. Hereinafter, acquiring the assembler code from the executable file of the application 15 and performing analysis may be referred to as assembler analysis. The memory management unit 12 operates, for example, as a filter driver for monitoring the processing of the application 15 for the OS 11. The details of the memory management unit 12 will be described later.

The management information storage unit 13 stores various management information used for memory management by the memory management unit 12. Details of the management information will be described later.

The setting unit 14 makes various settings related to memory management. The setting unit 14 registers the hook module in the information processing device 1. The hook module is a program module realized by the memory management unit 12.

Application 15 is software that runs on OS 11. The application 15 mounted on the information processing apparatus 1 may be one or a plurality.

The display device 2 can communicate with the information processing device 1 and displays the information output from the information processing device 1. The display device 2 displays, for example, the information generated by the memory management unit 12. The display device 2 may be included in the information processing device 1.

FIG. 2 is a diagram showing an example of the memory management unit 12. The memory management unit 12 includes a detection unit 21, a recording unit 22, a write determination unit 23, a write instruction unit 24, a read determination unit 25, a read instruction unit 26, and an output unit 27.

The detection unit 21 detects that the application 15 to be monitored outputs a memory securing instruction, a data writing instruction to the memory, or a data reading instruction from the memory to the OS 11. The detection unit 21 detects, for example, by hooking an instruction from the application 15 to the OS 11. Hereinafter, the application 15 to be monitored is referred to as a monitored application.

When the detection unit 21 detects an instruction for securing an area (first area) in the memory, the recording unit 22 records information indicating the first area in the first area management table. The first area management table is stored in the management information storage unit 13.

When the detection unit 21 detects a data write command to the first area of the memory, the write determination unit 23 is based on the write command and the information indicating the first area recorded in the first area management table. It is determined whether the data can be written in the first area. Hereinafter, the data specified as the write target in the write command is referred to as the write target data.

When the write determination unit 23 determines that the write target data cannot be written in the first area, the write instruction unit 24 outputs an instruction to secure a second area different from the first area in the memory to the OS 11. Further, the write instruction unit 24 outputs an instruction to write an instruction to write a part of the data to be written to the first area and write the remaining part to the second area to the OS 11.

Based on the instruction from the write instruction unit 24, the OS 11 newly secures a second area, writes a part of the data in the first area, and writes the remaining part in the second area.

When the write determination unit 23 determines that the write target data cannot be written to the first area, the recording unit 22 associates the information indicating the second area with the information indicating the first area and puts it in the second area management table. Record. The information indicating the second area is, for example, the start address of the second area and the reserved memory size. The second area management table is stored in the management information storage unit 13.

When the write determination unit 23 determines that the write target data is not writable in the first area, the output unit 27 outputs information regarding writing of the data to the second area.

In this embodiment, when the write instruction unit 24 instructs the OS 11 to write data in the second area, it is considered that an overrun has occurred.

When the detection unit 21 detects a read command, the read determination unit 25 determines whether at least a part of the read target area is included in the second area based on the read command and the information indicating the first area. judge. Hereinafter, the data specified as the read target in the read command is referred to as the read target data.

When the read instruction unit 26 determines that at least a part of the read target area is included in the second area, the read instruction unit 26 outputs an instruction to read at least a part of the read target data from the second area to the OS 11. The read instruction unit 26 specifies a second area to be instructed to the OS 11 based on the information indicating the second area associated with the information indicating the first area.

When the read determination unit 25 determines that at least a part of the read target area is included in the second area, the output unit 27 outputs information regarding reading of data from the second area.

The output unit 27 may generate, for example, information regarding writing data to the second area or reading data from the second area and display it on the display device 2. Further, the output unit 27 may transmit the generated information to another information processing device or the like (for example, a management server) capable of communicating with the information processing device 1.

FIG. 3 is a diagram showing an example of the first area management table. As shown in FIG. 3, the first area management table includes a module name, a handle name, a base address, a size, and a link identification (ID). The handle name, Base address, and size recorded in the first area management table are examples of information indicating the first area. Each item of the first area management table is recorded by the recording unit 22 when the detection unit 21 detects an instruction for securing the first area in the memory.

The "module name" indicates the module name of the program that outputs the memory allocation instruction to the OS 11. "Handle name" indicates a handle name used for memory allocation. The "base address" indicates the start address of the reserved memory. “Size” indicates the size of the memory to be allocated [byte]. The "link ID" is an example of information that associates the first area with the second area.

The information recorded in the first area management table is not limited to the information shown in FIG. For example, the information recorded in the first area management table may include the end address of the first area to be secured.

FIG. 4 is a diagram showing an example of the second area management table. The second area management table includes a link ID, a Base address, and a size. The Base address and size are examples of information indicating the second region. When the second area is secured, the recording unit 22 records each item of the second area management table.

The "link ID" corresponds to the link ID in the first area management table shown in FIG. The recording unit 22 records the same link ID as the link ID associated with the base address and size of the first region of the expansion source in association with the base address and size of the second region.

The "Base address" indicates the start address of the memory in the second area. “Size” indicates the memory size [byte] of the second area.

The information recorded in the second area management table is not limited to the information shown in FIG. For example, the information recorded in the second area management table may include the end address of the second area to be secured.

The first area management table and the second area management table may be one table. For example, when the second area is secured, the recording unit may record the Base address and size of the second area in the first area management table in association with the information indicating the first area.

FIG. 5 is a diagram showing an example of a second area management table when expansion is performed a plurality of times. The second area management table 1 shown in FIG. 5A is a table generated when the first expansion (securing of the second area) is performed, and is linked to the second area management table shown in FIG. This is a configuration in which ID'is added. The recording unit 22 records the link ID, the base address, and the size in the second area management table 1 when the first expansion is performed.

The second area management table 2 shown in FIG. 5B is a table generated when the second expansion is performed. The second area management table 2 includes a link ID ′, a link ID ″, a base address, and a size. The link ID'of the second area management table 2 corresponds to the link ID'of the second area management table 1. That is, the link ID'is information that associates the second region secured for the first time with the second region secured for the second time.

For example, when a write command for data exceeding the total size of the first area and the second area is output after the first securing of the second area is performed, another second area is secured and the recording unit is used. 22 generates the second area management table 2. Then, the recording unit 22 records the link ID', the base address, and the size of the second area management table 2. Further, the recording unit 22 records the same ID as the link ID'recorded in the second area management table 2 in the link ID'of the second area management table 1.

The link ID ″ is recorded to associate the second area secured for the second time with the second area secured for the third time when the second area is secured for the third time. Therefore, the recording unit 22 does not record the link ID ″ at the time when the second region is secured for the second time.

FIG. 6 is a diagram showing a method of expanding the memory area. In the example shown in FIG. 6, it is assumed that the OS 11 secures the first area A, the first area B, and the first area C in response to the instruction to secure the memory. Further, it is assumed that the monitored application outputs a write command for data exceeding the size of the first area A, and the OS 11 secures the second area A corresponding to the first area A. Further, it is assumed that the monitored application outputs a write command for data exceeding the size of the first area B, and the OS 11 secures the second area B corresponding to the first area B. That is, one piece of data is divided and stored in the first area A and the second area A. Further, one piece of data is divided and stored in the first area B and the second area B.

As shown in FIG. 6, when the second area is secured, the second area and the expansion source first area may not be continuous areas on the memory. In the present embodiment, as shown in FIGS. 3 to 5, in the first area management table and the second area management table, the information indicating the first area and the information indicating the second area are associated with each other by the link ID. There is. Therefore, when at least a part of the read target area is included in the second area, the read instruction unit 26 specifies the second area included in the read target area, and tells the OS 11 to read the data from the specified second area. Can be instructed.

FIG. 7 is a diagram showing an example of a trace table. The trace table is a table showing the correspondence between registers and handles. The recording unit 22 records the handle name of the handle used for the memory access and the register name of the register in which the information about the memory access is stored in the trace table in association with each other. The trace table is stored in, for example, the management information storage unit 13.

G_hMem100, g_hMem200 and g_hMem300 shown in FIG. 7 are examples of handle names. Further, rcx and rax shown in FIG. 7 are examples of register names. In the example shown in FIG. 7, g_hMem200 and rcx correspond to each other, and g_hMem200 and rcx correspond to each other.

By referring to the trace table, the memory management unit 12 can easily specify which handle the value stored in the register is related to.

FIG. 8 is a diagram showing an example of information regarding writing of data to the second region. When the write determination unit 23 determines that the write target data is not writable in the first area, the output unit 27 outputs the information related to data writing shown in the example of FIG.

The “time” shown in FIG. 8 is, for example, the timing at which the write instruction unit 24 gives an instruction to write to the second area to the OS 11. "Event" indicates the content of the event that occurred. In the case of writing to the second area, the output unit 27 describes, for example, "overrun occurrence". In the "detailed information", for example, the start address and size of the second area where writing is performed are described. In the "stack information", the name of the module and the function that executed the write, and the address of the stack area used by the module are described. The "stack information" shown in FIG. 8 indicates that an overrun has occurred in the write process executed by the function "WriteMem" in the module "mod_4.dll".

In the "stack information", the module and function that caused the overrun and the calling module and function are described in order. That is, the information shown in FIG. 8 indicates that the function "function3" in the module "mod_3.dll" called the function "WriteMem" in the module "mod_4.dll". Further, the information shown in FIG. 8 indicates that the function "function 2" in the module "mod_2.dll" has called the function "function 3" in the module "mod_3.dll". Further, the information shown in FIG. 8 indicates that the function "function1" in the module "mod_1.dl" has called the function "function2" in the module "mod_1.dl".

When an overrun by the application 15 occurs and the OS 11 generates an exception and terminates the application abnormally, the overrun occurrence timing and the exception occurrence timing do not match. Therefore, when the information is not output, it is difficult to specify the timing of overrun. Further, when the information is not output, it is difficult to specify the module, the function, the address and the size of the written memory area that caused the overrun, and the like.

The information processing apparatus 1 of the present embodiment outputs information regarding writing to the second area, such as the timing of overrun occurrence, the module and function that caused the overrun, the address and size of the written memory area, and the like. Can be specified.

FIG. 9 is a diagram showing an example of information regarding reading of data from the second region. The “time” shown in FIG. 9 is, for example, the timing at which the read instruction unit 26 gives an instruction to read from the second area to the OS 11. "Event" indicates the content of the event that occurred. When the output unit 27 outputs information when reading from the second area, it is described as, for example, "overrun area reading". In the "detailed information", for example, the start address of the second region and the data size to be read are described.

In the "stack information", the name of the module and the function that executed the reading, and the address of the stack area used by the module are described. The information shown in FIG. 9 indicates that an overrun has occurred in the reading process executed by the function "ReadMem" in the module "mod_4.dll". Further, similarly to FIG. 8, the module and the function that caused the reading into the overrun area and the calling module and the function are described in order.

The information processing apparatus 1 of the present embodiment outputs information regarding data reading from the second area, so that the reading timing, the module that executed the reading from the second area, the function, and the address and size of the read memory area. Etc. can be clearly stated.

Hereinafter, the processing flow of the information processing apparatus 1 in the present embodiment will be described.
FIG. 10 is a flowchart showing an example of the setting process of the embodiment. The setting unit 14 makes various settings related to memory management (step S101). The setting unit 14 generates, for example, a setting file in which the name of the application to be monitored, the information output format, and the like are recorded according to the operation of the user.

The setting unit 14 registers the hook module in the information processing device 1 (step S102). The hook module is a program module realized by the memory management unit 12. For example, the setting unit 14 installs the hook module in the information processing apparatus 1 according to the operation of the user, and makes the hook module executable.

FIG. 11 is a flowchart showing an example of processing by the memory management unit 12. The process shown in FIG. 11 starts when the hook module realized by the memory management unit 12 is activated. When there are a plurality of monitored applications, the memory management unit 12 executes the process shown in FIG. 11 for each monitored application.

The detection unit 21 determines whether the monitored application has been started (step S201). The detection unit 21 determines, for example, whether the started application is a monitoring target based on the process ID, the monitoring target application name recorded in the setting file, or the like. When the detection unit 21 determines that the monitored application is not started (NO in step S201), the process does not shift to step S202.

When the detection unit 21 determines that the monitored application has been started (YES in step S201), the process proceeds to step S202.

When the detection unit 21 detects that the monitored application outputs an instruction for allocating an area (first area) in the memory to the OS 11 (YES in step S202), the memory management unit 12 executes the memory allocation monitoring process. (Step S203). The details of the memory allocation monitoring process in step S203 will be described later. If NO in step S202, the process proceeds to step S204.

When the detection unit 21 detects that the monitored application outputs a data write command to the first area of the memory to the OS 11 (YES in step S204), the memory management unit 12 executes the memory write monitoring process (step). S205). The details of the memory write monitoring process in step S205 will be described later. If NO in step S204, the process proceeds to step S206.

When the detection unit 21 detects that the monitored application has output a read instruction for the data written in the memory to the OS 11 (YES in step S206), the memory management unit 12 executes the memory read monitoring process (step S207). ). The details of the memory read monitoring process will be described later. If NO in step S206, the process proceeds to step S208.

The detection unit 21 determines whether the monitored application has stopped (step S208). If it is determined that the application to be monitored is not stopped (NO in step S208), the process returns to step S202.

When it is determined that the monitored application is stopped (YES in step S208), the detection unit 21 determines whether or not the monitoring end instruction has been received (step S209). The monitoring end instruction is given based on, for example, a user operation.

If the memory management unit 12 has not received the monitoring end instruction (NO in step S209), the memory management unit 12 returns the process to step S201. When the memory management unit 12 receives the monitoring end instruction (YES in step S209), the memory management unit 12 ends the process.

FIG. 12 is a flowchart showing an example of the memory allocation monitoring process in step S203 of FIG.

The recording unit 22 records the information indicating the first area in the first area management table (step S301). The recording unit 22 adds a column to, for example, the first area management table shown in FIG. Then, the recording unit 22 records, as information indicating the first area, the name of the module in which the memory allocation instruction is executed, the name of the handle used for allocating the memory, the base address of the memory to be allocated, and the size of the memory to be allocated.

The recording unit 22 determines whether or not a trace table corresponding to the handle name used for allocating the memory exists (step S302). If NO in step S302, the recording unit 22 creates a trace table corresponding to the handle name used for allocating the memory (step S303). The trace table is, for example, the table shown in FIG. 7, and at the time of creation, the handle name is recorded and the register name is not recorded.

If YES in step S302 or after the processing in step S303, the recording unit 22 records the register name of the register in which the Base address of the memory to be allocated is stored in the trace table corresponding to the handle name used for allocating the memory. (Step S304). It is assumed that the Base address of the memory to be secured is stored in the register in advance by the processing of the OS 11.

If the register name recorded in step S304 is recorded in another trace table, the recording unit 22 deletes the register name (step S305).

FIG. 13 is a flowchart showing an example of the memory write monitoring process in step S205 of FIG. The write determination unit 23 specifies in the memory area (first area) corresponding to which handle the write start address in the write command exists based on the first area management table (step S401). The write determination unit 23 hooks the write instruction, for example, and acquires the write start address included in the write instruction. Then, when the write start address exists between the Base address of any handle in the first area management table and the Base address + size, the write determination unit 23 has the write address in the memory area of the handle. Judge that there is. When the end address of the first area is included in the first area management table, the write determination unit 23 may determine whether the write start address is included between the Base address and the end address. Hereinafter, the handle used for writing specified by the write determination unit 23 in step S401 is referred to as a write target handle.

The write determination unit 23 identifies a register in which a value obtained by adding the write target data size to the write start address is stored, for example, by assembler analysis (step S402). It is assumed that the value obtained by adding the write target data size to the write start address is stored in the register in advance by the processing of the OS 11.

The recording unit 22 records the register name of the register specified in step S402 in the trace table of the write target handle specified in step S401 (step S403). That is, the recording unit 22 records the write target handle in association with the register name of the register specified in step S402. The register name is an example of information indicating a register.

The write determination unit 23 calculates offset1, which is the difference between the value stored in the register and the Base address associated with the write target handle in the first area management table (step S405). As described above, the register value is a value obtained by adding the write target data size to the write start address.

For example, when the write determination unit 23 stores the write start address and the write data size in the trace table, the write start address and the write data size are acquired from the registers, respectively, and the acquired write start address and the acquired write start address are used. The write data size may be added and used in the calculation of step S405.

The write determination unit 23 refers to the first area management table and determines whether the data to be written can be written in the first area (step S406). The write determination unit 23, for example, refers to the first area management table and determines that the write target data can be written to the first area when the offset1 is equal to or smaller than the size of the first area of the write target handle. (YES in step S406). Further, the write determination unit 23 refers to the first area management table, and if offset1 is larger than the size of the first area of the write target handle, determines that the write target data is not writable in the first area (step). NO in S406).

When NO in step S406, the write instruction unit 24 secures a second area different from the first area, writes a part of the data to be written to the first area, and writes the remaining part to the second area. Is instructed to OS 11 (step S407). The second area secured in step S407 is an area having a size obtained by subtracting the size of the write target handle from offset1. The write instruction unit 24, for example, divides the data to be written into a first part writable in the first area and a second part which is the remaining part, writes the first part in the first area, and the second part. Instructs OS 11 to write to the second area. The OS 11 writes based on the instruction from the write instruction unit 24.

The recording unit 22 creates a second area management table (step S408). Then, the recording unit 22 records the information indicating the second area in association with the information indicating the first area (step S409). For example, the recording unit 22 records the link ID in association with the write target handle in the first area management table, and associates the link ID with the Base address and size of the second area in the second area management table. Record.

The output unit 27 outputs information regarding writing of data to the second area (step S410). The output unit 27 generates, for example, the information shown in FIG. 8, displays it on the display device 2, or stores it in a predetermined area.

As described above, when the size of the data to be written exceeds the size of the memory area secured in advance, the write determination unit 23 newly secures the second area and writes the data to the second area to the OS 11. Instruct. Therefore, the information processing device 1 of the present embodiment can suppress the forced termination of the application.

Further, since the output unit 27 outputs information regarding data writing to the second area, the overrun occurrence timing, the module and function that caused the overrun, the address and size of the written memory area, and the like are clearly indicated. be able to.

14 and 15 are flowcharts showing an example of the memory read monitoring process in S207 of FIG. 11. The read determination unit 25 hooks the read instruction, identifies the handle used for reading, and acquires the base address and size corresponding to the handle from the first area management table (step S501). Hereinafter, the handle specified in step S501 is referred to as a read target handle.

The recording unit 22 identifies the register in which the read start address is stored by assembler analysis, and stores the register name of the specified register in the trace table in association with the handle to be read (step S502). It is assumed that the read start address is stored in the register in advance by the processing of OS11.

The read determination unit 25 identifies the register of the handle to be read from the trace table, and acquires the data stored in the register (step S503). That is, the read determination unit 25 acquires the read start address in the read instruction from the register.

The read determination unit 25 identifies the register in which the read target data size is stored by assembler analysis, and acquires the read target data size from the register (step S504). It is assumed that the data size to be read is stored in the register in advance by the processing of the OS 11.

The read determination unit 25 calculates offset2 by the following formula (step S505).
offset2 = read start address-base address of read target handle

The read determination unit 25 determines whether the entire range of the read target area is included in the second area (step S506). When offset2 is larger than the size of the first area of the read target handle, the read determination unit 25 determines that the read target data is not included in the first area and the entire range of the read target data is included in the second area. (YES in step S506). When the offset 2 is equal to or smaller than the size of the first region reserved for the read target handle, the read determination unit 25 determines that at least a part of the read target data is included in the first region (NO in step S506). ..

If NO in step S506, the read determination unit 25 determines whether a part of the read target area is included in the second area (step S507). When the value obtained by adding offset2 and the read target data size is equal to or less than the size of the first area, the read determination unit 25 includes the read end address in the first area, so that the read target data is stored only in the first area. (NO in step S507). When the value obtained by adding offset2 and the read target data size is larger than the size of the first area, the read determination unit 25 includes the read end address in the second area, so that a part of the read target area is included in the second area. (YES in step S507).

If NO in step S507, the memory read monitoring process ends. That is, the reading instruction unit 26 does not output an instruction to the OS 11, and the OS 11 executes the reading process based on the instruction from the application 15.

If YES in step S507, the read instruction unit 26 instructs the OS 11 to read data from the read start address to the end address of the first region (step S508). The read instruction unit 26 calculates, for example, the address at the end of the first area by adding the base address and the size of the first area management table, and uses it in the process of step S508.

Then, the read instruction unit 26 instructs the OS 11 to read the read residual data from the start address of the second area (step S509). The read instruction unit 26 instructs the OS 11, for example, the start address of the second area and the read remaining data size. The read remaining data size is a value obtained by subtracting the size to be read in the first area from the read target data size. The read instruction unit 26 identifies a second area corresponding to the first area based on, for example, the link ID of the first area management table and the link ID of the second area management table. Then, the read instruction unit 26 acquires the start address (base address) of the second area from the second area management table and uses it for the process of step S509.

The OS 11 reads the data to be read based on the instruction from the read instruction unit 26.

The output unit 27 outputs information regarding reading of data from the second area (step S510). For example, the output unit 27 generates the information shown in FIG. 9 and outputs it to the display device 2 or stores it in a predetermined area.

If YES in step S506, the read instruction unit 26 instructs the OS 11 to read the data to be read from the new read start address in the second area (step S511 in FIG. 15). The read determination unit 25 calculates a new read start address by the following formula and uses it for the process of step S511.
New read start address = offset2-size of first area + base address of second area

The read instruction unit 26 identifies a second area corresponding to the first area based on, for example, the link ID of the first area management table and the link ID of the second area management table. Then, the read instruction unit 26 acquires the Base address of the second area from the second area management table and uses it in the above equation.

The OS 11 reads the data to be read based on the instruction from the read instruction unit 26.

In step S511, the read instruction unit 26 may, for example, rewrite the value of the register in which the read start address is stored to a new read start address.

The output unit 27 outputs information regarding reading of data from the second area (step S512). For example, the output unit 27 generates the information shown in FIG. 9 and outputs it to the display device 2 or stores it in a predetermined area.

As described above, when at least a part of the read target area is included in the second area, the read instruction unit 26 indicates the read target area to the OS 11 and sends an instruction to read. Since the second area management table is recorded in the write monitoring process, the read instruction unit 26 can instruct the OS 11 of an appropriate area even when the read target area includes the second area.

Hereinafter, examples will be described.
FIG. 16 is a source code used for the monitored application in the embodiment. The source code shown in FIG. 16 is written in C language, but the source code used for the monitored application may be written in another programming language. The source code shown in FIG. 16 is a part of the source code used for the monitored application. Further, "// memory allocation", "// memory write", and "// memory read" shown in FIG. 16 are comments for explaining the processing contents and are skipped at the time of compilation.

In this embodiment, the monitored application allocates 100 bytes of memory by using the handles "g_hMem100", "g_hMem200", and "g_hMem300" in the memory allocation process (1-1, 1-2, 1-3). ).

Further, the monitored application writes 300 bytes of data to the memory corresponding to the handle "g_hMem100" in the memory write process (1-4). Further, the monitored application writes 250 bytes of data in the memory corresponding to the handle “g_hMem200” (1-5).

Further, in the memory reading process, the monitored application reads 10 bytes of data from the address obtained by adding 280 to the Base address of the first area corresponding to the handle "g_hMem100" (1-6). In the memory read process, the monitored application reads 30 bytes of data from the address obtained by adding 180 to the Base address of the first area corresponding to the handle "g_hMem200" (1-7).

FIG. 17 is a diagram showing an assembler code related to the memory allocation process in the embodiment. The source code shown in FIG. 17 is the code obtained by the assembler analysis, and corresponds to 1-1, 1-2, and 1-3 of FIG. “Rax” is an example of a register used for allocating memory, and other registers may be used. In the source code shown in FIG. 17, some source codes are omitted, not all source codes related to the memory allocation process.

FIG. 18 is a diagram showing a trace table in the memory allocation process of the embodiment. When the process shown in 2-1 of FIG. 17 is performed, the recording unit 22 records the handle name “g_hMem100” and the register name “rax” in association with each other, as shown in FIG. 18A.

When the process shown in 2-2 of FIG. 17 is performed, the recording unit 22 records the handle name “g_hMem200” and the register name “rax” in association with each other, as shown in FIG. 18B. Further, the recording unit 22 deletes the register name “rax” associated with the handle “g_hMem100”.

When the process shown in 2-3 of FIG. 17 is performed, the recording unit 22 records the handle name “g_hMem300” and the register name “rax” in association with each other, as shown in FIG. 18 (c). Further, the recording unit 22 deletes the register name "rax" associated with the handle name "g_hMem200".

FIG. 19 is a diagram showing a first area management table in the embodiment. When the memory allocation is executed by the program shown in FIGS. 16 and 17, the recording unit 22 records the first area management table shown in FIG. In the example shown in FIG. 19, for ease of explanation, an address showing the distance from a predetermined address in decimal is used as the Base address instead of the address in hexadecimal. For example, "Addr100" indicates an address whose distance from a predetermined address is 100 bytes. For example, "Addr200" indicates an address whose distance from a predetermined address is 200 bytes. For example, "Addr300" indicates an address whose distance from a predetermined address is 300 bytes.

FIG. 20 is a diagram showing a reserved memory area in the embodiment. The “first region A” shown in FIG. 20 is the first region corresponding to the handle “g_hMem100”. The "first region B" is the first region corresponding to the handle "g_hMem200". The "first region C" is the first region corresponding to the handle "g_hMem300".

FIG. 21 is a diagram showing an assembler code related to the memory writing process in the embodiment. The source code shown in FIG. 21 is the code obtained by the assembler analysis and corresponds to 1-4 and 1-5 of FIG. In the source code shown in FIG. 21, some source codes are omitted, not all source codes related to the memory writing process. For example, in the source code shown in FIG. 21, it is assumed that a code for writing the value obtained by adding the data size to be written to the write start address to the register rcx is described after "Func writemem", but the illustration is omitted. ..

FIG. 22 is a diagram showing a trace table in the memory writing process of the embodiment. When the process shown in 3-1 of FIG. 21 is performed, the recording unit 22 records the handle name “g_hMem100” and the register name “rcx” in association with each other, as shown in FIG. 22 (a). Then, it is assumed that the value "400" obtained by adding the write target data size to the write start address is written in rcx. The write determination unit 23 acquires the value of the register rcx associated with "g_hMem100" in the first area management table when the process shown in 3-3 of FIG. 21 is performed.

The write determination unit 23 calculates offset1, which is the difference between the acquired register rcx value and the Base address associated with g_hMem100 in the first area management table, as follows.
offset1 = 400-100 = 300

Since the offset 1 is larger than 100, which is the size of the write target handle, the write determination unit 23 determines that the write target data cannot be written in the first area.

The write instruction unit 24 instructs the OS 11 to newly secure a second area having a size of "200 bytes" obtained by subtracting "100 bytes", which is the size of the first area of the write target handle, from offset1. Further, the write instruction unit 24 instructs the OS 11 to write a part of the data to be written to the first area and write the remaining part to the second area.

When the process shown in 3-2 of FIG. 21 is performed, the recording unit 22 records the write target handle “g_hMem200” and the register name “rcx” in association with each other, as shown in FIG. 22 (b). .. Further, the recording unit 22 deletes the register rcx associated with the write target handle “g_hMem100”. Then, it is assumed that the value "450" obtained by adding the write target data size to the write start address is written in the register "rcx". The write determination unit 23 acquires the value of the register “rcx” associated with the write target handle “g_hMem200” in the first area management table when the process shown in 3-3 of FIG. 21 is performed.

The write determination unit 23 calculates offset1, which is the difference between the acquired value of the register “rcx” and the Base address associated with the handle “g_hMem200” in the first area management table, as follows.
offset1 = 450-200 = 250

Since the offset 1 is larger than 100, which is the size of the first area of the write target handle, the write determination unit 23 determines that the write target data cannot be written in the first area.

The write instruction unit 24 instructs the OS 11 to newly secure a second area of the size "150 bytes" obtained by subtracting the size of the write target handle from offset1. Further, the write instruction unit 24 instructs the OS 11 to write a part of the data to be written to the first area and write the remaining part to the second area.

FIG. 23 is a diagram showing a second area management table and a first area management table after the writing process in the embodiment. FIG. 23A is a second area management table created by the recording unit 22 when data writing is executed by the program shown in FIGS. 16 and 21. FIG. 23B is a first area management table updated by the recording unit 22 when data writing is executed by the program shown in FIGS. 16 and 21.

As described above, the write instruction unit 24 instructs the OS 11 to secure a second area in the write process by the write target handle “g_hMem100”. Then, the recording unit 22 records the link ID “ID_A”, the Base address “Addr1000”, and the size “200” as information indicating the second area corresponding to the write target handle “g_hMem100”.

The recording unit 22 records the same link ID “ID_A” as the link ID recorded in the second area management table in association with the write target handle “g_hMem100” in the first area management table.

Further, the write instruction unit 24 instructs the OS 11 to secure a second area in the write process by the write target handle “g_hMem200”. Then, the recording unit 22 records the link ID “ID_B”, the Base address “Addr1200” of the second area, and the size “150” as information indicating the second area corresponding to the write target handle “g_hMem200”.

Then, the recording unit 22 records the same link ID “ID_B” as the link ID of the second area management table in association with the write target handle “g_hMem200” in the first area management table.

FIG. 24 is a diagram showing a method of expanding the memory area in the embodiment. In this embodiment, the first region A corresponding to the handle “g_hMem100” and the newly secured second region A correspond to each other. That is, in the writing process, the first area A is expanded so that the first area A and the second area A correspond to the handle “g_hMem100”. Further, in this embodiment, the first region B corresponding to the handle “g_hMem200” and the newly secured second region B correspond to each other. That is, in the writing process, the first area B is expanded so that the first area B and the second area B correspond to the handle “g_hMem200”.

FIG. 25 is an assembler code relating to the memory reading process in the embodiment. The source code shown in FIG. 25 is the code obtained by the assembler analysis and corresponds to 1-6 and 1-7 of FIG. In the source code shown in FIG. 25, not all the source code related to the memory reading process but a part of the source code is omitted.

FIG. 26 is a diagram showing a trace table in the memory reading process of the embodiment. When the process shown in 4-1 of FIG. 25 is performed, the recording unit 22 records the handle “g_hMem100” and the register name “rcx” in association with each other, as shown in FIG. 26 (a). Then, it is assumed that the value "Addr380" indicating the read start address is written in the register "rcx".

The read determination unit 25 identifies the register name “rcx” associated with the read target handle “g_hMem100” from the trace table when the process shown in 4-3 of FIG. 25 is performed. Then, the read determination unit 25 acquires the read start address “Addr380” stored in the register “rcx”. When the process shown in 4-4 of FIG. 25 is performed, the read determination unit 25 identifies the register r8 in which the read target data size is stored, and acquires the read target data size “10” from r8.

The read determination unit 25 calculates offset2 by the following formula.
offset2 = read start address-base address of read target handle = 380-100 = 280

Since the calculated offset 2 is larger than the size of the first area reserved for the read target handle, the read determination unit 25 determines that the entire range of the read target area is included in the second area.

The read instruction unit 26 instructs the OS 11 to acquire the read target data from the new read start address in the second area. The read determination unit 25 calculates a new read start address by the following formula.
New read start address = offset2-first area size + second area base address = 280-100 + 1000 = 1180 (Addr1180)

Further, when the process shown in 4-2 of FIG. 21 is performed, the recording unit 22 records the handle “g_hMem200” and the register name “rcx” in association with each other, as shown in FIG. 26B. The recording unit 22 deletes the register name “rcx” associated with the handle “g_hMem100”. Then, it is assumed that the value "Addr280" indicating the read start address is written in the register rcx.

When the process shown in 4-3 of FIG. 25 is performed, the read determination unit 25 identifies the register name “rcx” associated with the read target handle “g_hMem200” from the trace table and stores it in the rcx. Acquires the read start address "Addr280". When the process shown in 4-4 of FIG. 25 is performed, the read determination unit 25 identifies the register r8 in which the read target data size is stored, and acquires the read target data size “30” from r8.

The read determination unit 25 calculates offset2 by the following formula.
offset2 = read start address-base address of read target handle = 280-200 = 80

The calculated offset2 "80" is smaller than the size "100" of the first region. Further, the value "110" (80 + 30), which is the sum of offset2 and the data size to be read, is larger than the size "100" of the first region. Therefore, the read determination unit 25 determines that a part of the read target area is included in the second area.

The read instruction unit 26 instructs the OS 11 to read data from the read start address "Addr280" to the end address "300" of the first area.

The read instruction unit 26 refers to the link ID "ID_B" corresponding to the read target handle "g_hMem200" in the first area management table, and sets the Base address "Addr1200" corresponding to the link ID "ID_B" in the second area management table. get. Then, the read instruction unit 26 instructs the OS 11 to read the read residual data from the Base address "Addr1200" of the second area acquired from the second area management table. The read remaining data size is a value "10" obtained by subtracting the size "20" to be read in the first area from the read target data size "30". Therefore, the read instruction unit 26 instructs the OS 11, for example, the start address “Addr1200” of the second region and the read remaining data size “10”.

FIG. 27 is a diagram showing a memory area in the reading process of the embodiment. In FIG. 27, “a” is an area where reading is performed by the handle “g_hMem100”. As described above, according to the instruction of the read instruction unit 26, the OS 11 reads the data of the size "10" from the new read start address "Addr1180".

Note that "a'" shown in FIG. 27 is an area where the read start address in the read command is "Addr380" and is read when the read process of the present embodiment is not performed. The instruction from the monitored application does not consider that the read target data is written in the second area. Therefore, if the reading process of the present embodiment is not performed, the reading may be performed from an area different from the area in which the actual reading target data is stored, as shown in "a'" in FIG. 27.

Further, for example, when the designation of the read start address in the read command is "Addr100 + 80", "Addr200 + 80", or "Addr300 + 80", the area to be read is the same when the read process of the present embodiment is not performed. .. However, when the second area is secured, the area in which the actual read target data is stored may be different.

In FIG. 27, “b1” and “b2” are areas where reading is performed by the handle “g_hMem200”. The read instruction unit 26 instructs the OS 11 to read the area "b1" from the read start address "Addr280" to the address "Addr300" at the end of the first area. Further, the read instruction unit 26 instructs the OS 11 to read the area “b2” having the remaining read data size “10” from the start address “Addr1200” of the second area acquired from the second area management table. Then, the OS 11 reads data from "b1" and "b2" shown in FIG. 27.

In the above processing, the memory management unit 12 acquires various addresses, data sizes, and the like stored in the registers by the OS 11, but is not limited to such an example. For example, the memory management unit 12 may acquire various addresses, data sizes, and the like by referring to a command sent from the application 15 to the OS. That is, even when various addresses, data sizes, and the like are not stored in the registers, the memory management unit 12 can acquire various addresses, data sizes, and the like.

Next, an example of the hardware configuration of the information processing apparatus 1 will be described.
FIG. 28 is a diagram showing an example of the hardware configuration of the information processing apparatus 1. As shown in the example of FIG. 28, in the information processing device 1, the processor 111, the memory 112, the auxiliary storage device 113, the communication interface 114, the medium connection unit 115, the input device 116, and the output device 117 are connected to the bus 100. To.

The processor 111 executes the program expanded in the memory 112. A memory management program that performs processing in the embodiment may be applied to the program to be executed. The "register" in this embodiment may be, for example, a storage circuit in the processor 111.

The memory 112 is, for example, a Random Access Memory (RAM). The memory 112 in FIG. 28 is applied to the “memory” in the present embodiment.

The auxiliary storage device 113 is a storage device that stores various types of information, and for example, a hard disk drive, a semiconductor memory, or the like may be applied. The memory management program that performs the processing of the embodiment may be stored in the auxiliary storage device 113.

The communication interface 114 is connected to a communication network such as a Local Area Network (LAN) or Wide Area Network (WAN), and performs data conversion and the like associated with the communication. When the output unit 27 transmits information to another information processing device or the like, the information is transmitted via the communication interface 114.

The medium connection unit 115 is an interface to which the portable recording medium 118 can be connected. An optical disc (for example, Compact Disc (CD) or Digital Versatile Disc (DVD)), a semiconductor memory, or the like may be applied to the portable recording medium 118. A memory management program that performs the processing of the embodiment may be recorded on the portable recording medium 118.

The input device 116 is, for example, a keyboard, a pointing device, or the like, and receives instructions and information input from the user.

The output device 117 is, for example, a display device, a printer, a speaker, or the like, and outputs an inquiry or instruction to a user, a processing result, or the like. The output device 117 shown in FIG. 28 may be applied to the display device 2 shown in FIG.

The management information storage unit 13 shown in FIG. 1 may be realized by a memory 112, an auxiliary storage device 113, a portable recording medium 118, or the like. The memory management unit 12 and the setting unit 14 shown in FIG. 1 may be realized by the processor 111 executing the memory management program expanded in the memory 112.

The memory 112, the auxiliary storage 113, and the portable recording medium 118 are computer-readable and non-temporary tangible storage media, not temporary media such as signal carriers.

<Others>
The present embodiment is not limited to the embodiments described above, and various changes, additions, and omissions may be made without departing from the gist of the present embodiment.

1 Information processing device 2 Display device 11 OS
12 Memory management unit 13 Management information storage unit 14 Setting unit 15-1 to 15-n Application 21 Detection unit 22 Recording unit 23 Write judgment unit 24 Write instruction unit 25 Read judgment unit 26 Read instruction unit 27 Output unit 100 Bus 111 Processor 112 Memory 113 Auxiliary storage 114 Communication interface 115 Media connection 116 Input device 117 Output device 118 Portable recording medium

Claims (9)

On the computer
When an instruction to secure the first area in the memory is detected, the information indicating the first area is recorded.
When a command to write data to the first area is detected, it is determined whether or not the data can be written to the first area based on the write command and the information indicating the first area.
When it is determined that the data is not writable in the first area, a second area different from the first area is secured in the memory, and a part of the data is written in the first area to obtain the data. Outputs an instruction to write the remaining part to the second area.
A memory management program characterized by executing processing. To the computer
When it is determined that the data is not writable in the first area, the information indicating the second area is recorded in association with the information indicating the first area.
The memory management program according to claim 1, wherein the process is executed. To the computer
When it is determined that the data cannot be written in the first area, information regarding writing of the data to the second area is output.
The memory management program according to claim 1 or 2, wherein the process is executed. To the computer
When the write command is detected, when the difference between the value obtained by adding the size of the data to the write start address included in the write command and the start address of the first area is larger than the size of the first area. It is determined that the data is not writable in the first area.
The memory management program according to any one of claims 1 to 3, wherein the process is executed. To the computer
When a read instruction for the data written in the memory is detected, at least a part of the read target area is included in the second area based on the read instruction and the information indicating the first area. Judging whether
When it is determined that at least a part of the read target area is included in the second area, at least a part of the data is associated with the information indicating the first area. Outputs an instruction to read from the second area specified based on the indicated information.
The memory management program according to claim 2, wherein the process is executed. To the computer
When it is determined that at least a part of the read target area is included in the second area, information regarding reading of the data from the second area is output.
The memory management program according to claim 5, wherein the process is executed. To the computer
When the read command is detected and the value obtained by subtracting the start address of the first area from the read start address is larger than the size of the first area, it is determined that the entire range of the read target area is included in the second area. death,
The value obtained by subtracting the start address of the first area from the read start address is equal to or less than the size of the first area, and the read target data size is obtained by subtracting the start address of the first area from the read start address. When the value obtained by adding the above is larger than the size of the first region, it is determined that a part of the read target region is included in the second region.
The memory management program according to claim 5 or 6, wherein the process is executed. The computer
When an instruction to secure the first area in the memory is detected, the information indicating the first area is recorded.
When a command to write data to the first area is detected, it is determined whether or not the data can be written to the first area based on the write command and the information indicating the first area.
When it is determined that the data is not writable in the first area, a second area different from the first area is secured in the memory, and a part of the data is written in the first area to obtain the data. Outputs an instruction to write the remaining part to the second area.
A memory management method characterized by performing processing. When an instruction to secure the first area in the memory is detected, a recording unit for recording information indicating the first area and a recording unit.
When a write command for data to the first area is detected, a write determination is made to determine whether the data can be written in the first area based on the write command and the information indicating the first area. Department and
When it is determined that the data cannot be written in the first area, a second area different from the first area is secured in the memory, a part of the data is written in the first area, and the data is written. A write instruction unit that outputs an instruction to write the remaining part of the data to the second area, and a write instruction unit.
A memory management device characterized by being equipped with.

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