JP6986221B2 - Manufacturing method of hole electrode substrate, hole electrode substrate and semiconductor device - Google Patents

Description

The present disclosure describes a method for manufacturing a hole electrode substrate, a hole electrode substrate, and a semiconductor device.

Conventionally, a hole electrode substrate having a substrate having holes on the surface and a hole electrode inside the holes has been adopted. For example, Patent Document 1 discloses a through electrode substrate as an example of a hole electrode substrate. In the through electrode substrate described in Patent Document 1, for example, the hole electrode first forms a seed layer on the side wall of the through hole provided in the substrate by a physical film forming method such as a vapor deposition method or a sputtering method, and subsequently. , Obtained by depositing a conductive material on the seed layer by an electrolytic plating method.

Japanese Unexamined Patent Publication No. 2016-72433

When the physical film forming method is adopted, the higher the aspect ratio of the pores, the more difficult it is to form the seed layer over the entire side wall of the pores. On the other hand, according to the electroless plating method, it is considered possible to form a seed layer over the entire side wall of the hole even when the aspect ratio of the hole is high. However, when the seed layer is formed by the electroless plating method, there is a concern that the adhesion of the seed layer to the substrate will be insufficient.

An object to be solved by the embodiment of the present disclosure is to provide a method for manufacturing a hole electrode substrate, a hole electrode substrate, and a semiconductor device capable of improving the adhesion of the hole electrode to the substrate.

In order to solve the above problems, in one aspect of the present disclosure,
Prepare a substrate containing silicon or a silicon compound and having holes on the first surface.
A hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface is formed.
It comprises covering at least a part of the outer edge of the surface portion and forming a first wiring in contact with the side surface of the surface portion.
A method for manufacturing a hole electrode substrate is provided, wherein the formation of the hole electrode comprises forming a conductive layer constituting at least a part of each of the side wall portion and the surface portion by electroless plating.

The first wiring may include a layer that is in contact with the first surface of the substrate and the surface portion of the hole electrode and contains titanium.

An insulating layer is formed on the first wiring, and the insulating layer is formed.
A through hole is formed through the insulating layer to form a through hole.
The insulating layer may be provided with a second wiring connected to the first wiring through the through hole.

The formation of the first wiring may be performed by physical film formation.

The physical film formation may be sputtering.

The formation of the first wiring may be performed by chemical film formation.

The substrate may be a glass substrate.

The electroless plating may be electroless copper plating.

The formation of the surface portion
The surface portion is formed so as to have an annular portion that covers the peripheral edge portion of the hole and a linear portion that extends radially outward from the annular portion.
The formation of the first wiring is
The first wiring may be performed so as to cover at least a part of the annular portion or the linear portion of the surface portion.

The linear portion may be formed so that the width of the linear portion in the direction orthogonal to the radial direction is 50 μm or less, which is larger than 0 μm.

A substrate containing silicon or a silicon compound and having holes on the first surface,
A hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface.
A hole electrode substrate comprising a first wiring that covers at least a part of the outer edge of the surface portion and is in contact with the side surface of the surface portion.

The first wiring may include a layer that is in contact with the first surface of the substrate and the surface portion of the hole electrode and contains titanium.

A second conductive film containing titanium may be provided between the first surface and the first wiring.

An insulating layer on the first wiring provided with a through hole,
A second wiring connected to the first wiring through the through hole on the insulating layer may be provided.

The substrate may be a glass substrate.

The surface portion is
An annular portion covering the peripheral portion of the hole and an annular portion
It has a linear portion extending radially outward from the annular portion, and has a linear portion.
The first wiring may cover at least a part of the annular portion or the linear portion of the surface portion.

The linear portion in the direction orthogonal to the radial direction may be 50 μm or less, which is larger than 0 μm.

In another aspect of the present disclosure,
A substrate containing silicon or a silicon compound and having a hole on the first surface, a hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface, and the above-mentioned A first hole electrode substrate having a first wiring that covers at least a part of the outer edge of the surface portion and is in contact with the side surface of the surface portion.
Provided is a semiconductor device comprising a semiconductor element electrically connected to the hole electrode substrate.

A plurality of the hole electrode substrates are provided.
The plurality of hole electrode substrates and the semiconductor chip may overlap in a direction intersecting the first surface.

According to the present disclosure, the adhesion of the hole electrode to the substrate can be improved.

It is a top view which shows the through silicon via substrate by this embodiment. It is sectional drawing which shows the through silicon via substrate by this embodiment. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment. FIG. 2 is a cross-sectional view showing a method of manufacturing a through silicon via substrate according to the present embodiment following FIG. 2A. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 2B. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 2C. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 3A. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 3B. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 3C. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 4A. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 4B. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 4C. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 5A. It is sectional drawing which shows the manufacturing method of the through silicon via substrate by this embodiment following FIG. 5B. It is sectional drawing which shows the through silicon via substrate by the 1st modification of this embodiment. It is sectional drawing which shows another example of the through silicon via substrate by the 1st modification of this Embodiment. It is a top view which shows the through silicon via substrate by the 2nd modification of this embodiment. It is sectional drawing which shows the through silicon via substrate by the 2nd modification of this embodiment. It is sectional drawing which shows the through silicon via substrate by the 3rd modification of this embodiment. It is sectional drawing which shows the through silicon via substrate by the 4th modification of this embodiment. It is sectional drawing which shows the hole electrode substrate by the 5th modification of this embodiment. It is a figure which shows the semiconductor device by the 6th modification of this embodiment. It is a figure which shows another example of the semiconductor device by the 6th modification of this embodiment. It is a figure which shows the example of the product to which a hole electrode substrate can be applied.

Hereinafter, the configuration of the hole electrode substrate and the manufacturing method thereof according to the embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that the embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Further, in the present specification, terms such as "board", "base material", "sheet" and "film" are not distinguished from each other based only on the difference in names. For example, "base material" and "base material" are concepts including members that can be called sheets or films. In addition, the length and angle values used in the present specification are not limited to a strict meaning, and are interpreted to include a range in which similar functions can be expected. Further, in the drawings referred to in the present embodiment, the same parts or parts having similar functions may be designated by the same reference numerals or similar reference numerals, and the repeated description thereof may be omitted. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

First, an embodiment of a through electrode substrate provided with a through electrode in a through hole will be described as an example of the hole electrode substrate of the present disclosure with reference to FIGS. 1 to 5C. FIG. 1A is a plan view showing a through silicon via substrate 1 according to the present embodiment. FIG. 1B is a cross-sectional view taken along the line IB-IB of FIG. 1A showing a through silicon via substrate 1 according to the present embodiment.

As shown in FIG. 1B, the through electrode substrate 1 of the present embodiment includes a substrate 2, a first through electrode 3 which is an example of a hole electrode, first wirings 41 and 42, and an insulating layer 9.

(Board 2)
The substrate 2 has a first surface 21 and a second surface 22 on the opposite side of the first surface 21. In the example of FIG. 1B, the first surface 21 and the second surface 22 are parallel to each other. In order to position the first through electrode 3 inside the substrate 2, the substrate 2 is provided with a first through hole 23 that penetrates the substrate 2 from the first surface 21 to the second surface 22 as an example of the hole. .. The first through hole 23 has a circular shape in a cross section perpendicular to the through direction, that is, the thickness direction D1 of the substrate 2. Although not shown, a plurality of the first through holes 23, the through electrodes 3 located inside the through holes 23, and the insulating layer 9 are provided at intervals in the surface direction of the substrate 2 orthogonal to the thickness direction D1. ..

In the example of FIG. 1B, the inner diameter of the first through hole 23 is almost the same from the first surface 21 to the second surface 22. That is, the first through hole 23 in FIG. 1B has a cylindrical side wall. The inner diameter of the first through hole 23 may be gradually decreased or increased from one of the first surface 21 and the second surface 22 toward the other. That is, the first through hole 23 may have a tapered side wall.

The substrate 2 contains silicon or a silicon compound. The substrate 2 is, for example, a glass substrate. The glass substrate may be, for example, non-alkali glass and soda glass. The components of soda glass are mainly composed of SiO, Na ₂ O, and Ca O. The component of the non-alkali glass is mainly composed of SiO ₂ / B ₂ O ₃ / Al ₂ O ₃ . The glass substrate can be suitably used for the through silicon via substrate 1 that requires transparency. Further, the glass substrate can also be suitably used as a substrate on which a high-performance LSI is mounted. This is because the signal transmission loss is small as compared with the silicon substrate, and it is suitable for signal processing in the GHz band. The substrate 2 may be a silicon substrate.

(First Through Silicon Via 3)
The first through electrode 3 is a conformal via type through electrode having a hollow portion. As shown in FIGS. 1A and 1B, the first through silicon via 3 has a side wall portion 31 and a first surface portion 32 and a second surface portion 33, which are examples of surface portions.

The side wall portion 31 covers the side wall of the first through hole 23. Here, when a certain component located on the side wall of the first through hole 23 "covers" another component, a certain structure is formed along a direction parallel to the in-plane direction of the first surface 21 of the substrate 2. When looking at an element, it means that one component overlaps with another. As an example, one component is in contact with another. It should be noted that inclusions may be present between one component and another. When a component is a side wall portion 31, the side wall portion 31 is another component when the side wall portion 31 is viewed along a direction parallel to the in-plane direction of the first surface 21 of the substrate 2. It overlaps the side wall of the first through hole 23. The insulating layer 9 is located inside the side wall portion 31. In other words, the insulating layer 9 fills the first through hole 23 inside the side wall portion 31. By filling the first through hole 23, for example, the insulating layer 9 can prevent the resin before solidification from entering the inside of the first through hole 23 and deteriorating the yield when the resin of the element is sealed. The inside of the first through hole 23 may be a gap portion in which the insulating layer 9 does not exist.

The first surface portion 32 is continuous with the side wall portion 31 on the first surface 21. The first surface portion 32 has an annular shape concentric with the first through hole 23 when viewed in a plan view. The first surface portion 32 covers the peripheral edge portion of the first through hole 23 on the first surface 21. Here, the fact that a certain component located on the first surface 21 "covers" another component means that when a certain component is viewed along the normal direction of the first surface 21 of the substrate 2. It means that one component overlaps with another. As an example, one component is in contact with another. It should be noted that inclusions may be present between one component and another. When a component is the first surface portion 32, the first surface portion 32 is the other component when the first surface portion 32 is viewed along the normal direction of the first surface 21 of the substrate 2. It overlaps with the peripheral edge of the first through hole 23 on the first surface 21.

The second surface portion 33 is continuous with the side wall portion 31 on the second surface 22. Like the first surface portion 32, the second surface portion 33 also has an annular shape concentric with the first through hole 23. The second surface portion 33 covers the peripheral edge portion of the first through hole 23 on the second surface 22. Here, a component located on the second surface 22 "covers" another component when the component is viewed along the normal direction of the second surface 22 of the substrate 2. It means that one component overlaps with another. As an example, one component is in contact with another. It should be noted that inclusions may be present between one component and another. When a component is the second surface portion 33, the second surface portion 33 is the other component when the second surface portion 33 is viewed along the normal direction of the second surface 22 of the substrate 2. It overlaps with the peripheral edge of the first through hole 23 on the second surface 22.

The side wall portion 31, the first surface portion 32, and the second surface portion 33 are each an electroless plating layer 3a formed by an electroless plating method and an electrolytic plating formed on the electroless plating layer 3a by an electroless plating method. It has a layer 3b.

The electroless plating layer 3a and the electrolytic plating layer 3b constituting the first through electrode 3 contain, for example, Cu (copper) as a main component. The electroless plating layer 3a and the electrolytic plating layer 3b may contain Al (aluminum), W (tungsten), Ti (titanium), Ta (tantal) and other refractory compounds as main components.

(1st wiring 41, 42)
The first wiring 41 on the first surface portion 32 side is a layer located on the first surface 21 and on the first surface portion 32 and having conductivity. The first wiring 42 on the second surface portion 33 side is a layer located on the second surface 22 and on the second surface portion 33 and having conductivity.

The first wiring 41 on the first surface portion 32 side covers the outer edge of the first surface portion 32, and the first portion 41a in contact with the side surface 321 of the first surface portion 32, that is, the outer peripheral surface, and the first portion 41a in a predetermined direction. It has a stretched second portion 41b. The first wiring 42 on the side of the second surface portion 33 covers the outer edge of the second surface portion 33, and the side surface 331 of the second surface portion 33, that is, the first portion 42a in contact with the outer peripheral surface, and the first portion 42a in a predetermined direction from the first portion 42a. It has a stretched second portion 42b. The outer edge of the surface portions 32 and 33 refers to the outer edge portion of the surface portions 32 and 33 in the radial direction D2 with respect to the center of the first through hole 23. The first wirings 41 and 42 may cover the outer edges of the surface portions 32 and 33 as well as the surface portions 32 and 33 inside the outer edges. In the example of FIGS. 1A and 1B, the second portions 41b and 42b are linearly extended from the first portions 41a and 42a toward the radial outer D21.

Further, in the examples of FIGS. 1A and 1B, the first portions 41a and 42a of the first wirings 41 and 42 cover the outer edges of the surface portions 32 and 33 over the entire circumference. That is, the first portions 41a and 42a have an annular shape in a plan view. The present disclosure is not limited to such an embodiment, and the first wirings 41 and 42 may cover at least a part of the outer edges of the surface portions 32 and 33.

The first wirings 41 and 42 have a seed layer 411 and 421 formed by sputtering, which is an example of physical film formation, and an electrolytic plating layer 412 and 422 formed on the seed layers 411 and 421 by an electrolytic plating method. ..

The seed layers 411 and 421 contain, for example, at least one of Cu and Ti as a main component. The seed layers 411 and 421 may have a multi-layer structure including a lower Ti layer formed by physical film formation and an upper Cu layer formed by physical film formation. By providing the Ti layer under the Cu layer, the adhesion of the seed layers 411 and 421 to the substrate 2 can be improved. The electrolytic plating layer 412 and 422 contain, for example, Cu (copper) as a main component.

According to the first wirings 41 and 42, the outer edges of the surface portions 32 and 33 are covered with the layer formed by the physical film formation so that the surface portions 32 and 33 are not peeled off from the surfaces 21 and 22 of the substrate 2. The adhesion of the surface portions 32 and 33 to the substrate 2 can be improved. As a result, the yield can be improved.

(Production method)
Next, a method for manufacturing the through silicon via substrate 1 of the present embodiment will be described.

In the first embodiment, first, the substrate 2 is prepared. Then, the first through hole 23 is formed in the substrate 2 from the first surface 21 to the second surface 22. The first through hole 23 is formed by, for example, laser processing. The first through hole 23 may be formed by blasting. As a result, the substrate 2 provided with the first through hole 23 is prepared. Next, the first through electrode 3 is formed on the substrate 2. The formation of the first through electrode 3 is performed so that the first through electrode 3 has a side wall portion 31, a first surface portion 32, and a second surface portion 33.

FIG. 2A is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment. In the formation of the first through electrode 3, first, as shown in FIG. 2A, electroless plating covering the side wall of the first through hole 23, the first surface 21, and the second surface 22 is performed by the electroless plating method. Form layer 3a. The electroless plating method is, for example, an electroless copper plating method in which a plating solution containing at least copper ions is brought into contact with the side wall of the first through hole 23, the first surface 21 and the second surface 22. The plating solution contains, for example, a copper compound such as copper sulfate for providing copper ions, and additives such as formaldehyde and sodium hydroxide.

Before forming the electroless plating layer 3a, a base treatment may be performed on the substrate 2 to improve the adhesion of the electroless plating layer 3a. The base treatment may be, for example, an organic material or an inorganic material. If it is an organic material, it may contain an adhesive resin material, for example, an epoxy resin or a heat effect material. If it is an inorganic material, it may include addition of a catalyst such as Pd (palladium), activation treatment, sintering of the catalyst, and the like.

FIG. 2B is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 2A. After forming the electroless plating layer 3a, as shown in FIG. 2B, the electroless plating layer 3b is formed on the electroless plating layer 3a by the electrolytic plating method. The electrolytic plating method is, for example, an electrolytic copper plating method. As a result, the conductive layer 30 in which the electroless plating layer 3a and the electrolytic plating layer 3b are laminated is obtained. The conductive layer 30 at least partially constitutes the side wall portion 31 and the surface portions 32, 33. That is, the conductive layer 30 constitutes the side wall portion 31 and the surface portions 32, 33 by itself, or constitutes the side wall portion 31 and the surface portions 32, 33 together with other constituent portions by the surface treatment or the like. The steps shown in FIGS. 2A and 2B are steps of partially forming the conductive layer 30 constituting at least a part of each of the side wall portion 31 and the surface portions 32 and 33 by electroless plating.

FIG. 2C is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 2B. After forming the electrolytic plating layer 3b, as shown in FIG. 2C, a dry film having an insulating layer 9 on the support film 101 is placed on the first through hole 23 side from both the first surface 21 side and the second surface 22 side. Push into. By pushing in the dry film, the first through hole 23 is filled with the insulating layer 9. The insulating layer 9 is pushed in, for example, by a vacuum laminating method. The insulating layer 9 is a layer containing a photosensitive resin such as a photosensitive polyimide. The first through hole 23 does not have to be filled with the insulating layer 9.

Hereinafter, a step for forming the surface portions 32 and 33 on one side, that is, one side at a time, and forming the first wirings 41 and 42 one by one will be described. The surface portions 32 and 33 may form both of them at the same time, and the first wirings 41 and 42 may also form both of them at the same time. FIG. 3A is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 2C. After pushing the insulating layer 9, the support film 101 on the first surface 21 side is peeled off. After peeling off the support film 101, the insulating layer 9 on the first surface 21 side is exposed. After the exposure, the insulating layer 9 is isotropically removed by supplying a developing solution to the insulating layer 9 on the first surface 21 side. As a result, as shown in FIG. 3A, the unnecessary insulating layer 9 on the first surface 21 is removed, leaving the insulating layer 9 inside the first through hole 23.

FIG. 3B is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 3A. After removing the insulating layer 9 on the first surface 21, the support film 101 on the second surface 22 side is peeled off. After peeling off the support film 101, the insulating layer 9 on the second surface 22 side is exposed. After the exposure, the insulating layer 9 is isotropically removed by supplying a developing solution to the insulating layer 9 on the second surface 22 side. As a result, as shown in FIG. 3B, the unnecessary insulating layer 9 on the second surface 22 is removed, leaving the insulating layer 9 inside the first through hole 23. In this way, the insulating layer 9 of FIG. 1B is obtained.

FIG. 3C is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 3B. After forming the insulating layer 9, as shown in FIG. 3C, a positive resist 103 covering the opening of the first through hole 23 and its peripheral edge is formed on the second surface 22 by photolithography.

FIG. 4A is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 3C. After forming the resist 103 on the second surface 22, the conductive layer 30 is etched using the resist 103 as a mask. As a result, as shown in FIG. 4A, the excess conductive layer 30 on the second surface 22 is removed, leaving the second surface portion 33. In this way, the second surface portion 33 is formed.

FIG. 4B is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 4A. After forming the second surface portion 33, as shown in FIG. 4B, a positive resist 103 covering the opening of the first through hole 23 and its peripheral edge is formed on the first surface 21 by photolithography.

FIG. 4C is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 4B. After forming the resist 103 on the first surface 21, the conductive layer 30 is etched using the resist 103 as a mask. As a result, as shown in FIG. 4C, the excess conductive layer 30 on the first surface 21 is removed, leaving the first surface portion 32. In this way, the first through electrode 3 having the first surface portion 32, the second surface portion 33, and the side wall portion 31 is formed.

In the process of FIG. 2B, the electrolytic plating layer 3b is formed on the surfaces 21 and 22 of the substrate 2 on the entire surface, and the electrolytic plating layer 3b is formed in a pattern corresponding to the surface portions 32 and 33 in the process of FIG. 4A. Was there. On the other hand, after forming a resist having a punching pattern corresponding to the surface portions 32 and 33 on the electroless plating layer 3a, the electrolytic plating layer is applied only to the regions corresponding to the surface portions 32 and 33 using this resist as a mask. 3b may be formed.

After forming the first through silicon via 3 as described above, the first wiring 41 is formed. FIG. 5A is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 4C. In the formation of the first wiring 41, first, as shown in FIG. 5A, a seed layer 411 covering the first surface portion 32, the insulating layer 9, and the first surface 21 is formed by sputtering. In the example of FIG. 5A, the seed layer 411 is in contact with the first surface portion 32, the insulating layer 9, and the first surface 21. By forming the first wiring 41 by sputtering, the adhesion of the first wiring 41 to the substrate 2 can be improved. Further, since the seed layer 411 is in contact with the side surface 321 of the first surface portion 32, the adhesion of the first surface portion 32 having the electroless plating layer 3a having weak adhesion to the first surface 21 is improved. Can be done. The seed layer 411 may be formed by laminating a Ti layer and a Cu layer in order. By forming the Ti layer, the adhesion of the first wiring 41 to the substrate 2 can be further improved. The thickness of the Ti layer may be 50 nm, and the thickness of the Cu layer may be 200 nm.

The first wirings 41 and 42 may be formed by chemical film formation such as plasma CVD method. By forming the first wirings 41 and 42 by chemical film formation, the film formation conditions such as temperature, pressure, and gas flow rate can be controlled with high accuracy.

FIG. 5B is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 5A. After forming the seed layer 411, as shown in FIG. 5B, a positive resist 105 having a punching pattern corresponding to the first wiring 41 is formed on the seed layer 411 by photolithography. Then, the electrolytic plating layer 412 of the first wiring 41 is formed by the electrolytic plating method using the resist 105 as a mask. The electrolytic plating method is, for example, an electrolytic copper plating method.

FIG. 5C is a cross-sectional view showing a method of manufacturing the through silicon via substrate 1 according to the present embodiment following FIG. 5B. After forming the electroplating layer 412, the resist 105 is peeled off. After the resist 105 is peeled off, the excess seed layer 411 on the first surface 21 is removed by etching, leaving the first wiring 41. In this way, the first wiring 41 is formed. By performing the same processing as in FIGS. 5A to 5C on the second surface 22 side, the first wiring 42 on the second surface 22 is formed.

Here, of the electroless plating layer 3a of the first through electrode 3, the electroless plating layer 3a of the surface portions 32 and 33 may have insufficient adhesion to the substrate 2. This is because, in the electroless plating method, the electroless plating layer 3a is formed in a state where the roughness of the glass surfaces 21 and 22 is low, so that the adhesion between the electroless plating layer 3a and the glass interface is weakened. If the first wirings 41 and 42 do not cover the outer edges of the surface portions 32 and 33, the surface portions 32 and 33 may be peeled off due to insufficient adhesion of the surface portions 32 and 33. ..

On the other hand, in the present embodiment, the first wirings 41 and 42 cover the outer edges of the surface portions 32 and 33. As a result, the first wirings 41 and 42 can press the surface portions 32 and 33 toward the substrate 2, so that the adhesion of the surface portions 32 and 33 to the substrate 2 can be improved. In particular, when the first wirings 41 and 42 cover the outer edges of the surface portions 32 and 33 within a range of 2 μm or more, the adhesion of the surface portions 32 and 33 to the substrate 2 can be improved more reliably.

Further, in the present embodiment, the contact area between the first wirings 41 and 42 and the surface portions 32 and 33 can be increased by contacting the first wirings 41 and 42 with the side surfaces 321 and 331 of the surface portions 32 and 33. .. Thereby, the adhesion between the first wirings 41 and 42 and the surface portions 32 and 33 can be improved. By improving the adhesion between the first wirings 41 and 42 and the surface portions 32 and 33, the first wirings 41 and 42 can more stably press the surface portions 32 and 33 to the substrate 2 side, so that the substrate can be pressed. The adhesion of the surface portions 32 and 33 to 2 can be further improved.

Further, according to the present embodiment, the first wiring 41 on the first surface portion 32 side is in contact with the first surface 21 and the first surface portion 32 of the substrate 2 and has a seed layer 411 containing titanium. It is possible to improve the adhesion of the first wiring 41 on the first surface portion 32 side to the substrate 2, and it is also possible to reduce the electric resistance and reduce the diffusion coefficient, that is, improve the barrier property. Similarly, the first wiring 42 on the side of the second surface portion 33 comes into contact with the second surface 22 and the second surface portion 33 of the substrate 2 and has the seed layer 421 containing titanium, so that the second surface portion 22 with respect to the substrate 2 is second. It is possible to improve the adhesion of the first wiring 42 on the surface portion 33 side, and it is possible to reduce the electric resistance and the diffusion coefficient. The seed layers 411 and 421 may contain chromium instead of titanium. Even when the seed layers 411 and 421 contain chromium, the adhesion of the first wirings 41 and 42 to the substrate 2 can be improved.

Further, by using physical film formation as a film forming method having better adhesion than the electroless plating method for forming the seed layers 411 and 421 of the first wirings 41 and 42, the first wirings 41 and 42 for the substrate 2 are formed. Adhesion can be improved. In particular, as the physical film formation, the adhesion of the first wirings 41 and 42 can be effectively improved by using sputtering that discharges in a vacuum state and drives the seed layers 411 and 421 into the glass surfaces 21 and 22. Since the adhesion of the first wirings 41 and 42 can be improved, the width W1 of the first wirings 41b and 42b in the direction orthogonal to the stretching direction D2 can be narrowed.

On the other hand, when the first wirings 41 and 42 are formed by chemical film formation such as plasma CVD method, the film formation conditions such as temperature, pressure and gas flow rate can be controlled with high accuracy.

(First modification)
FIG. 6A is a cross-sectional view showing the through silicon via substrate 1 according to the first modification of the present embodiment. As shown in FIG. 6A, the through silicon via substrate 1 of the first modification is, in addition to the configuration of the through silicon via substrate 1 of FIGS. 1A and 1B, further, the insulating layers 61 and 62 on the first wirings 41 and 42. And the second wirings 81 and 82 on the insulating layers 61 and 62.

The insulating layers 61 and 62 are provided with second through holes 71 and 72 that penetrate the insulating layers 61 and 62 in the thickness direction D1. A part of the first wirings 41 and 42 is exposed from the insulating layers 61 and 62 by the second through holes 71 and 72. The insulating layers 61 and 62 may be, for example, a resin such as photosensitive polyimide. The second through holes 71 and 72 may be formed by, for example, photolithography.

The second wirings 81 and 82 are connected to the first wirings 41 and 42 through the second through holes 71 and 72. Specifically, it is connected to the first wirings 41 and 42 via a filled via type second through electrode 80 located inside the second wirings 81 and 82 and the second through holes 71 and 72. The second through electrodes 80 and the second wirings 81 and 82 may be formed by, for example, photolithography or electroplating.

FIG. 6B is a cross-sectional view showing another example of the through silicon via substrate 1 according to the first modification of the present embodiment. As shown in FIG. 6B, the second wirings 81 and 82 may have an in-plane spread on the insulating layers 61 and 62.

According to the first modification, by having the second wirings 81 and 82 connected to the first wirings 41 and 42 through the second through holes 71 and 72 on the insulating layers 61 and 62, for example, a plurality of wirings 81 and 82 are provided. It is possible to flexibly cope with the case where the through electrodes are laminated in the thickness direction D1 or the case where the through electrode substrate 1 and the semiconductor element are electrically connected. Further, when the second wirings 81 and 82 have a spread, the degree of freedom in layout of electronic components such as semiconductor elements and passive elements electrically connected to the second wirings 81 and 82 can be improved.

(Second modification)
FIG. 7A is a plan view showing the through silicon via substrate 1 according to the second modification of the present embodiment. FIG. 7B is a plan view showing the through silicon via substrate 1 according to the second modification of the present embodiment. FIG. 7B is a sectional view taken along the line VIIB-VIIB of FIG. 7A. In the through silicon via substrate 1 of FIGS. 1A and 1B, the first wirings 41 and 42 cover the outer edges of the ring-shaped surface portions 32 and 33 over the entire circumference.

On the other hand, as shown in FIGS. 7A and 7B, in the second modification, the first surface portion 32 has the first annular portion 32a covering the peripheral edge portion of the first through hole 23 and the first annular portion 32a. It has a first linear portion 32b extending from the portion 32a to the radial outer D21 of the first through hole 23. The first linear portion 32b is an aspect of the outer edge of the first surface portion 32. The first wiring 41 on the first surface portion 32 side covers the outer end portion 322 of the radial portion 32b in the radial direction D2 as a part of the first linear portion 32b. Further, in the second modification, the second surface portion 33 has a second annular portion 33a that covers the peripheral edge portion of the first through hole 23, and a radial outer direction from the second annular portion 33a to the first through hole 23. It has a second linear portion 33b extending to D21. The second linear portion 33b is an aspect of the outer edge of the second surface portion 33. The first wiring 42 on the second surface portion 33 side covers the outer end portion 332 of the second linear portion 33b in the radial direction D2 as a part of the second linear portion 33b.

According to the second modification, the adhesion of the surface portions 32 and 33 to the substrate 2 can be improved by covering the linear portions 32b and 33b with the first wirings 41 and 42. Thereby, the line width of the linear portions 32b and 33b can be reduced. For example, the line width W2 of the linear portions 32b and 33b in the direction orthogonal to the radial direction D2 can be formed to be 50 μm or less, which is larger than 0 μm. When the line width W2 is 50 μm or less, the electroless plating layer is more likely to be peeled off. The peeling of the electroless plating layer 3a of the shaped portions 32b and 33b can be reliably suppressed. In addition, instead of the linear portions 32b and 33b, or together with the linear portions 32b and 33b, the first wirings 41 and 42 may cover at least a part of the annular portions 32a and 33a.

(Third and fourth modified examples)
FIG. 8 is a cross-sectional view showing the through silicon via substrate 1 according to the third modification of the present embodiment. FIG. 9 is a cross-sectional view showing the through silicon via substrate 1 according to the fourth modification of the present embodiment. As shown in FIG. 8, at least a part of the inner edges of the surface portions 32 and 33 may be covered with the insulating layer 9. Further, as shown in FIG. 9, the insulating layer 9 that covers at least a part of the inner edges of the surface portions 32 and 33 may be covered with the inner edges of the first wirings 41 and 42.

(Fifth variant)
FIG. 10 is a cross-sectional view showing a through-hole electrode substrate 1 according to a fifth modification of the present embodiment. So far, the through silicon via substrate 1 has been described as an example of the hole electrode substrate. As shown in FIG. 10, one aspect of the present disclosure is a substrate 2 having a bottomed hole 230 as a hole, that is, a substrate 2 having a recess, a hole electrode 3 inside the bottomed hole 230, and a surface portion 32 of the hole electrode 3. The hole electrode substrate 1 may be provided with a first wiring 41 that covers at least a part of the outer edge. The hole electrode 3 differs from the through electrode 3 in that it has a bottom wall portion 33 that covers the bottomed hole 230.

According to the fifth modification, the adhesion of the surface portion 32 to the substrate 2 can be improved by covering the surface portion 32 of the hole electrode 3 with the first wiring 41.

(Sixth modification)
FIG. 11 is a diagram showing a semiconductor device 1000 according to the sixth modification of the present embodiment. The semiconductor device 1000 includes a plurality of through silicon via substrates 1 arranged or laminated so as to overlap each other in the thickness direction D1 orthogonal to the first surface 21. Each through silicon via substrate 1 is electrically connected to the LSI substrate 1001. Each through electrode substrate 1 includes, for example, a semiconductor element (not shown) such as a DRAM electrically connected to the first wirings 41 and 42 described above, and a connection terminal 1002 electrically connected to the first wirings 41 and 42. And have. The through silicon via boards 1 adjacent to each other in the thickness direction D1 have their connection terminals 1002 facing each other. The through silicon via boards 1 adjacent to each other in the thickness direction D1 are electrically connected to each other via bumps 1003 located between the connection terminals 1002 facing each other. Further, the through silicon via board 1 adjacent to the LSI board 1001 in the thickness direction D1 has its connection terminal 1002 facing the connection terminal 1004 of the LSI board 1001. The LSI board 1001 and the through silicon via board 1 adjacent to the LSI board 1001 are electrically connected to each other via bumps 1005 located between the connection terminals 1002 and 1004 facing each other. The bumps 1003 and 1005 are metals such as indium, copper and gold.

In the example of FIG. 11, the number of layers of the through silicon via substrate 1 is two, but the number of layers of the through silicon via substrate 1 may be three or more. Further, for the electrical connection between the through electrode substrate 1 and another substrate, a bonding technique other than bumps such as eutectic bonding may be used, and polyimide, epoxy resin, or the like is applied and fired to penetrate. The electrode substrate 1 and another substrate may be adhered to each other.

FIG. 12 is a diagram showing another example of the semiconductor device 1000 according to the sixth modification of the present embodiment. The semiconductor device 1000 shown in FIG. 12 has semiconductor chips 1006 and 1007 and a through silicon via substrate 1, which are examples of semiconductor elements laminated in the thickness direction D1. These semiconductor chips 1006 and 1007 and the through silicon via substrate 1 are electrically connected to the LSI substrate 1001. The semiconductor chips 1006 and 1007 are, for example, a MEMS device, a CPU, a memory, and the like.

In the example of FIG. 12, the through electrode substrate 1 is located between the semiconductor chip 1006 and the semiconductor chip 1007, and the through electrode substrate 1 is electrically connected to each of the semiconductor chips 1006 and 1007 via the connection terminal 1008 and the bump 1009. Is connected. The semiconductor chip 1006 is mounted on the LSI substrate 1001. On the other hand, the semiconductor chip 1007 is electrically connected to the LSI substrate 1001 via the wire 1010. In the example of FIG. 12, the through silicon via substrate 1 is used as an interposer for stacking a plurality of semiconductor chips and mounting them three-dimensionally. According to the example of FIG. 12, a multifunctional semiconductor device can be manufactured by stacking a plurality of semiconductor chips having different functions. For example, by using the semiconductor chip 1006 as a 3-axis acceleration sensor and the semiconductor chip 1007 as a 2-axis magnetic sensor, it is possible to manufacture a semiconductor device in which a 5-axis motion sensor is realized by one module.

When the semiconductor chip is a sensor formed by a MEMS device or the like, the sensing result may be output by an analog signal. In this case, the low-pass filter, amplifier, and the like may also be formed on the semiconductor chip or the through silicon via substrate 1.

(Example of application to products)
FIG. 13 is a diagram showing an example of a product to which the hole electrode substrate 1 of each of the above embodiments can be applied. The hole electrode substrate 1 according to the embodiment of the present disclosure can be applied to various products. For example, the hole electrode substrate 1 can be mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

The aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, changes and partial deletions are possible without departing from the conceptual idea and purpose of the present disclosure derived from the contents specified in the claims and their equivalents.

1 Through Silicon Via Board 2 Substrate 21 First Surface 3 First Through Electrode 31 Side Wall Part 32 First Surface Part 41 First Wiring

Claims (18)

Prepare a substrate containing silicon or a silicon compound and having holes on the first surface.
A hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface is formed.
It comprises covering at least a part of the outer edge of the surface portion and forming a first wiring in contact with the side surface of the surface portion.
The formation of the hole electrode comprises that formed by electroless plating a conductive layer constituting each of the at least a portion of said side wall portion and said surface portion,
The hole is provided so as to penetrate the substrate from the first surface to the second surface on the opposite side of the first surface.
A method for manufacturing a hole electrode substrate, wherein the hole electrode is formed so as to further have a second surface portion continuous with the side wall portion on the second surface. The method for manufacturing a hole electrode substrate according to claim 1, wherein the first wiring is in contact with the first surface of the substrate and the surface portion of the hole electrode and includes a layer containing titanium. An insulating layer is formed on the first wiring, and the insulating layer is formed.
A through hole is formed through the insulating layer to form a through hole.
The method for manufacturing a hole electrode substrate according to claim 1 or 2, wherein a second wiring connected to the first wiring is formed on the insulating layer through the through hole. The method for manufacturing a hole electrode substrate according to any one of claims 1 to 3, wherein the first wiring is formed by physical film formation. The method for manufacturing a hole electrode substrate according to claim 4, wherein the physical film formation is sputtering. The method for manufacturing a hole electrode substrate according to any one of claims 1 to 3, wherein the first wiring is formed by chemical film formation. The method for manufacturing a hole electrode substrate according to any one of claims 1 to 6, wherein the substrate is a glass substrate. The method for manufacturing a hole electrode substrate according to any one of claims 1 to 7, wherein the electroless plating is electroless copper plating. The formation of the surface portion
The surface portion is formed so as to have an annular portion that covers the peripheral edge portion of the hole and a linear portion that extends radially outward from the annular portion.
The formation of the first wiring is
The method for manufacturing a hole electrode substrate according to any one of claims 1 to 8, wherein the first wiring covers at least a part of the annular portion or the linear portion of the surface portion. The method for manufacturing a hole electrode substrate according to claim 9, wherein the linear portion is formed so that the width of the linear portion in the direction orthogonal to the radial direction is 50 μm or less, which is larger than 0 μm. A substrate containing silicon or a silicon compound and having holes on the first surface,
A hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface.
Covers at least a portion of the outer edge of the surface portion, Bei example and a first wiring in contact with the side surfaces of said surface portion,
The hole is provided so as to penetrate the substrate from the first surface to the second surface on the opposite side of the first surface.
The hole electrode is a hole electrode substrate further having a second surface portion continuous with the side wall portion on the second surface. The hole electrode substrate according to claim 11, wherein the first wiring is in contact with the first surface of the substrate and the surface portion of the hole electrode and includes a layer containing titanium. An insulating layer on the first wiring provided with a through hole,
The hole electrode substrate according to claim 11 or 12, further comprising a second wiring connected to the first wiring through the through hole on the insulating layer. The hole electrode substrate according to any one of claims 11 to 13, wherein the substrate is a glass substrate. The surface portion is
An annular portion that covers the peripheral portion of the hole and an annular portion.
It has a linear portion extending radially outward from the annular portion, and has a linear portion.
The hole electrode substrate according to any one of claims 11 to 14, wherein the first wiring covers at least a part of the annular portion or the linear portion of the surface portion. The hole electrode substrate according to claim 15, wherein the width of the linear portion in the direction orthogonal to the radial direction is 50 μm or less, which is larger than 0 μm. A substrate containing silicon or a silicon compound and having a hole on the first surface, a hole electrode having a side wall portion covering the side wall of the hole and a surface portion continuous with the side wall portion on the first surface, and the above-mentioned A first hole electrode substrate having a first wiring that covers at least a part of the outer edge of the surface portion and is in contact with the side surface of the surface portion.
E Bei and a semiconductor element electrically connected to said hole electrode substrate separately from said hole electrode substrate,
The hole is provided so as to penetrate the substrate from the first surface to the second surface on the opposite side of the first surface.
The hole electrode is a semiconductor device further having a second surface portion continuous with the side wall portion on the second surface. A plurality of the hole electrode substrates are provided.
The semiconductor device according to claim 17, wherein the plurality of hole electrode substrates overlap in a direction intersecting the first surface.

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