JP6981223B2 - Sparse matrix vector product calculation device and sparse matrix vector product calculation method - Google Patents

Description

The present invention relates to a sparse matrix vector product calculation device and a sparse matrix vector product calculation method.

CAE (Computer Aided Engineering) is known as a technique for performing simulations related to product design on a computer using a simulation tool. For example, CAE may be performed for the purpose of structural analysis or fluid analysis.

One of the calculation methods used in the simulation in CAE is the conjugate gradient method (CG method). In addition, most of the execution time of the CG method is occupied by the operation of the sparse matrix vector product (SpMV: Sparse matrix-vector multiplication).

Further, as a technology for speeding up SpMV, a plurality of processing devices sharing a memory use sparse matrix data converted from a CSR (Compressed Sparse Row format) format to a JAD (Jagged Diagonal format) format to perform SpMV. The techniques to do are known.

Japanese Unexamined Patent Publication No. 2001-209631 Japanese Unexamined Patent Publication No. 8-212186

By the way, the size of the sparse matrix for which SpMV is calculated in the CG method may be very large. Further, in the CG method, since SpMV is repeatedly performed, a sparse matrix transfer may be performed between the CPU and the memory each time the SpMV is repeated. However, with the above technique, it may be difficult to shorten the transfer time of a sparse matrix between the CPU and the memory and to speed up the CG method.

In one aspect, it is an object of the present invention to provide a sparse matrix vector product calculation device and a sparse matrix vector product calculation method capable of speeding up the conjugate gradient method.

In one embodiment, the sparse matrix vector product arithmetic unit stores the arithmetic data input from the conjugate gradient method controller that controls the conjugate gradient method. The operational data includes a vector that can calculate the product of a sparse matrix and a sparse matrix compressed in a columnar format. The sparse matrix vector product arithmetic unit has a reading unit that reads a vector and a sparse matrix from an arithmetic data storage unit. The sparse matrix vector product calculation device has a calculation unit that executes a calculation of the sparse matrix vector product using the vector read by the reading unit and the sparse matrix. The sparse matrix vector product arithmetic unit has a writing unit that writes the result of the operation by the arithmetic unit to the arithmetic data storage unit. The sparse matrix vector product operation device uses a first element, which is an element of a vector, and a second element, which is a non-zero element of a sparse matrix corresponding to the first element, as a second element of a plurality of arithmetic units. It has an allocation unit that is assigned to a calculation unit that is previously associated with a row of two elements. The arithmetic unit includes a plurality of write ports and a read port corresponding to each of the plurality of write ports, and stores the partial sum in association with the rows of a sparse matrix, a multiport memory, a first element, and a second. When the element of is assigned, it corresponds to a plurality of multipliers that output a value obtained by multiplying the first element and the second element, and one of a plurality of write ports and the write port. With multiple adders connected to the read port, the value output by the multiplier plus the partial sum corresponding to the row of the second element read from the read port is written from the write port to the multiport memory. , Have.

According to one embodiment, the conjugate gradient method can be accelerated.

FIG. 1 is a diagram showing an example of SpMV. FIG. 2 is a diagram showing an example of the CSR format. FIG. 3 is a diagram showing an example of SpMV processing. FIG. 4 is a diagram showing an example of the simulation device according to the first embodiment. FIG. 5 is a diagram showing an example of the ELL format and the JAD format. FIG. 6 is a diagram showing an example of arithmetic data in the first embodiment. FIG. 7 is a diagram showing an example of the pretreatment unit in the first embodiment. FIG. 8 is a diagram showing an example of the acceleration unit in the first embodiment. FIG. 9 is a diagram showing an example of the processing of SpMV in the first embodiment. FIG. 10 is a diagram showing an example of a calculation unit in the first embodiment. FIG. 11 is a flowchart showing an example of the processing by the CG method in the first embodiment. FIG. 12 is a flowchart showing an example of SpMV processing in the first embodiment. FIG. 13 is a flowchart showing an example of the arithmetic processing in the first embodiment. FIG. 14 is a diagram showing a hardware configuration example.

Hereinafter, examples of the sparse matrix vector product calculation device and the sparse matrix vector product calculation method disclosed in the present application will be described in detail with reference to the drawings. The present invention is not limited to this embodiment. In addition, the examples shown below may be appropriately combined as long as they do not cause a contradiction.

The simulation apparatus 10 described later in the first embodiment executes a simulation using the CG method. The CG method is a method for finding a solution of a linear equation by iterative operation of SpMV.

In the following, it is assumed that each index of the matrix, vector and array starts from 0. Further, an element in which the row index of the matrix M is i and the column index is j may be expressed as _Mij. Also, it may be referred to as the index is i component of vector v v _i. Further, an element in which the index of the array array [] is i may be expressed as array [i].

Further, the row direction of the matrix is the direction in which the row index increases, which is the same as the right direction. It is assumed that the column direction of the matrix is the direction in which the column index increases and is in agreement with the downward direction.

Here, as an example, the flow of processing when the simulation device 10 obtains a solution of an n-dimensional linear equation using the CG method will be described. At this time, the simulation apparatus 10 obtains a vector x such that the product with the matrix A is a vector y from the matrix A of n × n and the vector y of the number of elements n. In the following, a matrix such as the matrix A may be referred to as a coefficient matrix, a vector such as the vector x may be referred to as a solution vector, and a vector such as the vector y may be referred to as a constant vector. The coefficient matrix and the constant vector are known, but the true value of the solution vector is unknown.

First, the simulation device 10 sets an arbitrary initial value in the vector x, and executes the calculation of the product of the matrix A and the vector x, that is, SpMV. Then, the simulation apparatus 10 sets the vector x so that the vector y'approaches the vector y based on the gradient calculated from the residual of the vector y'and the vector y obtained as a result of the SpMV of the matrix A and the vector x. Update.

Further, the simulation apparatus 10 executes SpMV of the matrix A and the updated vector x. After that, the simulation device 10 repeats updating the SpMV and the vector x until a predetermined condition is satisfied, and the vector x at that time can be obtained as a solution of a linear equation or an approximate solution.

When simulating product design using the CG method, the coefficient matrix may be a sparse matrix. A sparse matrix is a matrix in which many of the elements of the matrix are zero. Here, a sparse matrix SpMV will be described with reference to FIG. FIG. 1 is a diagram showing an example of SpMV. As shown in FIG. 1, the matrix A is a sparse matrix. At this time, the element y _{0 of the} vector y is calculated by the equation (1).

y ₀ = a ₀₀ x x ₀ + 0 x x ₁ + 0 x x ₂ + a ₀₃ x x ₃ + 0 x x ₄ ... (1)

Here, the second term, the third term, and the fifth term of the equation (1) are always 0. Therefore, the processor does not need to refer to _{the elements x 1} , x ₂ and x ₄ of the vector x when performing the calculation of the equation (1).

However, processors such as CPUs and GPUs (Graphics Processing Units) acquire data by burst transfer from memory. Therefore, for example, the data that the CPU can acquire from the memory in one transfer cycle is limited to a continuous fixed amount of data.

Here, consider a case where the CPU, in which the data that can be acquired in one transfer cycle is three consecutive elements of the vector x, performs the calculation of the equation (1). Further, at this time, it is assumed that each element of the vector x is continuously stored in the memory in the order of the index.

In this case, the CPU first _{acquires x 0} in the first transfer cycle in order to calculate _{a 00} × x _0. Then, CPU _to compute the _{a 03} × _{x 3,} to obtain the _{x 3} in the second transfer cycle. As described above, the CPU needs at least two transfer cycles to calculate the equation (1).

If the elements acquired by the CPU from the vector x _{are continuous such as x 0} and x ₁ , the CPU can acquire the necessary elements in one transfer cycle. On the contrary, when the elements of the vector to be acquired are not continuous, that is, when the access to the vector is random, the required transfer cycle increases, and as a result, the calculation speed of SpMV decreases.

In addition, the original number of linear equations used in the simulation can be large, ranging from millions to over 10 million. In such a case, the size of the coefficient matrix and the solution vector becomes very large, and the influence on the calculation speed of SpMV due to the lack of continuity in the elements of the acquired vector also becomes large.

Also, the sparse matrix may be represented in a compressed form. One of the sparse matrix compression formats is the CSR format. FIG. 2 is a diagram showing an example of the CSR format. As shown in FIG. 2, a sparse matrix in the CSR format is represented by three arrays of row_off, col, and val.

Non-zero elements (non-zero elements) of a sparse matrix are stored in the array val in ascending order of row index in the sparse matrix. For non-zero elements with the same row index, the one with the smaller column index is in the first order in the array val.

Further, in the array col, the column index of each non-zero element is stored at the corresponding position of each non-zero element stored in the array val. In the array row_off, the index that is the index of the array col and stores the column index of the non-zero element with the smallest column index among the non-zero elements of each row of the sparse matrix is the row index of the non-zero element. Are stored in ascending order.

Here, for example, row index and column index of an element a ₀₀ of the matrix A in FIG. 1 are both 0. Further, the index of the element a ₀₀ in the array val is 0. Therefore, the element of index 0 of the array col is 0. In addition, an index of the sequence col, index column index of a ₀₀ is the most column index is less nonzero elements of the non-zero elements are stored in the first row (row index is 0 line) of the sparse matrix Is 0. Therefore, the element of index 0 of the array row_off is 0.

Further, for example, row index and column index of an element a ₃₀ of the matrix A in FIG. 1, respectively is 3 and 0. Also, index of the element _{a 30} in the array val is 6. Therefore, the element of the index 6 of the array col is 0. In addition, an index of the sequence col, index column index of a ₃₀ is the most column index is less non-zero elements are stored within the non-zero elements of the fourth line (row index is 3 rows) of the sparse matrix Is 6. Therefore, the element of index 3 of the array row_off is 6.

Using the pseudo code of FIG. 3, the processing of SpMV by the CPU when the matrix A of FIG. 1 is represented in the CSR format will be described. FIG. 3 is a diagram showing an example of SpMV processing. I in FIG. 3 corresponds to the index of the element of the vector y. Further, j corresponds to the index of the vector x. Further, x [] and y [] are arrays storing the vector x and the vector y, respectively.

For example, as shown in FIG. 2, row_off [0] is 0 and row_off [1] is 2. Further, col [0] is 0 and col [1] is 3. Therefore, as shown in the third and fourth rows of FIG. 3, when i = 0, the CPU acquires x [0] and x [3] and corresponds to each element of the acquired x []. Add the product with the elements of val [] to y [0]. That is, when i = 0, the CPU performs the calculation of the equation (1). In this case, the calculation speed of SpMV is reduced due to the influence of the fact that the elements of x [] to be acquired are not continuous.

The purpose of the SpMV apparatus 10e of the first embodiment is to suppress a decrease in the calculation speed of the SpMV due to non-continuous access to the vector while minimizing the transfer of a sparse matrix when performing a simulation by the CG method. It is something to do.

[Function block]
Next, an example of the simulation device 10 having the sparse matrix vector product calculation device 10b in this embodiment will be described with reference to FIG. FIG. 4 is a diagram showing an example of the simulation device according to the first embodiment. As shown in FIG. 4, the simulation device 10 in this embodiment includes a conjugate gradient method control device 10a and a sparse matrix vector product calculation device 10b. The conjugate gradient method control device 10a is realized by, for example, a CPU. On the other hand, the sparse matrix vector product arithmetic unit 10b is realized by, for example, FPGA (Field Programmable Gate Array).

The conjugate gradient method control device 10a has a conversion unit 11 and an update unit 12. Further, the sparse matrix vector product arithmetic unit 10b has an arithmetic data storage unit 13, a preprocessing control unit 14, a preprocessing unit 15, and an acceleration unit 16.

The conjugate gradient method control device 10a controls the CG method. Specifically, the conjugate gradient method control device 10a executes the CG method based on the settings and the like input from the user, and at that time, causes the sparse matrix vector product calculation device 10b to execute SpMV. The preprocessing for the coefficient matrix in SpMV is performed by the sparse matrix vector product arithmetic unit 10b.

The conversion unit 11 compresses a coefficient matrix, which is a sparse matrix used in SpMV, in a column-oriented format. For example, the conversion unit 11 converts a coefficient matrix expressed in a row-oriented format such as uncompressed or CSR into a column-oriented format such as CSC (Compressed Sparse Column format) format, ELL (Ellpack-Itpack generalized diagonal format) format, or JAD. Convert to format etc.

FIG. 5 is a diagram showing an example of the ELL format and the JAD format. As shown in FIG. 5, when converting the matrix A to the ELL format, the conversion unit 11 assumes a matrix in which the non-zero elements of the matrix A are packed on the left side, and acquires the elements in column units of the assumed matrix. Store in an array. Further, when converting the matrix A to the JAD format, the conversion unit 11 sorts the rows of the assumed matrix in the order of the number of elements, and then stores the elements in the array in the same manner as in the ELL format.

In this embodiment, the conversion unit 11 converts the matrix A into the JAD format, and stores the converted coefficient matrix as arithmetic data in the arithmetic data storage unit 13 of the sparse matrix vector product arithmetic apparatus 10b. Further, at this time, the conversion unit 11 stores the solution vector in which the initial value is set together with the coefficient matrix in the arithmetic data storage unit 13, and causes the sparse matrix vector product arithmetic unit 10b to execute SpMV.

FIG. 6 is a diagram showing an example of arithmetic data in the first embodiment. As shown in FIG. 6, the arithmetic data which is a coefficient matrix in JAD format is represented by four arrays of colond, value, jdptr and perm.

Here, an example of a method of creating each array in JAD format by the conversion unit 11 will be described. First, the conversion unit 11 stores the row indexes of the matrix A in the array perm in the order of the number of elements in each row. Next, the conversion unit 11 focuses the rows of the matrix A according to the order of the row indexes stored in the array perm, and among the elements not stored in the array value of each row, the leftmost element is set to the array value. Store. The conversion unit 11 proceeds to the next row when the element is stored in the array value of the focused row or when the element to be stored does not exist in the focused row.

Further, the conversion unit 11 stores the column index of the element stored in the array value at the corresponding position in the array colond. Further, the conversion unit 11 stores the index of the storage destination in the array value of the element of the row whose row index order is first stored in the array perm in the array jdptr.

The update unit 12 updates the solution vector based on the result of SpMV by the sparse matrix vector product arithmetic unit 10b according to the procedure of the CG method. Here, it is assumed that the sparse matrix vector product calculation device 10b stores the calculated value of the constant vector obtained as a result of SpMV in the calculation data storage unit 13. Further, the update unit 12 can further store the updated solution vector in the operation data storage unit 13, and cause the sparse matrix vector product calculation device 10b to execute SpMV.

The arithmetic data storage unit 13 is arithmetic data input from the conjugate gradient method control device 10a that controls the conjugate gradient method, and is compressed in a column-oriented format with a solution vector capable of calculating the product of the coefficient matrix. Stores operational data including a coefficient matrix. The coefficient matrix is a sparse matrix. For example, the arithmetic data storage unit 13 can store a coefficient matrix compressed in the ELL format or the JAD format. However, in this embodiment, the arithmetic data storage unit 13 stores the coefficient matrix compressed in the JAD format.

The pre-processing unit 15 includes a processing unit corresponding to each of a plurality of pre-processing for preset calculation data, and executes pre-processing using the processing unit corresponding to the designated pre-processing. The pre-processing control unit 14 designates the pre-processing designated by the conjugate gradient method control device 10a to the pre-processing unit 15. The user may specify the preprocessing for the conjugate gradient method control device 10a.

The pretreatment unit 15 will be described with reference to FIG. 7. FIG. 7 is a diagram showing an example of the pretreatment unit in the first embodiment. As shown in FIG. 7, the pretreatment unit 15 includes a diagonal scaling processing unit 151, an STOR processing unit 152, an ILU processing unit 153, and an AMG processing unit 154.

The diagonal scaling processing unit 151 performs preprocessing by diagonal scaling. The STOR processing unit 152 performs preprocessing by STOR (Symmetric Successive Over-relaxation). The ILU processing unit 153 performs pretreatment by ILU (Incomplete LU Factorization) (0), ILU (1) and the like. The AMG processing unit 154 performs pretreatment by AMG (Algebraic Multigrid). The processing unit provided in the preprocessing unit 15 is not limited to that shown in FIG. 7. The preprocessing unit 15 may have a plurality of processing units that perform preprocessing on the matrix.

Each processing unit included in the pre-processing unit 15 is arranged so as to be reconfigurable by changing the connection destination of the circuit or the like. For example, when the pre-processing designated by the pre-processing control unit 14 is diagonal scaling, the pre-processing unit 15 enables the connection between the arithmetic data storage unit 13 and the diagonal scaling processing unit 151. At that time, the pre-processing unit 15 invalidates the connection between the arithmetic data storage unit 13 and the STOR processing unit 152, the ILU processing unit 153, and the AMG processing unit 154.

The acceleration unit 16 executes SpMV. Further, the execution result of SpMV by the acceleration unit 16 is stored in the arithmetic data storage unit 13. The result of the calculation is, for example, a calculated value of a constant vector. Further, the acceleration unit 16 is configured to speed up the CG method.

Here, the pre-processing unit 15 can execute the pre-processing every time the SpMV by the acceleration unit 16 is completed. Further, the acceleration unit 16 executes SpMV every time the preprocessing by the preprocessing unit 15 is completed. As a result, the sparse matrix vector product arithmetic unit 10b can repeatedly perform preprocessing and SpMV.

At that time, the conjugate gradient method control device 10a interrupts the iterative processing by the sparse matrix vector product arithmetic unit 10b at a predetermined timing, and acquires the calculated value of the constant vector. The conjugate gradient method control device 10a updates the solution vector stored in the arithmetic data storage unit 13 based on the gradient calculated from the residual between the acquired calculated value and the true value.

The acceleration unit 16 will be described with reference to FIG. FIG. 8 is a diagram showing an example of the acceleration unit in the first embodiment. As shown in FIG. 8, the acceleration unit 16 includes a load unit 161, an allocation unit 162, and a plurality of calculation units 163. Further, the acceleration unit 16 is connected to the arithmetic data storage unit 13. Further, the load unit 161 has a read unit 161a and a write unit 161b.

The reading unit 161a reads the solution vector and the coefficient matrix from the arithmetic data storage unit 13. The allocation unit 162 allocates data necessary for the calculation to each of the calculation units 163. The arithmetic unit 163 executes SpMV using the solution vector and the coefficient matrix read by the reading unit 161a. The writing unit 161b writes the result of the calculation by the calculation unit 163 to the calculation data storage unit 13.

Specifically, the allocation unit 162 associates the elements of the solution vector and the elements of the coefficient matrix corresponding to the elements of the solution vector with the rows of the elements of the coefficient matrix in the plurality of arithmetic units 163 in advance. It is assigned to the calculation unit 163. When the elements of the solution vector and the elements of the coefficient matrix are assigned, the calculation unit 163 executes an operation for obtaining the product of the elements of the assigned solution vector and the elements of the coefficient matrix and the sum of the products.

Here, the processing of the acceleration unit 16 will be described with reference to an example in which the arithmetic data is as shown in FIG. The arithmetic data storage unit 13 stores the elements of the vector x, which is a solution vector. Further, the arithmetic data storage unit 13 includes an array value storing the elements of the matrix A, which is a coefficient matrix, an array colond for specifying the columns of the elements of the matrix A, and an array jdptr and an array for specifying the rows of the elements of the matrix A. Remember at least the perm. The contents of each sequence are as shown in FIG.

The element of the vector x is an example of the first element. Further, the element of the matrix A is an example of the second element. The array value is an example of the first data. The array colond is an example of the second data. The array jdptr and the array perm are examples of the third data.

Further, it is assumed that the arithmetic data storage unit 13 has at least the same number of ports as the number of arithmetic units 163. Further, it is assumed that any of the rows of the matrix A is associated with each of the arithmetic units 163 in advance. Each row of the matrix A corresponds to each element of the vector y, which is a constant vector. Further, it is assumed that each of the arithmetic units 163 corresponds to any of the ports provided in the arithmetic data storage unit 13.

The processing of SpMV by the acceleration unit 16 will be described with reference to the pseudo code of FIG. FIG. 9 is a diagram showing an example of the processing of SpMV in the first embodiment. Rho_max in FIG. 9 is the maximum value of the index of the array jdptr. Further, x [] and y [] are arrays storing the vector x and the vector y, respectively.

For example, when j is 0 and i is jdptr [0], that is, 0, as shown in FIG. 9, the reading unit 161a first uses jdptr [0], perm [0], value [0], and colond [0]. Is read. Further, since colond [0] is 0, the reading unit 161a reads x [0], x [1], and x [2] by burst transfer. Then, the allocation unit 162 allocates jdptr [0], perm [0], value [0], colond [0], and x [0] to the corresponding arithmetic unit 163. At this time, the calculation unit 163 adds value [0] * x [0] to y [perm [0]].

Next, when j remains 0 and i becomes 1, the reading unit 161a reads jdptr [0], perm [0], value [1], and colond [1]. Further, since collind [1] is 0 and x [0] has already been read, the reading unit 161a does not read x [0] here. Then, the allocation unit 162 allocates jdptr [0], perm [0], value [1], colond [1], and x [0] to the corresponding arithmetic unit 163. Here, since perm [0] = 3, the arithmetic unit 163 adds value [1] * x [0] to y [3].

When the processing further progresses and j becomes 1 and i becomes jdptr [1], that is, 5, the reading unit 161a reads jdptr [1], perm [1], value [5], and cold [5]. Further, since colond [5] is 1 and x [1] has already been read, the reading unit 161a does not read x [1] here. Then, the allocation unit 162 allocates jdptr [1], perm [1], value [5], colond [5], and x [1] to the corresponding arithmetic unit 163. Here, since perm [1] = 1, the arithmetic unit 163 adds value [5] * x [1] to y [1].

When the processing further progresses and j becomes 2 and i becomes jdptr [2], that is, 10, the reading unit 161a reads jdptr [2], perm [2], value [10], and cold [10]. Further, since colond [10] is 2 and x [2] has already been read, the reading unit 161a does not read x [2] here. Then, the allocation unit 162 allocates jdptr [2], perm [2], value [10], colond [10], and x [2] to the corresponding arithmetic unit 163. Here, since perm [2] = 2, the arithmetic unit 163 adds value [10] * x [2] to y [2].

When the processing further progresses and j becomes 2 and i becomes jdptr [2] + 1, that is, 11, the reading unit 161a reads the value [11] and the colond [11]. Further, since the colond [11] is 3 and the x [3] has not been read, the reading unit 161a reads x [3], x [4], and x [5] by burst transfer here. Then, the allocation unit 162 allocates jdptr [2], perm [2], value [11], colond [11], and x [3] to the corresponding arithmetic unit 163. Here, since perm [2] = 2, the arithmetic unit 163 adds value [11] * x [3] to y [2].

In this way, since the acceleration unit 16 can perform the SpMV calculation using the continuously read elements of x [], the random access can be relaxed and the CG method can be speeded up. When the number of consecutive x [] elements that can be read and acquired in one transfer cycle is up to three and the arithmetic data is in the CRS format as shown in FIG. 2, at least the x [] elements can be read. Eight transfer cycles are required. On the other hand, if the number of consecutive x [] elements that can be read and acquired in one transfer cycle is up to three and the arithmetic data is in the JAD format as shown in FIG. 6, the transfer required for reading the x [] elements. The cycle is 2 times.

The allocation unit 162 puts the elements of the matrix A stored in the array value and the elements of the vector x corresponding to the columns of the elements of the matrix A specified by the array colon into the arithmetic unit 163 together with the array jdptr and the array perm. assign. As a result, the arithmetic unit 163 can specify the row index of each element of the matrix A before sorting in the JAD format.

The arithmetic unit 163 will be described with reference to FIG. FIG. 10 is a diagram showing an example of a calculation unit in the first embodiment. As shown in FIG. 10, the arithmetic unit 163 has a multi-port memory 163a, a plurality of multipliers 163b, and a plurality of adders 163c connected to each of the plurality of multipliers 163b. Further, the arithmetic unit 163 has a plurality of pipeline registers 163d connected to each of the multi-port memory 163a and the plurality of adders 163c.

The multi-port memory 163a includes a plurality of write ports and a read port corresponding to each of the plurality of write ports, and stores the partial sum in association with the row of the coefficient matrix.

The multiport memory 163a has write ports 1w, 2w, 3w and 4w. Further, the multi-port memory 163a has read ports 1r, 2r, 3r and 4r. The write ports 1w, 2w, 3w, and 4w correspond to the read ports 1r, 2r, 3r, and 4r, respectively. The number of the multiplier 163b, the adder 163c, the pipeline register 163d, the write port, and the read port is not limited to that shown in FIG.

The multiplier 163b outputs a value obtained by multiplying the element of the vector x and the element of the matrix A. The adder 163c is connected to one of a plurality of write ports and a read port corresponding to the write port. The adder 163c writes the value output by the multiplier 163b and the partial sum corresponding to the row of the second element read from the read port to the multiport memory 163a from the write port.

The arithmetic unit 163 can execute the calculation of the partial sum of the vectors y in parallel by using the combination of the plurality of multipliers 163b, the adder 163c, and the write port and the read port. Therefore, the allocation unit 162 can set the element of the vector y as the responsible element in each calculation unit 163 and allocate the calculation data of each charge element to each calculation unit 163.

[Processing flow]
Next, the process in this embodiment will be described with reference to FIG. FIG. 11 is a flowchart showing an example of the processing by the CG method in the first embodiment. First, the conversion unit 11 of the conjugate gradient method control device 10a compresses the coefficient matrix and converts it into a column-oriented format (step S10). Further, the conversion unit 11 stores the converted coefficient matrix in the calculation data storage unit 13 of the sparse matrix vector product calculation device 10b.

Next, the preprocessing unit 15 of the sparse matrix vector product arithmetic unit 10b acquires the sparse matrix from the arithmetic data storage unit 13 and executes the preprocessing (step S20). At this time, the pre-processing unit 15 reconfigures each processing unit in advance in order to execute the pre-processing designated by the pre-processing control unit 14. Further, the preprocessing unit 15 stores the preprocessed arithmetic data in the arithmetic data storage unit 13.

Next, the acceleration unit 16 executes SpMV (step S30). The execution of SpMV by the acceleration unit 16 will be described later. Here, when the preset end condition of the CG method is not satisfied (step S40: No), the sparse matrix vector product arithmetic unit 10b returns to S20 and repeats the process. On the other hand, when the preset end condition of the CG method is satisfied (step S40: Yes), the conjugate gradient method control device 10a and the sparse matrix vector product calculation device 10b end the process. For example, the end condition The end condition may be that the iteration is performed a predetermined number of times, or that the residual of the constant vector has converged.

The processing of SpMV by the sparse matrix vector product arithmetic unit 10b will be described with reference to FIG. FIG. 12 is a flowchart showing an example of SpMV processing in the first embodiment. First, the reading unit 161a of the acceleration unit 16 reads the operation data from the operation data storage unit 13 (step S310). The arithmetic data includes each element of the coefficient matrix and the solution vector expressed in a column-oriented format.

Next, the allocation unit 162 allocates the calculation data to each calculation unit 163 (step S320). Then, the calculation unit 163 executes a calculation using the assigned calculation data (step S330). The arithmetic processing by the arithmetic unit 163 will be described later.

Here, when there is unread arithmetic data in the arithmetic data storage unit 13 (step S340: Yes), the reading unit 161a returns to S310 and repeats the process. On the other hand, when there is no unread arithmetic data in the arithmetic data storage unit 13 (step S340: No), the sparse matrix vector product arithmetic unit 10b ends the process.

The arithmetic processing by the arithmetic unit 163 will be described with reference to FIG. FIG. 13 is a flowchart showing an example of the arithmetic processing in the first embodiment. Here, it is assumed that the coefficient matrix is expressed in JAD format. First, value [i], x [colind [i]], jdptr, and perm are input to the calculation unit 163 as calculation data (step S331). At this time, value [i] and x [colind [i]] are input to the multiplier 163b. Further, jdptr and perm are input to the pipeline register 163d.

Here, the adder 163c reads y [perm [j]] from any of the read ports of the multiport memory 163a according to the jdptr and perm input to the pipeline register 163d (step S332). Next, the adder 163c adds value [i] * x [colind [i]] to y [perm [j]] (step S333). Then, the adder 163c writes y [perm [j]] from the write port corresponding to the read port that has read y [perm [j]] according to the jdptr and perm input to the pipeline register 163d (step S334). ).

[effect]
As described above, the arithmetic data storage unit of the sparse matrix vector product arithmetic unit in this embodiment stores the arithmetic data input from the conjugate gradient method control apparatus that controls the conjugate gradient method. The operational data includes a vector that can calculate the product of a sparse matrix and a sparse matrix compressed in a columnar format. The sparse matrix vector product arithmetic unit reads the vector and the sparse matrix from the arithmetic data storage unit. The sparse matrix vector product operation device performs the operation of the sparse matrix vector product using the read vector and the sparse matrix. The sparse matrix vector product arithmetic unit writes the arithmetic result in the arithmetic data storage unit. As described above, after the coefficient matrix is input from the conjugate gradient method control device to the arithmetic data storage unit, the sparse matrix vector product operation device repeatedly performs SpMV without performing transfer between the devices of the sparse matrix. be able to. Therefore, the sparse matrix vector product arithmetic unit can speed up the CG method.

Further, the sparse matrix vector product arithmetic unit has a first element which is an element of a vector and a second element which is a non-zero element of a sparse matrix corresponding to the first element among a plurality of arithmetic units. It is assigned to the arithmetic unit previously associated with the line of the second element of. When the first element and the second element are assigned, the calculation unit executes an operation for obtaining the product of the first element and the second element and the sum of the products. Thereby, the sparse matrix vector product arithmetic unit can execute SpMV using the coefficient matrix represented in the column-oriented format.

Further, the arithmetic data storage unit specifies, as arithmetic data, the first data storing the second element, the second data specifying the column of the second element, and the row of the second element. At least the data of 3 may be stored. The sparse matrix vector product arithmetic unit uses the second element stored in the first data and the vector element corresponding to the column of the second element specified by the second data as the third data. And assign it to the arithmetic unit. As a result, the sparse matrix vector product arithmetic unit can handle the coefficient matrix as an array.

The multi-port memory of the arithmetic unit includes a plurality of write ports and read ports corresponding to each of the plurality of write ports, and stores the partial sum in association with the rows of a sparse matrix. The plurality of multipliers output a value obtained by multiplying the first element and the second element. The adder is connected to one of the write ports and the read port corresponding to that write port, the value output by the multiplier and the second element read from the read port. Write the value obtained by adding the partial sum corresponding to the line from the write port to the multiport memory. As a result, the sparse matrix vector product arithmetic unit can further perform parallel calculation inside each arithmetic unit.

The arithmetic data storage unit may have at least the same number of ports as the number of arithmetic units. As a result, the sparse matrix vector product arithmetic unit can read the arithmetic data in parallel for each arithmetic unit and perform parallel processing of SpMV.

The arithmetic data storage unit may store a sparse matrix compressed in ELL format or JAD format. As a result, the sparse matrix vector product arithmetic unit can obtain a coefficient matrix represented in a column-oriented format.

The pre-processing unit may include a processing unit corresponding to each of a plurality of pre-processing for preset arithmetic data, and may execute the pre-processing using the processing unit corresponding to the designated pre-processing. The pre-processing control unit designates the pre-processing specified by the conjugate gradient method control device for the pre-processing unit. As a result, the sparse matrix vector product arithmetic unit can be made to execute the preprocessing specified by the user for the conjugate gradient method controller.

The preprocessing unit may execute preprocessing each time the operation of the sparse matrix vector product by the arithmetic unit is completed. The arithmetic unit executes a sparse matrix vector product operation each time the preprocessing by the preprocessing unit is completed. As a result, the sparse matrix vector product arithmetic unit can repeat SpMV without transferring the arithmetic data between the apparatus.

[system]
Further, it is also possible to manually perform a part of the processes described as being automatically performed among the processes described in each embodiment. Alternatively, all or part of the process described as being performed manually can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above document and drawings can be arbitrarily changed unless otherwise specified.

Further, each component of each of the illustrated devices is a functional concept, and does not necessarily have to be physically configured as shown in the figure. That is, the specific form of distribution or integration of each device is not limited to the one shown in the figure. That is, all or a part thereof can be functionally or physically distributed / integrated in any unit according to various loads, usage conditions, and the like. For example, the pretreatment unit 15 and the acceleration unit 16 shown in FIG. 4 may be integrated. Further, each processing function performed by each device is realized by a predetermined processor (CPU, GPU, FPGA, etc.) and a program analyzed and executed by the processor, or a program in which all or any part thereof is analyzed and executed. It can be realized as hardware by wired logic.

[Hardware configuration]
FIG. 14 is a diagram showing a hardware configuration example. As shown in FIG. 14, the simulation device 10 has a communication interface 50a, an HDD (Hard Disk Drive) 50b, a memory 50c, a CPU 10d, and an FPGA 50e.

The communication interface 50a is a network interface card or the like that controls communication of other devices. The HDD 50b is an example of a storage device that stores programs, data, and the like. Examples of the memory 50c include RAM (Random Access Memory) such as SDRAM (Synchronous Dynamic Random Access Memory), ROM (Read Only Memory), flash memory and the like. The CPU 50d functions as the conjugate gradient method control device 10a. Further, the FPGA 50e functions as a sparse matrix vector product arithmetic unit 10b.

10 Simulation device 10a Conjugated gradient method control device 10b Sparse matrix vector multiplier calculation device 11 Conversion unit 12 Update unit 13 Operation data storage unit 14 Preprocessing control unit 15 Preprocessing unit 16 Acceleration unit 161 Load unit 161a Reading unit 161b Writing unit 162 Allocation unit 163 Arithmetic unit 163a Multiport memory 163b Multiplier 163c Adder 163d Pipeline register

Claims (7)

Arithmetic data input from a conjugate gradient method controller that controls the conjugate gradient method, including a vector that can calculate the product of a sparse matrix and the sparse matrix compressed in a column-oriented format. Arithmetic data storage unit to store and
A reading unit that reads the vector and the sparse matrix from the arithmetic data storage unit,
An arithmetic unit that executes an operation of a sparse matrix vector product using the vector read by the reading unit and the sparse matrix.
A writing unit that writes the result of the calculation by the calculation unit to the calculation data storage unit, and a writing unit.
The first element, which is an element of the vector, and the second element, which is a non-zero element of the sparse matrix corresponding to the first element, are combined with the second element of the plurality of arithmetic units. It has a line of and an allocation unit to be assigned to the arithmetic unit associated in advance.
The calculation unit
A multi-port memory having a plurality of write ports and a read port corresponding to each of the plurality of write ports and storing the partial sum in association with the rows of the sparse matrix.
When the first element and the second element are assigned, a plurality of multipliers that output a value obtained by multiplying the first element and the second element, and a plurality of multipliers.
The value output by the multiplier and the row of the second element read from the read port connected to any one of the plurality of write ports and the read port corresponding to the write port. A plurality of adders that write the sum of the corresponding partial sums from the write port to the multiport memory, and
A sparse matrix vector product arithmetic unit characterized by having. As the calculation data, the calculation data storage unit stores the first data in which the second element is stored, the second data for specifying the column of the second element, and the row of the second element. At least memorize the third data to be identified and
The allocation unit uses the second element stored in the first data and the element of the vector corresponding to the column of the second element specified by the second data as the third element. The sparse matrix vector product calculation device according to claim 1 , wherein the data is assigned to the calculation unit together with the data of the above. The sparse matrix vector product arithmetic unit according to claim 1 or 2 , wherein the arithmetic data storage unit includes at least as many ports as the number of arithmetic units. The sparse matrix vector product arithmetic unit according to any one of claims 1 to 3 , wherein the arithmetic data storage unit stores the sparse matrix compressed in an ELL format or a JAD format. A pre-processing unit that has a processing unit corresponding to each of a plurality of pre-processing for the arithmetic data set in advance and executes pre-processing using the processing unit corresponding to the specified pre-processing, and a pre-processing unit.
A pre-processing control unit that designates the pre-processing specified by the conjugate gradient method control device for the pre-processing unit,
The sparse matrix vector product arithmetic unit according to any one of claims 1 to 4, further comprising. The preprocessing unit executes preprocessing each time the calculation of the sparse matrix vector product by the calculation unit is completed.
The sparse matrix vector product arithmetic unit according to claim 5 , wherein the arithmetic unit executes an operation of a sparse matrix vector product each time the preprocessing by the preprocessing unit is completed. Arithmetic data input from a conjugate gradient method controller that controls the conjugate gradient method, including a vector that can calculate the product of a sparse matrix and the sparse matrix compressed in a column-oriented format. A sparse matrix vector product arithmetic unit having an arithmetic data storage unit to store
The vector and the sparse matrix are read from the arithmetic data storage unit, and the vector and the sparse matrix are read.
The first element, which is an element of the vector, and the second element, which is a non-zero element of the sparse matrix corresponding to the first element, are combined with the second element of the plurality of arithmetic units. Assign to the arithmetic unit associated with the line in advance,
The arithmetic unit to which the first element and the second element are assigned is made to execute the operation of the sparse matrix vector product using the vector and the sparse matrix read by the reading process.
Run the process of writing the result of arithmetic in the arithmetic data storage unit,
The process of executing the above operation is
A plurality of multipliers are made to output a value obtained by multiplying the first element and the second element.
Multiple additions connected to one of the write ports of the multiport memory that stores the partial sum in association with the rows of the sparse matrix and the read port of the multiport memory corresponding to the write port. The device is made to write the value output by the multiplier and the partial sum corresponding to the row of the second element read from the read port to the multiport memory from the write port. A characteristic sparse matrix vector product calculation method.

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