JP6981057B2 - Data transfer device and data transfer method - Google Patents

Description

The present invention relates to a data transfer device and a data transfer method.

An image processing device that transfers image data line by line using a high-speed serial interface such as PCI Express (registered trademark) that transfers image data between a scanner or plotter and a controller is known. When performing high-speed serial communication, in order to improve transfer efficiency, a configuration is adopted in which transfer data is buffered in a certain amount and data is transferred without interruption.

When buffering transfer data, there is a disadvantage that arbitration does not work in a situation where the buffer is filled with a request with a low priority before a request with a high priority is generated. A data transfer method that generates traffic statistics and feeds them back to the arbiter in order to make proper arbitration work against the demerit is already known (for example, Patent Document 1).

However, in the data transfer method in the conventional technology, it is not focused that the main factor that prevents proper arbitration is the increase in read latency, and there is no means for monitoring the read latency, so that the traffic There was a problem that it took a relatively long time to generate statistical information and feed it back to the arbiter.

The present invention has been made in view of the above points, and an object thereof is to reduce read latency and to surely complete the transfer of data for one line of images within a predetermined transfer cycle of one line.

Therefore, in order to solve the above-mentioned problems, the data transfer device receives a read request and a write request and transfers them to an interface that accesses the memory, and a transfer unit that is transferred to the interface and data transfer from the memory is completed. and a read request measuring unit for measuring a number of previously thrown a number of not a have the rie de request, the transfer unit, from the time when the number of throwing the destination becomes a first value or more, the interface the transfer of write requests to the number of throwing the destination is interrupted until reduced to less than the first value.

The read latency can be reduced, and the transfer of data for one line of images can be reliably completed within a predetermined transfer cycle of one line.

It is a figure for demonstrating a write data buffer. It is a figure for demonstrating the latency at the time of a read operation. It is a figure for demonstrating the relation between the read latency and the processing performance at the time of read modify write (RMW) operation. It is a figure which shows the hardware configuration example of the data transfer apparatus 100 in 1st Embodiment. It is a figure which shows the functional configuration example of the data transfer apparatus 100 in 1st Embodiment. It is a figure which shows the functional structure example of the read-write transfer band arbitration part 105 in 1st Embodiment. It is a flowchart for demonstrating operation of the Outstanding number measuring unit 12 in 1st Embodiment. It is a flowchart for demonstrating the operation of the read / write transfer band arbitration section 105 in 1st Embodiment. It is a figure which shows the functional structure example of the read-write transfer band arbitration section 105 in the 2nd Embodiment. It is a flowchart for demonstrating the operation of the read / write transfer band arbitration section 105 in the 2nd Embodiment. It is a figure which shows the functional structure example of the read-write transfer band arbitration part 105 in 3rd Embodiment. It is a figure for demonstrating the operation of the write request counting part 17 in 3rd Embodiment. It is a flowchart for demonstrating the operation of the write request counting part 17 in 3rd Embodiment. It is a flowchart for demonstrating operation of the read-write transfer arbitration section 11 in 3rd Embodiment. It is a figure which shows the functional structure example of the read-write transfer band arbitration part 105 in 4th Embodiment. It is a figure for demonstrating the operation of the write request counting part 17 in 4th Embodiment. It is a flowchart for demonstrating the operation of the write request counting part 17 in 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining a write data buffer. As a background, if a buffer for transfer is provided, the time for processing the request stored in the buffer increases. The read request is a non-posted transfer, that is, a transfer that requires a notification of the completion of processing, and there is a limitation on the number of cuttings (the number of unprocessed requests or the number of forward-throwing requests). Therefore, when the number of Outputs reaches the upper limit, the next read request is issued after waiting for a read response to be returned. Here, if the write request fills the empty buffer during the read response waiting period, the read transfer band is further lowered, and it is easy to fall into a situation where the write transfer band is excessive. Further, in a high-speed MFP (Multi Function Peripheral), the one-line data transfer period is several tens of us, so that the time required for proper arbitration execution is required to be several us to several tens of us or less. A write request issued during the period when no read request is issued fills the transfer buffer, and waiting for the completion of the write request and the write data transfer increases the read latency, resulting in a decrease in the read transfer bandwidth. Problems occur.

When there is a difference between the buffer write speed and the buffer read speed, the time required from the state where the data written in the write data buffer for buffering is full to the time when all the data is read will be described below.

For example, if the size of the write data buffer is 4096 Bytes and the read speed of the buffer is 1000 MB / s, the time from the full state to the empty write data buffer is 4096 [Byte] / 1000 [MB / s] =. It becomes 4.096 [us]. In order to maintain the issuance order of read requests and write requests, read requests issued after the write data buffer is full are always read from the 4096 BYte write data stored prior to the write data buffer. It will be processed after it is issued. Assuming that the normal read latency is 0.5 us, the read latency issued with the write data buffer in the FULL state is 0.5 [us] + 4.096 [us] = 4.596 [us]. It will be an increasing calculation.

To prevent the write data from staying in the write data buffer, the buffer write speed may be slower than the buffer read speed. However, if the buffer read speed dynamically changes due to processing by the arbiter at the end of the buffer, the buffer read speed It is necessary to have a mechanism to slow down the buffer writing speed by following the above. If the buffer read speed cannot be directly observed on the master side, the retention state of the write data in the write data buffer can be predicted by observing the read latency, and it is possible to indirectly understand that the buffer read speed is decreasing. can. That is, the read latency is monitored by monitoring the retention state of the write data buffer by the number of outputs obtained from the difference between the number of read requests issued and the number of read responses received, and suppressing the write requests so that the number of outputs does not reach the upper limit. A method of preventing the increase of the number is conceivable.

FIG. 2 is a diagram for explaining the latency during read operation. 2 (A) and 2 (B) both show an example in which four read requests are thrown ahead (Outstanding) at the same timing.

FIG. 2A is an example in which the read response (RD1 to RD8) to the read request (RC1 to RC8) is responsive to the read data transfer without any time gap. The read response or read data corresponding to the read request RC1 is RD1, and RD2 to RD8 also correspond to RC2 to RC8, respectively. When the read request is transmitted at the timing shown in FIG. 2A, if the read response time is shorter than that in FIG. 2A, there is no period during which the read data is not transferred during the read data transfer, so that the read is read. The band is maintained in an ideal amount.

On the other hand, FIG. 2B shows an example in which a period in which read data is not transferred occurs during read data transfer due to an increase in read latency, that is, read response time. If there is a period during which read data is not transferred due to an increase in read latency, a write request is likely to be made during that period, the increase in read latency is accelerated, and the read bandwidth is rapidly reduced.

FIG. 3 is a diagram for explaining the relationship between read latency and processing performance during read-modify-write (RMW) operation. FIG. 3A is an example of executing RMW processing. In the RMW processing, a part of the image on the memory is read out, the image processing is performed, and the next image processing cannot be started until the image is written back again. Therefore, the period during which the image processing means performs image processing and the period during which the image to be processed is read / written from the memory affect the RMW processing time.

In FIG. 3B, the read response time is shortened, so that the waiting time of the image processing means is reduced. In the example shown in FIG. 3B, the image processing performance is improved by 1.5 times as compared with FIG. 3A.

FIG. 4 is a diagram showing a hardware configuration example of the data transfer device 100 according to the first embodiment. As shown in FIG. 4, the data transfer device 100 includes a CPU (Central Processing Unit) 1001, a ROM (Read Only Memory) 1002, a RAM (Random Access Memory) 1003, a wired logic circuit 1004, and an interface connected to each other. It has 1005 and.

The program that realizes the processing in the data transfer device 100 is stored in the ROM 1002 or the RAM 1003. The ROM 1002 or the RAM 1003 stores the installed program and also stores necessary files, data, and the like. The ROM 1002 may be any of a mask ROM, a PROM (Programmable ROM), an EEPROM (Electrical Erasable ROM), a flash memory, a memory card as an external storage medium, or a plurality thereof. The RAM 1003 may be any of DRAM (Dynamic RAM), SRAM (Static RAM), SDRAM (Synchronous DRAM) and the like. Further, the ROM 1002 or the RAM 1003 may be connected to the CPU 1001 via a memory controller. The wired logic circuit 1004 is a circuit that executes the processing performed by the data transfer device 100 by the wired logic, and is composed of a flip-flop, a gate circuit, and the like. The interface 1005 includes a high-speed serial interface, and may also include other input / output ports and the like.

The data transfer device 100 is one or a plurality of LSI (Large Scale Integration) devices, LSI chips, LSI chipsets, ASICs (Application Specific Integrated Circuits), etc., which include a part or all of the above-mentioned hardware configuration. You may.

Further, the data transfer device 200 may have the same hardware configuration as the data transfer device 100.

FIG. 5 is a diagram showing a functional configuration example of the data transfer device 100 according to the first embodiment. As shown in FIG. 5, the data transfer device 100 has an I / F control function 106 including a function A101, a function B102, a function C103, an arbiter 104, a read / write transfer band arbitrator 105, and a write data buffer. Each of these parts is realized by a process of causing the CPU 1001 to execute one or more programs installed in the data transfer device 100 or a wired logic circuit 1004.

The data transfer device 200 has a function a201, a function b202, an arbiter 203, an I / F control function 204 including a write data buffer, and a memory controller 205 connected to the shared memory 300.

The data transfer device 100 having a master function (function A101 or the like) that requests memory access to the shared memory 300 and the data transfer device 200 that controls access to the shared memory 300 and the shared memory 300 have a posted write request. It is connected by a Write type I / F. The posted-write method is a method that does not require notification of the completion of processing. When the shared memory 300 is write-accessed from the function A101, the write data is shared memory via the buffer (speed buffering write data buffer) implemented in the I / F control function 106 and the I / F control function 204, respectively. Transferred to 300.

Here, the write band from the I / F control function 204 to the arbiter 203 is increased because the function a201 or the function b202 mounted on the data transfer device 200 accesses the memory controller 205 and the arbiter 203 is congested. When the write data transfer speed from the function A101 is reduced due to restrictions, the write data from the function A101 is transferred to the Buf (speed buffering write data buffer) implemented in the I / F control function 106 and the I / F control function 204. ) Accumulates.

In order to maintain the issuance order of read requests and write requests, read requests issued later are always processed after the write data stored in advance of the speed buffer write data buffer is read from the buffer. .. As described above, the accumulation of write data in the write data buffer causes a delay in the read response, resulting in a decrease in the read band and a decrease in the processing performance of the function for performing the read modify / write operation.

The read / write transfer band arbitration unit 105 constantly measures the number of read request destination throws (Outstanding number), and the number of read request destination throws is a hardware-like read request determined by the buffer capacities of the data transfer device 100 and the data transfer device 200. If the upper limit of the number of first throws is exceeded, the transfer of the write request is interrupted. The increase in read latency due to the accumulation of write data in the write data buffer for speed buffer is eliminated by the temporary interruption of the write request, and the read response is restored. The read / write transfer band arbitration unit 105 may arbitrate the read band with a predetermined degree of priority, or may arbitrate so that the read band and the write band are equal to each other.

The shared memory 300 is a storage unit that temporarily stores image data, a program for the CPU, and the like. The data processed by the functions A101, B102, C103 or the functions a201 and b202 is expanded in the shared memory 300.

The data transfer device 100 has one or more built-in functions (function A101, function B102, function C103) that access the shared memory 300 as a master and perform finite read request destination throwing (Outstanding). Further, the data transfer device 100 is a device provided with an I / F control function 106 that serves as an access route to the shared memory 300 for a posted-write write request and a read request for the shared memory 300. In this embodiment, the data transfer device 200 is connected by an I / F that makes a posted-write write request. The I / F control function 106 is equipped with a Buf (speed buffering write data buffer) in order to improve the transfer efficiency of write data. The read / write transfer band arbitration unit 105 will be described in detail with reference to FIG.

The data transfer device 200 includes an I / F control function 204 for passing a read / write request from the data transfer device 100 to the shared memory 300, and a memory controller 205 connected to the shared memory 300, via an arbiter 203. Access the shared memory 300. The arbiter 203 may wait for write access from the I / F control function 204 to the memory controller 205 due to reasons such as concentration of access from the function a201 or the function b202 to the shared memory 300. The I / F control function 204 is equipped with a Buffer (speed buffering write data buffer) in order to improve the transfer efficiency of write data.

FIG. 6 is a diagram showing a functional configuration example of the read / write transfer band arbitration unit 105 according to the first embodiment. FIG. 6 shows the detailed function of the read / write transfer band arbitration unit 105 shown in FIG.

The read / write transfer band arbitration unit 105 may be built in the data transfer device 100 and may be realized by a wired logic composed of a flip-flop and a gate circuit. The write request, read request, and read data (read response) output from the data transfer device 100 are relayed, and the read request destination throwing number (output number) is constantly monitored from the read request and read response (Outstanding number measuring unit 12). ), A function to stop the write request (read / write transfer arbitration unit) when the number of read destination throws (output number) exceeds the hardware upper limit determined by the buffer capacity of the data transfer device 100 and the data transfer device 200. 11 and a write request transfer unit 15).

The operation of each function will be described below.

The Output number measuring unit 12 measures the number of forward throws (Outstanding number) of the read request from the read request transfer information received from the read request transfer unit 13 and the read response transfer information received from the read data transfer unit 14. Since the read request is outgoing, the next read request may be issued before the read data corresponding to the previously issued read request is returned. The measured Output number information is notified to the read / write transfer arbitration unit 11 at the timing when the read request transfer information is received from the read request transfer unit 13 and at the timing when the read response transfer information is received from the read data transfer unit 14.

The read request transfer unit 13 observes the read request transferred from the arbiter 104 to the I / F control function 106 by constantly monitoring the data transfer protocol, and every time the read request is transferred, it is monitored as read request transfer information. Notify the number measuring unit 12.

The read data transfer unit 14 observes the read data transferred from the I / F control function 106 to the arbiter 104 by constantly monitoring the data transfer protocol, and every time the read data is transferred, it is installed as read response transfer information. Notify the number measuring unit 12.

The read / write transfer arbitration unit 11 writes during the period in which the Output number information notified from the Output number measurement unit 12 exceeds the hardware upper limit value determined by the buffer capacities of the data transfer device 100 and the data transfer device 200. The write request transfer interruption instruction is continuously issued to the write request transfer unit 15 so as to stop the request.

The write request transfer unit 15 transfers the write request transferred from the arbiter 104 to the I / F control function 106, and sends a write request while the read / write transfer arbitration unit 11 issues a write request transfer interruption instruction. It works to temporarily stop.

Like the write request transfer unit 15, the write data transfer unit 16 may operate to interrupt the write data transfer in response to the write request transfer interruption instruction from the read / write transfer arbitration unit 11.

FIG. 7 is a flowchart for explaining the operation of the Monitoring number measuring unit 12 in the first embodiment.

The Output number measuring unit 12 repeats the operations of S01 to S08 for each clock (synchronous signal) when the reset of the device is released. The end is not shown in FIG. 6 because the completion of the operation is a system reset or power off to the data transfer device 100.

In step S01, the read request transfer unit 13 determines whether or not a new read request has been transferred. If the new read request has been transferred, the process proceeds to step S02 (YES in S01), and if the new read request has not been transferred, the process proceeds to step S04 (NO in S01).

In step S02, the read request transfer unit 13 notifies the reading request transfer information to the updating number measurement number 12. Subsequently, the Outstanding number measuring unit 12 counts up the read request destination throwing counter based on the read request transfer information notified from the read request transfer unit 13 (S03).

In step S04, the read data transfer unit 14 determines whether or not new read data has been transferred. If new read data has been transferred, the process proceeds to step S05 (YES in S04), and if no new read data has been transferred, the process proceeds to step S07 (NO in S04).

In step S05, the read data transfer unit 14 notifies the updating number measurement unit 12 of the read response transfer information. Subsequently, the Output number measuring unit 12 counts down the read request destination throwing counter based on the read response transfer information received from the read data transfer unit 14 (S06). Here, if the read request destination throw counter has been counted up in step S03, the read request destination throw counter is counted down in step S06, so that the read request destination throw counter becomes plus or minus zero, and the counter becomes counter. The value does not change.

In step S07, the Output number measuring unit 12 notifies the read / write transfer arbitration unit 11 of the value of the read request destination throw counter as the Output number information.

In step S08, the clock (synchronous signal) input is awaited, and the process returns to step S01.

FIG. 8 is a flowchart for explaining the operation of the read / write transfer band arbitration unit 105 in the first embodiment. The read / write transfer arbitration unit 11 repeats the operations of S01 to S04 for each clock (synchronization signal) when the reset of the device is released. The end is not shown in FIG. 7 because the completion of the operation is a system reset or power off to the data transfer device 100.

In step S11, it is determined whether or not the number of Outputs received from the Output number measuring unit 12 is equal to the upper limit value in terms of hardware determined from the buffer capacity of the number of read request destinations (the number of Outputs). If the number of Outputs received from the Output number measuring unit 12 is equal to the upper limit of the number of read request destination throws, the process proceeds to step S13 (YES in S11). NO of S11).

In step S12, the write request transfer interruption instruction is negated to the write request transfer unit 15. If the write request transfer interruption instruction has been negated before, the output of the negate is continued.

In step S13, the write request transfer interruption instruction is asserted to the write request transfer unit 15. If the write request transfer suspension instruction has been previously asserted, the asserted output is continued.

In step S14, the read / write transfer band arbitration unit 105 waits for a clock (synchronous signal) input and returns to step S01.

The write request transfer unit 15 suspends the transfer of the write request transferred from the arbiter 104 during the period in which the write request transfer interruption instruction is asserted, and executes the write request transfer only during the negated period.

As described above, according to the first embodiment, when the read request destination throwing number reaches the upper limit value, the data transfer device 100 interrupts the transfer of the write request, so that the transfer band is written. It is possible to prevent a state of excessive demand. That is, the data transfer device 100 can reduce the read latency and reliably complete the transfer of data for one image line within a predetermined transfer cycle of one line.

Next, the second embodiment will be described. The second embodiment will explain the differences from the first embodiment. Therefore, the same as in the first embodiment may be used without particular mention.

FIG. 9 is a diagram showing a functional configuration example of the read / write transfer band arbitration unit 105 according to the second embodiment.

In the second embodiment, in addition to the function of the read / write transfer band arbitration unit 105 in the first embodiment, the read request destination for determining the write request interruption instruction assert to be performed by the read / write transfer arbitration unit 11. A function is added in which the number of throws (number of arbitrations) can be arbitrarily set from the CPU 1001 after the reset release of the data transfer device 100 is released. Since the number of write requests is excessive and the time required for write data transfer increases, the read latency increases, and as a result, the number of outputs is increased. Therefore, the number of outputs is determined by the buffer capacity, etc. in terms of hardware. By suppressing the issuance of write requests when an arbitrary number of monitoring is reached before the upper limit is reached, it is possible to shorten the period during which the read latency is increased. Since the threshold value of the optimum number of cuttings depends on the characteristics of the entire system, particularly the data transfer device 200, and the usage of the system, the data transfer device 100 has a function that can be set to an arbitrary value from the CPU 1001 according to the system. It can be adapted to multiple different systems without changing the specifications of.

FIG. 10 is a flowchart for explaining the operation of the read / write transfer band arbitration unit 105 in the second embodiment.

In step S21, after the reset release of the data transfer device 100 for turning on the power is released, the CPU 1001 sets the read / write transfer arbitration unit 11 to the number of monitoring which is a threshold value for determining the interruption of the write request transfer. Any value can be set for the number of Outputs that is the threshold value.

Subsequently, it is determined whether or not the number of Outputs received from the Output number measuring unit 12 is equal to the threshold value of the number of Outputs set from the CPU 1001 in step S21. If the number of Outputs received from the Output number measuring unit 12 is equal to or greater than the threshold value, the process proceeds to step S24 (YES in S22), and if they are not equal, that is, if the number is less than the threshold value, the process proceeds to step S23 (NO in S22).

Steps S23 to S25 correspond to steps S12 to S14 shown in FIG. 8, and the operation is the same.

As described above, according to the second embodiment, the data transfer device 100 can set the read / write transfer band arbitration unit 105 to a threshold value of an arbitrary number of printings for determining the interruption of the write request. Therefore, when the number of Outputs reaches the threshold value, the issuance of the write request is suppressed, and the period in which the read latency is increased can be shortened.

Next, a third embodiment will be described. The third embodiment will explain the differences from the second embodiment. Therefore, the same as in the second embodiment may be used without particular mention.

FIG. 11 is a diagram showing a functional configuration example of the read / write transfer band arbitration unit 105 according to the third embodiment.

In the third embodiment, the write request counting unit 17 monitors the issuance of read requests and write requests, and measures the number of write requests issued during a period in which a certain number of read requests are transferred. , Is added as a function to notify the read / write transfer arbitration unit 11. Further, in the write request counting unit 17, the number of read requests for determining the period for executing the write request count is set from the CPU 1001. Further, in the read / write transfer arbitration unit 11, the threshold value of the number of write requests for determining the issuance of the write request interruption instruction is set from the CPU 1001. As shown in FIG. 11, the read request transfer information is input from the read request transfer unit 13 to the write request count unit 17. Further, the write request transfer information is input from the write request transfer unit 15 to the write request count unit 17. Further, the write request counting unit 17 outputs the number of write requests to the read / write transfer arbitration unit 11.

When the number of read requests for determining the period for executing the write request count set by the CPU 1001 is, for example, 4, the number of write requests issued during the period when the latest 4 read requests are issued is counted. Then, the read / write transfer arbitration unit 11 is notified as the number of write requests. The read / write transfer arbitration unit 11 determines the number of write requests from the write request counting unit 17 and the number of write requests for determining the issuance of the write request interruption instruction set from the CPU 1001 under the condition that the number of outstandings is larger than the threshold value set by the CPU 1001. If the number of write requests is equal to or greater than the threshold value, the write request transfer interruption instruction is asserted.

As for the number of read requests that determine the period for executing the write request count, the write request count unit 17 is notified of the number of read destinations (the number of outputs) measured by the Output number measuring unit 12 instead of the set value by the CPU 1001. After providing a path, it may be determined by a method of reflecting the number of lead destination throws (Outstanding number) at that time in real time.

The increase in read latency may be due to the continuous issuance of the most recent write request. Suppressing the transfer of write requests when the read latency is increased by continuously issuing write requests more recently than the number of read requests set by the CPU 1001 that determines the period for performing the write request count. It is also possible to prevent the transfer from being excessively suppressed.

FIG. 12 is a diagram for explaining the operation of the write request counting unit 17 in the third embodiment. The write request counting unit 17 has a finite number and a finite number of counters, and may be implemented by a wired logic circuit, or may be realized by a process in which a program is executed by the CPU 1001.

The “counter 0” shown in FIG. 12 is accumulated while counting up the number of issued write requests based on the write request transfer information notified from the write request transfer unit 15, and is notified by the read request transfer unit 13. Based on the read request transfer information, the value is shifted to counter 1 each time a read request is issued, and 0 is cleared.

The counters 1 to N-1 shift the counter value to the counter having a larger number each time a read request is issued. The counter N discards the counter value each time a read request is issued, and the value of the counter N-1 is newly shifted.

The write request counting unit 17 sums the counter values for the number of read requests preset by the CPU 1001 to obtain the number of write requests, and notifies the read / write transfer arbitration unit 11. That is, the number of write requests notified by the write request counting unit 17 to the read / write transfer arbitration unit 11 is counted for each period in which the preset number of read requests is issued, and the number of write requests issued in the period is counted. It changes accordingly.

FIG. 13 is a flowchart for explaining the operation of the write request counting unit 17 in the third embodiment. When the reset of the data transfer device 100 is released, the write request counting unit 17 performs the operations of steps S32 to S37 for each clock (synchronous signal) after the count period setting (number of read requests) is performed by the CPU 1001. repeat. The end is not shown in FIG. 13 because the completion of the operation is a system reset or power off to the data transfer device 100.

In step S31, the CPU 1001 sets the number of read requests issued to determine the count period of the number of write requests issued in the register held by the write request counting unit 17 after the reset release of the data transfer device 100 after the power is turned on. Any value can be set for the number of issued read requests.

In step S32, when the read request transfer information indicating the issuance of a new read request is notified from the read request transfer unit 13 (YES in S32), the counters 0 to N of the write request count unit 17 set the values of the respective counters. Shifts to a counter whose number is +1. Further, the value of the counter 0 is cleared to 0, the counter N discards the value held by the counter 0, the value held by the counter N-1 is overwritten (step S33), and the process proceeds to step S34. If the read request transfer information indicating that a new read request is issued is not notified from the read request transfer unit 13 (NO in S32), the process proceeds to step S34.

In step S34, when the write request transfer information indicating that a new write request is issued is notified from the write request transfer unit 15 (YES in S34), the write request counting unit 17 increments the value of the held counter 0. (Step S35) The process proceeds to step S36. If the write request transfer information indicating that a new write request is issued is not notified from the write request transfer unit 15 (NO in S34), the process proceeds to step S36.

In step S36, the read / write transfer arbitration unit 11 is notified of the value obtained by adding the counters for the number of read requests set in step S31 as the number of write requests.

In step S37, the write request counting unit 17 waits for a clock (synchronous signal) input and returns to step S32.

FIG. 14 is a flowchart for explaining the operation of the read / write transfer arbitration unit 11 in the third embodiment. Steps S42 and S45 shown in FIG. 14 are added to the flowchart shown in FIG.

Step S41 is the same as step S21 shown in FIG. In step S42, the CPU 1001 sets the number of write request transfers, which is a threshold value for determining the interruption of the write request transfer after the reset release of the data transfer device 100 after the power is turned on. Any value can be set for the number of write request transfers that is the threshold value. Step S43 is the same as step S22 shown in FIG. If YES in step S43, the process proceeds to step S45, and if NO, the process proceeds to step S44.

In step S45, when the number of write requests issued from the write request counting unit 17 is equal to or greater than the threshold value set in step S42 (YES in S45), the process proceeds to step S46, and similarly to step S24 shown in FIG. The write request transfer interruption instruction is asserted to the write request transfer unit 15, and the process proceeds to step S47. If the write request transfer suspension instruction has been previously asserted, the asserted output is continued. On the other hand, when the number of write requests issued from the write request counting unit 17 is less than the threshold value set in step S42 (NO in S45), the process proceeds to step S44, and the write request transfer is interrupted to the write request transfer unit 15. Negative instructions. If the write request transfer interruption instruction has been negated from before, the output of the negate is continued and the process proceeds to step S47. Step S47 is the same as step S25 shown in FIG.

As described above, according to the third embodiment, the data transfer device 100 determines the number of read requests for determining the period for performing the write request count, and the write request transfer as a threshold value for determining the interruption of the write request transfer. By setting the number, it is possible to suppress the transfer of the write request when the read latency is increased by continuously issuing the write request in the latest, and it is possible to suppress the transfer excessively. It can also be controlled to prevent.

In the third embodiment, when the write data transfer is performed by the Non-Posted-Write method, the shift type counter group shown in FIG. 12 is unnecessary, and the data transfer device 100 uses only one counter. , The number of write requests for which the write has not been completed and the write response has not been returned, that is, the number of updating of the write request may be measured. According to the measurement, the data transfer can be controlled based on the number of write requests stored in the buffer, and the read / write transfer bandwidth balance can be arbitrated based on long-term statistics.

Next, a fourth embodiment will be described. The fourth embodiment will explain the differences from the third embodiment. Therefore, the same as in the third embodiment may be used without particular mention.

FIG. 15 is a diagram showing a functional configuration example of the read / write transfer band arbitration unit 105 according to the fourth embodiment.

A function has been added to the write request counting unit 17 to set an upper limit period for the CPU 1001 to count write requests. Further, a function for controlling a period for counting write requests has been added to the write request counting unit 17. In this function, the write request counting unit 17 is provided with a register for holding the read request issuance time for each counter, and the past counter value exceeding the upper limit period for counting write requests set by the CPU 1001 is discarded, and the upper limit is discarded. A new function to determine the number of write requests is added without referring to past information that exceeds the period.

With this function, the count value of the write request accumulated in the period when the master issuing the read request is not operating and there is no read request can be excluded by setting the upper limit period. Specifically, if the read request threshold is set so as to control the balance between the number of write requests and the number of read requests within the range of the number of Read requests that have been arbitrated or less, the read response to the read request will eventually expire after the latency period has passed. Is returned, so the read latency is guaranteed to be a finite period, but in order to average the balance between the read request and the write request over a longer period, the read request threshold is set in a range larger than the number of arbitrations. If it is decided, the master that issues the read request can also measure the number of write requests during the period when the read request is not issued in the first place and prevent it from being reflected in the arbitration control.

FIG. 16 is a diagram for explaining the operation of the write request counting unit 17 in the fourth embodiment. The write request counting unit 17 has a finite number and a finite number of counters, and may be implemented by a wired logic circuit, or may be realized by a process in which a program is executed by the CPU 1001.

“Counter 0” to “Counter N” shown in FIG. 16 are the same as the counters shown in FIG. 12, but further have a read request issuance time storage unit for each counter. As for the read request issuance time, the time when the read request transfer information notified from the read request transfer unit 13 is received is recorded in the "read request issuance time 0" corresponding to the "counter 0", and the read request is sent in the same manner as the counter value. Every time it is issued, it shifts to a counter with a large number. The read request issuance time is compared with the upper limit period for counting write requests, and the counter whose upper limit period has passed is cleared to 0. Therefore, the counter value that has passed the upper limit period is added as 0 to the number of write requests notified to the read / write transfer arbitration unit 11, and is not reflected in the number of write requests.

FIG. 17 is a flowchart for explaining the operation of the write request counting unit 17 in the fourth embodiment. Step S52, step S55 and step S56 shown in FIG. 17 are added to the flowchart shown in FIG.

Step S51 is the same as step S31. In step S52, the CPU 1001 sets an upper limit period for counting write requests in the write request counting unit 17. Step S53 is the same as step S32. Step S54 is the same as step S33.

In step S55, the write request counting unit 17 determines whether or not there is a counter whose read request issuing time exceeds the upper limit period set in step S52. If there is a counter that exceeds the upper limit period (YES in S55), the value of the counter is cleared to 0 (S56). If there is no counter that exceeds the upper limit period (NO in S55), the process proceeds to step S57.

Steps S57 to S60 are the same as steps S34 to S37.

As described above, according to the fourth embodiment, in the data transfer device 100, the master that issues the read request is not operating by setting the upper limit period for counting the write request, and the read request is made. It is possible to clear the count value of the write request accumulated in the past when the period in which there was no is continued. That is, the threshold value of the number of read requests that determines the period for measuring the number of write requests in a range larger than the upper limit of the number of arbitrations determined from the buffer capacity in order to average the balance between the read request and the write request in a longer period. When is set, the master that issues the read request also measures the number of write requests during the period when the read request is not issued in the first place, and it is possible to prevent the measurement result from being reflected in the arbitration control. ..

In the embodiment of the present invention, the shared memory 300 is an example of the memory. The I / F control function 106 is an example of a buffer. The Output number measuring unit 12 is an example of a read request measuring unit. The write request counting unit 17 is an example of a light request measuring unit. The number of Outputs that serves as a threshold value for determining the interruption of the write request transfer is an example of the first value or the third value. The number of read requests issued, which determines the count period for the number of write requests issued, is an example of the second value. The number of write request transfers, which is a threshold value for determining the interruption of the write request transfer, is an example of the fourth value.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such a specific embodiment, and various modifications are made within the scope of the gist of the present invention described in the claims.・ Can be changed.

100 Data transfer device 1001 CPU
1002 ROM
1003 RAM
1004 Wired logic circuit 1005 Interface 101 Function A
102 Function B
103 Function C
104 Arbiter 105 Read / write transfer band arbitrator 106 I / F control function 200 Data transfer device 201 Function a
202 function b
203 Arbiter 204 I / F control function 205 Memory controller 300 Shared memory 11 Read / write transfer mediation unit 12 Output number measurement unit 13 Read request transfer unit 14 Read data transfer unit 15 Write request transfer unit 16 Write data transfer unit 17 Write request count unit

Japanese Patent No. 4878185

Claims (11)

A transfer unit that receives read and write requests and transfers them to an interface that accesses memory.
It has a read request measuring unit that measures the number of forward throws, which is the number of read requests that have been transferred to the interface and the data transfer from the memory has not been completed.
The transfer unit interrupts the transfer of the write request to the interface from the time when the number of forward throws becomes equal to or greater than the first value until the number of forward throws decreases to less than the first value. Transfer device. The data transfer device according to claim 1, wherein the first value is a value based on the capacity of the buffer of the interface. The data transfer device according to claim 1, wherein the first value can be set to any value. Further having a write request measuring unit for measuring the number of received write requests during the period in which the read request of the number of the most recent second value was transferred.
Claims 1 to 3 that the transfer unit interrupts the transfer of the write request when the number of forward throws is the third value or more and the number of the received write requests is the fourth value or more. The data transfer device according to any one of the above. The data transfer device according to claim 4, wherein the third value is a value based on the capacity of the buffer of the interface. The data transfer device according to claim 4, wherein the third value can be set to any value. The data transfer device according to claim 4, wherein the second value is a value based on the number of forward throws. The data transfer device according to any one of claims 4 to 7, wherein the second value can be set to any value. The data transfer device according to any one of claims 4 to 8, wherein the fourth value can be set to any value. The write request measuring unit determines the number of the write requests received during the period in which the read request was transferred, among the read requests having the number of the latest second values, in which the transferred time does not exceed the upper limit period. The data transfer device according to any one of claims 4 to 9 for measurement. The procedure for receiving read and write requests and forwarding them to an interface that accesses memory,
A procedure for measuring the number of forward throws, which is the number of read requests that have been transferred to the interface and the data transfer from the memory has not been completed, and the procedure.
Data for executing a procedure of suspending the transfer of the write request to the interface from the time when the number of first throws becomes equal to or more than the first value until the number of first throws decreases to less than the first value. Transfer method.

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