JP6976078B2 - Element board, recording head, and recording device - Google Patents

Description

The present invention relates to a device substrate, a recording head, and a recording device.

The recording element substrate of the inkjet recording device configured by the semiconductor integrated circuit receives a clock signal (CLK) and an image data signal (DATA) from the recording device main body, and performs a recording operation according to the image data. Due to high-speed printing in recent years, the frequency of clock signals and image data signals has become about several hundred MHz. The clock signal and the image data signal are out of phase due to variations in the transmission circuit and the reception circuit, but as the speed increases, the phase shift becomes significantly more susceptible, making it difficult to synchronize the clock signal and the data signal. .. Therefore, there is a need for a means for correcting the phase shift between the clock signal and the data signal.

As a technique for correcting the phase shift between the clock signal and the data signal, there is a technique in which a PLL (Delay Locked Loop) circuit or a PLL (Phase Locked Loop) circuit is provided on the receiving circuit side. Patent Document 1 discloses an example of an inkjet recording device that corrects a phase shift between a clock signal and a data signal on the transmission circuit side. In the inkjet recording device described in Patent Document 1, the control IC on the recording device main body side (transmission circuit side) repeatedly reads out the image data signal received by the recording element substrate (reception circuit side), and confirms the reception result. The optimum phase correction amount is determined.

International Publication No. 2012/102709

In the prior art, a training period is required for the DLL or PLL to operate stably. In the technique of Patent Document 1, since it is necessary to confirm the reception result of the recording element substrate a plurality of times in order to perform one phase correction, it takes time to determine the phase correction amount. Therefore, there is a problem that it is difficult to periodically correct the phase and it is difficult to follow the phase change due to the temperature change or the change with time.
The present invention has been made to solve the above problems, and is a phase correction means that does not require a training period for stable operation and can follow a phase change due to a temperature change or a time change. It is an object of the present invention to provide a highly reliable circuit configuration.

In order to solve the above problems, the present invention has the following configurations. That is, an element substrate, the element and a driving circuit for driving the device, the first signal and a receiving circuit for receiving the second signal, the first signal and the second signal correcting the phase shift, and a correction circuit for outputting to the driving circuit, the correction circuit includes at least the first signal a first time unit delay time is a plurality of different delay signal to The first generation circuit and the plurality of delay signals generated by the first generation circuit have different delay times in the first time unit with respect to the first signal. A first signal delay circuit comprising a second generation circuit that generates a plurality of delay signals each delayed in a second time unit shorter than one time, and at least the second signal with respect to the second signal . A third generation circuit that generates a plurality of delay signals having different delay times in one time unit and a third generation circuit having different delay times in the first time unit with respect to the second signal. A second signal delay circuit including a fourth generation circuit that generates a plurality of delay signals delayed in the second time unit with respect to a plurality of delay signals generated by the circuit, and the first signal delay circuit. A latch circuit that latches a plurality of delay signals generated by the signal delay circuit is included, the timing of the delay signal latched by the latch circuit and the second signal is compared, and the first is based on the result of the comparison. A first selection circuit that selects a delay signal to be output to the drive circuit from a plurality of delay signals generated by one signal delay circuit, and a plurality of delay signals generated by the second signal delay circuit. The timing of the delay signal latched by the latch circuit and the delay signal selected by the first selection circuit is compared including the latch circuit to be latched, and the second signal delay circuit is based on the result of the comparison. It has a second selection circuit that selects a delay signal to be output to the drive circuit from a plurality of generated delay signals, and the first time is larger than the output delay time of the latch circuit .

According to the present invention, in the circuit configuration, the training period is unnecessary and the phase difference can be corrected instantaneously. Therefore, it is possible to follow the phase change due to the temperature change and the time change, and it is possible to provide a highly reliable circuit configuration.

The external perspective view which shows the structural example of the inkjet recording apparatus. The figure which shows the example of the control structure of the inkjet recording apparatus which concerns on this invention. The figure which shows the structural example of the recording apparatus which concerns on 1st Embodiment. The figure which shows the timing chart of the recording apparatus which concerns on 1st Embodiment. The figure which shows the structural example of the correction circuit which concerns on 1st Embodiment. The figure which shows the timing chart of the 1st signal correction circuit which concerns on this invention. The figure which shows the timing chart of the 2nd signal correction circuit which concerns on this invention. The figure which shows the circuit example of the 1st determination circuit which concerns on this invention. The figure which shows the circuit example of the 1st multiplexer which concerns on this invention. The figure which shows the circuit example of the 2nd determination circuit which concerns on this invention. The figure which shows the circuit example of the 2nd multiplexer which concerns on this invention. The perspective view which shows the structural example of the recording head which concerns on this invention. The figure which shows the circuit example of the minute delay circuit which concerns on 1st Embodiment. The figure for demonstrating the reason why a plurality of delay circuits and determination circuits were provided in this invention. The figure which shows the structural example of the correction circuit which concerns on 2nd Embodiment. The figure which shows the circuit example of the minute delay circuit which concerns on 2nd Embodiment.

In this specification, "record" (sometimes referred to as "print") is not limited to the case of forming significant information such as characters and figures, and may be significant or unintentional. Furthermore, regardless of whether or not it is manifested so that it can be visually perceived by humans, it also represents the case where an image, a pattern, a pattern, etc. is widely formed on a recording medium or the medium is processed.

The term "recording medium" refers not only to paper used in general recording equipment, but also to a wide range of materials such as cloth, plastic film, metal plate, glass, ceramics, wood, and leather that can accept ink. It shall be.

Furthermore, "ink" (sometimes referred to as "liquid") should be broadly construed as in the definition of "print" above. Therefore, by being applied onto the recording medium, it is used for forming images, patterns, patterns, etc., processing the recording medium, or processing ink (for example, coagulation or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be used.

Furthermore, the term "recording element" collectively refers to the ejection port, the liquid passage communicating with the ejection port, and the element that generates energy used for ink ejection, unless otherwise specified.

Further, the term "nozzle" is used as a general term for the ejection port, the liquid passage communicating with the ejection port, and the element for generating energy used for ink ejection, unless otherwise specified.

The element substrate (head substrate) for a recording head used below does not indicate a mere substrate made of a silicon semiconductor, but indicates a configuration in which each element, wiring, and the like are provided.

Further, the term “on the substrate” means not only the top of the element substrate but also the surface of the element substrate and the inside side of the element substrate in the vicinity of the surface. Further, the term "build-in" as used in the present invention is not a term indicating that each element of a separate body is simply arranged as a separate body on the surface of a substrate, and each element is manufactured as a semiconductor circuit. It indicates that it is integrally formed and manufactured on an element plate by a process or the like.

The recording head according to the present invention is used in a recording device provided with a full-line type recording head whose recording width corresponds to the width of a recording medium. However, the present invention is not limited to this, and may be used for a recording device provided with a serial type recording head.

[Overview of recording device]
FIG. 1 is a perspective for explaining the structure of a recording device 100 provided with a full-line inkjet recording head (hereinafter referred to as a recording head) 101K, 101C, 101M, 101Y and a recovery system unit for ensuring stable ink ejection at all times. It is a perspective view.

In the recording device 100, the recording medium 15 is supplied from the feeder unit 17 to the printing position by the recording head 101, and is conveyed by the transfer unit 16 provided in the housing 18 of the recording device 100.

The image is printed on the recording medium 15 from the recording head 101K when the reference position of the recording medium 15 reaches below the recording head 101K that ejects the black (K) ink while conveying the recording medium 15. Is discharged. Similarly, the recording medium 15 reaches each reference position in the order of the recording head 101C for ejecting cyan (C) ink, the recording head 101M for ejecting magenta (M) ink, and the recording head 101Y for ejecting yellow (Y) ink. Then, ink of each color is ejected to form a color image. The recording medium 15 on which the image is printed in this way is discharged to the stacker tray 20 and deposited.

The recording device 100 further includes an ink cartridge (not shown) that can be replaced for each ink for supplying ink to the transport unit 16, the recording heads 101K, 101C, 101M, and 101Y. Further, it has a pump unit (not shown) for supplying ink to the recording head 101 and a recovery operation, a control board (not shown) for controlling the entire recording device 100, and the like. The front door 19 is an opening / closing door for replacing the ink cartridge.

[Control configuration]
Next, a control configuration for executing the recording control of the recording device described with reference to FIG. 1 will be described.

FIG. 2 is a block diagram showing a configuration of a control circuit of the recording device 100. In FIG. 2, the controller 30 includes an MPU 31, a ROM 32, a gate array (GA) 33, and a DRAM 34. The interface 40 is an interface for inputting recorded data. The ROM 32 is a non-volatile storage area and stores a control program executed by the MPU 31. The DRAM 34 is a DRAM that stores data such as recording data and a recording signal supplied to the recording head 101. The gate array 33 is a gate array that controls the supply of recording signals to the recording head 101, and also controls data transfer between the interface 40, the MPU 31, and the DRAM 34. The carriage motor 90 is a motor for conveying the recording head 101 (101K, 101C, 101M, 101Y). The transport motor 70 is a motor for transporting recording paper. The head driver 50 drives the recording head 101. The motor drivers 60 and 80 are motor drivers for driving the transfer motor 70 and the carriage motor 90, respectively.

In a recording device having a configuration using a full-line recording head as shown in FIG. 1, there is no carriage motor 90 or a motor driver 80 for driving the motor. For this reason, parentheses are added in FIG.

Explaining the operation of the control configuration, when the recorded data enters the interface 40, the recorded data is converted into a recording signal for recording between the gate array 33 and the MPU 31. Then, the motor drivers 60 and 80 are driven, and the recording head 101 is driven according to the recording data sent to the head driver 50 to perform recording.

<First Embodiment>
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, the notation of the first, second, ... For each component shown in the following description is given for convenience for the sake of explanation, and does not necessarily match the notation shown in the claims. It's not something to do.

[Recording head configuration]
FIG. 3 is a diagram showing an outline around a recording head 101 included in the recording device 100 according to the first embodiment of the present invention. FIG. 3 shows an example of a full-line type recording head 101. A perspective view of the recording head 101 is shown in FIG. As shown in FIG. 12, the full-line type recording head 101 has a plurality of recording element substrates 103 arranged and has a printing width of 700 or more as a recording medium. The arrangement configuration and shape of the recording element substrate 103 are not limited to those shown in FIG. 12, and may be other configurations.

The recording element substrate 103 receives the first reception circuit 106 that receives the first signal 111 (DATA), the second reception circuit 107 that receives the second signal 112 (CLK), and the third signal 113. A third receiving circuit 108 is provided. The first signal 111, the second signal 112, and the third signal 113 are supplied from the head control IC 109 arranged on the recording device main body board 102 to the respective recording element boards 103 via the transmission line 110. .. In FIG. 3, n recording element substrates 103-1 to 103-n are shown, and it is assumed that they all have the same configuration here. Hereinafter, when individual explanations are required, they are shown with subscripts, and when the explanations are common, the subscripts are omitted.

The first signal 111, the second signal 112, and the third signal 113 are input to the correction circuit 105. The correction circuit 105 corrects the phase difference between the first signal 111 (DATA) and the second signal 112 (CLK) for each cycle of the third signal 113, and corrects the phase difference between the fourth signal 114 (Dadj) and the second signal 112 (CLK). The signal 115 (CKadj) of 5 is output. The fourth signal 114 (Dadj) is a signal in which the phase of the first signal 111 (DATA) is corrected. The fifth signal 115 (CKadj) is a signal whose phase of the second signal 112 (CLK) is corrected. The fourth signal 114 (Dadj) and the fifth signal 115 (CKadj) output from the correction circuit 105 are input to the drive circuit 104. Since the drive circuit 104 is driven by the fourth signal 114 (Dadj) and the fifth signal 115 (CKadj) whose phase difference is corrected, the image data signal and the clock signal can be reliably synchronized. It is possible to receive accurate image data. Each drive circuit 104 corresponds to a recording element (not shown) and drives the corresponding recording element.

FIG. 4 is a diagram showing a timing chart of the recording device 100 according to the first embodiment. The first signal 111 will be referred to as an image data signal (DATA), the second signal 112 will be referred to as a clock signal (CLK), and the third signal 113 will be referred to as a latch signal (LT). The line time refers to the time for printing one column or one line of images on a recording medium. The recording element substrate 103 divides one line time into a predetermined number of blocks and performs time-division driving in which the recording elements are sequentially driven, and the latch time indicates the time per block. The latch signal (LT) is a signal for identifying one block. In FIG. 4, the line time of 1 is divided into latch times of m.

One latch time is composed of a period for transmitting the test flag signal 200, a period for transmitting the image data signal 201, and a pause period 203. The pause period 203 is a period during which the logic of the image data signal (DATA) and the clock signal (CLK) does not transition. The recording device 100 according to the first embodiment instantly corrects the phase shift between the image data signal (DATA) and the clock signal (CLK) during the transmission period of the test flag signal 200 after the pause period 203.

Specifically, the phase difference between the test flag signal 200 transmitted after the pause period 203 and the clock signal (CLK) is grasped, and the optimum phase correction amount is determined. During the period of transmitting the image data signal 201, the determined phase correction amount is maintained, and the phase correction amount is reset at the rising edge of the latch signal (LT). By repeating such an operation every one latch time, the recording device 100 can follow the phase change due to the temperature change and the time change, and can secure the reliability.

FIG. 5 is a diagram showing an example of a block configuration of the correction circuit 105 in the recording device 100 according to the first embodiment. The correction circuit 105 includes a first signal correction circuit 300 that corrects the phase of the first signal 111 (DATA) and a second signal correction circuit 301 that corrects the phase of the second signal 112 (CLK). NS. The first signal correction circuit 300 includes a first delay circuit 302, a second delay circuit 303, a first determination circuit 304, a second determination circuit 305, a first multiplexer 306, and a first timing signal generation circuit. It is composed of 340 and a first minute delay circuit 330. Further, the second signal correction circuit 301 includes a third delay circuit 320, a fourth delay circuit 321, a third determination circuit 322, a fourth determination circuit 323, a second multiplexer 324, and a second timing signal. It is composed of a generation circuit 341 and a second minute delay circuit 331. The operation of the signal delay circuit shown as a delay circuit and a minute delay circuit will be described below.

The operation of the correction circuit 105 will be described below with reference to FIG. The first delay circuit 302 generates (n + 1) / two first delay signals 309 (D_0, D_2, D_4 ... D_n-1) in which the first signal 111 (DATA) is delayed. The first determination circuit 304 compares the phases of the first delay signal 309 and the second signal 112 (CLK). In the first determination circuit 304, the rising edge of which delay signal among the first delay signals 309 (D_0, D_2, D_4 ... D_n-1) is the same as the rising edge of the second signal 112 (CLK). Alternatively, it is determined whether it is the closest, and the first determination signal 307 is output based on the determination result.

Further, in the second delay circuit 303, the first minute delay circuit 330 is connected to the input side. As a result, a signal in which the first signal 111 (DATA) is delayed by the first minute delay circuit 330 is input to the second delay circuit 303, and this is further delayed by the second delay circuit 303. Then, (n + 1) / 2 second delay signals 310 (D_1, D_3, D_5 ... D_n) are generated. The second determination circuit 305 compares the phases of the second delay signal 310 and the second signal 112 (CLK). In the second determination circuit 305, among the second delay signals 310 (D_1, D_3, D_5 ... D_n), the rising edge of which delay signal is the same as or the most rising edge of the second signal 112 (CLK). It is determined whether they are close to each other, and a second determination signal 308 is output based on the determination result. Supplementally, D_1 of the second delay signal 310 is delayed from D_1 of the first delay signal 309 by a time corresponding to the delay amount of the first minute delay circuit 330. D_3 of the second delay signal 310 is delayed from D_2 of the first delay signal 309 by a time corresponding to the delay amount of the first minute delay circuit 330. As described above, each of the second delay signals 310 is delayed by a predetermined time as compared with each of the first delay signals 309.

The first multiplexer 306 sets a delay signal having a near edge determined by the first determination circuit 304 and the second determination circuit 305 based on the first determination signal 307 and the second determination signal 308. It functions as a selection circuit that selects one of the delay signal 309 and the second delay signal 310 and outputs it as the fourth signal 114 (Dadj). That is, the first multiplexer 306 identifies the phase of DATA (first signal 111) based on the first determination signal 307 and the second determination signal 308. The details of the operation here will be described later.

The third delay circuit 320 generates (m + 1) / two third delay signals 327 (CK_0, CK_2, CK_4 ... CK_m-1) in which the second signal 112 (CLK) is delayed. The third determination circuit 322 compares the phases of the third delay signal 327 and the fourth signal 114. In the third determination circuit 322, of the third delay signals 327 (CK_0, CK_2, CK_4 ... CK_m-1), the rising edge of which delay signal is the falling edge of the fourth signal 114 (Dadj). It is determined whether they are the same or the closest, and a third determination signal 325 is output.

The fourth delay circuit 321 further delays the signal obtained by delaying the second signal 112 (CLK) by the second minute delay circuit 331, and (m + 1) / two fourth delay signals 328 (CK_1, CK_3, CK_5 ... CK_m) is generated. The fourth determination circuit 323 compares the phases of the fourth delay signal 328 and the fourth signal 114. In the fourth determination circuit 323, among the fourth delay signals 328 (CK_1, CK_3, CK_5 ... CK_m), the rising edge of which delay signal is the same as the falling edge of the fourth signal 114 (Dadj) or It is determined whether it is the closest, and a fourth determination signal 326 is output based on the determination result. Supplementally, due to the second minute delay circuit 331, each of the fourth delay signals 328 is delayed by a predetermined time as compared with each of the third delay signals 327. For example, CK_1 is delayed from CK_1 by a time corresponding to the delay amount of the second minute delay circuit 331. CK_3 is delayed from CK_2 by a time corresponding to the delay amount of the second minute delay circuit 331.

The second multiplexer 324 has the same or closest delay signal as the edge determined by the third determination circuit 322 and the fourth determination circuit 323 based on the third determination signal 325 and the fourth determination signal 326. A delay signal, which is half the delay time with respect to the delay time, is selected from the third delay signal 327 and the fourth delay signal 328, and is output as the fifth signal 115 (CKadj). That is, the second multiplexer 324 identifies the deviation between DATA (first signal 111) and CLK (second signal 112) based on the third determination signal 325 and the fourth determination signal 326. , Will be corrected. The details of the operation here will be described later.

In FIG. 5, the number of unit delay circuits constituting each delay circuit in the first signal correction circuit 300 and the second signal correction circuit 301 is shown by using different subscripts n and m. n and m may be the same number.

The first delay circuit 302, the second delay circuit 303, the third delay circuit 320, and the fourth delay circuit 321 are composed of a plurality of stages of unit delay circuits 350. FIG. 13A shows a circuit example of the unit delay circuit 350, and is composed of, for example, an eight-stage inverter circuit. The delay time generated in the first minute delay circuit 330 and the second minute delay circuit 331 is configured to be half the delay time (td / 2) of the delay time (td) generated in the unit delay circuit 350. .. FIG. 13B shows another circuit example of the first minute delay circuit 330 and the second minute delay circuit 331, which is a four-stage inverter circuit which is half of the circuit example of the unit delay circuit 350. This is a configured example.

FIG. 6 is a diagram showing a timing chart of the first signal correction circuit 300, and FIG. 7 is a diagram showing a timing chart of the second signal correction circuit 301. FIG. 8 is a diagram showing circuit examples of the first determination circuit 304 and the second determination circuit 305, and FIG. 10 is a diagram showing circuit examples of the third determination circuit 322 and the fourth determination circuit 323. The first determination circuit 304, the second determination circuit 305, the third determination circuit 322, and the fourth determination circuit 323 can be configured only by a digital circuit such as a latch circuit or a flip-flop circuit.

FIG. 9 is a diagram showing a circuit of the first multiplexer 306. The first multiplexer 306 has a first delay signal 309 (D_0, D_2, D_4.) Based on the first determination signal 307 and the second determination signal 308, as shown in the truth table shown in FIG. .... One signal is selected from D_n-1) and the second delay signal 310 (D_1, D_3, D_5 ... D_n) and output as the fourth signal 114 (Dadj). Further, FIG. 11 is a diagram showing a circuit of the second multiplexer 324. The second multiplexer 324 has a third delay signal 327 (CK_0, CK_2, CK_4, based on the third determination signal 325 and the fourth determination signal 326, as shown in the truth table shown in FIG. .... One signal is selected from the CK_m-1) and the fourth delay signal 328 (CK_1, CK_3, CK_5 ... CK_m) and output as the fifth signal 115 (CKadj). The logic shown in the truth table can be realized only by digital circuits such as AND gates and CMOS switches. In addition, "*" shown in the truth table of FIGS. 9 and 11 means don't care.

The detailed operation of the first signal correction circuit 300 will be described below with reference to FIGS. 6, 8 and 9. In the example of FIG. 6, the second signal 112 (CLK) is delayed by the time ts from the position of a in the ideal state with respect to the first signal 111 (DATA), and a phase difference is shown. ing. Further, this is an example in which the test flag signal 200 is set to the 2-bit signal “10”.

In the plurality of latch circuits 600 of FIG. 8, since the first delay signal 309 is input as a latch pulse, the first delay signal 309 (D_0, D_2, D_4 ... D_n-1) is synchronized with each of the first delay signals 309. The logic "High" level is transferred from the first stage latch 600-0 to the second stage latch 600-n-1. Similarly, since the second delay signal 310 is input as a latch pulse in the plurality of latch circuits 602, the first stage is synchronized with each of the second delay signals 310 (D_1, D_3, D_5 ... D_n). The logic "High" level is transferred from the latch 602-1 to the subsequent latch 602-n. Here, a time difference corresponding to the delay time (td) generated in the unit delay circuit 350 occurs between the first delay signals D_0 and D_2. Similarly, a time difference corresponding to the delay time (td) generated in the unit delay circuit 350 occurs between the second delay signals D_1 and D_3. Further, a time difference corresponding to the delay time (td / 2) generated in the first minute delay circuit 330 occurs between the first delay signal D_0 and the second delay signal D_1. As a result, the first delay signal 309 (D_0, D_2, D_4 ... D_n-1) and the second delay signal 310 (D_1, D_3, D_5 ... D_n) are delayed as shown in FIG. The signal is delayed by time dt / 2.

Next, the first timing signal generation circuit 340 generates a signal edge2 synchronized with the rising edge of the second signal 112 (CLK), and the edge2 is input to the plurality of flip-flop circuits 601 and 603. The flip-flop circuits 601 and 603 have the first determination signal 307 (Qd) and the first determination signal 307 (Qd) indicating to which stage of the latch in the latch circuits 600 and 602 the above-mentioned "High" level logic is transferred at the rising edge of the edge2. The second determination signal 308 (Qd) is output.

In the example of FIG. 6, Qd has a “High” level from the 0th bit to the 3rd bit and a “Low” level after the 4th bit, and is the second stage latch 602-3 of the latch circuit 602 driven by the delay signal D_3. Indicates that the "High" level has been transferred to. This means that it is the delay signal D_3 that coincides with the rising edge of the second signal 112 (CLK). The multiplexer 306 of FIG. 9 sets D_3 to the fourth according to the first determination signal 307 (Qd) and the second determination signal 308 (Qd) output from the first determination circuit 304 and the second determination circuit 305. It is output as a signal 114 (Dadj).

Next, the detailed operation of the second signal correction circuit 301 will be described with reference to FIGS. 7, 10, and 11. The plurality of latch circuits 800 in FIG. 10 synchronize with the third delay signal 327 (CK_0, CK_2, CK_4 ... CK_m-1) from the first-stage latch 800-0 to the second-stage latch 800-m-1. The logical "High" level is transferred. Similarly, the plurality of latch circuits 802 synchronize with each of the fourth delay signals 328 (CK_1, CK_3, CK_5 ... CK_m) and logically “High” from the first-stage latch 802-0 to the second-stage latch 802-m. The level is transferred. Here, a time difference corresponding to the delay time (td) generated in the unit delay circuit 350 occurs between the third delay signals CK_0 and CK_2. Similarly, a time difference corresponding to the delay time (td) generated in the unit delay circuit 350 occurs between the fourth delay signals CK_1 and CK_3. Further, a time difference corresponding to the delay time (td / 2) generated in the second minute delay circuit 330 occurs between the third delay signal CK_0 and the fourth delay signal CK_1. As a result, the third delay signal 327 (CK_0, CK_2, CK_4 ... CK_n-1) and the fourth delay signal 328 (CK_1, CK_3, CK_5 ... CK_n) are delayed as shown in FIG. The signal is delayed by time dt / 2.

Next, the second timing signal generation circuit 341 generates a signal edge4 synchronized with the falling edge of the fourth signal 114 (Dadj), and the edge4 is input to the plurality of flip-flop circuits 801 and 803. The third determination signal 325 (Qc) and the third determination signal 325 (Qc) indicating to which stage of the latch in the latch circuits 800 and 802 the above-mentioned "High" level logic was transferred when the flip-flop circuits 801 and 803 started up of edge4. The determination signal 326 (Qc) of 4 is output. Further, the signal edge5 is a signal in which edge4 is captured at the rising edge of CLK, and is supplied to the second multiplexer 324 to be used as a masking signal.

In the example of FIG. 7, Qc has a “High” level from the 0th bit to the 4th bit and a “Low” level after the 5th bit, and the latch 800-4 of the third stage of the latch circuit 800 driven by the delay signal CK_4. Indicates that the "High" level has been transferred to. This means that it is the delay signal CK_4 that coincides with the falling edge of the fourth signal 114 (Dadj). The multiplexer 324 of FIG. 11 selects CK_2 having a delay time half that of CK_4 according to the third determination signal 325 (Qc) and the fourth determination signal 326 (Qc), and the AND gate 901 at the signal edge5. The unnecessary part is masked and output as a fifth signal 115 (CKadj). As a result, the time ts is corrected, the edge of the clock signal returns to the position a in the ideal state, and synchronization with the data signal can be ensured.

The first signal correction circuit 300 is a two-system delay circuit of the first delay circuit 302 and the second delay circuit 303 in order to generate (n + 1) delay signals that delay the first signal 111. It is a feature that it is provided. Further, the first signal 111 input to the second delay circuit 303 by the first minute delay circuit 330 is delayed by (td / 2) hours. With such a configuration, (n + 1) delay signals delayed by (td / 2) time are generated, and the phase can be finely adjusted with the resolution of (td / 2) time.

As shown in FIG. 14, the delay time td of the unit delay circuit 350 needs to be longer than the output delay time lat required for the latch circuit to transfer the “High” level logic to the next-stage latch circuit. (Td> latch). This is because, in order to perform correct phase determination, it is necessary to input a latch pulse (delay signal) to the latch circuit after the first stage of the latch can reliably transfer the High level to the next stage. Since the output delay time flip of the latch circuit is determined by the operating speed of the transistor, it is necessary to lengthen td when a semiconductor process in which the operating speed of the transistor is slow is used. On the other hand, in the present embodiment, as shown in FIG. 14B, the delay circuit and the determination circuit are provided in two systems, and the minute delay circuit is provided to satisfy the constraint of (td> phase) while satisfying the (td / 2) time. The configuration is such that the phase can be adjusted with the resolution of. Therefore, even when it is necessary to lengthen the td, the phase can be adjusted with fine resolution.

The delay time td of the unit delay circuit 350 needs to be larger than the output delay time lat of the latch circuit as described above, but since the resolution is to be as fine as possible, the output delay time 2 lat for two stages of the latch circuit is desired. It is desirable to make it shorter than. That is, it is desirable that the condition is (tlat <td <2tlat). Further, in the present embodiment, an example in which the delay time of the minute delay circuit is configured by td / 2 is shown, but the present invention is not limited to this, and the same effect can be obtained if the delay time of the unit delay circuit is smaller than the delay time td. It is possible to get.

The third delay circuit 320, the fourth delay circuit 321 and the second minute delay circuit 331 of the second signal correction circuit 301 are also provided for the same reason as described above. Since the details are the same as those of the first signal correction circuit 300, the description thereof will be omitted. That is, in the present embodiment, in the correction circuit 105, the first signal correction circuit 300 and the second signal correction circuit 301 each include two delay circuits. Therefore, when the number of delay circuits of the first signal correction circuit 300 and the second signal correction circuit 301 are n and m, the number of delay circuits is two. Further, the number of minute delay circuits provided in each signal correction circuit is indicated by n-1 and m-1, and in the present embodiment, the number of minute delay circuits is the first signal correction circuit 300 and the number of minute delay circuits. There will be one in each of the second signal correction circuits 301.

With the above configuration, the recording device according to the first embodiment of the present invention does not require a training period for the circuit to operate stably, and can instantly correct the phase difference. Further, by correcting the phase periodically (for example, every one latch time), it is possible to follow the change in the phase due to the temperature change or the change with time, and it is possible to secure the reliability.

Further, as described above, the correction circuit according to the present embodiment does not require the capacitance (capacitor) required for an analog circuit such as a DLL circuit or a PLL circuit. A very large area is required to provide the capacitance (capacitor) in the substrate, but the correction circuit according to the present embodiment can be configured only by the digital circuit as described above, so that the area can be saved.

Further, since the correction circuit according to the present embodiment can be realized only by a digital circuit, it is excellent in noise resistance as compared with the conventional technique using an analog circuit such as a DLL circuit or a PLL circuit. In particular, the correction circuit according to the present embodiment is suitable for the recording element substrate because the current of A (ampere) order flows instantaneously in the recording element substrate when the recording element is driven and a large amount of electromagnetic noise is generated.

<Second embodiment>
FIG. 15 is a diagram showing a configuration example of the correction circuit 105 of the recording device according to the second embodiment of the present invention. Since the configuration other than the correction circuit 105 is the same as that of the first embodiment, the description thereof will be omitted. Further, also in the correction circuit 105, the same configuration as that of the first embodiment is shown with the same reference number.

The correction circuit 105 includes a first signal correction circuit 300 that corrects the phase of the first signal 111 (DATA) and a second signal correction circuit 301 that corrects the phase of the second signal 112 (CLK). NS. The first signal correction circuit 300 includes a first delay circuit 302, a second delay circuit 303, a third delay circuit 1301, a first determination circuit 304, a second determination circuit 305, and a third determination circuit 1302. , A first multiplexer 306, a first timing signal generation circuit 340, a first minute delay circuit 1305, and a second minute delay circuit 1306. Further, the second signal correction circuit 301 includes a fourth delay circuit 320, a fifth delay circuit 321, a sixth delay circuit 1307, a fourth determination circuit 322, a fifth determination circuit 323, and a sixth determination. It is composed of a circuit 1308, a second multiplexer 324, a second timing signal generation circuit 341, a third minute delay circuit 1311, and a fourth minute delay circuit 1312. The difference from the first embodiment is that the first signal correction circuit 300 and the second signal correction circuit 301 are provided with three delay circuits and three determination circuits, respectively. Further, the delay time of the first minute delay circuit 1305 and the third minute delay circuit 1311 is (td / 3), and the delay of the second minute delay circuit 1306 and the fourth minute delay circuit 1312. It differs from the first embodiment in that the time is (2td / 3).

FIG. 16A shows a circuit example of the unit delay circuit 350 according to the second embodiment, and is composed of, for example, a six-stage inverter circuit. FIG. 16B shows a circuit example of the second minute delay circuit 1306 and the fourth minute delay circuit 1312, and is an example configured by a four-stage inverter circuit. As a result, a delay time of 2/3 of the delay time td of the unit delay circuit 350 is realized. Further, FIG. 16C shows a circuit example of the first minute delay circuit 1305 and the third minute delay circuit 1311, and is an example configured by a two-stage inverter circuit. As a result, a delay time of 1/3 of the delay time td of the unit delay circuit 350 is realized.

According to the above-described configuration, in the second embodiment of the present invention, (n + 1) delay signals in which the first signal 111 is delayed by (td / 3) time and the second signal 112 are (td / 3). By generating (m + 1) delay signals delayed by time, the phase can be finely adjusted with the resolution of (td / 3) time. The second embodiment has an advantage over the first embodiment in that the phase can be adjusted with a finer resolution. Since the operation is the same as that of the first embodiment, detailed description thereof will be omitted.

Therefore, when the number of delay circuits of the first signal correction circuit 300 and the second signal correction circuit 301 are n and m, the number of delay circuits is three. The number of minute delay circuits provided in each signal correction circuit is two in each of the first signal correction circuit 300 and the second signal correction circuit 301 in the present embodiment.

In the above, in the first and second embodiments, the phase adjustment with finer resolution is realized by providing the delay circuit and the determination circuit for the signal in multiple stages (multiple systems), respectively. However, the number of stages is not limited to the above, and it is possible to realize finer resolution by providing more systems.

100 ... Recording device, 101 ... Recording head, 103 ... Recording element board, 104 ... Drive circuit, 105 ... Correction circuit, 302 ... First delay circuit, 303 ... Second delay circuit, 304 ... First determination circuit, 305 ... 2nd determination circuit, 306 ... 1st multiplexer, 330 ... 1st minute delay circuit, 340 ... 1st timing signal generation circuit

Claims (8)

It is an element substrate
With the element
The drive circuit that drives the element and
A receiving circuit that receives the first signal and the second signal,
Correcting the phase difference between the first signal and the second signal, and a correction circuit for outputting to said driving circuit,
The correction circuit
At least, a first generation circuit that generates a plurality of delay signals having different delay times for the first signal in the first time unit, and a first generation circuit for generating the first signal in the first time unit. A second generation that generates a plurality of delay signals having different delay times and delayed by a second time unit shorter than the first time with respect to the plurality of delay signals generated by the first generation circuit. A first signal delay circuit, including a circuit,
At least, the third generation circuit of the second delay time at the first time unit to the signal to generate a plurality of different delay signals, the first time unit with respect to said second signal Includes a fourth generation circuit that generates a plurality of delay signals having different delay times from each other and delayed by the second time unit with respect to the plurality of delay signals generated by the third generation circuit. The second signal delay circuit and
A latch circuit that latches a plurality of delay signals generated by the first signal delay circuit is included, and the timings of the delay signal latched by the latch circuit and the second signal are compared, and the result of the comparison is obtained. Based on this, a first selection circuit that selects a delay signal to be output to the drive circuit from a plurality of delay signals generated by the first signal delay circuit, and
A latch circuit that latches a plurality of delay signals generated by the second signal delay circuit is included, and the timing of the delay signal latched by the latch circuit and the delay signal selected by the first selection circuit is compared. Then, a second selection circuit that selects a delay signal to be output to the drive circuit from a plurality of delay signals generated by the second signal delay circuit based on the result of the comparison, and a second selection circuit.
Have,
The element substrate, characterized in that the first time is larger than the output delay time of the latch circuit. The first selection circuit corresponds to at least a plurality of delay signals generated by the first generation circuit, and outputs a plurality of determination signals for determining a signal close to the edge of the first signal. A first determination circuit, which corresponds to a plurality of delay signals generated by the second generation circuit and outputs a configuration with a plurality of determination signals for determining a signal close to the edge of the first signal. It has 2 judgment circuits and
The second selection circuit corresponds to at least a plurality of delay signals generated by the third generation circuit, and is used to determine a signal close to the edge of the delay signal selected by the first selection circuit. Corresponds to the third determination circuit that outputs the determination signal of the above and the plurality of delay signals generated by the fourth generation circuit, and determines a signal close to the edge of the delay signal selected by the first selection circuit. It has a fourth determination circuit that outputs a plurality of determination signals for the purpose of
The element substrate according to claim 1. The first selection circuit is generated by the first signal delay circuit based on a plurality of determination signals output from the first determination circuit and a plurality of determination signals output from the second determination circuit. It has a first multiplexer that selects a delayed signal from the delayed signal.
The second selection circuit is generated by the first signal delay circuit based on the plurality of determination signals output from the third determination circuit and the plurality of determination signals output from the second determination circuit. It has a second multiplexer that selects a delayed signal from the delayed signal.
The element substrate according to claim 2. The first signal is a data signal and is
The element substrate according to claim 1 , wherein the second signal is a clock signal. The correction circuit corrects the phase shift for each cycle of the third signal received from the outside.
The element substrate according to claim 1. The second time is one half of the first time.
The element substrate according to claim 1. A recording head including one or a plurality of element substrates according to any one of claims 1 to 6. A recording device including one or more recording heads according to claim 7.

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