JP6961517B2 - Semiconductor devices and control methods for semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

As an interface for connecting semiconductor devices, there is an SPI (Serial Peripheral Interface). SPI is a kind of serial bus, and since the number of connecting lines is smaller than that of a parallel bus, there is an advantage that a semiconductor device can be miniaturized.

Patent Document 1 discloses a technique that enables an external device to specify a memory address at high speed when transferring memory data of a microcomputer to an external device by SPI communication.

Japanese Unexamined Patent Publication No. 09-293047

By the way, in an application field where miniaturization of a semiconductor device is required, it may be necessary to implement communication by another communication method (for example, parallel communication) in addition to SPI communication.

However, in a conventional semiconductor device, since it is necessary to mount a circuit and a terminal of another communication method together with a circuit and a terminal for SPI communication, there is a problem that the manufacturing cost of the semiconductor device becomes high and the size becomes large. There is a point.

The present invention has been made in view of the above circumstances, and controls a semiconductor device and a semiconductor device capable of implementing a communication method other than SPI communication while suppressing an increase in manufacturing cost and an increase in size. It is intended to provide a method.

In order to solve the above problems, the present invention is a semiconductor device that performs SPI communication between a master device and a slave device, and the master device transmits data to the slave device via a first signal line. A first data transmitting means, a first data transmitting / receiving means for receiving data from the slave device via the second signal line, and a chip for transmitting a chip select signal to the slave device via the third signal line. The slave device has a select signal transmitting means, and the slave device has a second data receiving means for receiving data transmitted from the master device via the first signal line, and the second data receiving means with respect to the master device. It has a second data transmission / reception means for transmitting data via a signal line, and a chip select signal receiving means for receiving the chip select signal from the master device via the third signal line, and by the SPI communication. In the case of communication, when the chip select signal is put into a predetermined logical state, the data transmitted by the second data transmission / reception means is received by the first data transmission / reception means, and communication is performed by a method other than the SPI communication. The chip select signal is placed in a logic state opposite to that of the predetermined logic state, and the data transmitted by the first data transmission / reception means is received by the second data transmission / reception means.
With such a configuration, it is possible to implement a communication method other than SPI communication while suppressing an increase in manufacturing cost and an increase in size.

Further, the present invention is characterized in that the method other than the SPI communication is parallel communication.
According to such a configuration, high-speed communication can be realized by parallel communication.

Further, in the present invention, the first data transmitting / receiving means includes a first data receiving unit that receives data from the slave device, a first data transmitting unit that transmits data to the slave device, and the first data. The second data transmission / reception means includes a second data reception unit that receives data from the master device, and the first selection unit that selects either a reception unit or the first data transmission unit. It has a second data transmission unit that transmits data to the master device, and a second selection unit that selects either the second data reception unit or the second data transmission unit, and by the SPI communication. When communicating, the first selection unit selects the first data receiving unit, the second selection unit selects the second data transmitting unit, and communication is performed by a method other than the SPI communication. The first selection unit selects the first data transmission unit, and the second selection unit selects the second data reception unit.
According to such a configuration, the communication method and the communication direction can be switched with a simple configuration.

Further, in the present invention, the slave device is a MMIC (Monolithic Microwave Integrated Circuit), and the master device changes the stored value of the register built in the MMIC by the SPI communication and is controlled by the parallel communication. The MMIC is characterized in that radio waves are transmitted and received.
According to such a configuration, even an MMIC that is easily affected by the line length of the circuit or the like can implement a new communication method without affecting the high frequency characteristics.

Further, the present invention is characterized in that the master device is composed of an FPGA (Field-Programmable Gate Array) or a SoC (System-on-a-Chip).
According to such a configuration, a new communication method can be easily implemented according to the purpose of use.

Further, the present invention relates to a method for controlling a semiconductor device that performs SPI communication between a master device and a slave device, wherein the master device transmits data to the slave device via a first signal line. A transmission step, a first data transmission / reception step of receiving data from the slave device via the second signal line, and chip select signal transmission for transmitting a chip select signal to the slave device via the third signal line. The slave device has a second data receiving step of receiving data transmitted from the master device via the first signal line, and the second signal line to the master device. It has a second data transmission / reception step of transmitting data via the master device and a chip select signal reception step of receiving the chip select signal from the master device via the third signal line, and communicates by the SPI communication. In this case, when the chip select signal is put into a predetermined logical state, the data transmitted in the second data transmission / reception step is received in the first data transmission / reception step, and communication is performed by a method other than the SPI communication, the chip is used. The select signal is placed in a logic state opposite to that of the predetermined logic state, and the data transmitted in the first data transmission / reception step is received in the second data transmission / reception step.
According to such a method, it is possible to implement a communication method other than SPI communication while suppressing an increase in manufacturing cost and an increase in size.

According to the present invention, it is possible to provide a semiconductor device and a control method for the semiconductor device, which can implement a communication method other than SPI communication while suppressing an increase in manufacturing cost and an increase in size.

It is a figure which shows the structural example of the semiconductor device which concerns on embodiment of this invention. It is a block diagram which shows the structural example of FPGA shown in FIG. It is a block diagram which shows the structural example of the DO / Rxsel0 transmission part shown in FIG. It is a block diagram which shows the structural example of the DI / Rxsel1 transmission / reception part shown in FIG. It is a block diagram which shows the structural example of MMIC shown in FIG. It is a block diagram which shows the structural example of the DO / Rxsel0 receiving part shown in FIG. It is a block diagram which shows the structural example of the DI / Rxsel1 transmission / reception part shown in FIG. It is a timing diagram for demonstrating the operation of the embodiment shown in FIG. This is an example of a flowchart executed by the FPGA shown in FIG. This is an example of a flowchart executed by the MMIC shown in FIG.

Next, an embodiment of the present invention will be described.

(A) Explanation of Configuration of Embodiment of the Present Invention FIG. 1 is a diagram showing a schematic configuration example of a semiconductor device according to the embodiment of the present invention. In the example shown in FIG. 1, the semiconductor device 1 has an FPGA (Field-Programmable Gate Array) 10 and an MMIC (Monolithic Microwave Integrated Circuit) 30 as main components. Note that, instead of FPGA 10, SoC (System-on-a-Chip) may be used.

The FPGA 10 is a kind of PLD (Programmable Logic Device) which is a programmable gate array, and is a semiconductor device whose configuration can be freely set by a designer.

The MMIC 30 is a type of microwave integrated circuit (MIC), which is an integrated circuit in which a microwave circuit conventionally composed of discrete components is formed on a single semiconductor substrate. In the present embodiment, for example, the MMIC 30 configures a radar device that detects the position and speed of the target by transmitting radio waves in the GHz band and analyzing the reflected wave reflected by the target. It will be explained by listing in. The present invention may be applied to MMICs in other fields of application, or the present invention may be applied to semiconductor devices other than MMICs.

The FPGA 10 and the MMIC 30 are connected by four connecting lines 21 to 24 for SPI communication and other communication. The FPGA 10 and the MMIC 30 can exchange information by SPI communication using these four connection lines 21 to 24, and can exchange information by another communication method (parallel communication in this embodiment).

Here, the connection line 21 is a connection line that transmits a CS (Chip Select) signal for selecting a peripheral device (MMIC 30 in FIG. 1) in the SPI communication method.

The connection line 22 is a connection line that transmits a clock signal to the MMIC 30 in the SPI communication method, and drives (ON / OFF) an amplification unit for amplifying a radio wave to be transmitted in parallel communication, which is another communication method. TxDRV signal for is transmitted.

The connection line 23 is a connection line for transmitting a DO signal which is a serial data signal from the FPGA 10 to the MMIC 30 in the SPI communication method, and a connection for transmitting the Rxsel0 signal which is a parallel data signal from the FPGA 10 to the MMIC 30 in the parallel communication. It is a line.

The connection line 24 is a connection line for transmitting a DI signal which is a serial data signal from the MMIC 30 to the FPGA 10 in the SPI communication method, and a connection for transmitting the Rxsel1 signal which is a parallel data signal from the FPGA 10 to the MMIC 30 in the parallel communication. It is a line.

FIG. 2 is a diagram showing a configuration example of a portion of the FPGA 10 shown in FIG. 1 related to communication with the MMIC 30. As shown in FIG. 2, the part related to the communication of the FPGA 10 with the MMIC 30 includes the central control unit 11, the CS transmission unit 12, the CLK / TxDRV transmission unit 13, the DO / Rxsel0 transmission unit 14, and the DI / Rxsel1 transmission / reception unit 15. Have.

Here, the central control unit 11 has a built-in storage unit, and controls each unit of the device based on a program or the like stored in the storage unit.

The CS transmission unit 12 sets the CS (Chip Select) signal to the “L” state in the case of SPI communication and the CS signal to the “H” state in the case of parallel communication according to the control of the central control unit 11. To. It should be noted that the logic may be reversed.

The CLK / TxDRV transmission unit 13 transmits a serial clock signal in the case of SPI communication, and controls on / off of an amplification unit that amplifies the transmission signal in the case of parallel communication, according to the control of the central control unit 11. TxDRV signal for

The DO / Rxsel0 transmission unit 14 transmits a serial data signal in the case of SPI communication and a parallel data signal (Rxsel0) in the case of parallel communication according to the control of the central control unit 11.

The DI / Rxsel1 transmission / reception unit 15 receives the serial data signal in the case of SPI communication and transmits the parallel data signal (Rxsel1) in the case of parallel communication according to the control of the central control unit 11.

FIG. 3 shows a configuration example of the DO / Rxsel0 transmission unit 14 shown in FIG. In the example of FIG. 3, the DO / Rxsel0 transmission unit 14 has a data transmission unit 141 and an amplification unit 142. Here, the data transmission unit 141 converts the data supplied from the central control unit 11 into a serial data signal or a parallel data signal and supplies the data to the amplification unit 142. The amplification unit 142 amplifies and transmits the serial data signal or the parallel data signal supplied from the data transmission unit 141.

FIG. 4 shows a configuration example of the DI / Rxsel1 transmission / reception unit 15 shown in FIG. In the example of FIG. 4, the DI / Rxsel1 transmission / reception unit 15 has a data reception unit 151, a data transmission unit 152, a selection unit 153, and an amplification unit 154, 155. Here, the data receiving unit 151 receives the serial data signal supplied from the MMIC 30 via the amplification unit 154 in the case of SPI communication, and supplies the serial data signal to the central control unit 11. In the case of parallel communication, the data transmission unit 152 converts the data supplied from the central control unit 11 into a parallel data signal and supplies it to the amplification unit 155. The selection unit 153 turns on / off the operation of the amplification units 154 and 155 according to the control of the central control unit 11. The amplification unit 154 amplifies and outputs the serial data signal supplied from the MMIC 30. The amplification unit 155 amplifies and outputs the parallel data signal supplied from the data transmission unit 152.

FIG. 5 is a diagram showing a configuration example of a portion of the MMIC 30 shown in FIG. 1 related to communication with the FPGA 10. As shown in FIG. 5, the part related to the communication of the MMIC 30 with the FPGA 10 includes the central control unit 31, the CS receiving unit 32, the CLK / TxDRV receiving unit 33, the DO / Rxsel0 receiving unit 34, and the DI / Rxsel1 transmitting / receiving unit 35. Have.

Here, the central control unit 31 has a built-in storage unit, and controls each unit of the device based on a program or the like stored in the storage unit.

The CS receiving unit 32 receives the CS signal supplied from the FPGA 10 and notifies the central control unit 31 of the state of the CS signal.

The CLK / TxDRV receiving unit 33 receives the serial clock signal in the case of SPI communication and controls the on / off of the amplifier that amplifies the transmission signal in the case of parallel communication according to the control of the central control unit 31. TxDRV signal is received.

The DO / Rxsel0 receiving unit 34 receives the serial data signal (DO) in the case of SPI communication and the parallel data signal (Rxsel0) in the case of parallel communication according to the control of the central control unit 31.

The DI / Rxsel1 transmission / reception unit 35 transmits a serial data signal (DI) in the case of SPI communication and receives a parallel data signal (Rxsel1) in the case of parallel communication according to the control of the central control unit 31.

FIG. 6 shows a configuration example of the DO / Rxsel0 receiving unit 34 shown in FIG. In the example of FIG. 6, the DO / Rxsel0 receiving unit 34 has a data receiving unit 341 and an amplification unit 342. Here, the amplification unit 342 amplifies the serial data signal or the parallel data signal supplied from the FPGA 10 and supplies the serial data signal or the parallel data signal to the data reception unit 341. The data receiving unit 341 converts the serial data signal or the parallel data signal supplied from the amplification unit 342 into the original data and supplies the data to the central control unit 31.

FIG. 7 shows a configuration example of the DI / Rxsel1 transmission / reception unit 35 shown in FIG. In the example of FIG. 7, the DI / Rxsel1 transmission / reception unit 35 includes a data reception unit 351, a data transmission unit 352, a selection unit 353, and an amplification unit 354,355. Here, the data receiving unit 351 receives the parallel data signal supplied from the FPGA 10 via the amplification unit 354 in the case of parallel communication, and supplies the parallel data signal to the central control unit 31. In the case of serial communication, the data transmission unit 352 converts the data supplied from the central control unit 31 into a serial data signal and supplies it to the amplification unit 355. The selection unit 353 turns on / off the operation of the amplification units 354 and 355 according to the control of the central control unit 31. The amplification unit 354 amplifies and outputs the parallel data signal supplied from the FPGA 10. The amplification unit 355 amplifies and outputs the serial data signal supplied from the data transmission unit 352.

(B) Description of Operation of Embodiment of the Present Invention Next, the operation of the embodiment of the present invention will be described. In the following, after explaining the operation of the embodiment of the present invention based on the timing diagram shown in FIG. 8, the central control unit 11 and FIG. 5 shown in FIG. 2 are referred to with reference to the flowcharts shown in FIGS. 9 and 10. The process executed by the central control unit 31 shown in the above will be described.

In the example shown in FIG. 8, parallel communication by PIN communication is executed at times T1 to T4, and serial communication by SPI communication is executed at times T5 to T6.

In the PIN communication, the central control unit 11 instructs the DI / Rxsel1 transmission / reception unit 15 to transmit a parallel signal.

As a result, in the DI / Rxsel1 transmission / reception unit 15, the selection unit 153 stops the operation of the amplification unit 154 and operates the amplification unit 155. As a result, the DI / Rxsel1 transmission / reception unit 15 is in a state where parallel data signals can be transmitted.

Next, the central control unit 11 instructs the CS transmission unit 12 to put the CS signal in the “H” state. As a result, as shown in FIG. 8A, the CS transmission unit 12 puts the CS signal in the “H” state.

When the CS signal becomes "H", the CS receiving unit 32 detects this and notifies the central control unit 31. When the CS receiving unit 32 notifies that the CS signal is in the “H” state, the central control unit 31 instructs the DI / Rxsel1 transmitting / receiving unit 35 to receive the parallel data signal. do.

As a result, in the DI / Rxsel1 transmission / reception unit 35, the selection unit 353 operates the amplification unit 354 and stops the operation of the amplification unit 355. As a result, the DI / Rxsel1 transmission / reception unit 35 is in a state where it can receive the parallel data signal.

Next, the central control unit 11 sets the DO / Rxsel0 signal to the “L” state as shown in FIG. 8C, and sets the DI / Rxsel1 signal to the “L” state as shown in FIG. 8D. Put it in a state. In the DO / Rxsel0 receiving unit 34 of the MMIC 30, the amplification unit 342 amplifies the DO / Rxsel0 signal and supplies it to the data receiving unit 341. The data receiving unit 341 supplies the received DO / Rxsel0 signal to the central control unit 31. In the DI / Rxsel1 transmission / reception unit 35, the amplification unit 354 amplifies the DI / Rxsel1 signal and supplies it to the data reception unit 351. The data receiving unit 351 supplies the received DI / Rxsel1 signal to the central control unit 31.

The central control unit 31 recognizes that both the DO / Rxsel0 signal and the DI / Rxsel1 signal are in the “L” state based on the data supplied from the data receiving units 341 and 351. As a result, the central control unit 31 selects the receiving antenna Rx1 from the four receiving antennas (not shown) (see FIG. 8F).

Next, the central control unit 11 controls the CLK / TxDRV transmission unit 13 at time T2 to transmit the TxDRV signal. As a result, as shown in FIG. 8B, the TxDRV is pulsed into an “H” state.

The CLK / TxDRV receiving unit 33 of the MMIC 30 detects that the TxDRV is in the “H” state and notifies the central control unit 31. Since the TxDRV is in the “H” state, the central control unit 31 drives the amplification unit by the TxVGA signal and transmits the transmission signal from a transmission antenna (not shown) as shown in FIG. 8 (E). The transmitted signal transmitted in this way is reflected by the object and received by the receiving antenna Rx1.

Next, at time T3, the central control unit 11 sets the DO / Rxsel0 signal to the “H” state as shown in FIG. 8C, and sets the DI / Rxsel1 signal to the “H” state as shown in FIG. 8D. Set to "L" state.

The central control unit 31 recognizes that the DO / Rxsel0 signal is “H” and the DI / Rxsel1 signal is “L” based on the data supplied from the data receiving units 341 and 351. As a result, the central control unit 31 selects the receiving antenna Rx2 (see FIG. 8 (G)).

Next, the central control unit 11 controls the CLK / TxDRV transmission unit 13 at time T4 to transmit the TxDRV signal. As a result, as shown in FIG. 8B, the TxDRV is pulsed into an “H” state.

The CLK / TxDRV receiving unit 33 of the MMIC 30 detects that the TxDRV is in the “H” state and notifies the central control unit 31. Since the TxDRV is in the “H” state, the central control unit 31 transmits the transmission signal from a transmission antenna (not shown) as shown in FIG. 8 (E). The transmitted signal transmitted in this way is reflected by the object and received by the receiving antenna Rx2.

Next, at time T5, the central control unit 11 sets the DO / Rxsel0 signal to the “L” state as shown in FIG. 8C, and sets the DI / Rxsel1 signal to the “L” state as shown in FIG. 8D. Set to "H" state.

The central control unit 31 recognizes that the DO / Rxsel0 signal is “L” and the DI / Rxsel1 signal is “H” based on the data supplied from the data receiving units 341 and 351. As a result, the central control unit 31 selects the receiving antenna Rx3 (see FIG. 8H).

Next, the central control unit 11 controls the CLK / TxDRV transmission unit 13 at time T6 to transmit the TxDRV signal. As a result, as shown in FIG. 8B, the TxDRV is pulsed into an “H” state.

The CLK / TxDRV receiving unit 33 of the MMIC 30 detects that the TxDRV is in the “H” state and notifies the central control unit 31. Since the TxDRV is in the “H” state, the central control unit 31 transmits the transmission signal from a transmission antenna (not shown) as shown in FIG. 8 (E). The transmitted signal transmitted in this way is reflected by the object and received by the receiving antenna Rx3.

Next, at time T7, the central control unit 11 sets the DO / Rxsel0 signal to the “H” state as shown in FIG. 8C, and sets the DI / Rxsel1 signal to the “H” state as shown in FIG. 8D. Set to "H" state.

The central control unit 31 recognizes that the DO / Rxsel0 signal is “H” and the DI / Rxsel1 signal is “H” based on the data supplied from the data receiving units 341 and 351. As a result, the central control unit 31 selects the receiving antenna Rx4 (see FIG. 8 (I)).

Next, the central control unit 11 controls the CLK / TxDRV transmission unit 13 at time T8 to transmit the TxDRV signal. As a result, as shown in FIG. 8B, the TxDRV is pulsed into an “H” state.

The CLK / TxDRV receiving unit 33 of the MMIC 30 detects that the TxDRV is in the “H” state and notifies the central control unit 31. Since the TxDRV is in the “H” state, the central control unit 31 transmits the transmission signal from a transmission antenna (not shown) as shown in FIG. 8 (E). The transmitted signal transmitted in this way is reflected by the object and received by the receiving antenna Rx4.

Next, the central control unit 11 instructs the CS transmission unit 12 to put the CS signal in the “L” state in order to shift from the PIN communication to the SPI communication at the time T9. As a result, the CS transmission unit 12 puts the CS signal in the “L” state.

Further, the central control unit 11 controls the DI / Rxsel1 transmission / reception unit 15 to receive the serial data signal. As a result, the selection unit 153 of the DI / Rxsel1 transmission / reception unit 15 operates the amplification unit 154 and stops the operation of the amplification unit 155.

In the MMIC 30, the CS receiving unit 32 detects that the CS signal is in the “L” state and notifies the central control unit 31. Since the CS signal is in the “L” state, the central control unit 31 determines that the SPI communication has been started, and controls the DI / Rxsel1 transmission / reception unit 35 to transmit the serial data signal. As a result, the selection unit 353 of the DI / Rxsel1 transmission / reception unit 35 stops the operation of the amplification unit 354 and operates the amplification unit 355.

When shifting to SPI communication, the CLK / TxDRV transmission unit 13 of the FPGA 10 transmits a clock signal. The DO / Rxsel0 transmission unit 14 transmits a serial data signal to the MMIC 30 in synchronization with this clock signal. That is, the data supplied from the central control unit 11 is converted into a serial data signal by the data transmission unit 141, amplified by the amplification unit 142, and then supplied to the MMIC 30. In the MMIC 30, the amplification unit 342 amplifies the serial data signal and supplies it to the data reception unit 341. The data receiving unit 341 converts the serial data signal supplied from the amplification unit 342 into the original data and supplies it to the central control unit 31.

Further, the data supplied by the central control unit 31 is supplied to the data transmission unit 352, converted into a serial data signal, and then supplied to the amplification unit 355. The amplification unit 355 amplifies and outputs the serial data signal supplied from the data transmission unit 352.

In the DI / Rxsel1 transmission / reception unit 15 of the FPGA 10, since the amplification unit 154 is in the operating state, the amplification unit 154 amplifies the serial data signal supplied from the MMIC 30 and supplies it to the data reception unit 151. The data receiving unit 151 converts the serial data signal supplied from the amplification unit 154 into the original data and supplies it to the central control unit 11.

In SPI communication, for example, the data stored in the register built in the MMIC 30 is rewritten by the central control unit 31, or the data stored in the register is read out and transmitted to the FPGA 10. Or something. Thereby, for example, the intensity of the transmitted radio wave can be changed, and the operation can be corrected by the temperature. Of course, operations other than these may be performed.

Next, an example of the processing executed in the embodiment shown in FIG. 1 will be described with reference to FIGS. 9 and 10.

FIG. 9 is a diagram for explaining an example of processing executed by the central control unit 11 shown in FIG. When the processing of the flowchart shown in FIG. 9 is started, the following steps are executed.

In step S10, the central control unit 11 determines whether or not to execute the PIN communication, and if it is determined to execute the PIN communication (step S10: Y), the process proceeds to step S11, and in other cases (step S10). : N) proceeds to step S15. For example, at the time T1 in FIG. 8, if it is determined that the PIN communication is to be executed, it is determined to be Y and the process proceeds to step S11.

In step S11, the central control unit 11 puts the CS signal in the “H” state. More specifically, the central control unit 11 controls the CS transmission unit 12 to bring the CS signal to the “H” state. As a result, as shown in FIG. 8A, the CS signal is in the “H” state at time T1.

In step S12, the central control unit 11 executes control for switching DI to transmission. More specifically, the central control unit 11 controls the DI / Rxsel1 transmission / reception unit 15 to switch to transmission. As a result, the selection unit 153 stops the operation of the amplification unit 154 and operates the amplification unit 155.

In step S13, the central control unit 11 executes PIN communication. More specifically, as shown in FIG. 8, the central control unit 11 controls the DO / Rxsel0 transmission unit 14 and the DI / Rxsel1 transmission / reception unit 15 to transmit parallel data signals. Further, the CLK / TxDRV transmission unit 13 is controlled to transmit the TxDRV signal. As a result, the MMIC 30 can transmit radio waves to the object and receive the reflected waves reflected by the object by the receiving antennas Rx1 to Rx4.

In step S14, the central control unit 11 determines whether or not to end the PIN communication, and if it is determined to end (step S14: Y), the process proceeds to step S15, and in other cases (step S14: N). Return to step S13 and repeat the same process. In the example of FIG. 8, the same operation is repeated until the reception operation by the receiving antennas Rx1 to Rx4 is completed.

In step S15, the central control unit 11 determines whether or not to execute SPI communication, and if it is determined to execute SPI communication (step S15: Y), the process proceeds to step S16, and in other cases (step S15). : N) proceeds to step S20. For example, at the time T9 in FIG. 8, if it is determined that SPI communication is to be executed, it is determined to be Y and the process proceeds to step S16.

In step S16, the central control unit 11 puts the CS signal in the “L” state. More specifically, the central control unit 11 controls the CS transmission unit 12 to bring the CS signal to the “L” state. As a result, as shown in FIG. 8A, the CS signal is in the “L” state at time T9.

In step S17, the central control unit 11 executes control for switching DI to reception. More specifically, the central control unit 11 controls the DI / Rxsel1 transmission / reception unit 15 to switch to reception. As a result, the selection unit 153 operates the amplification unit 154 and stops the operation of the amplification unit 155.

In step S18, the central control unit 11 executes SPI communication. More specifically, as shown in FIG. 8, the DO / Rxsel0 transmission unit 14 transmits a serial data signal to the MMIC30, and the DI / Rxsel1 transmission / reception unit 15 is controlled to receive the serial data signal from the MMIC30.

In step S19, the central control unit 11 determines whether or not to end the SPI communication, and if it is determined to end (step S19: Y), the process proceeds to step S20, and in other cases (step S19: N). Return to step S18 and repeat the same process.

In step S20, the central control unit 11 determines whether or not to end the process, ends the process when it is determined to end (step S20: Y), and ends the process in other cases (step S20: N). Returns to step S10 and repeats the same process.

Next, an example of the processing executed by the central control unit 31 shown in FIG. 5 will be described with reference to FIG. When the processing of the flowchart shown in FIG. 10 is started, the following steps are executed.

In step S30, the central control unit 31 refers to the output of the CS receiving unit 32, determines whether or not the CS signal is “H”, and determines that it is “H” (step S30: Y). In other cases (step S30: N), the process proceeds to step S31. For example, if it is determined that the CS signal is “H” at the time T1 in FIG. 8, the process proceeds to step S31.

In step S31, the central control unit 31 executes control for switching DI to reception. More specifically, the central control unit 31 controls the DI / Rxsel1 transmission / reception unit 35 to switch to reception. As a result, the selection unit 353 operates the amplification unit 354 and stops the operation of the amplification unit 355.

In step S32, the central control unit 31 executes PIN communication. More specifically, as shown in FIG. 8, the DO / Rxsel0 receiving unit 34 and the DI / Rxsel1 transmitting / receiving unit 35 are controlled to receive the parallel data signal. Further, the TxDRV signal transmitted from the CLK / TxDRV transmission unit 13 is received. As a result, the MMIC 30 transmits radio waves to the object and receives the reflected waves reflected by the object by the receiving antennas Rx1 to Rx4.

In step S33, the central control unit 31 determines whether or not to end the PIN communication, and if it is determined to end (step S33: Y), the process proceeds to step S34, and in other cases (step S33: N). Return to step S32 and repeat the same process. In the example of FIG. 8, the same operation is repeated until the reception operation by the receiving antennas Rx1 to Rx4 is completed.

In step S34, the central control unit 31 refers to the output of the CS receiving unit 32, determines whether or not the CS signal is “L”, and determines that the CS signal is “L” (step S34: Y). In other cases (step S34: N), the process proceeds to step S38. For example, if it is determined that the CS signal is “L” at the time T9 in FIG. 8, the process proceeds to step S35.

In step S35, the central control unit 31 executes control for switching DI to transmission. More specifically, the central control unit 31 controls the DI / Rxsel1 transmission / reception unit 35 to switch to transmission. As a result, the selection unit 353 stops the operation of the amplification unit 354 and operates the amplification unit 355.

In step S36, the central control unit 31 executes SPI communication. More specifically, as shown in FIG. 8, the DO / Rxsel0 receiving unit 34 receives the serial data signal, and the DI / Rxsel1 transmitting / receiving unit 35 transmits the serial data signal.

In step S37, the central control unit 31 determines whether or not to end the SPI communication, and if it is determined to end (step S37: Y), the process proceeds to step S38, and in other cases (step S37: N). Return to step S36 and repeat the same process. In the example of FIG. 8, the same operation is repeated until the SPI communication is completed.

In step S38, the central control unit 31 determines whether or not to end the process, ends the process when it is determined to end (step S38: Y), and ends the process in other cases (step S38: N). Returns to step S30 and repeats the same process.

As described above, according to the processing of the flowcharts shown in FIGS. 9 and 10, the above-described operation can be realized with reference to FIG.

(C) Description of Modified Embodiment The above embodiment is an example, and it goes without saying that the present invention is not limited to the above-mentioned case. For example, in the above embodiment, the PIN communication is executed together with the SPI communication, but the communication other than the PIN communication may be executed.

Further, in the above embodiment, the PIN communication is such that the information is transmitted from the FPGA 10 to the MMIC 30, but the information may be transmitted from the MMIC 30 to the FPGA 10.

Further, in the above embodiment, communication is performed between the FPGA 10 and the MMIC 30, but a combination other than these may be used. For example, Soc may be used instead of FPGA 10, a device that handles high-frequency signals, or a digital peripheral device may be used in addition to MMIC30.

Further, in the examples of FIGS. 4 and 7, transmission / reception is switched by operating the amplification units 154, 155 and the amplification units 354, 355 by the selection unit 153 and the selection unit 353, or by stopping the operation. However, other methods may be used.

Further, in the above embodiment, the CS signal is set to the "L" state when the SPI communication is executed, and the CS signal is set to the "H" state when the PIN communication is performed. At the time of execution, the CS signal may be set to the “H” state, and in the case of PIN communication, the CS signal may be set to the “L” state.

Further, in the example of FIG. 8, in the PIN communication, the process of transmitting the radio wave and switching the antenna is executed, but the present invention may be applied to other uses.

1 Semiconductor system 10 FPGA (master device)
11 Central control unit 12 CS transmission unit (chip select signal transmission means)
13 CLK / TxDRV transmitter 14 DO / Rxsel0 transmitter (first data transmission means)
15 DI / Rxsel1 transmitter / receiver (first data transmitter / receiver means)
21-24 Connection line 30 MMIC (slave device)
31 Central control unit 32 CS receiving unit (chip select signal receiving means)
33 CLK / TxDRV receiver 34 DO / Rxsel0 receiver (second data receiving means)
35 DI / Rxsel1 transmitter / receiver (second data transmitter / receiver means)
141 Data transmission unit 142 Amplification unit 151 Data reception unit (first data reception unit)
152 Data transmission unit (1st data transmission unit)
153 Selection section (1st selection section)
154 Amplification unit 155 Amplification unit 341 Data reception unit 342 Amplification unit 351 Data reception unit (second data reception unit)
352 data transmission unit (second data transmission unit)
353 Selection section (2nd selection section)
354 Amplification unit 355 Amplification unit Rx1 to Rx4 receiving antenna

Claims (6)

In a semiconductor device that performs SPI communication between a master device and a slave device,
The master device is
A first data transmission means for transmitting data to the slave device via the first signal line,
A first data transmission / reception means for receiving data from the slave device via the second signal line, and
It has a chip select signal transmitting means for transmitting a chip select signal to the slave device via a third signal line.
The slave device is
A second data receiving means for receiving data transmitted from the master device via the first signal line, and
A second data transmission / reception means for transmitting data to the master device via the second signal line,
It has a chip select signal receiving means for receiving the chip select signal from the master device via the third signal line.
When communicating by the SPI communication, the chip select signal is put into a predetermined logical state, and the data transmitted by the second data transmitting / receiving means is received by the first data transmitting / receiving means, and by a method other than the SPI communication. When communicating, the chip select signal is put into a logic state opposite to the predetermined logic state, and the data transmitted by the first data transmission / reception means is received by the second data transmission / reception means.
A semiconductor device characterized by this. The semiconductor device according to claim 1, wherein the method other than the SPI communication is parallel communication. The first data transmitting / receiving means includes a first data receiving unit that receives data from the slave device, a first data transmitting unit that transmits data to the slave device, the first data receiving unit, and the first data receiving unit. It has a first selection unit that selects one of the data transmission units, and
The second data transmitting / receiving means includes a second data receiving unit that receives data from the master device, a second data transmitting unit that transmits data to the master device, the second data receiving unit, and the second data receiving unit. It has a second selection unit that selects one of the data transmission units, and
When communicating by the SPI communication, the first selection unit selects the first data receiving unit and the second selection unit selects the second data transmitting unit, and communicates by a method other than the SPI communication. The first selection unit selects the first data transmission unit, and the second selection unit selects the second data reception unit.
The semiconductor device according to claim 1 or 2. The slave device is an MMIC (Monolithic Microwave Integrated Circuit), and the master device changes the stored value of a register built in the MMIC by the SPI communication and controls the MMIC by parallel communication to transmit radio waves to the MMIC. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is transmitted and received. The semiconductor device according to any one of claims 1 to 4, wherein the master device is composed of an FPGA (Field-Programmable Gate Array) or a SoC (System-on-a-Chip). In the control method of a semiconductor device that performs SPI communication between a master device and a slave device,
The master device is
A first data transmission step of transmitting data to the slave device via the first signal line, and
A first data transmission / reception step of receiving data from the slave device via the second signal line, and
It has a chip select signal transmission step of transmitting a chip select signal to the slave device via a third signal line.
The slave device is
A second data receiving step of receiving data transmitted from the master device via the first signal line, and
A second data transmission / reception step of transmitting data to the master device via the second signal line, and
It has a chip select signal receiving step of receiving the chip select signal from the master device via the third signal line.
When communicating by the SPI communication, the chip select signal is put into a predetermined logical state, and the data transmitted in the second data transmission / reception step is received in the first data transmission / reception step, and by a method other than the SPI communication. When communicating, the chip select signal is put into a logic state opposite to the predetermined logic state, and the data transmitted in the first data transmission / reception step is received in the second data transmission / reception step.
A method for controlling a semiconductor device.

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