JP6958424B2 - Switching power supply - Google Patents

Description

The present invention relates to a switching power supply device having a function of suppressing an overshoot of an output voltage.

As this type of switching power supply device, the switching power supply device disclosed in Patent Document 1 below is known. This switching power supply device has a switching transformer having a primary winding, a secondary winding, and an auxiliary winding, and by switching an input DC through the primary winding, a predetermined voltage is applied to the secondary winding side. A FET for generating supply power (DC power), a switching control unit that controls switching of the FET, and a supply when the output current output to the outside of the device based on the generated supply power is equal to or less than a predetermined current value. A constant voltage control unit that feedback-controls the FET via a switching control unit to stabilize the DC voltage of power to the first voltage value, and an output current to a predetermined current value when the output current exceeds a predetermined current value. A constant current control unit that feedback-controls the FET via a switching control unit to limit the DC voltage of the supply power based on the induced voltage of the auxiliary winding, and a second voltage that is higher than the first voltage value. It is provided with a voltage limiting unit that feedback-controls the FET via a switching control unit in order to limit the value to or less than the value.

In this case, the constant voltage control unit and the constant current control unit detect the output voltage and the output current, maintain the output voltage at the first voltage value until the output current reaches a predetermined current value, and the output current is predetermined. When the current value is reached, a control signal (sink current) for performing feedback control for lowering the output voltage while maintaining the output current at a predetermined current value is output. The switching power supply device includes a phototransistor that generates a control voltage corresponding to the sink current on the primary side of the transformer. Further, the switching control unit has an auxiliary power supply unit that outputs a power supply voltage whose voltage changes according to the induced voltage by rectifying and smoothing the induced voltage of the auxiliary winding, and a reference voltage (reference voltage) based on this power supply voltage. It includes a reference voltage generation circuit for generating (constant voltage), an error amplifier, and a switching signal generation circuit.

The operation of this switching power supply device will be described. First, in the steady state, in the switching power supply device, the error amplifier of the switching control unit amplifies the error voltage between the control voltage from the phototransistor and the reference voltage from the reference voltage generation circuit, and obtains the amplified control voltage. Output to the switching signal generation circuit. Next, the switching signal generation circuit outputs a switching signal having a duty ratio according to the control voltage to control FET switching, thereby performing a constant voltage operation that stabilizes the output voltage to the target first voltage value. Run. Further, when the output current reaches a predetermined current value (when the steady state changes to an overload state), the switching signal generation circuit reduces the output voltage while maintaining the output current at the predetermined current value. Perform current operation.

Next, the operation when the state suddenly changes from the overloaded state to the no-load state (the state where the output current is small) will be described. In this case, in the overload state before the transition to the no-load state, the FET has a duty ratio (limitation) that keeps (limits) the output current at a predetermined current value by lowering the output voltage in order to reduce the power supplied to the load. The switching operation (constant current operation) is executed with a duty ratio smaller than the duty ratio in the steady state). On the other hand, when the output current becomes low and no load is applied, the constant current operation is momentarily stopped (the error amplifier rapidly raises the control voltage to the switching signal generation circuit). Therefore, the FET performs a switching operation with a large duty ratio, which causes the output voltage to start rising towards the first voltage value. Further, the induced voltage of the auxiliary winding also rises in response to the rise in the output voltage, and as a result, the power supply voltage output from the auxiliary power supply unit also rises.

However, the constant voltage control unit cannot immediately respond to this state. That is, the FET continues the switching operation at this large duty ratio. Therefore, the output voltage continuously rises and exceeds the target first voltage value.

In this case, in the switching power supply device, even when the constant voltage control unit cannot respond, when the output voltage reaches the second voltage value (> first voltage value) (that is, the power supply voltage from the auxiliary power supply). When the voltage reaches the voltage corresponding to this second voltage value), the current limiting unit detects this and forcibly lowers the control voltage from the phototransistor input to the error amplifier. As a result, the error amplifier lowers the control voltage output to the switching signal generation circuit, so that the switching signal generation circuit lowers the on-duty ratio of the control signal. Therefore, when the FET switches according to this control signal, the output voltage is limited to the second voltage value slightly exceeding the first voltage value. After that, as a result of the constant voltage control by the constant voltage control unit functioning, the switching signal generation circuit stabilizes the output voltage to the first voltage value. In this way, according to this switching power supply device, an excessive overshoot phenomenon (generation of transient overvoltage (surge voltage)) that may occur in the output voltage due to the operation delay of the feedback control of the constant voltage control unit. Can be effectively prevented.

Japanese Unexamined Patent Publication No. 11-206116 (Pages 2-5, Fig. 1-3)

However, the conventional switching power supply device starts the voltage limiting operation after the output voltage reaches the second voltage value exceeding the target first voltage value. Therefore, in this switching power supply device, when the voltage limiting unit has an infinite response speed, the output voltage can theoretically be suppressed to the second voltage value, but the response speed is finite. Therefore, in reality, although the overshoot phenomenon (generation of transient overvoltage) can be reduced to some extent, there is a problem that it is difficult to sufficiently reduce it (transient overvoltage of a magnitude that can cause a problem may occur). ing.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a switching power supply device capable of significantly reducing a transient overvoltage generated in an output voltage.

In order to achieve the above object, the switching power supply device according to the present invention compares the output detection voltage whose voltage value changes according to the voltage value of the output voltage output to the load with a predetermined reference voltage. When the output detection voltage exceeds the reference voltage, the output voltage is lowered, and when the output detection voltage is lower than the reference voltage, the output voltage is raised to control the output voltage to be the target voltage. The constant voltage control operation, the overload detection operation that repeatedly detects whether or not the load has transitioned to the overload state based on the output current output to the load, and the load by lowering the output voltage. A switching power supply device that executes an overload protection operation that reduces the power supplied to the device, and when the transition to the overload state is detected in the overload detection operation, the overload protection operation and the overload protection operation and the above. When the output detection voltage raising operation for raising the output detection voltage to be compared with the reference voltage by a constant voltage is executed and the end of the overload state is detected in the overload detection operation, the overload protection operation is executed. Is stopped, and the output detection voltage raising operation is continued for a predetermined first period from the time when the end of the overload state is detected.

Specifically, this switching power supply device includes a switching element, a power conversion unit that converts an input voltage into the output voltage and outputs the current, and a voltage value of the output voltage while detecting the output voltage. A voltage detection unit that outputs a first detection voltage whose voltage value changes according to the current value, and a current detection unit that detects the output current and outputs a second detection voltage whose voltage value changes according to the current value of the output current. The switching control unit includes a unit and a switching control unit that executes the constant voltage control operation, the overload detection operation, the overload protection operation, and the output detection voltage raising operation, and the switching control unit is based on the second detection voltage. While comparing whether or not the output current is equal to or greater than the predetermined reference current in a cycle shorter than the first period, the transition to the overload state is detected when the output current is equal to or greater than the reference current. The overcurrent detection circuit that executes the overload detection operation that outputs the overcurrent state signal, and the first voltage of the constant voltage are set to the first voltage each time the overcurrent state signal is output from the overcurrent detection circuit. A signal generation circuit that starts the signal generation operation to generate for one period and generates the first voltage at the zero voltage level when the signal generation operation is stopped, and the first detection voltage and the first voltage. An output detection voltage raising circuit that executes the output detection voltage raising operation and an output detection output from the output detection voltage raising circuit are provided with an addition circuit that inputs and adds and outputs as the output detection voltage. An error amplification circuit that amplifies the error between the voltage and the reference voltage and outputs it as an error signal, and a control that controls the switching operation of the switching element based on the second detection voltage, the overcurrent state signal, and the error signal. By providing a control circuit that executes the constant voltage control operation and the overload protection operation by outputting a signal, the above operation is executed.

Therefore, before the actual output voltage reaches the target voltage, the output detection voltage used as the signal indicating the output voltage can be made to reach the reference voltage indicating the target voltage, so that the actual output voltage does not reach the target voltage. The constant voltage control operation can be started and the output detection voltage can be returned to the signal indicating the actual output voltage at the end of the first period. As a result, according to this switching power supply device, an operation of maximizing the output voltage (for example, a control signal having the maximum duty ratio) is performed without starting the constant voltage control operation until the output voltage reaches the target voltage. Unlike conventional switching power supply devices that execute (control operation to output to the switching element), the transient overvoltage that occurs in the output voltage when the output voltage reaches the target voltage can be significantly reduced.

In the switching power supply device according to the present invention, the constant voltage is set so that the output detection voltage when the transition to the overload state is detected in the overload detection operation is lower than the reference voltage. ing.

As a result, even when the output detection voltage raising operation for raising the output detection voltage by a certain voltage is being executed, when the overload protection operation is stopped, the output voltage lowered by this overload detection operation is increased. The operation to make it can be started immediately.

In the switching power supply device according to the present invention, the first period is an elapsed time from the time when the end of the overload state is detected, and is increased by stopping the overload protection operation at the time when the end is detected. The output detection voltage, which rises in response to the output voltage, is defined to be equivalent to the elapsed time until the reference voltage is reached.

As a result, when the output voltage reaches the target voltage, the output detection voltage raising operation that raises the output detection voltage compared with the reference voltage by a certain voltage is stopped, and the output detection voltage indicating the output voltage itself is used as the basis for the output detection voltage. , The constant voltage control operation for controlling the output voltage to the target voltage can be started. Therefore, it is possible to further reduce the transient overvoltage that may occur when the output voltage reaches the target voltage, and shorten the time required for the output voltage to be maintained at the target voltage.

In the switching power supply device according to the present invention, the signal generation circuit is a timer circuit that executes a measurement operation for measuring the first period, and when the measurement operation is executed by the timer circuit, the first voltage is set to the constant voltage. The timer circuit includes a voltage generation circuit that generates and generates the first voltage at a zero voltage level when the measurement operation is stopped, and the timer circuit operates the measurement operation when the overcurrent state signal is input when the measurement operation is stopped. The execution is started, and when the overcurrent state signal is input during the operation of the measurement operation, the execution of the measurement operation is newly started.

As a result, the output detection voltage is set during the overload state (the period during which the measurement operation in the first period is repeated from the beginning) and the period from the end of the overload state period to the completion of the measurement operation in the first period. It is possible to reliably execute the output detection voltage raising operation in which the output detection voltage is raised by a constant voltage.

According to the present invention, the output detection voltage used as a signal indicating the output voltage can be made to reach the reference voltage indicating the target voltage before the actual output voltage reaches the target voltage, so that the actual output voltage is the target. Since the constant voltage control operation can be started before the voltage is reached, the transient overvoltage (surge voltage) that occurs in the output voltage when the output voltage reaches the target voltage can be significantly reduced.

It is a block diagram of the switching power supply device 1. It is an output characteristic figure which shows the relationship between the output current Io of the switching power supply device 1 and the output voltage V2. It is a block diagram of the overcurrent detection circuit 11. It is a waveform diagram for demonstrating operation of an overcurrent detection circuit 11. It is a block diagram of the signal generation circuit 21. It is a waveform diagram for demonstrating the operation of the signal generation circuit 21. It is a waveform diagram for demonstrating the operation of the switching power supply device 1. It is a partially enlarged view of FIG.

Hereinafter, embodiments of the switching power supply device will be described with reference to the drawings.

First, the configuration of the switching power supply device 1 shown in FIG. 1 as a switching power supply device will be described.

As an example, the switching power supply device 1 includes a pair of input terminals 2a and 2b (hereinafter, also referred to as "input terminal 2" when not particularly distinguished) and a pair of output terminals 3a and 3b (hereinafter, when not particularly distinguished, "output terminal 3". ”), A power conversion unit 4, a voltage detection unit 5, a current detection unit 6 and a switching control unit 7 are provided, and an overload protection function (in this example, a constant current voltage drooping type overload protection function) is provided. It is configured as a constant voltage DC power supply device. The overload protection function is not limited to the constant current voltage drooping type.

As shown in FIG. 1, the power conversion unit 4 includes a switching element 4a (field effect transistor, bipolar transistor, etc.) and is an input voltage (AC voltage or DC voltage) input between the input terminals 2. V1 is converted into an output voltage V2 (a DC voltage based on the potential of the internal ground G to which the output terminal 3b is connected) and output between the output terminals 3. The power conversion unit 4 can be composed of various known circuits such as a one-stone forward type circuit, a one-stone flyback type circuit, a push-pull type circuit, and a full bridge type circuit. .. Further, the power conversion unit 4 may have an isolated circuit configuration including an isolation transformer or a non-insulated circuit configuration that does not use an isolation transformer.

The voltage detection unit 5 detects the output voltage V2 and outputs the first detection voltage Vd1 (DC voltage (voltage value Vv) based on the potential of the internal ground G) proportional to the voltage value of the output voltage V2. .. The voltage detection unit 5 uses the voltage value of the output voltage V2 itself, or, for example, a voltage value obtained by dividing the voltage value of the output voltage V2 by a voltage dividing circuit using a plurality of resistors connected in series between the output terminals 3. It can be configured to output as 1 detection voltage Vd1.

As shown in FIG. 1, the current detection unit 6 is arranged on the output terminal 3 side and is supplied to the load LD connected to the output terminal 3 (output current of the power conversion unit 4) Io. Is detected, and the second detection voltage Vd2 (voltage based on the potential of the internal ground G) of the voltage value Vi proportional to the current value of the output current Io is output. The current value of the current (input current) flowing from the input terminal 2 to the power conversion unit 4 is proportional to the current value of the output current Io. Therefore, although not shown, the current detection unit 6 is arranged on the input terminal 2 side, and the current detection unit 6 detects the current value of the input current and outputs the above-mentioned second detection voltage Vd2. It can also be adopted. The arrangement position of the current detection unit 6 is not limited to the above configuration in which the current detection unit 6 is arranged on the output terminal 3 side with reference to the arrangement position of the voltage detection unit 5. For example, it is possible to adopt a configuration in which the voltage detection unit 5 is arranged on the power conversion unit 4 side with reference to the arrangement position. Further, the current value of the alternating current (switching current) switched in the power conversion unit 4 may be proportional to the current value of the output current Io. Therefore, although not shown, the current detection unit 6 is arranged in the power conversion unit 4, and the current detection unit 6 detects the current value of the switching current and has a voltage proportional to the current value of the output current Io. A configuration that outputs a second detection voltage Vd2 having a value of Vi can also be adopted.

Further, the current detection unit 6 can be configured by, for example, a circuit including a current detection resistor having a low resistance value (for example, a minute resistance value of less than 1Ω), or a current probe (Hall element or the like) including a magnetic electric conversion element (Hall element or the like). It can also be configured with a current probe that can detect DC current).

The switching control unit 7 includes an overcurrent detection circuit 11, an output detection voltage raising circuit 12, an error amplifier circuit 13, and a control circuit 14, and switches when the load LD is not in the overload state (in the steady state). A constant voltage control operation for controlling the switching operation of the element 4a to control the output voltage V2 to the target voltage Vtg as shown in FIG. 2 is executed, and when the load LD is in the overload state (reference that the output current Io is described later). In an overcurrent state where the current is Ir or more), an overload protection operation is executed in which the switching operation of the switching element 4a is controlled to reduce the output voltage V2 to reduce the power supplied to the load LD. do. In this example, as an example, in the overload protection operation, as shown in FIG. 2, the switching control unit 7 supplies the output current Io by lowering the output voltage V2 while maintaining the output current Io at a predetermined reference current Ir. It is configured to reduce power (perform a constant current voltage drooping overload protection operation).

The overcurrent detection circuit 11 has a first detection voltage Vd2 (voltage value Vi) and a reference voltage Vri (voltage value Vr1) predetermined for overcurrent detection (detection of an overload state), which will be described later. When the second detection voltage Vd2 is equal to or higher than the reference voltage Vri (that is, when Vi ≧ Vr1) while comparing in a cycle shorter than the period T1, the output current Io is the predetermined reference current Ir (overload state). The overload detection operation that outputs the overcurrent state signal S1 indicating that the reference current (reference current for determining) has been reached (the overcurrent state is equal to or higher than the reference current Ir) is executed.

In this example, as an example, as shown in FIGS. 3 and 4, the overcurrent detection circuit 11 compares the second detection voltage Vd2 with the reference voltage Vri, and when the second detection voltage Vd2 is equal to or higher than the reference voltage Vri ( A signal that becomes high when Vi ≧ Vr1, that is, in an overcurrent state), and becomes low when the second detection voltage Vd2 is less than the reference voltage Vri (when Vi <Vr1, that is, when it is not in an overcurrent state). The comparator 11a that outputs Sa, the signal Sa, and the reference clock Sck in the switching control unit 7 (a frequency sufficiently higher than the switching frequency of the switching element 4a output from a clock generation circuit (not shown) (constant period Tc (third cycle Tc)). A flipflop 11b (in this example, as an example, a D flipflop 11b) that inputs a clock)) and outputs a signal Sb having the same polarity by synchronizing the signal Sa with the reference clock Skc. ), And the signal Sb and the reference clock Sck are input, and the logical product of these signals Sb and Sck is output as the overcurrent state signal S1 (in other words, the reference clock Sck is in the overcurrent state only during the high period of the signal Sb). It is configured to include an AND circuit 11c (which is output as a signal S1).

With this configuration, as shown in FIG. 4, the overcurrent detection circuit 11 equivalently compares the second detection voltage Vd2 and the reference voltage Vri at a fixed period Tc (synchronized with the reference clock Sck). When the second detection voltage Vd2 is equal to or higher than the reference voltage Vri (in the overload state), the overcurrent state signal S1 is output (in this example, it is synchronized with the reference clock Sck as a pulse signal having a pulse width of the reference clock Sck). Executes the overload detection operation. The overcurrent detection circuit 11 adopts a configuration in which the overcurrent state signal S1 is output as a pulse signal having a constant period Tc as described above in the overcurrent state, but the configuration is limited to this configuration. Instead, for example, a configuration that outputs the above signal Sa as an overcurrent state signal S1 (that is, a configuration that outputs an overcurrent state signal S1 that is not synchronized with the reference clock Sck) can also be adopted.

As shown in FIG. 1, the output detection voltage raising circuit 12 includes a signal generation circuit 21 and an addition circuit 22, and inputs the first detection voltage Vd1 output from the voltage detection unit 5, and the first detection voltage. The output detection voltage raising operation (voltage value Vv of the first detection voltage Vd1) is output as the output detection voltage Vd0 (voltage value Vv1) by adding the first voltage Vad to Vd1 (voltage signal proportional to the output voltage V2). The operation of changing to the value Vv1 and outputting) is executed.

As an example in this example, the signal generation circuit 21 includes an OR circuit 21a, a counter 21b, a comparison circuit 21c, a flip-flop 21d (in this example, an RS flip-flop 21d), and a flip-flop 21e ( In this example, as an example, a D flip-flop 21e) and a voltage generation circuit (SG) 21f are provided.

The OR circuit 21a inputs the overcurrent state signal S1 from the overcurrent detection circuit 11 and the reset signal Srst described later output from the D flip-flop 21e, and generates a logical sum of these as a clear signal (CLR signal). Then, it is output to the clear terminal (CLR terminal) described later of the counter 21b. The counter 21b is composed of an n-bit up counter (in this example, a 4-bit up counter having four output terminals Q0 to Q3) as an example, and is a reference input to the clock terminal (CK terminal). A counter operation (increment operation) is executed in synchronization with the clock Sck. As the counter 21b, an n-bit down counter can also be used. Further, the counter 21b has a clock enable terminal (CKEN terminal) for enabling the reference clock Sck and a clear terminal (zero) for clearing (zeroing) the count value Dct output from the output terminals Q0 to Q3. It is equipped with a CLR terminal).

The comparison circuit 21c has an n-bit first data input terminal (in this example, a 4-bit data input terminal D0 to D3) and an n-bit second data input terminal (in this example, a 4-bit data input terminal). It has a data input terminal P0 to P3) and a comparison output terminal So, and is high when the data input to both data input terminals D0 to D3 and P0 to P3 match, and when they do not match, it becomes high. A low comparison output signal So (for easy understanding, the same code as that of the comparison output terminal So is assigned) is output from the comparison output terminal So. In this case, the count value Dctt output from the output terminals Q0 to Q3 of the counter 21b is input to the data input terminals D0 to D3, and the length of the first period T1 described later is input to the data input terminals P0 to P3. The indicated set value Dt is input from the control circuit 14. With this configuration, the comparison circuit 21c outputs a comparison output signal So that becomes high only when the count value Dctt from the counter 21b matches the set value Dt.

In the RS flip-flop 21d, the overcurrent state signal S1 is input to the set terminal (S terminal), and the comparison output signal So is input to the reset terminal (R terminal). With this configuration, the RS flip-flop 21d outputs an enable signal Sen which becomes high by the input of the overcurrent state signal S1 and becomes low by the input of the comparison output signal So from the output terminal Q. In the D flip-flop 21e, the comparison output signal So is input to the input terminal D, and the reference clock Sck is input to the clock terminal CK. With this configuration, the D flip-flop 21e synchronizes the comparison output signal So input to the input terminal D with the reference clock Sck, and outputs the reset signal Srst.

The voltage generation circuit 21f is composed of, for example, a power supply device including an enable terminal (EN terminal) for controlling output on / off. Further, the voltage generation circuit 21f outputs the first voltage Vad as a predetermined constant voltage level (voltage value Vv2) during the period when a high level voltage is input to the EN terminal (when the output is enabled). Output from the terminal (Vout terminal) and output from the output terminal (Vout terminal) with the first voltage Vad as the zero voltage level during the period when a low level voltage is input to the EN terminal (when the output is disabled). do. In this example, as shown in FIG. 5, an enable signal Sen is input from the RS flip-flop 21d to the EN terminal of the voltage generation circuit 21f. With this configuration, the voltage generation circuit 21f outputs the first voltage Vad at the voltage value Vv2 only during the period when the enable signal Sen is high, and zeros the first voltage Vad during the period when the enable signal Sen is low. It is output as a voltage level (that is, the output at the voltage value Vv2 of the first voltage Vad is stopped).

The adder circuit 22 is composed of, for example, a voltage adder circuit configured by using an operational amplifier, inputs a first detection voltage Vd1 and a first voltage Vad, and adds a first voltage Vad to the first detection voltage Vd1. Then, it is output as an output detection voltage Vd0 (voltage value Vv1). With this configuration, when the first voltage Vad is output at the voltage value Vv2 (≠ 0), the addition circuit 22 adds the first voltage Vad to the first detection voltage Vd1 (voltage of the first detection voltage Vd1). The value Vv is increased by the voltage value Vv2 and output as the output detection voltage Vd0 (voltage value Vv1 (= Vv + Vv2)). When the first voltage Vad is output as the zero voltage level, the first detection voltage Vd1 is zero. The voltage levels are added (that is, the first detection voltage Vd1 is substantially unchanged), and the output is output as the output detection voltage Vd0 (voltage value Vv1 (= Vv)).

With this configuration, in the signal generation circuit 21, as shown in FIG. 6, the overcurrent state signal is transmitted from the overcurrent detection circuit 11 during the period when the second detection voltage Vd2 is equal to or higher than the reference voltage Vri (overload state period). Since S1 is output, the RS flip flop 21d starts outputting the enable signal Sen in synchronization with the first overcurrent state signal S1. As a result, the voltage generation circuit 21f also starts output at the voltage value Vv2 of the first voltage Vad in synchronization with the first overcurrent state signal S1. On the other hand, since the high enable signal Sen is input to the CKEN terminal, the counter 21b is in a state where the counting operation synchronized with the reference clock Sck is possible, but the overcurrent state signal output from the overcurrent detection circuit 11 Since S1 is input as a CLR signal to the CLR terminal via the OR circuit 21a, the operation of clearing the count value Dct is executed. Therefore, since the count value Dctt from the counter 21b does not match the set value Dt, the comparison circuit 21c outputs a low comparison output signal So from the comparison output terminal So.

As a result, the enable signal Sen is output from the RS flip-flop 21d during the period when the second detection voltage Vd2 becomes equal to or higher than the reference voltage Vri (the period in the overload state), so that the voltage generation circuit 21f voltage the first voltage Vad. The state of outputting as the value Vv2 is continued. Further, the state in which the reset signal Srst is not output from the D flip-flop 21e continues.

After that, as shown in FIG. 6, when the second detection voltage Vd2 becomes less than the reference voltage Vri (when the overload state ends), the output of the overcurrent state signal S1 from the overcurrent detection circuit 11 ( In this example, the output of the pulse signal of a fixed period Tc) is stopped. In this case, the overcurrent state signal S1 is not output to the counter 21b as a CLR signal via the OR circuit 21a. As a result, the counter 21b in the state where the high-level enable signal Sen is input to the CKEN terminal counts in synchronization with the reference clock Sck immediately after the overcurrent detection circuit 11 stops the output of the overcurrent state signal S1. (Increment operation of count value Dct) is started. On the other hand, the comparison circuit 21c continues to output the low comparison output signal So until the count value Dctt matches the set value Dt. Therefore, since the RS flip-flop 21d continues to output the enable signal Sen and the D flip-flop 21e continues to not output the reset signal Srst, the counter 21b continues the above-mentioned counting operation. Further, the voltage generation circuit 21f also continues the operation of outputting the first voltage Vad as the voltage value Vv2.

Further, after that, as shown in FIG. 6, when the count value Dctt of the counter 21b reaches the same value as the set value Dt, the comparison circuit 21c detects a match with the set value Dt of the count value Dctt, and detects a match with the set value Dt. The comparison output signal So is output at a high level. In this case, since the high-level comparison output signal So is input to the reset terminal (R terminal) of the RS flip-flop 21d, the low-level enable signal is transmitted from the output terminal Q in synchronization with the input of the comparison output signal So. Start the output of Sen. As a result, the counter 21b stops the counting operation because the low-level enable signal Sen is input to the CKEN terminal. Further, the voltage generation circuit 21f stops the operation of outputting the first voltage Vad as the voltage value Vv2, and starts the operation of outputting the first voltage Vad as the zero voltage level.

In this way, the signal generation circuit 21 has a set value synchronized with the reference clock Sck by the counter 21b from the period when the second detection voltage Vd2 becomes equal to or higher than the reference voltage Vri (the period of the overload state) and the end of this period. In a certain period (first period T1 = set value Dt × Tc) until the counting operation (measurement operation) for Dt is completed, the operation of outputting the first voltage Vad as the voltage value Vv2 is continued. For example, in the example shown in FIG. 6, since the set value Dt is set to the value "11 (decimal number)", this first period T1 is set to 11 × Tc. On the other hand, the signal generation circuit 21 executes an operation of outputting the first voltage Vad as a zero voltage level in a period other than the two periods of the overload state and the first period T1. That is, in the signal generation circuit 21, the OR circuit 21a, the counter 21b, the comparison circuit 21c, the RS flip-flop 21d, and the D flip-flop 21e are timer circuits that execute a measurement operation for measuring the first period T1 and are overcurrent. When the state signal S1 is input, the execution of this measurement operation is started, and when a new overcurrent state signal S1 is input during the operation of this measurement operation, it functions as a timer circuit that newly starts the execution of this measurement operation. In this case, the signal generation circuit 21 executes a signal generation operation that outputs the first voltage Vad as a voltage value Vv2 when the measurement operation by the timer circuit is executed, and also this signal generation operation when the measurement operation by the timer circuit is stopped. It stops and outputs the first voltage Vad as the zero voltage level. As shown in FIG. 6, the signal generation circuit 21 of this example adopts a configuration in which the first voltage Vad is output so as to quickly reach the zero voltage level after the completion of the first period T1. Although not shown, it is also possible to adopt a configuration in which the first voltage Vad is output so as to gradually reach the zero voltage level by arranging a filter circuit or the like in the subsequent stage of the voltage generation circuit 21f.

Further, as described above, when the comparison circuit 21c outputs the comparison output signal So at a high level, the D flip-flop 21e inputs the comparison output signal So input to the input terminal D to the clock terminal CK. It is synchronized with the reference clock Sck (that is, delayed by one cycle Tc of the reference clock Sck) and output as a reset signal Srst (high level signal). This reset signal Srst is input as a CLR signal to the CLR terminal of the counter 21b via the OR circuit 21a. Therefore, the counter 21b clears the count value Dct in synchronization with the reset signal Srst (returns to the initial state).

Therefore, the output detection voltage raising circuit 12 provided with the signal generation circuit 21 inputs the first detection voltage Vd1 output from the voltage detection unit 5, and starts from the period of the overload state and the end of this period. In the first period T1, the first voltage Vad (voltage value Vv2 during this period) is added to the first detection voltage Vd1 and output as an output detection voltage Vd0 (voltage value Vv1 = voltage value Vv + voltage value Vv2). Then, in a period other than these two periods, the first voltage Vad (zero voltage level in this period) is added to the first detection voltage Vd1 to obtain the output detection voltage Vd0 (voltage value Vv1 = voltage value Vv). Output (that is, the first detection voltage Vd1 is output as it is as the output detection voltage Vd0).

The error amplification circuit 13 amplifies the error between the output detection voltage Vd0 (voltage value Vv1) and the reference voltage Vrv (voltage value Vr2) output from the output detection voltage raising circuit 12, and outputs the error signal Ver. This reference voltage Vrv is a reference voltage for controlling the output voltage V2 to the target voltage Vtg, and the voltage value Vr2 is the voltage of the first detection voltage Vd1 when the output voltage V2 is controlled to the target voltage Vtg. It is predetermined to match the value Vv.

The control circuit 14 is composed of, for example, a CPU or the like, and is a control signal S2 (for example,) that controls the switching operation of the switching element 4a based on the second detection voltage Vd2, the reference voltage Vri, the overcurrent state signal S1 and the error signal Ver. By outputting the drive pulse signal for PWM control of the switching element 4a, the above-mentioned constant voltage control operation (that is, when the output detection voltage Vd0 exceeds the reference voltage Vrv, the output voltage V2 is lowered, and the output detection voltage Vd0 When is lower than the reference voltage Vrv, the output voltage V2 is increased to maintain the output voltage V2 at the target voltage Vtg), and the above-mentioned overload protection operation (maintain the output current Io to the predetermined reference current Ir). While doing so, the output voltage V2 is lowered to reduce the power supplied to the load LD).

Next, the operation of the switching power supply device 1 will be described. The power conversion unit 4 receives the supply of the control signal S2 output from the control circuit 14 of the switching control unit 7, converts the input voltage V1 into the output voltage V2, and is connected to the output terminals 3. It is assumed that the operation of outputting to the LD is being executed. Therefore, the voltage detection unit 5 detects the output voltage V2 and outputs the first detection voltage Vd1 (voltage value Vv), and the current detection unit 6 detects the output current Io supplied to the load LD. , The second detection voltage Vd2 (voltage value Vi) is output.

First, the operation when the load LD is not in the overload state (when in the steady state as in the period P1 shown in FIG. 7) will be described. In this state, since the output current Io has not reached the reference current Ir, the second detection voltage Vd2 is less than the reference voltage Vri (that is, Vi <Vr1). Therefore, in the overload detection operation, the overcurrent detection circuit 11 compares the second detection voltage Vd2 (voltage value Vi) with the reference voltage Vri (voltage value Vr1), and compares the overcurrent state signal S1 (overcurrent state). The output of the signal indicating that) is stopped.

As a result, in the output detection voltage raising circuit 12, the signal generation circuit 21 outputs the first voltage Vad as the zero voltage level, as shown in FIGS. 6 and 7. Therefore, the addition circuit 22 adds the first voltage Vad (zero voltage level) to the first detection voltage Vd1 and outputs the output as the output detection voltage Vd0. Therefore, the output detection voltage raising circuit 12 inputs the first detection voltage Vd1 from the voltage detection unit 5, and also inputs the first detection voltage Vd1 to which the first voltage Vad of the zero voltage level is added (that is, substantially the first detection voltage Vd1). 1 The detection voltage Vd1 is used as it is) and the output detection voltage Vd0 is output.

The error amplification circuit 13 amplifies the error between the output detection voltage Vd0 (voltage value Vv1) and the reference voltage Vrv (voltage value Vr2) output from the output detection voltage raising circuit 12 and uses it as an error signal Ver in the control circuit 14. Output. In the state where the output detection voltage Vd0 is the first detection voltage Vd1 itself, the error signal Ver indicates the difference between the output voltage V2 and the target voltage Vtg. The control circuit 14 detects that the overcurrent state signal S1 has not been output from the overcurrent detection circuit 11, and is not in an overcurrent state (that is, the load LD is not in an overload state (is a steady state)). Is determined, and the constant voltage control operation is executed. Specifically, the control circuit 14 controls the control signal S2 output to the switching element 4a so that the error signal Ver output from the error amplification circuit 13 becomes zero (switching operation of the switching element 4a). By controlling), a constant voltage control operation for controlling the output voltage V2 to the target voltage Vtg is executed as shown in FIG.

Therefore, even if the load LD fluctuates as in the period P1 shown in FIG. 7, when the output current Io does not reach the reference current Ir, the control circuit 14 executes the above constant voltage control operation and the error signal Ver. Is zero, that is, the switching operation of the switching element 4a is controlled so that the first detection voltage Vd1 as the output detection voltage Vd0 matches the reference voltage Vrv, and the output voltage V2 is set to a constant voltage (target voltage). Control to Vtg). In this example, the control circuit 14 determines whether or not the overcurrent state is in the overcurrent state based on the presence or absence of the output of the overcurrent state signal S1 from the overcurrent detection circuit 11, but the second one is unique. The detection voltage Vd2 and the reference voltage Vri are compared, and when the second detection voltage Vd2 is equal to or higher than the reference voltage Vri, it is determined to be an overcurrent state (overload state), and when the second detection voltage Vd2 is less than the reference voltage Vri, it is steady. It is also possible to adopt a configuration that determines a state (not an overcurrent state (overload state)).

Next, the operation when the load LD is in the overload state (when the period P2 shown in FIG. 7) will be described. In this state, the output current Io has reached the reference current Ir, which is an overcurrent state. As a result, since the second detection voltage Vd2 is equal to or higher than the reference voltage Vri (that is, because Vi ≧ Vr1), the overcurrent detection circuit 11 sets the second detection voltage Vd2 (voltage value Vi) in the overload detection operation. Compared with the reference voltage Vri (voltage value Vr1), as shown in FIG. 4, an overcurrent state signal S1 (a signal indicating an overcurrent state) is output.

As a result, in the output detection voltage raising circuit 12, the signal generation circuit 21 outputs the first voltage Vad as the voltage value Vv2 (≠ 0) as shown in FIGS. 6 and 7. Therefore, the addition circuit 22 adds the first voltage Vad to the first detection voltage Vd1 and outputs the output as the output detection voltage Vd0. Therefore, the output detection voltage raising circuit 12 outputs the first detection voltage Vd1 to which the first voltage Vad is added as the output detection voltage Vd0.

The error amplification circuit 13 amplifies the error between the output detection voltage Vd0 (voltage value Vv1) and the reference voltage Vrv (voltage value Vr2) output from the output detection voltage raising circuit 12 and uses it as an error signal Ver in the control circuit 14. Output. Regarding the voltage value Vv2 of the first voltage Vad added to the first detection voltage Vd1, as shown in FIG. 7, during the period P2 (that is, the overcurrent detection circuit 11 is overloaded in the overload detection operation). The voltage value Vv1 (= voltage value Vv + voltage value Vv2) of the output detection voltage Vd0 (when detecting the transition to the state) is set to be lower than the reference voltage Vrv (voltage value Vr2). do.

The control circuit 14 detects that the overcurrent state signal S1 is output from the overcurrent detection circuit 11, determines that it is in an overcurrent state (that is, the load LD is in an overload state), and determines that the load LD is in the overload state. Perform load protection operations. In this case, the control circuit 14 shifts from the control operation based on the error signal Ver to the control operation based on the second detection voltage Vd2 and the reference voltage Vri. Specifically, the control circuit 14 compares the second detection voltage Vd2 with the reference voltage Vri so that the second detection voltage Vd2 becomes the same as the reference voltage Vri (that is, the output current Io is the reference current Ir). By controlling the control signal S2 output to the switching element 4a (controlling the switching operation of the switching element 4a), the output voltage V2 is less than the target voltage Vtg as shown in FIG. The overload protection operation is executed, which is controlled within the voltage range of (that is, the power supply to the load LD is reduced by lowering the output voltage V2).

Subsequently, the operation when the load LD shifts from the overloaded state to the steady state (when shifting to the period P4 via the period P3 shown in FIG. 7) will be described. Note that FIG. 8 is an enlarged view of a period (a period including the period P3) surrounded by the alternate long and short dash line frame in FIG. 7.

When the load LD shifts from the overloaded state to the steady state, the output current Io drops below the reference current Ir. As a result, the overcurrent detection circuit 11 stops the output of the overcurrent state signal S1 as shown in FIGS. 4 and 6.

In this case, the control circuit 14 detects the end of the overload state and stops the overload protection operation described above. Since the first period T1 continues even in this state, the addition of the first voltage Vad (voltage value Vv2) to the first detection voltage Vd1 is executed. However, the voltage value Vv1 (= voltage value Vv + voltage value Vv2) of the output detection voltage Vd0 obtained by adding the first voltage Vad (voltage value Vv2) to the first detection voltage Vd1 is the reference voltage Vrv (voltage value Vr2) as described above. ) Is set to be lower than. Therefore, the error signal Ver output from the error amplifier circuit 13 that compares the output detection voltage Vd0 and the reference voltage Vrv and amplifies the difference is released from the drooping state of the output voltage when the overload protection operation is stopped. The control circuit 14 is controlled to cause the switching element 4a to perform a switching operation for raising the output voltage V2 to the maximum output voltage that can be output.

As a result, the control circuit 14 rapidly raises the lowered output voltage V2 by controlling the control signal S2 output to the switching element 4a (controlling the switching operation of the switching element 4a). For example, in the configuration in which the switching operation of the switching element 4a is PWM-controlled, the control circuit 14 has a value when the error signal Ver output from the error amplification circuit 13 matches the output detection voltage Vd0 and the reference voltage Vrv. Until, there is a control signal S2 that maximizes the duty ratio (however, there is a period during which the transition from the overload to the steady state cannot be recognized in the initial period of switching from the period P2 to the period P3, and in that period, Due to the influence of the overcurrent detection signal, the duty of the actual pulse operates at a value smaller than the duty in the steady state.) The control to output the output to the switching element 4a is executed, and the output voltage V2 is rapidly increased. As a result, the output voltage V2 rises with a slight delay with respect to the decrease in the output current Io.

On the other hand, in the output detection voltage raising circuit 12, the signal generation circuit 21 stops the output of the overcurrent state signal S1 from the overcurrent detection circuit 11 as shown in FIGS. Even after the end), the output at the voltage value Vv2 of the first voltage Vad is continued only for the first period T1. As a result, as shown in FIGS. 7 and 8, the output detection voltage raising circuit 12 continues to the error amplification circuit 13 with the voltage obtained by adding the first voltage Vad of the voltage value Vv2 to the first detection voltage Vd1 as the output detection voltage Vd0. And output. With this configuration, in this switching power supply device 1, the output detection voltage in the conventional switching power supply device (because the output detection voltage raising circuit 12 is not provided, as shown by the broken line in FIG. 8, the first detection voltage Vd1 itself). The output detection voltage Vd0 reaches the reference voltage Vrv earlier by the amount by which the first voltage Vad of the voltage value Vv2 is added to the first detection voltage Vd1 (only the time T2 indicated by the white arrow). Therefore, in the switching power supply device 1, in the state where the output of the overcurrent state signal S1 is stopped, the output detection voltage Vd0 of the control circuit 14 is thus set based on the error signal Ver from the error amplifier circuit 13. The fact that the reference voltage Vrv has been reached is detected earlier by this time T2 than the control circuit of the conventional switching power supply device, and the control for outputting the control signal S2 having the maximum duty ratio to the switching element 4a is terminated. , Start the constant voltage control operation in the steady state.

Specifically, in the example shown in FIG. 8, the control circuit 14 has a duty ratio in the period P3 after the period P2 in the overload state ends, regardless of the second detection voltage Vd2 and the voltage value of the error signal Ver. Is executed to output the control signal S2 having the maximum value to the switching element 4a to raise the output voltage V2. After that, the control circuit 14 receives a voltage value error signal Ver indicating that the output detection voltage Vd0 (Vv1 = Vv + Vv2) obtained by adding the first voltage Vad of the voltage value Vv2 to the first detection voltage Vd1 has reached the reference voltage Vrv. Is output from the error amplification circuit 13, and the execution of this control (control to output the control signal S2 having the maximum duty ratio to the switching element 4a) is continued in the period P3. Next, when the control circuit 14 detects that the error signal Ver of the voltage value indicating that the output detection voltage Vd0 has reached the reference voltage Vrv has been output from the error amplifier circuit 13, the control circuit 14 ends the execution of this control (period). P3 is terminated), and the period shifts to P4 during which the constant voltage control operation in the steady state is executed.

At this point, even if the output voltage V2 has not reached the target voltage Vtg, the output detection voltage Vd0 (= Vv + Vv2) is in a state of exceeding the reference voltage Vrv. Therefore, the control circuit 14 that has started the constant voltage control operation executes control to output the control signal S2 for lowering the output voltage V2 to the switching element 4a based on the error signal Ver indicating this state. .. However, due to the influence of the frequency characteristic of the control circuit 14, the output voltage V2 does not decrease immediately, but then continuously increases for a short time (a short time immediately after the start of the period P4). However, the control circuit 14 switches the control signal S2 determined based on the error signal Ver, instead of the control (control to output the control signal S2 having the maximum duty ratio to the switching element 4a) as in the period P3. The operation of outputting to the element 4a and controlling it is being executed. Therefore, even when the output voltage V2 subsequently reaches the target voltage Vtg, the duty is until the first detection voltage Vd1 itself reaches the reference voltage Vrv (that is, until the output voltage V2 reaches the target voltage Vtg). Unlike the conventional switching power supply device that executes control to output the control signal S2 having the maximum ratio to the switching element 4a, a situation in which a large transient overvoltage (see FIG. 8) as shown by a broken line occurs in the output voltage V2. (That is, the transient overvoltage generated in the output voltage V2 can be significantly reduced).

Next, when the first period T1 elapses from the time when the period P2 in the overload state ends (the time when the period P3 starts), in the output detection voltage raising circuit 12, the signal generation circuit 21 starts as shown in FIG. , The output of the first voltage Vad at the voltage value Vv2 is stopped, and the output of the first voltage Vad at the zero voltage level is started. As a result, the output detection voltage raising circuit 12 sets the first detection voltage Vd1 to which the first voltage Vad of the zero voltage level is added (that is, the first detection voltage Vd1 as it is) as the output detection voltage Vd0 in the error amplifier circuit 13. Output. The error amplifier circuit 13 amplifies the error between the output detection voltage Vd0 and the reference voltage Vrv and outputs the error signal Ver to the control circuit 14. In this case, the error signal Ver indicates the difference between the output voltage V2 and the target voltage Vtg. Therefore, the control circuit 14 that has already executed the constant voltage control operation controls the control signal S2 output to the switching element 4a so that the error signal Ver becomes zero (controls the switching operation of the switching element 4a). As shown in FIGS. 7 and 8, the output voltage V2 is controlled to the target voltage Vtg.

Further, in the above example shown in FIG. 8, the first period T1 is defined as a length that ends after the output voltage V2 that starts rising from the end of the overload state period P2 reaches the target voltage Vtg. However, the length of the first period T1 is not limited to this, and as shown in FIG. 8, any timing within a predetermined short period T3 including the timing when the output voltage V2 reaches the target voltage Vtg. It can also be specified as the length ending with. However, at the timing when the output voltage V2 reaches the target voltage Vtg, the control circuit 14 controls the switching element 4a based on the error signal Ver indicating the error between the output detection voltage Vd0 indicating the first detection voltage Vd1 as it is and the reference voltage Vrv. That is, the configuration in which the first period T1 is defined in the same manner as the elapsed time from the end of the overload state period P2 until the output voltage V2 that has started to rise reaches the target voltage Vtg. Is preferable. According to this configuration, the time required to maintain the output voltage V2 at the target voltage Vtg is shortened while further reducing the transient overvoltage that may occur when the output voltage V2 reaches the target voltage Vtg. Is possible.

As described above, in the switching power supply device 1, when the transition to the overload state is detected in the overload detection operation (during the period P2 shown in FIGS. 7 and 8), the overload protection operation is executed. At the same time, when the output detection voltage raising operation for increasing the output detection voltage Vd0 compared with the reference voltage Vrv by a constant voltage (voltage value Vv2) is executed and it is detected that the overload state has ended in the overload detection operation ( Period after the end of period P2: When the output of the overcurrent state signal S1 is stopped), the execution of the overload protection operation is stopped, and the end of the overload state is detected for the output detection voltage raising operation. The execution is continued from the time when the period P2 is completed (the end time of the period P2) to the predetermined first period T1. Specifically, in this switching power supply device 1, the voltage detection unit 5, the current detection unit 6, and the switching control unit 7 (overcurrent detection circuit 11, output detection voltage raising circuit 12, error amplifier circuit 13, and control circuit 14) ) And to perform such an operation.

Therefore, according to this switching power supply device 1, the output detection voltage Vd0 used as a signal indicating the output voltage V2 reaches the reference voltage Vrv indicating the target voltage Vtg before the actual output voltage V2 reaches the target voltage Vtg. Therefore, the constant voltage control operation is started before the actual output voltage V2 reaches the target voltage Vtg, and the output detection voltage Vd0 is returned to the signal indicating the actual output voltage V2 at the end of the first period T1. Can be done. As a result, according to the switching power supply device 1, the operation of maximizing the output voltage V2 without starting the constant voltage control operation until the output voltage V2 reaches the target voltage Vtg (specifically, the duty ratio). Unlike the conventional switching power supply device that executes the control operation (control operation to output the control signal S2 that maximizes) to the switching element 4a), the transient overvoltage that occurs in the output voltage V2 when the output voltage V2 reaches the target voltage Vtg. (Surge voltage) can be significantly reduced.

Further, according to this switching power supply device 1, the above constant voltage (voltage value) is set so that the output detection voltage Vd0 when the transition to the overload state is detected in the overload detection operation is lower than the reference voltage Vrv. Since Vv2) is specified, even in the state where the output detection voltage raising operation for increasing the output detection voltage Vd0 by a constant voltage (voltage value Vv2) is being executed, when the overload protection operation is stopped, this excess The operation of increasing the output voltage V2, which has been decreased by the load detection operation, can be immediately started.

Further, according to this switching power supply device 1, the first period T1 is defined in the same manner as the elapsed time until the output voltage V2, which has started to rise from the end of the overload state period P2, reaches the target voltage Vtg. At the timing when the output voltage V2 reaches the target voltage Vtg, the output detection voltage raising operation for raising the output detection voltage Vd0 compared with the reference voltage Vrv by a constant voltage (voltage value Vv2) is stopped, and the output voltage V2 itself. Based on the output detection voltage Vd0 indicating, the constant voltage control operation for controlling the output voltage V2 to the target voltage Vtg can be started. According to this configuration, the time required to maintain the output voltage V2 at the target voltage Vtg while further reducing the transient overvoltage (surge voltage) that may occur when the output voltage V2 reaches the target voltage Vtg. Can be shortened.

Further, the switching power supply device 1 is composed of a timer circuit (OR circuit 21a, counter 21b, comparison circuit 21c, RS flip flop 21d and D flip flop 21e) that executes a measurement operation for measuring the first period T1. Circuit), and when this measurement operation is executed by the timer circuit, the first voltage Vad is generated at a constant voltage (voltage value Vv2), and when this measurement operation is stopped, the first voltage Vad is generated at the zero voltage level. By configuring the signal generation circuit 21 in the above, the measurement operation of the first period T1 is completed from the end of the overload state period (the period in which the measurement operation of the first period T1 is repeated from the beginning) and the end of the overload state period. In the period until the voltage is increased, the output detection voltage raising operation for raising the output detection voltage Vd0 by a constant voltage (voltage value Vv2) can be reliably executed.

The timer circuit of the signal generation circuit 21 is not limited to the above configuration. For example, a one-shot multivibrator circuit can be adopted, and the control circuit 14 configured by the CPU executes the function of the timer circuit. It is also possible to adopt a configuration that does. Further, an example in which the set value Dt for defining the length of the first period T1 is set as a fixed value has been described above. For example, the control circuit 14 detects the timing when the output voltage V2 reaches the target voltage Vtg. , It is also possible to adopt a configuration in which the set value Dt is changed so that the end of the first period T1 coincides with this timing.

1 Switching power supply 4 Power conversion unit 4a Switching element 5 Voltage detection unit 6 Current detection unit 7 Switching control unit 11 Overcurrent detection circuit 12 Output detection voltage raising circuit 13 Error amplification circuit 14 Control circuit 21 Signal generation circuit 22 Addition circuit Io output Current LD Load S1 Overcurrent state signal S2 Control signal V1 Input voltage V2 Output voltage Vad 1st voltage Vd0 Output detection voltage Vd1 1st detection voltage Vd2 2nd detection voltage Ver Error signal Vrv Reference voltage Vv2 Constant voltage

Claims (5)

While comparing the output detection voltage whose voltage value changes according to the voltage value of the output voltage output to the load with the predetermined reference voltage, the output voltage is lowered when the output detection voltage exceeds the reference voltage. When the output detection voltage is lower than the reference voltage, the output voltage is increased to control the output voltage so that it becomes the target voltage, and the output current output to the load. Switching that executes an overload detection operation that repeatedly detects whether or not the load has transitioned to an overload state based on the above, and an overload protection operation that reduces the power supplied to the load by lowering the output voltage. It ’s a power supply,
When the transition to the overload state is detected in the overload detection operation, the overload protection operation and the output detection voltage raising operation for increasing the output detection voltage to be compared with the reference voltage by a constant voltage are performed. Run and
When the end of the overload state is detected in the overload detection operation, the execution of the overload protection operation is stopped, and the output detection voltage raising operation is performed in advance from the time when the end of the overload state is detected. A switching power supply that continues to run for the specified first period. The switching power supply according to claim 1, wherein the constant voltage is set so that the output detection voltage when the transition to the overload state is detected in the overload detection operation is lower than the reference voltage. Device. The first period is an elapsed time from the time when the end of the overload state is detected, and increases according to the output voltage that increases due to the stop of the overload protection operation at the time when the end is detected. The switching power supply device according to claim 1 or 2, wherein the output detection voltage is defined to be equivalent to the elapsed time until the reference voltage is reached. A power conversion unit that includes a switching element and converts an input voltage into the output voltage for output.
A voltage detection unit that detects the output voltage and outputs a first detection voltage whose voltage value changes according to the voltage value of the output voltage.
A current detection unit that detects the output current and outputs a second detection voltage whose voltage value changes according to the current value of the output current.
A switching control unit that executes the constant voltage control operation, the overload detection operation, the overload protection operation, and the output detection voltage raising operation is provided.
The switching control unit
When the output current is equal to or greater than the reference current while comparing whether or not the output current is equal to or greater than a predetermined reference current based on the second detection voltage in a cycle shorter than that of the first period, the excess An overcurrent detection circuit that executes the overload detection operation that detects the transition to the load state and outputs an overcurrent state signal, and
Each time the overcurrent state signal is output from the overcurrent detection circuit, the signal generation operation of generating the first voltage of the constant voltage over the first period is started, and the signal generation operation is stopped. The output is sometimes provided with a signal generation circuit that generates the first voltage at a zero voltage level, and an adder circuit that inputs and adds the first detection voltage and the first voltage and outputs the output detection voltage. An output detection voltage raising circuit that executes the detection voltage raising operation, and
An error amplification circuit that amplifies the error between the output detection voltage and the reference voltage output from the output detection voltage raising circuit and outputs it as an error signal.
Control to execute the constant voltage control operation and the overload protection operation by outputting a control signal for controlling the switching operation of the switching element based on the second detection voltage, the overcurrent state signal, and the error signal. The switching power supply device according to any one of claims 1 to 3, further comprising a circuit. The signal generation circuit is a timer circuit that executes a measurement operation for measuring the first period, and generates the first voltage at the constant voltage when the measurement operation is executed by the timer circuit, and when the measurement operation is stopped, the signal generation circuit generates the first voltage at the constant voltage. A voltage generation circuit that generates the first voltage at a zero voltage level is provided, and the timer circuit starts executing the measurement operation when the overcurrent state signal is input when the measurement operation is stopped, and the measurement operation is performed. The switching power supply device according to claim 4, wherein when the overcurrent state signal is input during operation, execution of the measurement operation is newly started.

Images