JP6950130B2 - Sequential comparison type AD converter, semiconductor device and electronic device - Google Patents

Description

The present invention relates to, for example, a secure sequential comparison type AD converter for a sensor system, a semiconductor device including the sequential comparison type AD converter, and an electronic device including the semiconductor device. Hereinafter, "analog-digital conversion" is referred to as "AD conversion".

FIG. 1A is a block diagram showing a configuration of a sequential comparison type AD converter according to a conventional example (see, for example, Patent Document 1), and FIG. 1B shows a state signal of the control circuit 10 of the sequential comparison type AD converter of FIG. 1A. It is a timing chart shown.

In FIG. 1A, the sequential comparison type AD converter according to the conventional example includes a control circuit 10, a sequential comparison control unit 20, a switch 1, a capacitive DA converter 2, a comparator 3, and a serial-parallel conversion (hereinafter referred to as. , "Serial-parallel conversion" is referred to as "SP conversion".) It is configured to include a device (SPC) 4.

The control circuit 10 generates a sample hold control signal φ _SH and a timing control signal φ _{0 to φ N-1,} and outputs them to the switch 1 and the sequential comparison control unit 20, respectively. The sequential comparison control unit 20 is based on the digital signal _SCOMP of the comparison result from the comparator 3 and the timing control signals φ _{0 to φ N-1,} and the DA conversion control signal SC1 for the capacitive DA converter 2. ~ SCM is generated and output to the capacitive DA converter 2. _{The switch 1 samples (samples) the input voltage V IN} input to the terminal T1 according to the sample hold control signal φ _SH from the control circuit 10 and outputs it to the capacitive DA converter 2. The capacitive DA converter 2 includes a capacitive array composed of a plurality of capacitors C1 to CM having capacitance values 1C, 2C, 4C, ..., ^2N- _{1C weighted with binaries, and a reference voltage V REF of the terminal T2.} A plurality of switches S1 to SM for selecting one of the above and the ground potential are included, _{and while holding the sampled input voltage VIN} , DA conversion is performed according to the DA conversion control signals SC1 to SCM and output to the comparator 3. do. The comparator 3 compares the DA-converted input voltage V _IN with the comparison threshold voltage V _CM of the terminal T3, and outputs the digital signal _SCOMP of the comparison result to the SP converter 4. The SP converter 4 _{decodes the digital signal SCOMP} of the comparison result by SP conversion, and outputs the output data D _OUT of the AD conversion value to the terminal T4.

In the sequential comparison type AD converter configured as described above, the sequential comparison control unit 20 performs the sequential comparison period ((SH)) after the sample hold (sampling hold ((SH)) period according to the control circuit state signal of FIG. 1B. In _{DN-1 to} D _{0 ), the input voltage VIN is determined} by a known dichotomy method from the most significant bit to the least significant bit while sequentially comparing the pair of voltages input to the comparator 3. The switches S1 to SM are sequentially selectively switched so that the _{voltage V DAC} substantially matches the DA conversion voltage V _{DAC, and the input voltage V IN} is AD-converted to output the output data D _OUT of the AD conversion value.

By the way, for example, in many AD converters mounted on a sensor system, the reference voltage terminal is composed of an output terminal of an external pin. A voltage waveform that depends on AD conversion data appears at the reference voltage terminal.

International Publication No. 2014/038198 Pamphlet

Ingrid Verbauhede, et al. , “Circuit Challenges from Cryptography,” ISSCC 2015 (IEEE International Solid-State Circuits Conference 2015), Digist Technical Papers, p. 428-249, February 2015. Minseo Kim, et al. , "A 82nW Chaotic-Map True Random Number Generator Based on Sub-Ranging SAR ADC," ESSCIRC 2016 (European Solid-State Circuits 2016) 157-160, September 2016. Suresh Chari, et al. , “Template Attacks,” CHES 2003 (Cryptographic Hardware and Embedded Systems 2003), pp. 13-28, February 2003. Naofumi Homma, Takafumi Aoki, "Keywords you should know, side-channel attacks", Journal of the Institute of Image Information and Television Engineers, Vol. 64, No. 11, pp. 1576-1579, November 2010

Therefore, when the reference voltage waveform is analyzed, the sensor data before encryption may be leaked. Further, if a voltage or the like is forcibly applied through the reference voltage terminal, there is a problem that the sensor data may be falsified.

An object of the present invention is to solve the above problems and to provide a sequential comparison type AD conversion device that is more secure than conventional examples.

Another object of the present invention is to provide a semiconductor device provided with a sequential comparison type AD conversion device that is more secure than a conventional example, and an electronic device provided with the semiconductor device.

The sequential comparison type AD converter according to the first invention is
A DA converter that samples and holds the input analog signal and DA-converts the digital data after sampling and holding into an analog signal.
A comparator that compares the analog signal from the DA converter with a predetermined threshold value and outputs a comparison result signal,
It is provided with a sequential comparison control unit that controls the DA converter so as to AD-convert the input analog signal into digital data sequentially from the most significant bit to the least significant bit by a dichotomy method.
A successive approximation type AD conversion device that AD-converts the input analog signal into digital data.
A random bit generation circuit that generates random bits, and
An inverting bit inverting circuit that inverts the comparison result signal for at least one bit below the most significant bit based on the random bit to generate an inverting bit.
Based on the random bit and the inverting bit, a predetermined dither voltage is changed from a predetermined comparison threshold value in the period indicated by the inverting bit so that the same comparison result signal can be obtained regardless of the presence or absence of the inverting. It is characterized by including a follow-up voltage generating circuit that generates a follow-up voltage, which is a threshold value for the comparator, and outputs the follow-up voltage to the comparator.

In the sequential comparison type AD converter, the random bit generation circuit is characterized in that a random bit is generated after sequential comparison of the least significant bits based on the comparison result signal.

The semiconductor device according to the second invention is a semiconductor device including the sequential comparison type AD conversion device.

The electronic device according to the third invention is characterized by including the semiconductor device.

Therefore, according to the sequential comparison type AD conversion device according to the present invention, it is possible to provide a sequential comparison type AD conversion device that is more secure than the conventional example.

It is a block diagram which shows the structure of the sequential comparison type AD converter which concerns on a prior art example. It is a timing chart which shows the state signal of the control circuit 10 of the sequential comparison type AD converter of FIG. 1A. It is a figure for demonstrating the problem of this invention, and is the block diagram which shows the structural example of the IoT sensor node circuit 30 including the known sequential comparison type AD converter 36. It is a circuit diagram which shows the structural example of the sequential comparison type AD converter 36 of FIG. 2A. It is a timing chart which shows the operation example of the IoT sensor node circuit 30 of FIG. 2A. It is a block diagram which shows the structural example of the sequential comparison type AD converter which concerns on embodiment. It is a timing chart which shows the state signal of the control circuit 10A of the sequential comparison type AD converter of FIG. 3A. It is a block diagram which shows the structural example of the random bit generation circuit 11 of FIG. 3A and its peripheral circuit. It is a timing chart which shows the basic operation of the sequential comparison type AD converter of FIG. 3A. It is a block diagram which shows the structural example of the bit inversion circuit 12 and the peripheral circuit of FIG. 3A. It is a timing chart which shows the bit inversion operation of the sequential comparison type AD converter of FIG. 3A. It is a circuit diagram which shows the structural example of the follow-up voltage generation circuit 13 of FIG. 3A. It is a timing chart which shows the voltage follow-up operation of the sequential comparison type AD converter of FIG. 3A. It is a circuit diagram which shows the structural example of the follow-up voltage generation circuit and its peripheral circuit in the AD conversion apparatus of FIG. 3A. It is a truth table which shows the operation example of the follow-up voltage generation circuit 13 of FIG. 7A. It is a timing chart which shows the operation example of the sequential comparison type AD conversion apparatus which includes the follow-up voltage generation circuit 13 of FIG. 7A. It is a graph which shows the comparison of the chip area between the AD conversion device without calibration of the conventional example, and the AD conversion device with calibration of 7% overhead according to the embodiment. FIG. 5 is a block diagram showing a configuration of an experimental system for evaluating a side channel attack (SCA) on the charging side of a reference voltage for an AD converter according to an embodiment. Leakage data measured by a side-channel attack (SCA) on the charging side of the reference voltage obtained by the experimental system of FIG. 8 using the template matching method, showing the time waveform of the output code when unprotected. It is a figure. 9A is a spectrum diagram showing a power spectrum of measured leakage data in the non-protected state of FIG. 9A. Leakage data measured by a side-channel attack (SCA) on the charging side of the reference voltage obtained by the experimental system of FIG. 8 using the template matching method, showing the time waveform of the output code during protection. Is. It is a spectrum diagram which shows the power spectrum of the measured leakage data at the time of protection of FIG. 10A. It is a spectrum diagram which shows the power spectrum without calibration in the experimental system of FIG. It is a spectrum diagram which shows the power spectrum with calibration in the experimental system of FIG. It is a graph which shows the calibration effect of the power spectrum in the experimental system of FIG. It is the experimental result obtained by the experimental system of FIG. 8, and is the table which shows each performance value at the time of protection and the time of not protection.

Hereinafter, each embodiment of the present invention will be described. In the drawings, the same or similar components are designated by the same reference numerals and detailed description thereof will be omitted.

As described above, the AD converter has a problem that the data processed by the AD converter is leaked by analyzing the reference voltage waveform during operation. By performing the dithering process according to the conventional technology, it is possible to reduce the correlation between the internal operation of the AD converter and the converted data, but since the dithering process superimposes noise on the input signal, reducing the input range is an issue. Become. Therefore, there is a demand for a method of eliminating the correlation between the reference voltage waveform and the converted data and preventing data leakage without sacrificing the performance of the AD converter. Hereinafter, the above-mentioned problems will be specifically described with reference to FIGS. 2A to 2C.

FIG. 2A is a diagram for explaining the problems of the present invention, and is a block diagram showing a configuration example of an IoT (Internet of Things) sensor node circuit 30 including a known successive approximation type AD converter 36. The sequential comparison type AD converter 36 is not limited to the IoT sensor node circuit 30, and may be built into an electronic device such as an IoT, a personal computer, a smart phone, or a mobile phone.

In FIG. 2A, the IoT sensor node circuit 30 includes terminals T11 to T13, a sensor signal processing IC 32, and an RF signal processing IC 33. Here, the sensor signal processing IC 32 includes a signal amplifier 35, a successive approximation type AD converter (SARADC) 36, and a microcomputer unit (MCU) 37 incorporating an encryption circuit 38. The sensor signal detected by the sensor 31 is input to the sequential comparison type AD converter 36 via the signal amplifier 35 in the sensor signal processing IC 32 via the terminal T11. The sequential comparison type AD converter 36 AD-converts the sensor signal and then outputs the sensor signal to the microcomputer unit 37. The microcomputer unit 37 encrypts the input sensor signal using the encryption circuit 38 and then processes the sensor signal. The latter digital signal is output to the RF signal processing IC 33. Next, the RF signal processing IC 33 is digitally modulated by a predetermined digital modulation method, and then converted to a radio frequency in a high frequency range to generate a digitally modulated radio signal, which is transmitted from the antenna 34.

FIG. 2B is a circuit diagram showing a configuration example of the known successive approximation type AD converter 36 of FIG. 2A, and FIG. 2C is a timing chart showing an operation example of the IoT sensor node circuit 30 of FIG. 2A.

A physical attack in the hardware domain against the IoT sensor node circuit 30 shown in FIG. 2A is one of the serious threats. The output digital information of the MCU and the signal on the wireless network are difficult to decrypt by encryption, but the encryption key may be extracted by a side channel attack (SCA) via the power supply terminal on the digital hardware block. However, this digital SCA has been widely discussed, and many countermeasures have been reported (see, for example, Non-Patent Document 1).

However, there is not much discussion about physical attacks on analog hardware blocks in the front-end circuitry of the sensor 31. In practice, the security of the subsequent digital blocks is even more important because it all depends on the security of the analog front-end circuitry. In this embodiment, the countermeasure circuit of SCA for the successive approximation type AD converter, which is mainly a general sensor analog front-end circuit block, will be described below. Here, since the analog information taken in from the sensor 31 is a very weak signal, it is impossible to directly probe it, but it flows through _{the input voltage VIN and the reference voltage terminal of the successive approximation type AD converter.} By utilizing the correlation with the electric charge (FIG. 2B), SCA for the successive approximation type AD converter becomes possible. That is, as shown in FIG. 2C, different spike waveforms appear at the reference voltage terminal according to the operation of the capacitive DA converter inside the successive approximation type AD converter. Therefore, the input voltage is analyzed by analyzing the reference voltage waveform. V _IN can be restored.

There are several potential circuit techniques to control side-channel leaks in successive approximation AD converters. Although the differential structure has a certain effect on protection, the correlation between the waveform of the _{analog input voltage V IN} and the waveform of the reference voltage V _{REF cannot be completely eliminated because the current flow during charge redistribution is not offset.} .. Another solution is dithering. Dithering is one of the methods for improving the performance against non-linear error by intentionally injecting noise into the analog input voltage _{VIN of the AD converter and subtracting the noise in the digital region of the subsequent stage.} This technique can hide the correlation between input and internal operation, such as logical masking against digital side channel attacks (SCA).

Hereinafter, embodiments according to the present invention for solving the above problems will be described.

Embodiment.
FIG. 3A is a block diagram showing a configuration example of the sequential comparison type AD converter according to the embodiment, and FIG. 3B is a timing chart showing a state signal of the control circuit 10A of the sequential comparison type AD converter of FIG. 3A.

In FIG. 3A, the sequential comparison type AD converter according to the embodiment includes a control circuit 10A, a sequential comparison control unit 20A, a switch 1, a capacitive DA converter 2, a comparator 3, and an SP converter (SPC). ) 4, a random bit generation circuit 11, a bit inversion circuit 12, and a follow-up voltage generation circuit 13. Therefore, the successive approximation type AD converter according to the embodiment differs from the sequential comparison type AD converter of FIG. 1A in the following points.
(1) A control circuit 10A is provided instead of the control circuit 10.
(2) Instead of the sequential comparison control unit 20, a sequential comparison control unit 20A is provided.
(3) A capacitive DA converter 2A is provided instead of the capacitive DA converter 2. Here, the capacitive DA converter 2A is a switch controlled by a capacitor C0 having a capacitance value 0.5C, which is half of the unit capacitance value C, and a corresponding control signal SC0, as compared with the capacitive DA converter 2. Further provided with S0.
(4) A random bit generation circuit 11, a bit inversion circuit 12, and a follow-up voltage generation circuit 13 are further provided.
The differences will be described in detail below.

The control circuit 10A generates a sample hold control signal φ _SH , a timing control signal φ _{0 to φ N-1,} and a redundant timing control signal φ _R , respectively, and generates a switch 1, a sequential comparison control unit 20A, and a random bit, respectively. Output to circuit 11. The sequential comparison control unit 20A is based on the digital signal _SCOMP of the comparison result from the comparator 3, the timing control signals φ ₀ , ..., φ _N-3 , φ _N-1, and the redundant timing control signal φ _R. , DA conversion control signals SC0 to SCM for the capacitive DA converter 2 are generated and output to the capacitive DA converter 2. _{The switch 1 samples the input voltage V IN} input to the terminal T1 according to the sample hold control signal φ _SH from the control circuit 10A and outputs it to the capacitive DA converter 2A. The capacitive DA converter 2A includes a capacitive array composed of a plurality of capacitors C0 to CM each having a binary-weighted capacitance value of 0.5C, 1C, 2C, 4C, ..., ^{2N-1C, and terminal T2.} A plurality of switches S0 to SM for selecting one of the reference voltage V _REF and the ground potential are included, and the sampled input voltage V _IN is DA-converted according to the DA conversion control signals SC0 to SCM to the comparator 3. Output. Comparator 3, an input voltage _{V IN} is DA converted, compared to the track-voltage _{V T} from the track-voltage generating circuit 13, and outputs the digital signal _{S COMP} the comparison result to the SP converter 4.

As shown in FIG. 3B, the control circuit 10A generates a redundant timing control signal φ _R indicating a random bit generation period φ _R after the least significant bit (LSB) comparison period φ _{0 indicated by the timing control signal φ 0} . In this specification, in order to make the corresponding time period easy to understand, the timing control signals φ _{0 to φ N-1} , φ _{R and the time period φ 0 to φ N-1} , φ indicated by those signals are used. _R is indicated by using the same reference numerals as each other.

Random bit generation circuit 11, a redundant timing control signal phi _R, based on the comparison result and a digital signal S _COMP, the bit inversion circuit 12 and the track-voltage generating circuit 13 generates a random bit D _R to be detailed later output do. Bit inverting circuit 12, according to a random bit D _R, and outputs the successive approximation control unit 20A inverts or non-inverts the comparator output signal at a timing of the timing control signal φ _N-2. The SP converter 4 _{decodes the digital signal SCOMP} of the comparison result by SP conversion, and outputs the output data D _OUT of the AD conversion value to the terminal T4.

FIG. 4A is a block diagram showing a configuration example of the random bit generation circuit 11 of FIG. 3A and its peripheral circuits, and FIG. 4B is a timing chart showing the basic operation of the sequential comparison type AD converter of FIG. 3A.

In Figure 4A, the random bit generation circuit 11 includes a delay-type flip-flop 11m, the comparison result of the digital signal S _COMP, a latch on the timing of the redundant timing control signal phi _R to the track-voltage generating circuit 13 as a random bit D _R Output. Thus, after the bit determination of the least significant bit (LSB), by controlling the capacitor C0 of the capacitance value 0.5C added to the DA converter 2A, the output voltage _{V DAC} DA converter 2A, comparison threshold Bring it closer to the voltage V _CM. Thereafter, comparator 3, a DA converter voltage _{V DAC} in the random bit generation period phi _R, compared compared to the threshold voltage _{V CM,} the comparison result of the digital signal _{S COMP} in the delay-type flip-flop 11m temporarily storing do. At this time, since _{the values of the DA conversion voltage V DAC} and the comparison threshold voltage V _CM are extremely close to each other, 1 or 0 is probabilistically output due to the thermal noise of the comparator 3 as shown in FIG. 4B. NS. That is outputted random bit D _R is generated in the bit inversion circuit 12 and the track-voltage generating circuit 13 having the probability distribution of the thermal noise of the comparator 3.

Incidentally, the additional capacitors C0 of the capacitance value 0.5C, the prior art compared to the by closer DA conversion voltage _{V DAC} to compare the threshold voltage _{V CM,} the probability distribution of the thermal noise of the comparator 3 (Fig. 4B ), And if the AD converter (σ >> 0.3LSB) is already within the probability distribution of the thermal noise of the comparator 3 at the comparison stage of the least significant bit (LSB), the capacitor C0 No need to add. Further, in the AD converter (σ << 0.3LSB) having sufficiently small thermal noise, additional capacitors having more accurate additional capacitance values 0.25C, 0.125C, 0.0625, ... Are required.

FIG. 5A is a block diagram showing a configuration example of the bit inverting circuit 12 of FIG. 3A and its peripheral circuits, and FIG. 5B is a timing chart showing a bit inverting operation of the successive approximation type AD converter of FIG. 3A.

In FIG. 5A, the bit inversion circuit 12 includes an exclusive OR gate 12e and a delay type flip-flop 12m. In the bit inversion circuit 12, exclusive OR gate 12e is a digital signal _{S COMP} the comparison result of lower than the most significant bit (MSB) bit next (N-2), exclusive of a random bit _{D R} The sum operation is performed and the output signal is output to the delayed flip-flop 12m. The delay type flip-flop 12m latches and latches the output signal from the exclusive OR gate 12e at the timing of _{the timing control signal φ N-2 , and uses the latched signal as the inverting bit DN-2} for sequential comparison with the follow-up voltage generation circuit 13. Output to the control unit 20A. As shown in Figure 5B, when the value of the random bit D _R is 0, the value of the DA converted voltage V _DAC for comparison the next bit is controlled so as to approach the conventional comparison threshold voltage V _CM that one, when the value of the random bit _{D R} is 1, DA converted voltage _{V DAC} is controlled to be compared threshold voltage _{V CM} opposite direction. _{By this control operation, the dither voltage V D,} which is the voltage difference due to inversion, is applied to the input voltage V _IN.

The inverting bit is not limited to the next bit (N-2) lower than the most significant bit (MSB). If the inverting bit is the next bit (N-2) lower than the most significant bit (MSB) or a bit lower than that, there can be one or more inverting bits, in which case a random bit. Can be realized by increasing the number of bits. The bit inverting circuit 12 of FIG. 5A is configured by using the exclusive OR gate 12e, but the present invention is not limited to this, and may be configured by, for example, a selector circuit that selectively selects and outputs a plurality of predetermined voltages. good.

FIG. 6A is a circuit diagram showing a configuration example of the follow-up voltage generation circuit 13 of FIG. 3A, and FIG. 6B is a timing chart showing the voltage follow-up operation of the successive approximation type AD converter of FIG. 3A.

In FIG. 6A, the follow-up voltage generation circuit 13 includes a capacitance array composed of capacitors C11 to C32, switches S12 and S32 for controlling the capacitance array, sampling switches S21 to S23, and a selector 13s. The track-voltage generating circuit 13, as shown in FIG. 6B, when the control operation reverse the DA converter 2A by bit inversion circuit 12, the comparator threshold voltage V _CM, is applied to the differential voltage dither by the voltage V _D min to follow the same direction as the control operation of the reverse. That is, the track-voltage generating circuit 13 generates a tracking voltage _{V T (= V CM + V} D). As a result, the applied dither voltage V _D can be subtracted from the comparison threshold voltage V _CM , and the same output code as in the case where the inversion operation is not performed can be obtained.

In Figure 6A, after the comparison threshold voltage _{V CM} by the sample-and-hold (sampling hold) period phi _SH was sampled and held by the switch S21 to S23, after the short time [Delta] [phi, controls the bottom plate voltage of the capacitor C12, C32 Then, by redistributing the charges, in addition to the _{comparative threshold voltage V CM , the voltage V CM} + V _D and the voltage V _CM −V _D are generated. That is, the three voltage _V CM + _{V D,} the voltage _{V M,} the voltage _V CM -V _D is generated. The selector 13s includes a random bit _{D R,} on the basis of the following bit _{D N-2} lower than the most significant bit (MSB), as follows, the three voltage _V CM + _{V D,} the voltage _{V M,} the voltage from V _CM -V _D by selecting one voltage outputs as follows voltage _{V T.}

₍₁₎ when _{D N-2} = 0, and outputs the comparison threshold voltage _{V CM.
(2)} and a _{D N-2} = 1 when _D R = 1, and outputs a voltage _V CM + _{V D.
(3)} when _{D N-2} = 1 a and _D R = 0, and outputs a voltage _V CM -V _D.

Incidentally, the track-voltage generating circuit 13 of FIG. 6A is constructed by using the capacitor array and the selector 13s, the present invention is not limited to this, three voltage V _{CM +} V by a plurality of dividing resistors a predetermined power supply voltage _D, configuration voltage _{V M,} the voltage _V CM -V _D to generate by the by the selector 13s 3 pieces of voltage _V CM + _{V D,} the voltage _{V M,} from the voltage _V CM -V _D to select one voltage You may.

FIG. 7A is a circuit diagram showing a configuration example of the follow-up voltage generation circuit 13 and its peripheral circuits in the AD conversion device of FIG. 3A. Further, FIG. 7B is a truth table showing an operation example of the follow-up voltage generation circuit 13 of FIG. 7A, and FIG. 7C is a timing chart showing an operation example of the sequential comparison type AD conversion device including the follow-up voltage generation circuit 13 of FIG. 7A. Is.

That is, FIG. 7A shows a configuration example of the tracking voltage generation circuit 13 and the calibration circuit 56 using the dither tracking DA converter. Here, the follow-up voltage generation circuit 13 is configured in the same manner as in FIG. 6A. From the comparative threshold voltage V _{CM , two voltages (V CM} ± V _D ) are generated by the charge redistribution capacitors C12 and C32 in order to follow both directions of the dithering process. To prevent exposure of switching operations using the reference voltage V _REF to external circuits, these voltages operate in sample hold phase (SH), are pre-made, and are one of these during follow-up operation. The voltage is selected by the selector 13s.

As shown in the table of FIG. 7B, the track-voltage generating circuit 13 includes a random bit D _R, based on the period designating bit D _8, it generates a tracking voltage V _T shown in the table. Here, the dither tracking DA converter track-voltage generating circuit 13 is different from the main volume type DA converter 36A, to calibrate the error of the output voltage of the dither follower DA converter (V _CM ± V _D) in the digital domain It does not have to be highly accurate because it can be done. _{Here, the error ε P} between the output voltage of the ideal dither-following DA converter and the output voltage of the actual dither-following DA converter is the redundancy of the capacitor CM with the capacitance value of 4C of the additional capacitive DA converter. It is estimated using the property and added to the output voltage data.

FIG. 7D is a graph showing a comparison of chip areas between the conventional non-calibrated AD converter and the calibrated AD converter according to the embodiment. Without calibration, the capacitive element of the dither tracking DA converter 13 needs to have the same accuracy as the main capacitive DA converter 36A. However, this calibration relaxes the capacitance accuracy of the dither tracking DA converter and can reduce it to a capacitance value that satisfies the thermal noise during sampling. As a result, the area overhead according to this embodiment can be suppressed to 7%, and the area of the AD converter is reduced to about half the size as compared with the case where a high-precision capacitance value is used without calibration. NS.

In the sequential comparison type AD converter configured as described above, the sequential comparison control unit 20A follows the sample hold period (SH) and then the sequential comparison period ( _{DN-1 to} D) according to the control circuit state signal of FIG. 3B. _{In 0 ), the input voltage V IN} is the DA conversion voltage V _DAC by a known dichotomy method from the most significant bit to the least significant bit while sequentially comparing the pair of voltages input to the comparator 3. The switches S1 to SM are sequentially and selectively switched so as to substantially match the above, and the input voltage _VIN is AD-converted and the output data D _OUT of the AD conversion value is controlled to be output. Here, in the next bit _{D N-2} periods phi _N-2 lower than the most significant bit (MSB), based on the random bit _{D R,} a bit inversion operation for the digital signal _{S COMP} the comparison result, the comparator by making changes of 3 to be compared voltage value of the track-voltage V _T, now the behavior of the plurality of internal operation exist for the same data, the leakage of internal data via the external reference voltage terminal T2 Can be prevented.

In the present embodiment, carried out in the next bit D _N-2 periods phi _N-2 lower than the most significant bit (MSB), based on the random bit D _R, a change of the bit inversion operation and the track-voltage V _T However, the present invention is not limited to this, and the bit inversion operation and the follow-up voltage _VT are changed in the _{following one or more bits of the next bit DN-2 lower than the most significant bit (MSB).} You may.

As described above, according to a semiconductor device such as an integrated circuit chip (hereinafter, "integrated circuit" is referred to as "IC") provided with an AD converter according to the present embodiment, a microcomputer IC chip or a discrete IC It is possible to prevent data processed by an AD converter mounted on an IC chip such as a chip from leaking to an external circuit via the external reference voltage terminal T2. In the prior art, the reduction of the input range was unavoidable in order to reduce the correlation between the data and the internal operation, but in the present embodiment, the input range is not reduced at all, so that the performance of the AD converter is not sacrificed. , Data security can be ensured. Therefore, it is possible to provide a secure AD conversion device as compared with the conventional example.

FIG. 8 is a block diagram showing a configuration of an experimental system for evaluating a side channel attack (SCA) via a reference voltage terminal on an AD converter according to an embodiment. The secure successive approximation AD converter 62 according to the present embodiment is prototyped with a sampling frequency of 1 MHz and a resolution of 10 bits, and as shown in FIG. 8, a signal is input from an arbitrary waveform signal generator (AWG) 61. NS. The reference voltage V _REF is supplied from an external power supply via a 1 ohm shunt resistor 64 and the reference voltage waveform is monitored by the oscilloscope 66 using the differential probe circuit 65.

In FIG. 8, a template attack is adopted to obtain the correlation between the input data and the reference voltage V _REF waveform (see, for example, Non-Patent Document 3). First, 64 input voltages having linear steps V _{Y0 to} V _Y63 are applied from the arbitrary waveform signal generator 61 to the successive approximation type AD converter 62, and the voltage waveform of _{each reference voltage ΔV REF is a template Y 0 to Y 63.} Is stored in a predetermined storage device. Next, the online signal V _X is input, and the correlation coefficient ρ (X, Y _N ) between the voltage waveform X of the reference voltage ΔV _REF and all 64 template signals Y _N is calculated using the following equation. Calculated.

Here, the covariance of the voltage waveform X and the template signal Y _{N is σ X and YN} , and the standard deviations are σ _X and σ _YN . Based on the calculated result of the correlation coefficient ρ (X, Y _N ), the index number of the template signal Y _{N with} the highest correlation is regarded as leaked data.

FIG. 9A is a diagram showing the time waveform of the output code in the non-protected state, which is the leaked data obtained by the experimental system of FIG. 8 by using the template matching method for the conventional successive approximation type AD converter. be. Further, FIG. 9B is a spectrum diagram showing a power spectrum of leaked data in the non-protected state of FIG. 9A. That is, FIGS. 9A and 9B show the experimental results of a reference voltage side channel attack (SCA) using the template matching method.

_{In FIG. 9A, the output waveforms of the leaked data D LEAK} and the AD converter output data D _OUT restored with respect to the input sine wave of 27 kHz are plotted on the graph. FIG. 9B shows the FFT spectra of the output waveforms of the leaked data D _LEAK and the AD converter output data D _OUT. Here, in the case of the sequential comparison type AD converter of the conventional example to which the dithering process proposed in the present embodiment is not applied, the effective number of bits of 4.6 bits (hereinafter referred to as "ENOB"). Is extracted, which indicates that most of the analog information is leaked.

FIG. 10A is a diagram showing the time waveform of the output code at the time of protection, which is the leaked data obtained by the experimental system of FIG. 80 using the template matching method, and FIG. 10B is the measurement at the time of protection of FIG. 10A. It is a spectrum diagram which shows the power spectrum of the leaked data. Data leakage from the successive approximation AD converter according to the protected embodiment is suppressed to 0.8-bit ENOB. The reason is that the dithering process according to the proposed embodiment induces a peak correlation to be obtained with an invalid code of the template. From the evaluation result, the successive approximation type AD converter according to the embodiment can protect 90% or more of analog information.

11A is a spectrum diagram showing the power spectrum of the experimental system of FIG. 8 without calibration, and FIG. 11B is a spectrum diagram showing the power spectrum of the experimental system of FIG. 8 with calibration. FIG. 12 is a graph showing the calibration effect of the power spectrum in the experimental system of FIG. Further, FIG. 13 is an experimental result obtained by the experimental system of FIG. 8 and is a table showing each performance value at the time of protection and at the time of non-protection.

As is clear from FIG. 11A, without calibration, the signal-to-noise ratio (Signal-to-noise and distortion ratio; hereinafter referred to as “SNDR”) is a small area, low precision dither tracking DA converter ("SNDR"). It drops to 43.8 dB due to the mismatch of the capacitors in the follow-up voltage generation circuit 13). However, as is clear from FIG. 11B, with calibration, it is improved to 10 dB or more, and the SNDR reaches 54.4 dB for an input signal of 30 kHz. As is clear from FIG. 12, in the proposed embodiment, the total power consumption is 65 μW, including the power overhead of 1.4 μW. As is clear from FIG. 13, the security enhancement technique according to the proposed embodiment achieves leakage suppression from 4.6 bits to 0.8 bits with speed, power, and area overhead of less than 10%.

As described above, according to the experimental results of the present embodiment, in the measurement of the successive approximation type AD converter having a speed of 1 MS / s, the resolution is 10 bits, the speed is reduced by only 8%, the power is increased by 2%, and 7 It demonstrates the suppression of information leakage from 4.6 bits to 0.8 bits with the overhead of increasing the area by%.

As described in detail above, according to the present embodiment, the data processed by the sequential comparison type AD converter mounted on the microcomputer IC chip or the discrete IC chip leaks to the outside via the reference voltage terminal. Can be prevented. In the prior art, reduction of the input range was unavoidable in order to reduce the correlation between the data and the internal operation, but in the present embodiment, the input range is not reduced at all, so that the performance of the sequential comparison type AD converter is sacrificed. Data security can be ensured without any need.

In the above embodiment, the input analog voltage _VIN is AD-converted to digital data, but the present invention is not limited to this, and the analog signal may be AD-converted to digital data.

In the above embodiments, the random bit generation circuit 11 in FIG. 5A, the redundant timing control signal phi _R, but to generate a random bit D _R on the basis of the digital signal S _COMP the comparison result, the present invention is is not limited to this, compared without using the digital signal S _COMP results, using a known pseudo-random signal generator, may generate a predetermined random bit when the redundant timing control signal phi _R.

As described in detail above, according to the sequential comparison type AD conversion device according to the present invention, it is possible to provide a sequential comparison type AD conversion device that is more secure than the conventional example. Since the secure AD converter is effective for data protection in a system using an AD converter such as a sensor system, it is utilized for a secure hardware construction business by the Electronic Commerce Safety Technology Research Association (ECSEC) and related companies. can.

1 Switch 2, 2A Capacitive DA converter 3 Comparator 4 Serial parallel converter (SP converter)
10,10A Control circuit 11 Random bit generation circuit 11m Delay type flip-flop 12-bit inversion circuit 12e Exclusive logical sum gate 12m Delay type flip-flop 13 Follow-up voltage generation circuit 13s Selector 20, 20A Sequential comparison control unit 30 IoT sensor node circuit 31 Sensor 32 Sensor signal processing IC
33 RF signal processing IC
34 Antenna 35 Signal amplifier 36, 36A Sequential comparison type AD converter 37 Microcomputer unit (MCU)
38 Encryption circuit 56 Calibration circuit 61 Arbitrary waveform signal generator 62 Sequential comparison AD converter 63 DC power supply 64 Resistance 65 Differential probe circuit 66 Oscilloscope C0 to CM, C11 to C32 Capacitor S0 to S32 Switch T1 to T14 terminal

Claims (4)

A DA converter that samples and holds the input analog signal and DA-converts the digital data after sampling and holding into an analog signal.
A comparator that compares the analog signal from the DA converter with a predetermined threshold value and outputs a comparison result signal,
It is provided with a sequential comparison control unit that controls the DA converter so as to AD-convert the input analog signal into digital data sequentially from the most significant bit to the least significant bit by a dichotomy method.
A successive approximation type AD conversion device that AD-converts the input analog signal into digital data.
A random bit generation circuit that generates random bits, and
An inverting bit inverting circuit that inverts the comparison result signal for at least one bit below the most significant bit based on the random bit to generate an inverting bit.
Based on the random bit and the inverting bit, a predetermined dither voltage is changed from a predetermined comparison threshold value in the period indicated by the inverting bit so that the same comparison result signal can be obtained regardless of the presence or absence of the inverting. A sequential comparison type AD converter including a follow-up voltage generating circuit that generates a follow-up voltage, which is a threshold value for the comparator, and outputs the follow-up voltage to the comparator. The sequential comparison type AD conversion device according to claim 1, wherein the random bit generation circuit generates random bits after sequential comparison of the least significant bits based on the comparison result signal. A semiconductor device including the sequential comparison type AD conversion device according to claim 1 or 2. An electronic device including the semiconductor device according to claim 3.

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