JP6949178B2 - Memory system - Google Patents

Description

Embodiments of the present invention relate to memory systems.

In a 3-bit / Cell NAND memory that has been miniaturized in recent years, in general, in order to avoid mutual interference between cells, all bits to be stored in the first memory cell are written at the same time, and then all bits are similarly written to adjacent cells. Are written at the same time, and then all Bits are rewritten (programmed) to the first memory cell again. However, when this method is used, it is necessary to retain the data on the controller side for rewriting.

1-3-3 coding is known as a method of programming all bits at the same time. This method is a coding in which 7 pieces between 8 threshold voltage regions of 3 bits / Cell are distributed to 1, 3 and 3 bits, respectively.

However, the NAND memory in recent years has been made three-dimensional, and the amount of write buffer required has increased, so that the cost of the memory controller has increased. Therefore, even in a three-dimensional non-volatile memory, it is desired to take measures to reduce the amount of write buffer of the memory controller while suppressing mutual interference between cells and bias of the bit error rate between pages.

Japanese Unexamined Patent Publication No. 2015-19571 U.S. Pat. No. 9230664

An object to be solved by the present invention is to provide a memory system capable of reducing the amount of write buffer of a memory controller while suppressing mutual interference between cells.

According to embodiments, a memory system is provided. The memory system includes a non-volatile memory having a plurality of memory cells and a memory controller. Each of the plurality of memory cells has a first threshold area indicating an erased state in which data has been erased, and a write state in which data is written at a voltage level higher than that of the first threshold area. It is a threshold region including the second to eighth threshold regions shown, and the nth threshold region has a higher voltage level than the (n-1) threshold region (n-1). n is a natural number of 2 or more and 8 or less) It is possible to store 3-bit data represented by the first to third bits by eight threshold areas. The memory controller includes a buffer, transmits a command for a first program specifying the data of the first bit stored in the buffer to the non-volatile memory, and after transmitting the command for the first program, sends the command to the buffer. It is configured to delete the stored data of the first bit and send a command for a second program specifying the data of the second bit and the third bit stored in the buffer to the non-volatile memory. NS. In the non-volatile memory, in response to the transmitted first program command, the threshold area in the memory cell is in an erased state in which the data is erased according to the data of the designated first bit. One of the thresholds of the ninth threshold region shown and the tenth threshold region indicating a writing state in which data is written with a higher voltage level than the ninth threshold region. The first program is executed on the memory cell so as to be an area. The non-volatile memory reads the data of the first bit from the memory cell in which the first program is executed in response to the transmitted command for the second program, and receives the read data of the first bit and the data of the first bit. From the ninth threshold area to any of the first to fourth threshold areas, based on the designated second and third bit data. A second program is executed on the memory cell so as to change from the tenth threshold area to any one of the fifth to eighth threshold areas. It is provided with a control unit to be operated. Of the first to seventh boundaries existing between adjacent threshold areas in the first to eighth threshold areas, the number of boundaries used for determining the value of the data of the first bit is 1, the number of boundary used for determination of the second bit of the data value is 3, the number of boundary used for determination of the third-bit data values are three der, the control unit Reads the data of the first bit a plurality of times from the memory cell in which the first program is executed in the second program, and obtains the result of a majority decision regarding the read result of the read first bit data. We want to use as.

FIG. 1 is a block diagram showing a configuration example of a storage device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the non-volatile memory of the first embodiment. FIG. 3 is a diagram showing a configuration example of a block of a memory cell array having a three-dimensional structure. FIG. 4 is a cross-sectional view of a part of a memory cell array of a NAND memory having a three-dimensional structure. FIG. 5 is a diagram showing an example of a threshold value region of the first embodiment. FIG. 6 is a diagram showing data coding of the first embodiment. FIG. 7 is a diagram showing the threshold distribution after the program in the first embodiment. FIG. 8A is a diagram showing a first example of the program sequence of the first embodiment. FIG. 8B is a diagram showing a second example of the program sequence of the first embodiment. FIG. 8C is a diagram showing a third example of the program sequence of the first embodiment. FIG. 9A is a flowchart showing an example of a writing procedure for the entire block according to the first embodiment. FIG. 9B is a sub-flow chart showing a writing procedure in the 1st stage according to the first embodiment. FIG. 9C is a sub-flow chart showing a writing procedure in the 2nd stage according to the first embodiment. FIG. 9D is a sub-flow chart showing a modified example of the writing procedure in the 2nd stage according to the first embodiment. FIG. 9E is a diagram for explaining a majority decision process of the reading result of a plurality of times. FIG. 10A is a diagram for explaining the amount of buffer data in the LM-Foggy-Fine program that employs 1-3-3 coding. FIG. 10B is a diagram for explaining the amount of buffer data in the program of the first embodiment. FIG. 11 is a diagram showing an example of a sequence of external program commands according to the first embodiment. FIG. 12A is a flowchart showing a processing procedure of reading a page with a word line in which the program is completed up to the 1st stage in the storage device according to the first embodiment. FIG. 12B is a flowchart showing a procedure for reading a page on a word line in which the program is completed up to the 2nd stage in the storage device according to the first embodiment. FIG. 13 is a diagram showing an example of a sequence of external read commands according to the first embodiment. FIG. 14A is a flowchart showing a writing procedure for the entire block according to the second embodiment. FIG. 14B is a sub-flow chart showing a writing procedure in the 1st stage and the 2nd stage according to the second embodiment. FIG. 15 is a diagram showing an example of a sequence of external program commands according to the second embodiment. FIG. 16 is a diagram for explaining data corruption caused by power interruption. FIG. 17 is a diagram for explaining a program of the 2nd stage according to the third embodiment. FIG. 18 is a flowchart showing a writing procedure in the 2nd stage according to the third embodiment. FIG. 19 is a diagram for explaining a program modification example of the 2nd stage according to the third embodiment. FIG. 20 is a diagram showing another example of 1-3-3 data coding. FIG. 21 is a diagram showing the threshold distribution after the program in the fourth embodiment. FIG. 22A is a sub-flow chart showing a writing procedure in the 1st stage according to the fourth embodiment. FIG. 22B is a sub-flow chart showing a writing procedure in the 2nd stage according to the fourth embodiment. FIG. 22C is a sub-flow chart showing a modified example of the writing procedure in the 2nd stage according to the fourth embodiment. FIG. 23 is a diagram showing an example of a sequence of external program commands according to the fourth embodiment. FIG. 24A is a flowchart showing a processing procedure of reading a page with a word line in which the program is completed up to the 1st stage in the storage device according to the fourth embodiment. FIG. 24B is a flowchart showing a processing procedure of reading a page with a word line in which the program is completed up to the 2nd stage in the storage device according to the fourth embodiment. FIG. 25 is a diagram showing an example of a sequence of external read commands according to the fourth embodiment. FIG. 26 is a diagram for explaining the configuration of the flag cell. FIG. 27A is a diagram for explaining a program for the flag cell according to the fifth embodiment. FIG. 27B is a diagram for explaining a program for a dummy cell according to a fifth embodiment. FIG. 28 is a flowchart showing a writing procedure in the 2nd stage according to the fifth embodiment. FIG. 29 is a flowchart showing a page reading processing procedure according to the fifth embodiment. FIG. 30 is a diagram showing an example of a sequence of external read commands according to the fifth embodiment. FIG. 31 is a diagram showing an example of the threshold value region of the sixth embodiment. FIG. 32 is a diagram of a first example showing the threshold distribution after the program in the sixth embodiment. FIG. 33 is a diagram showing data coding corresponding to the threshold distribution shown in FIG. FIG. 34 is a diagram of a second example showing the post-programmed threshold distribution in the sixth embodiment. FIG. 35 is a diagram showing data coding corresponding to the threshold distribution shown in FIG. 34. FIG. 36 is a diagram of a third example showing the threshold distribution after the program in the sixth embodiment. FIG. 37 is a diagram showing data coding corresponding to the threshold distribution shown in FIG.

The memory system and the writing method according to the embodiment will be described in detail with reference to the accompanying drawings. The present invention is not limited to these embodiments.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of a storage device according to the first embodiment. The storage device of this embodiment includes a memory controller 1 and a non-volatile memory 2. The storage device can be connected to the host. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

The non-volatile memory 2 is a memory that stores data non-volatilely, and includes, for example, a NAND memory (NAND flash memory). In the present embodiment, the non-volatile memory 2 will be described as a NAND memory having a memory cell capable of storing 3 bits per memory cell, that is, a NAND memory of 3 bits / Cell (TLC: Triple Level Cell). The non-volatile memory 2 is three-dimensional.

The memory controller 1 controls writing of data to the non-volatile memory 2 according to a write command from the host. Further, the memory controller 1 controls reading of data from the non-volatile memory 2 according to a reading command from the host. The memory controller 1 includes a RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to each other by an internal bus 16.

The host interface 13 outputs commands, user data (write data), and the like received from the host to the internal bus 16. Further, the host interface 13 transmits the user data read from the non-volatile memory 2, the response from the processor 12, and the like to the host.

The memory interface 15 controls a process of writing user data and the like to the non-volatile memory 2 and a process of reading from the non-volatile memory 2 based on the instruction of the processor 12.

The processor 12 controls the memory controller 1 in an integrated manner. The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When the processor 12 receives a command from the host via the host interface 13, the processor 12 controls according to the command. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the non-volatile memory 2 according to a command from the host. Further, the processor 12 instructs the memory interface 15 to read the user data and the parity from the non-volatile memory 2 according to the command from the host.

The processor 12 determines a storage area (memory area) on the non-volatile memory 2 with respect to the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for the page-based data (page data), which is the writing unit. In this specification, user data stored in one page of the non-volatile memory 2 is defined as unit data. The unit data is generally encoded and stored in the non-volatile memory 2 as a code word. In this embodiment, coding is not essential. The memory controller 1 may store the unit data in the non-volatile memory 2 without encoding, but FIG. 1 shows a configuration in which encoding is performed as a configuration example. If the memory controller 1 does not encode, the page data matches the unit data. Further, one codeword may be generated based on one unit data, or one codeword may be generated based on the divided data in which the unit data is divided. Further, one codeword may be generated using a plurality of unit data.

The processor 12 determines the memory area of the non-volatile memory 2 to be written for each unit data. A physical address is assigned to the memory area of the non-volatile memory 2. The processor 12 manages the memory area to which the unit data is written by using the physical address. The processor 12 specifies the determined memory area (physical address) and instructs the memory interface 15 to write the user data to the non-volatile memory 2. The processor 12 manages the correspondence between the logical address (logical address managed by the host) of the user data and the physical address. When the processor 12 receives a read command including a logical address from the host, the processor 12 identifies the physical address corresponding to the logical address, specifies the physical address, and instructs the memory interface 15 to read the user data.

In the present specification, a memory cell commonly connected to one word line is defined as a memory cell group MG. In the present embodiment, the non-volatile memory 2 is a 3 bit / Cell NAND memory, and one memory cell group MG corresponds to 3 pages. Each 3 bits of each memory cell corresponds to these 3 pages. In the present embodiment, these three pages are referred to as a Lower page (first page), a Middle page (second page), and an Upper page (third page).

The ECC circuit 14 encodes the user data stored in the RAM 11 to generate a code word. Further, the ECC circuit 14 decodes the code word read from the non-volatile memory 2.

The RAM 11 temporarily stores the user data received from the host until it is stored in the non-volatile memory 2, or temporarily stores the data read from the non-volatile memory 2 until it is transmitted to the host. The RAM 11 is, for example, a general-purpose memory such as a SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

FIG. 1 shows a configuration example in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15, respectively. However, the ECC circuit 14 may be built into the memory interface 15. Further, the ECC circuit 14 may be built in the non-volatile memory 2.

When a write request is received from the host, the storage device (memory system) operates as follows. The processor 12 temporarily stores the write data in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

When a read request is received from the host, the storage device operates as follows. The memory interface 15 inputs the code word read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13. In the non-volatile memory 2, a plurality of chips may be connected, and the non-volatile memory 2 and the memory interface 15 can be connected by a through via (TSV).

FIG. 2 is a block diagram showing a configuration example of the non-volatile memory of the present embodiment. The non-volatile memory 2 includes a NAND I / O interface 21, a control unit 22, a NAND memory cell array (memory cell unit) 23, and a page buffer 24. The non-volatile memory 2 is composed of, for example, a one-chip semiconductor substrate (for example, a silicon substrate).

The control unit 22 controls the operation of the non-volatile memory 2 based on a command or the like input from the memory controller 1 via the NAND I / O interface 21. Specifically, when a write request is input, the control unit 22 controls to write the requested data to a designated address on the NAND memory cell array 23. Further, when a read request is input, the control unit 22 controls to read the requested data from the NAND memory cell array 23 and output it to the memory controller 1 via the NAND I / O interface 21. The page buffer 24 is a buffer that temporarily stores the data input from the memory controller 1 at the time of writing to the NAND memory cell array 23, and temporarily stores the data read from the NAND memory cell array 23.

FIG. 3 is a diagram showing a configuration example of a block of a memory cell array having a three-dimensional structure. FIG. 3 shows one block BLK among a plurality of blocks constituting a memory cell array having a three-dimensional structure. Other blocks of the memory cell array also have the same configuration as in FIG. The present embodiment can also be applied to a memory cell having a two-dimensional structure.

As shown, the block BLK includes, for example, four finger FNGs (FNG0 to FNG3). Further, each finger FNG includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. The number of memory cell transistors MT is not limited to eight. The memory cell transistor MT is arranged so that its current path is connected in series between the selection transistors ST1 and ST2. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2. It is connected.

The gates of the selection transistors ST1 of the fingers FNG0 to FNG3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same select gate line SGS among the plurality of finger FNGs. Further, the control gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. That is, the word lines WL0 to WL7 and the select gate line SGS are commonly connected between the plurality of fingers FNG0 to FNG3 in the same block BLK, whereas the select gate line SGD is in the same block BLK. Is also independent for each finger FNG0 to FNG3.

Word lines WL0 to WL7 are connected to the control gate electrodes of the memory cell transistors MT0 to MT7 constituting the NAND string NS, and between the memory cell transistors MTi (i = 0 to n) in each NAND string NS. Are commonly connected by the same word line WLi (i = 0 to n). That is, the control gate electrodes of the memory cell transistors MTi in the same row in the block BLK are connected to the same word line WLi. In the following description, the NAND string NS may be referred to as a string.

Each memory cell is connected to the word line WLi and also to the bit line. Each memory cell can be identified by an address that identifies the word line WLi and the select gate lines SGD0 to SGD3 and an address that identifies the bit line. As described above, the data of the memory cells (memory cell transistor MT) in the same block BLK are collectively erased. On the other hand, reading and writing of data is performed in units of physical sector MS. One physical sector MS includes a plurality of memory cells connected to one word line WLi and belonging to one finger FNG.

During the read operation and the program operation, one word line WLi and one select gate line SGD are selected according to the physical address, and the physical sector MS is selected.

FIG. 4 is a cross-sectional view of a part of a memory cell array of a NAND memory having a three-dimensional structure. As shown in FIG. 4, a plurality of NAND strings NS are formed on the p-type well region (P-well). That is, on the p-type well region, a plurality of wiring layers 333 functioning as the select gate line SGS, a plurality of wiring layers 332 functioning as the word line WLi, and a plurality of wiring layers 331 functioning as the select gate line SGD are formed. Has been done.

Then, a memory hole 334 that penetrates these wiring layers 333, 332 and 331 and reaches the p-type well region is formed. A block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side surface of the memory hole 334, and a conductive film 338 is further embedded in the memory hole 334. The conductive film 338 functions as a current path for the NAND string NS, and is a region in which channels are formed during the operation of the memory cell transistors MT and the selection transistors ST1 and ST2.

In each NAND string NS, the selection transistor ST2, the plurality of memory cell transistors MT, and the selection transistor ST1 are sequentially stacked on the p-type well region. A wiring layer that functions as a bit wire BL is formed at the upper end of the conductive film 338.

Further, an n + type impurity diffusion layer and a p + type impurity diffusion layer are formed on the surface of the p-type well region. A contact plug 340 is formed on the n + type impurity diffusion layer, and a wiring layer that functions as a source line SL is formed on the contact plug 340. Further, a contact plug 339 is formed on the p + type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 339.

A plurality of the configurations shown in FIG. 4 are arranged in the depth direction of the paper surface of FIG. 4, and one finger FNG is formed by a set of a plurality of NAND strings arranged in a row in the depth direction.

FIG. 5 is a diagram showing an example of a threshold value region of the first embodiment. FIG. 5 shows an example of a threshold distribution of a 3-bit / Cell non-volatile memory 2. In the non-volatile memory 2, information is stored by the amount of electric charge stored in the floating gate of the memory cell. Each memory cell has a threshold voltage according to the amount of charge. Then, the plurality of data values stored in the memory cell are made to correspond to the plurality of areas (threshold area) of the threshold voltage.

The eight distributions (mountain-shaped) described as Er, A, B, C, D, E, F, and G in FIG. 5 indicate the respective threshold distributions within the eight threshold regions. In this way, each memory cell has a threshold distribution partitioned by seven boundaries. The horizontal axis of FIG. 5 shows the threshold voltage, and the vertical axis shows the distribution of the number of memory cells (number of cells).

In the present embodiment, the region where the threshold voltage is Vr1 or less is called region Er, the region where the threshold voltage is larger than Vr1 and Vr2 or less is called region A, and the threshold voltage is larger than Vr2 and Vr3 or less. The region where the threshold voltage is greater than Vr3 and Vr4 or less is referred to as region C. Further, in the present embodiment, the region where the threshold voltage is larger than Vr4 and Vr5 or less is called region D, and the region where the threshold voltage is larger than Vr5 and Vr6 or less is called region E, and the threshold voltage is called region E. The region larger than Vr6 and equal to or lower than Vr7 is called a region F, and the region where the threshold voltage is larger than Vr7 is called a region G.

Further, the threshold distributions corresponding to the regions Er, A, B, C, D, E, F, and G are distributed, respectively, Er, A, B, C, D, E, F, and G (1st to 8th). Distribution). Vr1 to Vr7 are threshold voltages that serve as boundaries between regions.

In the non-volatile memory 2, a plurality of data values are associated with each of a plurality of threshold areas (that is, threshold distributions) of the memory cell. This correspondence is called data coding. This data coding is defined in advance, and at the time of writing (programming) data, the charge is injected into the memory cell so as to be within the threshold area corresponding to the data value to be stored according to the data coding. Then, at the time of reading, a reading voltage is applied to the memory cell, and the data is determined depending on whether the threshold value of the memory cell is lower or higher than the reading voltage. When the threshold voltage is lower than the read voltage, the data value in the "erased" state is defined as "1". If the threshold voltage is greater than or equal to the read voltage, it is in the "programmed" state and the data is defined as "0".

When reading data, the data is determined by whether the threshold value is lower or higher than the read level of the boundary to be read. When the threshold value is the lowest, it is in the "erased" state, and the data of all bits is defined as "1". If the threshold is higher than the "erased" state, it is in the "programmed" state and the data is defined as "1" or "0" according to the coding.

FIG. 6 is a diagram showing data coding of the first embodiment. In the present embodiment, the eight threshold distributions (threshold regions) shown in FIG. 5 correspond to the eight data values of 3 bits, respectively. The relationship between the threshold voltage and the data values of the bits corresponding to the Upper, Middle, and Lower pages is as shown below.
-The memory cell whose threshold voltage is in the Er region is in a state of storing "111".
A memory cell whose threshold voltage is in the A region is in a state of storing "101".
-The memory cell whose threshold voltage is in the B region is in a state of storing "001".
-The memory cell whose threshold voltage is in the C region is in a state of storing "011".
-The memory cell whose threshold voltage is in the D region is in a state of storing "010".
-The memory cell whose threshold voltage is in the E region is in a state of storing "110".
A memory cell whose threshold voltage is in the F region is in a state of storing "100".
-The memory cell whose threshold voltage is in the G region is in a state of storing "000".

In this way, the state of 3-bit data of each memory cell can be represented for each area of the threshold voltage. When the memory cell is in an unwritten state (“erased” state), the threshold voltage of the memory cell is within the Er region. Further, in the code shown here, only 1 bit is stored between any two adjacent states, such as storing the data "111" in the Er (erasing) state and storing the data "101" in the A state. The data changes. As described above, the coding shown in FIG. 6 is a Gray code in which the data changes by only 1 bit between any two adjacent regions.

In the coding of the present embodiment shown in FIG. 6, the threshold voltage serving as a boundary for determining the bit value of each page is as shown below.
-The threshold voltage that serves as the boundary for determining the bit value on the Lower page is Vr4.
-The threshold voltages that serve as boundaries for determining the bit value on the Middle page are Vr2, Vr5, and Vr7.
-The threshold voltages that serve as boundaries for determining the bit value on the Upper page are Vr1, Vr3, and Vr6.

In this way, the number of threshold voltages serving as boundaries for determining the bit value (hereinafter referred to as the number of boundaries) is 1, 3, and 3, respectively, on the Lower page, Middle page, and Upper page. Hereinafter, such coding is referred to as 1-3-3 coding using the number of boundaries of each of the Lower page, Middle page, and Upper page. What should be noted here is that the maximum number of adjacent data and changing boundaries for each page is 3. The fact that the maximum number of boundaries is 3 means that when eight states are represented by 3 bits, the maximum number of boundaries is the minimum and the bias of bit error is reduced.

The control unit 22 of the non-volatile memory 2 controls the programming to the NAND memory cell array 23 and the reading from the NAND memory cell array 23 based on the coding shown in FIG.

The size of the three-dimensional memory cell is larger than that of the two-dimensional NAND memory of the generation that has been miniaturized in recent years, and the mutual interference between cells is small. In this case, generally, a method of programming all bits at the same time (if each bit is assigned to a different page, all pages are programmed at the same time) is adopted.

When programming all bits at the same time, 1-2-4 coding or 2-3-2 coding is used as the data coding. In 1-2-4 coding, when distributing 7 boundaries between 8 threshold distributions to 3 pages, 1 on the Lower page, 2 on the Middle page, 4 on the Upper page, and so on. Boundaries are distributed to. Also, in 2-3-2 coding, when distributing 7 boundaries between 8 threshold distributions to 3 pages, 2 on the Upper page, 3 on the Middle page, and 2 on the Lower page. The boundaries are distributed like this.

However, in the case of 1-2-4 coding, the number of boundaries is remarkably biased on each page, and as a result, the bias of the bit error rate between pages becomes large. This is because most of the causes of bit errors are caused by the threshold shift to the adjacent distribution, and the number of bit errors increases as the page has a large number of boundaries. This leads to the need to enhance the ECC correction capability required to correct page data errors, even if the error rates as memory cells are the same, so the speed of the storage device, It worsens cost and power consumption. The bias in the number of boundaries also causes a bias in the read speed.

Further, in the NAND memory of 3 bit / Cell, the mutual interference between cells is larger than that of the NAND memory of 1 bit / Cell or 2 bit / Cell. For this reason, in the generation of NAND memory that has been miniaturized in recent years, in general, in order to suppress mutual interference between cells, charges are gradually injected into the floating gate of the memory cell by using three or two stages. There is a programming method (LM-Foggy-Fine program or Foggy-Fine program). In this LM-Foggy-Fine program, after writing the first stage (LM stage), the adjacent cell is written, the cell returns to the previous cell, the second stage (Foggy stage) is written, and then further. The writing is performed in the adjacent cell again, and then the memory cell is returned to the previous memory cell, and the writing is performed by the three program stages of the third stage (Fine stage).

In the Foggy-Fine program, after writing the first stage (Foggy stage), the adjacent cell is written, and then the memory cell is returned to and the second stage (Fine stage) is used for the two program stages. Writing is performed. Each program stage in this case is an execution unit of the program, and the one-word line WLi program is completed by executing three program stages.

In the program of the LM stage, which is the first stage, the input data may be only Lower page data. In the second stage, the Foggy stage program, the program is executed using eight threshold distributions. The threshold distribution (threshold region) at this time has a wider width than the threshold distribution in the final data coding. That is, Foggy writing is performed on the Foggy stage. This Foggy stage program requires all three pages of input data. The post-programmed threshold distribution of the Foggy stage is an intermediate state in which adjacent distributions overlap each other, so data cannot be read. In the third stage, the Fine stage program, the post-programmed threshold distribution of the Foggy stage is moved to the threshold distribution in the final data coding. That is, Fine writing is performed in the Fine stage. This Fine stage program also requires all three pages of input data. Since the threshold distribution after the program of the Fine stage is the final state in which the adjacent distributions are separated, the data can be read after the program of the Fine stage.

In the case of 2-3-2 coding, the number of boundaries is not biased, but in the data input of the LM-Foggy-Fine program, it is necessary to input data for 3 pages at all stages. In addition, when inputting data for the Foggy-Fine program, it is necessary to input data for two pages at every stage. This increases the time required for data input and deteriorates the speed of the storage device. In addition, the buffer amount (write buffer amount) of the write buffer for holding data for inputting to the NAND memory in the storage device is increased. This write buffer is generally allocated a part of the area of the RAM 11 included in the storage device.

As a countermeasure against these, there is a method of executing the LM-Foggy-Fine program by adopting 1-3-3 coding. In this method, since the LM-Foggy-Fine program is adopted, mutual interference between cells can be suppressed. Further, since the input of the LM stage can be data for one page, both the reduction of the write buffer amount and the suppression of the bias of the bit error rate due to the bias of the number of boundaries between each page are achieved at the same time.

However, when the NAND memory of the non-volatile memory 2 has a three-dimensional structure, the amount of write buffer is large even if the LM-Foggy-Fine program or the Foggy-Fine program that employs 1-3-3 coding is applied. As the size increases, the cost of the memory controller 1 increases.

Therefore, in the present embodiment, the storage device adopts 1-3-3 coding for the non-volatile memory 2 having a three-dimensional structure, and further, page-by-page writing is performed in two stages. implement. Thereby, in the present embodiment, even in the non-volatile memory 2 having the three-dimensional structure, the amount of the write buffer of the memory controller 1 is reduced while suppressing the mutual interference between cells and the bias of the bit error rate between each page.

Here, interference between adjacent memory cells will be described. The charge stored in the floating gate of one memory cell disturbs the electric field of the adjacent memory cell, resulting in noise that fluctuates the read threshold of the adjacent memory cell. The program and verification are performed under a certain electric field condition, and after the program is completed, the adjacent memory cells are programmed with different charges, which results in deterioration of read accuracy. This interference between adjacent memory cells becomes more pronounced as the memory device manufacturing technology becomes finer and the memory cell spacing decreases. Then, the interference between adjacent memory cells is largely caused by the adjacent memory cells having different bit lines on the same word line WLi and the adjacent memory cells having different word lines WLi on the same bit line.

Interference between adjacent memory cells can be mitigated by reducing the difference in electric field conditions between adjacent memory cells during programming and verification and when reading after the adjacent memory cells are programmed. Is. One way to reduce interference between adjacent memory cells on the same word line WLi with adjacent memory cells on different bitlines is to divide the program into multiple stages and avoid large changes in charge between each stage. There is a way to run a multi-stage program.

In the program sequence in this embodiment, 3 bits on one word line WLi are programmed by two program stages, that is, the 1st stage and the 2nd stage. Each program stage is an execution unit of the program, and the storage device of the present embodiment completes the program of the word line WLi by executing the two program stages. Further, in the present embodiment, any of 3 bits of pages is assigned to each of the two program stages. Specifically, Lower page data is assigned to the 1st stage program, and Middle page and Upper page data is assigned to the 2nd stage program.

FIG. 7 is a diagram showing the threshold distribution after the program in the first embodiment. FIG. 7 shows the threshold distribution after each program stage for the memory cells. FIG. 7 (T1) shows the threshold distribution of the erased state, which is the initial state before the program. FIG. 7 (T2) shows the threshold distribution after the program of the 1st stage. FIG. 7 (T3) shows the threshold distribution after programming the 2nd stage.

As shown in FIG. 7 (T1), all the memory cells of the NAND memory cell array 23 are in the distributed Er state in the unwritten state (“erased” state). As shown in (T2) of FIG. 7, the control unit 22 of the non-volatile memory 2 keeps the distribution Er for each memory cell according to the bit value to be written (stored) in the Lower page in the program of the 1st stage. Or inject a charge to move it to a distribution above the distribution Er. Specifically, the control unit 22 does not inject an electric charge when the bit value to be written to the Lower page is "1", and injects an electric charge when the bit value to be written to the Lower page is "0". Program to move the threshold voltage to the higher side.

As a result, the memory cell is programmed to the binary level by the Lower page data. It should be noted here that the function in the 1st stage program (first program) is a function of only Lower page data. The page data required for this execution is only the Lower page. Furthermore, since the threshold distribution after the 1st stage program is finally reprogrammed in the later 2nd stage program (second program), there is no need to finely shape the distribution, and a high-speed program can be performed. It is possible. Then, since the data after the program of the 1st stage looks like a binary, the Lower page data can be read. Therefore, the threshold level when programming in the 1st stage is controlled to be between Vr1 and Vr4 in view of allocating the transition to D or higher in the 2nd stage program.

Further, as shown in FIG. 7 (T3), in the 2nd stage program, two pages, a Middle page and an Upper page, are required for writing data. Then, the control unit 22 of the non-volatile memory 2 programs the threshold value distribution after the program of the 2nd stage so that each adjacent distribution becomes an eight-value level in the final state in which the adjacent distributions are separated. In this case, all page data can be read.

It should be noted that the program is typically performed by applying one or more program voltage pulses. After each program voltage pulse, a read is made to see if the memory cell has moved beyond the threshold boundary level. By repeating this application and reading, it becomes possible to move the threshold value of the memory cell within the range of a predetermined threshold value distribution.

The control unit 22 may continuously execute the program of the 1st stage and the program of the 2nd stage for one word line WLi, but in order to reduce the influence of interference between adjacent memory cells, a plurality of control units 22 may be executed. It is also possible to execute the program in a discontinuous order across the word lines WLi.

FIG. 8A is a diagram showing a first example of the program sequence of the first embodiment. FIG. 8B is a diagram showing a second example of the program sequence of the first embodiment. FIG. 8C is a diagram showing a third example of the program sequence of the first embodiment. 8A to 8C show a sequence (a two-stage programming method) in which the influence of interference between adjacent memory cells is reduced. FIG. 8A shows an example of the program order when the string in the block is one NAND memory. Further, FIGS. 8B and 8C show an example of the program order when the strings in the block are four NAND memories.

When writing is started, the control unit 22 advances through each program stage while straddling the word line WLi in a predetermined discontinuous order. That is, two different program stages are not executed consecutively on the same word line WLi.

For example, if the programs of the 1st stage and the 2nd stage are performed on the adjacent word line WLi after the program of the word line WLi is completed up to the 2nd stage, the fluctuation amount of the threshold value becomes large. When the fluctuation amount of the threshold value of the adjacent word line WLi is large, the interference between the adjacent memory cells between the adjacent word line WLi becomes large. Therefore, in order to reduce the interference between adjacent memory cells between the word line WLi, it is effective to reduce the fluctuation amount of the threshold value of the adjacent word line WLi after the program of the word line WLi is completed up to the 2nd stage. .. In such a sequence, the program stage of the adjacent word line WLi is only the 2nd stage after the program of the word line WLi is completed up to the 2nd stage.

In the case of the NAND memory shown in FIG. 8A (when the NAND memory of the non-volatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 receives the following instructions (1) to (1) based on the instruction from the processor 12. The programs are implemented in the order shown in (9). In the following processing, the operation of the program of the control unit 22 is based on the instruction from the processor 12, but the description that it is based on the instruction from the processor 12 is omitted for simplification of the description.

(1) First, the control unit 22 executes the program ST ₁₁ of the 1st stage of the word line WL0.
(2) Next, the control unit 22 executes the program ST ₁ 2 of the 1st stage of the word line WL1.
(3) Next, the control unit 22 executes the program ST ₁₃ of the 2nd stage of the word line WL0.
(4) Next, the control unit 22 performs a program ST ₁ 4 of 1st stage of the word line WL2.
(5) Next, the control unit 22 executes the program ST ₁₅ of the 2nd stage of the word line WL1.
(6) Next, the control unit 22 performs a program ST ₁ 6 of 1st stage of the word line WL3.
(7) Next, the control unit 22 performs a program ST ₁ 7 of 2nd stage of the word line WL2.
(8) Next, the control unit 22 performs a program ST ₁ 8 of 1st stage of the word line WL4.
(9) Next, the control unit 22 performs a program ST ₁ 9 of 2nd stage of the word line WL3.
Similarly, the control unit 22 proceeds with the processing in the order of the arrows pointing diagonally upward to the right in the table shown in FIG. 8A.

In the case of the NAND memory shown in FIG. 8B (when the NAND memory of the non-volatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 executes the programs in the order shown in (11) to (24) below. implement.

(11) First, the control unit 22 executes the program ST ₂ 1 of the 1st stage of the string St0_word line WL0.
(12) Next, the control unit 22 executes the program ST ₂ 2 of the 1st stage of the string St1_word line WL0.
(13) Next, the control unit 22 executes the program ST ₂ 3 of the 1st stage of the string St2_word line WL0.
(14) Next, the control unit 22 executes the program ST ₂ 4 of the 1st stage of the string St3_word line WL0.
(15) Next, the control unit 22 performs a program ST ₂ 5 of 1st stage string St0_ word line WL1.
(16) Next, the control unit 22 performs a program ST ₂ 6 of 2nd stage string St0_ word line WL0.
(17) Next, the control unit 22 performs a program ST ₂ 7 of 1st stage string St1_ word line WL1.
(18) Next, the control unit 22 executes the program ST ₂ 8 of the 2nd stage of the string St1_word line WL0.
(19) Next, the control unit 22 performs a program ST ₂ 9 of 1st stage string St2_ word line WL1.
(20) Next, the control unit 22 executes the program ST ₂ 10 of the 2nd stage of the string St2_word line WL0.
(21) Next, the control unit 22 executes the program ST ₂ 11 of the 1st stage of the string St3_word line WL1.
(22) Next, the control unit 22 executes the program ST ₂ 12 of the 2nd stage of the string St3_word line WL0.
(23) Next, the control unit 22 executes the program ST ₂ 13 of the 1st stage of the string St0_word line WL2.
(24) Next, the control unit 22 executes the program ST ₂ 14 of the 2nd stage of the string St0_word line WL1.
Similarly, the control unit 22 proceeds with the processing in the order of the arrows pointing diagonally upward to the right in the table shown in FIG. 8B. In FIG. 8B, the case where the number of strings in the block is four has been described, but the number of strings in the block may be three or less, or five or more.

In the case of the NAND memory shown in FIG. 8C (when the NAND memory of the non-volatile memory 2 has a three-dimensional structure), when writing is started, the control unit 22 executes the programs in the order shown in (31) to (50) below. implement.

(31) First, the control unit 22 executes the program ST ₃ 1 of the 1st stage of the string St0_word line WL0.
(32) Next, the control unit 22 executes the program ST ₃ 2 of the 1st stage of the string St1_word line WL0.
(33) Next, the control unit 22 executes the program ST ₃ 3 of the 1st stage of the string St2_word line WL0.
(34) Next, the control unit 22 executes the program ST ₃ 4 of the 1st stage of the string St3_word line WL0.
(35) First, the control unit 22 performs a program ST ₃ 5 of 1st stage string St0_ word line WL1.
(36) Next, the control unit 22 performs a program ST ₃ 6 of 1st stage string St1_ word line WL1.
(37) Next, the control unit 22 performs a program ST ₃ 7 of 1st stage string St2_ word line WL1.
(38) Next, the control unit 22 performs a program ST ₃ 8 of 1st stage string St3_ word line WL1.
(39) Next, the control unit 22 performs a program ST ₃ 9 of 2nd stage string St0_ word line WL0.
(40) Next, the control unit 22 executes the program ST ₃ 10 of the 2nd stage of the string St1_word line WL0.
(41) Next, the control unit 22 executes the program ST ₃ 11 of the 2nd stage of the string St2_word line WL0.
(42) Next, the control unit 22 performs a program ST ₃ 12 of 2nd stage string St3_ word line WL0.
(43) Next, the control unit 22 executes the program ST ₃ 13 of the 1st stage of the string St0_word line WL2.
(44) Next, the control unit 22 executes the program ST ₃ 14 of the 1st stage of the string St1_word line WL2.
(45) Next, the control unit 22 executes the program ST ₃ 15 of the 1st stage of the string St2_word line WL2.
(46) Next, the control unit 22 executes the program ST ₃ 16 of the 1st stage of the string St3_word line WL2.
(47) Next, the control unit 22 executes the program ST ₃ 17 of the 2nd stage of the string St0_word line WL1.
(48) Next, the control unit 22 executes the program ST ₃ 18 of the 2nd stage of the string St1_word line WL1.
(49) Next, the control unit 22 executes the program ST ₃ 19 of the 2nd stage of the string St2_word line WL1.
(50) Next, the control unit 22 executes the program ST ₃ 20 of the 2nd stage of the string St3_word line WL1.
In FIG. 8C, the case where the number of strings in the block is four has been described, but the number of strings in the block may be three or less, or five or more.

In this way, even if there are a plurality of strings, the order of the programs of each program stage of the word line WLi in one string is the same as in the case of one string. In the case of a non-volatile memory 2 having a three-dimensional structure in which a plurality of strings exist in a block, a program at a combination position of the word line WLi and the string generally first programs the same word line number in different strings. Then proceed to the next word line number. According to such an order, if FIG. 8A is combined by the number of strings, the order is as shown in FIG. 8B or FIG. 8C, for example.

Here, an example of a writing procedure according to the program order according to the first embodiment will be described with reference to FIGS. 9A to 9C. 9A-9C show the writing procedure when the program order shown in FIG. 8B or FIG. 8C is followed. As described above, since the memory controller 1 advances the program stage while straddling the word line WLi in a discontinuous order, the program is executed with a certain word line WLi group (block in this case) as a group of the program sequence. do.

FIG. 9A is a flowchart showing a first example of a writing procedure for the entire block according to the first embodiment. It is assumed that one block here has n + 1 word lines WLi of word lines WL0 to WLn (n is a natural number). FIG. 9B is a sub-flow chart showing a writing procedure in the 1st stage according to the first embodiment, and FIG. 9C is a sub-flow chart showing a writing procedure in the 2nd stage according to the first embodiment. Note that (1st) shown to the right of each step in FIG. 9A corresponds to the 1st stage shown in FIG. 9B, and (2nd) corresponds to the 2nd stage shown in FIG. 9C.

As shown in FIG. 9A, when writing is started, the control unit 22 executes the program of the 1st stage of the string St0_word line WL0 (step S10). Next, the control unit 22 executes the program of the 1st stage of the string St1_word line WL0 (step S20). After that, the control unit 22 performs the same processing as in steps S10 and S20 for each string. Then, the control unit 22 executes the program of the 1st stage of the string St3_word line WL0 (step S30).

Further, the control unit 22 executes a program of the 1st stage of the string St0_word line WL1 (step S40). Next, the control unit 22 executes a program of the 2nd stage of the string St0_word line WL0 (step S50). Next, the control unit 22 executes the program of the 1st stage of the string St1_word line WL1 (step S60). After that, the control unit 22 repeats the processes of steps S40, S50, and S60 for each word line WLi of each string.

Then, the control unit 22 executes the program of the 1st stage of the string St0_word line WLn (step S70). Next, the control unit 22 executes a program of the 2nd stage of the string St0_word line WLn-1 (step S80). After that, the control unit 22 repeats the processes of steps S70 and S80 for each word line WLi of each string.

Then, the control unit 22 executes the program of the 2nd stage of the string St3_word line WLn-1 (step S90). Next, the control unit 22 executes a program of the 2nd stage of the string St0_word line WLn (step S100). Next, the control unit 22 executes a program of the 2nd stage of the string St1_word line WLn (step S110). After that, the control unit 22 performs the same processing as in steps S100 and S110 for each string. Then, the control unit 22 executes a program of the 2nd stage of the string St3_word line WLn (step S120).

As shown in FIG. 9B, in the 1st stage program, first, the lower page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S210). Then, the Lower page data is input from the memory controller 1 to the non-volatile memory 2 (step S220). Further, a program execution command of the 1st stage is input from the memory controller 1 to the non-volatile memory 2 (step S230), which makes the chip busy (step S240).

When writing data, program voltage pulses are applied one or more times (step S250). Then, data reading is performed to confirm whether or not the memory cell has moved beyond the threshold boundary level (step S260).

Further, it is confirmed whether or not the number of fail bits of the data on the Lower page is smaller than the criteria (determination criterion) (step S270). When the number of fail bits of the data is equal to or greater than the criteria (steps S270, No), the processes of steps S250 to S270 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S270, Yes), the data becomes chip ready (step S280). By repeating application, reading, and confirmation in this way, it is possible to move the threshold value of the memory cell within the range of a predetermined threshold value distribution.

As shown in FIG. 9C, in the 2nd stage program, first, a middle page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S310). Then, the data of the Middle page is input from the memory controller 1 to the non-volatile memory 2 (step S320).

Next, the upper page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S330). Then, the data of the Upper page is input from the memory controller 1 to the non-volatile memory 2 (step S340). Next, the program execution command of the 2nd stage is input from the memory controller 1 to the non-volatile memory 2 (step S350), which makes the chip busy (step S360).

After that, the control unit 22 reads the Lower page data which is the IDL (Internal Data Load) (step S370). Then, based on the Lower page data, the Vth (threshold voltage) of the program destination of the Middle page and the Upper page is determined (step S380). After that, data is written to the Middle page and Upper page using the determined Vth.

Further, the control unit 22 can read a plurality of times in order to improve the reliability of the read data of the IDL, take a majority decision of the read result in the page buffer 24 in the chip, and use it as the next write data. Is. Of course, the control unit 22 can read a plurality of times in a normal read operation, take a majority vote of the read result in the chip, and use it as read data to the outside.

FIG. 9E is a diagram for explaining a majority decision process of the reading result of a plurality of times. In FIG. 9E, the correct bit is indicated by a circle (◯), and the incorrect bit is indicated by a cross mark (x). Further, FIG. 9E shows the result of the majority vote when the reading is performed three times.

In each bit, the result of the majority vote is judged to be erroneous when (a) it is erroneous three times and (b) it is erroneous both times. Assuming that the probability that each bit is wrong is p, when p = 0.2, (a) the probability of making a mistake three times is p × p × p = 0.2 × 0.2 × 0.2, and ( b) The probability of making a mistake twice is (1-p) × p × p = (1-0.2) × 0.2 × 0.2. Therefore, it is (p × p × p) + 3 × (1-p) × p × p = 0.104 that the result of the three majority decisions is determined to be incorrect. In this way, the control unit 22 can improve the reliability of the read data by performing the majority determination process of the read result of a plurality of times in the page buffer 24 in the chip.

When writing data to the Middle page and Upper page, one or more program voltage pulses are applied (step S390). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data reading of the Middle page and Upper page is performed (step S400).

Further, it is confirmed whether or not the number of fail bits of the data on the Middle page and the Upper page is smaller than that of the criteria (step S410). When the number of fail bits of data on the Middle page and Upper page is equal to or greater than the criteria (steps S410, No), the processes of steps S390 to S410 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S410, Yes), the data becomes chip ready (step S420).

Here, a modified example of the writing procedure shown in FIG. 9C will be described. FIG. 9D is a sub-flow chart showing a modified example of the writing procedure in the 2nd stage according to the first embodiment. In the processing procedure shown in FIG. 9D, the processing procedure of steps S310 to S420 is the same as that of FIG. 9C, except that the processing of step S370 described in FIG. 9C is not performed.

In the case of the processing procedure shown in FIG. 9D, the processing of steps S301 to S309 is performed before step S310. Specifically, first, a lower page read command is input from the memory controller 1 to the non-volatile memory 2 (step S301), which makes the chip busy (step S302).

After that, the control unit 22 reads the Lower page data which is the IDL at the threshold voltage of Vr4. Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr4 (step S303). After that, it becomes chip ready (step S304).

When the lower page data read by the control unit 22 is output (step S305), the lower page data is transmitted to the ECC circuit 14 (step S306). As a result, the ECC circuit 14 ECC corrects the Lower page data (step S307).

Then, the lower page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S308). As a result, the ECC circuit 14 inputs the data of the Lower page to the non-volatile memory 2 (step S309).

After that, the processes of steps S310 to S420 are performed. In step S380, the Vth of the program destination of the Middle page and the Upper page is determined based on the Lower page data from the ECC circuit 14.

In the 2nd stage program described above, the data input to the non-volatile memory 2 is only two pages, the Middle page and the Upper page. However, in this 2nd stage, Vth, which is the destination of the memory cell program, requires data for 3 pages including the Lower page (Vth before starting the 2nd stage). Therefore, in the program of this stage, as a preprocessing, the control unit 22 first reads the Lower page data, synthesizes the data with the input Middle page and Upper page, and determines the Vth of the program destination. I do.

The Lower page data can be read because the 1-3-3 coding in which the number of boundaries of the Lower page is 1 is adopted. By reading the Lower page data in the 2nd stage, it is not necessary to input the Lower page data in the 2nd stage. That is, since 1-3-3 coding is adopted and the Vth of the program destination is determined based on the Lower page data, the interference between adjacent memory cells between word lines WLi can be reduced, and one page data can be used once. All you have to do is enter the data.

As a result, when the LM-Foggy-Fine program is executed in 3 stages by adopting 1-3-3 coding, the amount of memory required for the write buffer of the memory controller 1 is a plurality of word lines (up to 7 pages). ), In the present embodiment, the maximum amount of memory required for the write buffer of the memory controller 1 is two pages.

Here, a comparison between the processing procedure of the LM-Foggy-Fine program adopting 1-3-3 coding and the program processing procedure of the present embodiment will be described. FIG. 10A is a diagram for explaining the amount of write buffer data in the LM-Foggy-Fine program that employs 1-3-3 coding.

In FIG. 10A and FIG. 10B described later, a time chart of data input for block writing and program execution is shown on the upper side, and a time chart for a period required to hold data in the write buffer is shown on the lower side. There is. In addition, in FIG. 10A and FIG. 10B described later, the case where the number of strings in one block is 1 is shown for simplification of the description. When there are multiple strings, the amount of memory required is as many as the number of strings.

In the case of 1-3-3 coding LM-Foggy-Fine program, in the first stage, LM stage, one page of data input and this one page of program (LM stage program) are performed. It is said. In the case of the 1-3-3 coding LM-Foggy-Fine program, in the second stage, the Foggy stage, data input for 3 pages and the program for these 3 pages (Foggy stage program) Is done. In the case of the 1-3-3 coding LM-Foggy-Fine program, in the third stage, the Fine stage, data input for three pages and the program for these three pages (Fine stage program) are performed. Is done.

Then, in each word line WL0, WL1, WL2, ..., One page of data written in the LM stage and three pages of data written in the Foggy stage until the program is started in the Fine stage. And must be stored in the write buffer.

Even in the LM-Foggy-Fine program, in order to reduce interference between adjacent memory cells, data for three pages of Lower / Middle / Upper are not written continuously. For example, after the LM stage to the word line WL0 is executed, before the Foggy stage to the word line WL0 is executed, the LM stage to the word line WL1 adjacent to the word line WL0 is executed. Further, after the Foggy stage to the word line WL0 is executed, before the Fine stage to the word line WL0 is executed, the Foggy stage to the word line WL1 adjacent to the word line WL0 is executed. Similarly, after the LM stage to the word line WL1 is executed and before the Foggy stage to the word line WL1 is executed, the LM stage to the word line WL2 adjacent to the word line WL1 is executed. Further, after the Foggy stage to the word line WL1 is executed, before the Fine stage to the word line WL1 is executed, the Foggy stage to the word line WL2 adjacent to the word line WL1 is executed.

As described above, in the LM-Foggy-Fine program, it takes a long time from the LM stage to the Fine stage in each word line WLi. For example, the following stage programs (P1) to (P5) are executed between the LM stage and the Fine stage on the word line WL1.
(P1) LM stage for word line WL2 (P2) Foggy stage for word line WL1 (P3) Fine stage for word line WL0 (P4) LM stage for word line WL3 (P5) Foggy stage for word line WL2

As described above, in the case of the 1-3-3 coding LM-Foggy-Fine program, in the first LM stage, the input data is only the Lower page. However, in the case of this method, it is necessary to retain the data for three pages of Lower / Middle / Upper in the write buffer until the data input of the final third Fine stage is completed. Further, in order to reduce the interference between adjacent memory cells, it is necessary to hold the data in the plurality of word lines WLi in the write buffer. For example, when the Foggy stage is executed for the word line WL2, the data for three pages for the word line WL1, the data for three pages for the word line WL2, and the data for one page for the word line WL3 Must be kept in the write buffer. As described above, in the case of the 1-3-3 coding LM-Foggy-Fine program, it is necessary that the data for up to 7 pages is held in the write buffer.

FIG. 10B is a diagram for explaining a write buffer amount (buffer data amount) in the program of the first embodiment. In the program of this embodiment, a two-stage program is used with 1-3-3 coding. In the program of this embodiment, in the 1st stage, data input for one page (Lower page) and the program for one page (1st program) are performed. Further, in the case of the program of the present embodiment, in the 2nd stage, data input for 2 pages (Middle page and Upper page) and the program for these 2 pages (2nd program) are performed.

Then, in each word line WL0, WL1, WL2, ..., The data may be stored in the write buffer at the time of data input of each stage, and when the program is started, the data is stored in the write buffer. It may be deleted. For example, when data is input in the 1st stage, this data is stored in the write buffer. Then, when the program is started in the 1st stage, the data stored in the write buffer may be deleted. Similarly, when data is input in the 2nd stage, this data is stored in the write buffer. Then, when the program is started in the 2nd stage, the data stored in the write buffer may be deleted.

Also in the program of this embodiment, in order to reduce the interference between adjacent memory cells, the data for three pages of Lower / Middle / Upper are not continuously written. For example, after the 1st stage to the word line WL0 is executed, before the 2nd stage to the word line WL0 is executed, the 1st stage to the word line WL1 adjacent to the word line WL0 is executed. Similarly, after the 1st stage to the word line WL1 is executed, before the 2nd stage to the word line WL1 is executed, the 1st stage to the word line WL2 adjacent to the word line WL1 is executed.

As described above, since the program of the present embodiment has two stages, the processing from the 1st stage to the 2nd stage is short in each word line WLi. For example, the program of the following stages (P11) is executed between the 1st stage and the 2nd stage on the word line WL1.
(P11) 1st stage for word line WL2

Further, in the case of the program of the present embodiment, it is sufficient to hold the data in the write buffer only from the start of the data input to the end of the data input, and when the program is started, the data is deleted from the write buffer. May be done. Therefore, in the case of the program of the present embodiment, the data that needs to be held in the write buffer is at most two pages of data.

As described above, in the present embodiment, all the page data is required only in the program of one stage, so that the data in the write buffer can be discarded once the data input is completed. Therefore, in the present embodiment, the number of pages that need to be held in the write buffer at the same time can be reduced.

The page data programmed into the non-volatile memory 2 is composed of a write buffer in the RAM 11 and is temporarily held, and then the data is input to the non-volatile memory 2 at the time of programming. In the present embodiment, the required capacity of the RAM 11 can be reduced, so that the cost can be reduced.

Also, when the LM-Foggy-Fine program or Foggy-Fine program is used, the data transfer of all page data must be performed twice or three times, which takes a long transfer time and consumes power during transfer. Is also required extra. In the present embodiment, all the page data is completed by one data transfer for each page, so that the transfer time and power consumption can be suppressed to about 1/2 to 1/3.

FIG. 11 is a diagram showing an example of a sequence of external program commands according to the first embodiment. FIG. 11A shows a sequence of external program commands in the 1st stage according to the first embodiment, and FIG. 11B shows a sequence of external program commands in the 2nd stage according to the first embodiment. Shown.

As shown in FIG. 11A, in the 1st stage, after the program start command (80h) is input, the address of the program target block page (Lower page address) is input, and then the program of the Lower page. Data is entered. Finally, when the program execution command (10h) is input, the chip becomes busy and the operation of the program is started inside the memory chip. By inputting such a program command, the Lower page is programmed.

As shown in FIG. 11B, in the 2nd stage, after the program start command (80h) is input, the address of the program target block page (the address of the Middle page) is input, and then the program of the Middle page is input. Data is entered. After that, the concatenation command (1Ah) of the program command is input, and the program data of the Upper page is input this time in the same sequence. Finally, when the program execution command (10h) is input, the chip becomes busy and the operation of the program is started inside the memory chip. By inputting such a program command, the Lower page is read, and the Middle page and Upper page are further programmed. Either the program data on the Middle page or the program data on the Upper page may be input first.

Here, the page reading process will be described. The method of reading the page differs depending on whether the program for the word line WLi including the page to be read is before or after writing the 2nd stage.

Before writing to the 2nd stage, only the Lower page is valid for the recorded data. Therefore, the control unit 22 reads data from the memory cell only when the read page is the Lower page. Then, in the case of other pages, the control unit 22 does not perform the memory cell read operation, but controls to forcibly output all "1" as read data.

On the other hand, in the case of the word line WLi completed up to the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is the Upper / Middle / Lower page. In this case, since the required read voltage differs depending on which page is read, the control unit 22 executes only the required read according to the selected page.

According to the coding shown in FIG. 6, since there is only one boundary between the threshold states in which the Lower page data changes, the control unit 22 sets the threshold value in any of the two ranges separated by the boundary. The data is determined by the location of. For example, when the threshold voltage is smaller than Vr4, the control unit 22 controls to output "1" as the data of the memory cell. On the other hand, when the threshold voltage is larger than Vr4, the control unit 22 controls to output "0" as the data of the memory cell.

Further, since there are three boundaries between the threshold states in which the data on the Middle page or Upper page changes, the control unit 22 positions the threshold value in any of the four ranges separated by those boundaries. Determine the data by doing.

Hereinafter, a specific processing procedure for reading the page will be described. FIG. 12A is a flowchart showing a procedure for reading a page with a word line before writing the 2nd stage in the storage device according to the first embodiment. FIG. 12B is a flowchart showing a procedure for reading a page on a word line in which the program is completed up to the 2nd stage in the storage device according to the first embodiment.

As shown in FIG. 12A, in the case of the word line WLi before writing in the 2nd stage, the control unit 22 selects the read page (step S510). When the read page is the Lower page (step S510, Lower), the control unit 22 reads out at the threshold voltage of Vr4 (step S520). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr4 (step S530).

Further, when the read page is a middle page (step S510, Middle), the control unit 22 controls to forcibly output "1" as the output data of the memory cell (step S540).

When the read page is an Upper page (step S510, Upper), the control unit 22 controls to forcibly output "1" as the output data of the memory cell (step S550).

Further, as shown in FIG. 12B, in the case of the word line WLi whose program has been completed up to the 2nd stage, the control unit 22 selects the read page (step S610). When the read page is the Lower page (step S610, Lower), the control unit 22 reads out at the threshold voltage of Vr4 (step S620). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr4 (step S630).

When the read page is a middle page (step S610, Middle), the control unit 22 reads at the threshold voltages of Vr1, Vr3, and Vr6 (steps S640, S650, S660). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1, Vr3, and Vr6 (step S670).

When the read page is the Upper page (step S610, Upper), the control unit 22 reads at the threshold voltages of Vr2, Vr5, and Vr7 (steps S680, S690, S700). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr2, Vr5, and Vr7 (step S710).

The memory controller 1 can manage and identify whether the program for the word line WLi is before or after the completion of the 2nd stage writing. Since the memory controller 1 controls the program, if the memory controller 1 records the progress status, the memory controller 1 can easily determine which address of the non-volatile memory 2 is in what program state. You can refer to it. In this case, when reading from the non-volatile memory 2, the memory controller 1 identifies what kind of program state the word line WLi including the target page address is in, and issues a read command according to the identified state. ..

FIG. 13 is a diagram showing an example of a sequence of external read commands according to the first embodiment. FIG. 13A shows a sequence of external read commands on the word line WLi in which the program is completed up to the 1st stage in the storage device according to the first embodiment, and FIG. 13B shows the first sequence. The sequence of the external read command on the word line WLi in which the program is completed up to the 2nd stage in the storage device according to the embodiment is shown.

As shown in FIG. 13A, in the case of the word line WLi before writing the 2nd stage, a command (2Dh) indicating the state before writing the 2nd stage is first input as a command to execute the read operation. After that, the read start command (00h) is input, and then the address of the block page to be read (the address of the Lower page, the Middle page, or the Upper page) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation is started inside the memory chip. By inputting such a program command, data is read from the Lower page, Middle page, or Upper page. After that, the chip becomes ready and the read data is output.

On the other hand, as shown in FIG. 13B, in the case of the word line WLi in which the program is completed up to the 2nd stage, a command (25h) indicating the completion state up to the 2nd stage is first input as a command to execute the read operation. Will be done. After that, the read start command (00h) is input, and then the address of the block page to be read (the address of the Lower page, the Middle page, or the Upper page) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation is started inside the memory chip. By inputting such a program command, data is read from the address of the Lower page, Middle page, or Upper page. After that, the chip becomes ready and the read data is output.

As described above, in the first embodiment, when programming the non-volatile memory 2 (3 bit / Cell NAND memory having a 3D structure or a 2D structure), 1-3-3 data coding is adopted and the program is programmed. The stage of is a two-stage system. Since the program is programmed in a two-stage system in this way, the amount of data input during the data program is reduced, and the amount of write buffer required for the memory controller 1 can be suppressed. In addition, the bias of the bit error rate between the pages of the non-volatile memory 2 can be reduced, and the cost of ECC can be reduced. Further, since data transfer is performed only once for each page, transfer time and power consumption can be suppressed.

Further, since each program stage is executed while straddling the word line WLi, the amount of interference between adjacent cells with the adjacent word line WLi can be reduced. Further, since 1-3-3 data coding is used, the IDL margin before the 2nd stage can be expanded, and the reliability of the write sequence can be improved. Further, since 1-3-3 data coding is used, the speed of the 1st stage program, that is, the program of the Lower page can be increased by setting one threshold boundary in the Lower page. The speed of the 1st stage program can be increased by gradually increasing the write voltage when writing and write verification are repeated, and making the step voltage larger than that of the 2nd stage program. Can be done.

(Second Embodiment)
Next, the second embodiment will be described with reference to FIGS. 14A, 14B and 15. In the second embodiment, the program of the 2nd stage of the word line WLn-1 and the program of the 1st stage of the word line WLn are collectively performed. In this embodiment as well, a case where the same data coding as that described with reference to FIG. 6 of the first embodiment is used will be described.

In the flow chart of the program shown in FIG. 9A, the program of the 1st stage and the program of the 2nd stage are all separated by one, and each program command and program data input are performed in each program. .. In this embodiment, the program command and the program data input are summarized as much as possible.

For example, as shown in FIG. 8B, the programs of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 are always continuous except for the beginning and end ends of the block. Therefore, in the present embodiment, this part is collectively referred to as a command input. That is, the program data of the Lower page of the word line WLn and the Middle / Upper page of the word line WLn-1 are collectively input by one command input. Even if LM-Foggy-Fine is adopted, the data of Lower / Middle / Upper pages can be input together with one program command (however, in this case, the pages in the same word line WLi) for 3 pages. It is the same amount of data input as was done.

By summarizing the input of the program command and the program data in this way, the frequency of command input and polling (regular check whether the chip busy has returned to ready) in the control performed by the memory controller 1 is reduced. It is possible to speed up and simplify the storage device.

Here, an example of a writing procedure according to the program order according to the second embodiment will be described with reference to FIGS. 14A and 14B. 14A and 14B show the writing procedure when the program order shown in FIG. 8B is followed. Of the processes shown in FIGS. 14A or 14B, the same processes as those described with reference to FIGS. 9A to 9C will be omitted.

FIG. 14A is a flowchart showing a writing procedure for the entire block according to the second embodiment. It is assumed that one block here has n + 1 word lines WLi of word lines WL0 to WLn (n is a natural number). Further, FIG. 14B is a sub-flow chart showing a writing procedure in the 1st stage and the 2nd stage according to the second embodiment. Note that (1st) shown to the right of each step in FIG. 14A corresponds to the 1st stage shown in FIG. 9B, (2nd) corresponds to the 2nd stage shown in FIG. 9C, and (1 and 2) are shown in FIGS. It corresponds to the 1st stage and the 2nd stage shown in 14B.

As shown in FIG. 14A, when writing is started, the control unit 22 executes the process of steps S810 to S830, which is the same process as steps S10 to S30. As a result, the program of the 1st stage of the word line WL0 of the strings St0 to St3 is executed.

Further, the control unit 22 executes a program of the 1st stage of the string St0_word line WL1 and a program of the 2nd stage of the string St0_word line WL0 (step S840). Next, the control unit 22 executes a program of the 1st stage of the string St1_word line WL1 and a program of the 2nd stage of the string St1_word line WL0 (step S850). Next, the control unit 22 executes a program of the 1st stage of the string St2_word line WL1 and a program of the 2nd stage of the string St2_word line WL0 (step S860). After that, the control unit 22 repeats the processes of steps S840, S850, and S860 for each word line WLi of each string.

Then, the control unit 22 executes the program of the 1st stage of the string St0_word line WLn and the program of the 2nd stage of the string St0_word line WLn-1 (step S870). Next, the control unit 22 executes a program of the 1st stage of the string St1_word line WLn and a program of the 2nd stage of the string St1_word line WLn-1 (step S880). After that, the control unit 22 repeats the processes of steps S870 and S880 for each word line WLi of each string.

Then, the control unit 22 executes the program of the 1st stage of the string St3_word line WLn and the program of the 2nd stage of the string St3_word line WLn-1 (step S890). Next, the control unit 22 executes the processes of steps S900 to S920, which are the same processes as those of steps S100 to S120. As a result, the program of the 2nd stage of the word line WLn of the strings St0 to St3 is executed.

As described above, at the beginning of the block, the program of only the 1st stage is executed as in the first embodiment, and at the end of the block, the program of only the 2nd stage is executed as in the first embodiment. In this case, the program of only the 1st stage is executed according to the procedure shown in FIG. 9B, and the program of only the 2nd stage is executed according to the procedure shown in FIG. 9C.

As shown in FIG. 14B, in the 1st stage and 2nd stage programs, the 1st stage program is executed after the 2nd stage program is executed. Specifically, first, the input start command of the data of the Middle page of the word line WLn-1 is input from the memory controller 1 to the non-volatile memory 2 (step S1010). Then, the data of the middle page of the word line WLn-1 is input from the memory controller 1 to the non-volatile memory 2 (step S1020).

Next, the input start command of the data of the Upper page of the word line WLn-1 is input from the memory controller 1 to the non-volatile memory 2 (step S1030). Then, the data of the Upper page of the word line WLn-1 is input from the memory controller 1 to the non-volatile memory 2 (step S1040).

Next, the input start command of the data of the Lower page of the word line WLn is input from the memory controller 1 to the non-volatile memory 2 (step S1050). Then, the data of the lower page of the word line WLn is input from the memory controller 1 to the non-volatile memory 2 (step S1060).

Next, the program execution commands of the 1st stage and the 2nd stage are input from the memory controller 1 to the non-volatile memory 2 (step S1070), which makes the chip busy (step S1080).

After that, one or a plurality of program voltage pulses are applied to the Lower page of the word line WLn (step S1090). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data reading of the Lower page of the word line WLn is performed (step S1100).

Further, it is confirmed whether or not the number of fail bits of the data on the Lower page is smaller than that of the criteria (step S1110). When the number of fail bits of the data on the Lower page is equal to or greater than the criteria (steps S1110, No), the processes of steps S1140 to S1160 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S1110, Yes), the Lower page data of the word line WLn-1 is read out (step S1120).

Then, the Vth (threshold voltage) of the program destination of the Middle page and the Upper page is determined based on the Lower page data of the word line WLn-1 (step S1130). After that, data is written to the Middle page and Upper page of the word line WLn-1 using the determined Vth.

When writing data to the Middle page and Upper page, one or more program voltage pulses are applied to the Middle page and Upper page of the word line WLn-1 (step S1140). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data reading of the middle page and the upper page of the word line WLn-1 is performed (step S1150).

Further, it is confirmed whether or not the number of fail bits of the data on the Middle page and the Upper page is smaller than that of the criteria (step S1160). When the number of fail bits of data on the Middle page and Upper page is equal to or greater than the criteria (steps S1160, No), the processes of steps S1140 to S1160 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S1160, Yes), the data becomes chip ready (step S1170).

The processing of steps S1010, S1030, and S1050 may be performed first. Further, any of the processes of steps S1020, S1040, and S1060 may be performed first. However, the process of step S1020 is performed after the process of step S1010, the process of step S1040 is performed after the process of step S1030, and the process of step S1060 is performed after the process of step S1050.

The processing of steps S112 to S1160 shown in FIG. 14B corresponds to the program of the 2nd stage of the word line WLn-1, and the processing of steps S109 to S1110 corresponds to the program of the 1st stage of the word line WLn. ing.

As described above, in FIG. 14B, the case where the program of the 1st stage of the word line WLn is executed before the program of the 2nd stage of the word line WLn-1 has been described. This is because the program of the 1st stage of the word line WLn is performed first so that the cell of the word line WLn-1 in which the 8-value Vth is written is not affected by the adjacent cell.

As described above, in the present embodiment, the data of the middle page and the upper page of the word line WLn-1 and the data of the lower page of the word line WLn are continuously input for three pages.

FIG. 15 is a diagram showing an example of a sequence of external program commands according to the second embodiment. The sequence of external program commands in the 1st stage is the same as that shown in FIG. 11A. The sequence of external program commands in the 2nd stage is the same as that shown in FIG. 11B. Therefore, here, a sequence of external program commands when the 2nd stage and the 1st stage are continuously programmed will be described. When the 1st stage and the 2nd stage are programmed consecutively, the 2nd stage command and the 1st stage command are continuously input.

Specifically, as shown in FIG. 15, after the program start command (80h) is input, the address of the program target block page (the address of the middle page of the word line WLn-1) is input, and then the word. The program data of the Middle page of line WLn-1 is input. After that, the concatenation command (1Ah) of the program command is input, and the program data of the Upper page of the word line WLn-1 is input in the same sequence. Then, the concatenation command (1Ah) of the program command is input, and the program data of the Lower page of the word line WLn is input this time in the same sequence. Finally, when the program execution command (10h) is input, the chip becomes busy and the operation of the program is started inside the memory chip.

By inputting such a program command, the Lower page of the word line WLn is programmed. Further, as the IDL, the Lower page data of the word line WLn-1 is read out. Then, the Vth of the program destination of the Middle page and the Upper page is determined based on the Lower page data, and the Middle page and the Upper page of the word line WLn-1 are programmed at the determined Vth.

Further, as another modification, after inputting the program command, the Lower page of the word line WLn-1 is read first as the IDL, then the Lower page of the word line WLn is programmed, and then Middle. The Vth of the program destination of the page and the Upper page is determined, and the middle page and the Upper page of the word line WLn can be programmed with the determined Vth. In this way, the Lower page data of the word line WLn-1 of the IDL can be read out before the interference between adjacent cells due to the writing of the word line WLn is received.

In this embodiment, the actual execution order of the program by the collective command of the 1st stage of the word line WLn and the 2nd stage of the word line WLn-1 can be changed. That is, either the program of the Lower page of the word line WLn shown in FIG. 15 or the reading of the Lower page data of the word line WLn-1 as the IDL may come first and can be exchanged. By performing IDL (reading the Lower page data of the word line WLn-1) before the program of the Lower page of the word line WLn, IDL can be performed without being affected by the program of the Lower page of the word line WLn. Become.

As described above, in the second embodiment, since the program of the 2nd stage of the word line WLn-1 and the program of the 1st stage of the word line WLn are collectively performed, the frequency of command input and polling is reduced. Therefore, the storage device can be speeded up and simplified.

(Third Embodiment)
Next, the third embodiment will be described with reference to FIGS. 16 to 19. In the third embodiment, when the program of the 2nd stage is executed, the program is first executed for the memory cell whose Vth distribution state is planned to be the area D or more, and then the Vth distribution state is set to the area C or less. Run the program on the memory cell you plan to do. In this embodiment as well, a case where the same data coding as that described with reference to FIG. 6 of the first embodiment is used will be described.

In a multi-bit / cell program, if a sudden power failure occurs during program execution, data will be destroyed. In such a case, the information of the program data of the target of the program executed when the power supply is cut off is lost from the memory cell. In such a case, the program may have already been completed, and past program data such as data discarded from the write buffer of the memory controller 1 may be lost. As a result, data recovery becomes impossible.

Such an event occurs when the power is cut off in the middle of the program on the Middle / Upper page of the 2nd stage. This situation will be described. FIG. 16 is a diagram for explaining data corruption caused by power interruption. FIG. 16 (T11) shows the Vth distribution state (data state) after the program of the 1st stage is completed. Further, (T12) in FIG. 16 shows the Vth distribution state during the program of the 2nd stage. Further, FIG. 16 (T13) shows the Vth distribution state after the power is cut off.

After the program of the 1st stage as shown in (T11) of FIG. 16 is completed, the program of the 2nd stage is started, and the Vth distribution state as shown in (T12) of FIG. 16 is obtained. Then, when the power supply is cut off during the Vth distribution state during writing as shown in FIG. 16 (T12), the Vth distribution state as shown in FIG. 16 (T13) is obtained.

Here, consider starting the program of the 2nd stage from the state after the completion of the 1st stage. Generally, inside the NAND memory, programs are executed in order from low Vth to high Vth. Therefore, as shown in FIG. 16 (T12), when the power supply is cut off when the 2nd stage program progresses halfway, the Vth distribution state as shown in FIG. 16 (T13) is obtained.

Here, the memory cells included in the positive distribution are a state in which the memory cells whose Lower page data is “1” and the memory cells whose Lower page data is “0” are mixed. Therefore, even if the Lower page data for which the program has already been completed is read in this state, the correct read data cannot be obtained. Even if the read voltage after the completion of the 2nd stage program is used, correct Lower page data cannot be obtained.

Therefore, in the present embodiment, the Vth order of the program on the Middle / Upper page of the 2nd stage is changed. FIG. 17 is a diagram for explaining a program of the 2nd stage according to the third embodiment. FIG. 17 shows a transition method of the Vth state in the 2nd stage. FIG. 17 (T21) shows the Vth distribution state after the program of the 1st stage is completed. Further, (T22) in FIG. 17 shows the Vth distribution state at the time when the program in the first half of the 2nd stage is completed. Further, (T23) in FIG. 17 shows the Vth distribution state at the time when the program in the latter half of the 2nd stage is completed.

When the 1st stage shown in FIG. 17 (T21) is completed, the control unit 22 of the present embodiment sets a memory cell in which the Vth distribution state of the writing destination becomes the area D or more as shown in FIG. 17 (T22). First, program (D-First program). Then, after completing the program of the Vth distribution state in the regions D to G, the control unit 22 executes the program of the Vth distribution state of the regions A to C as shown in FIG. 17 (T23).

As described above, the control unit 22 of the present embodiment starts the program to the memory cell that causes the Vth distribution state of the writing destination to be the area D or more before the program to the memory cell that causes the area C or less. Then, after completing the program to the memory cell that makes the Vth distribution state of the writing destination in the area D or more, the program in the memory cell that makes the Vth distribution state in the area C or less is completed.

As a result, the timing at which the memory cells whose Lower page data is "1" and the memory cells whose Lower page data is "0" are mixed does not occur. Therefore, even if the power supply is cut off in the 2nd stage, the control unit 22 can read the Lower page data by using the read voltage of either Vr1 or Vr4.

FIG. 18 is a flowchart showing a writing procedure in the 2nd stage according to the third embodiment. The same processing as that described with reference to FIG. 9C will be omitted. The steps S120 to S1280 of the 2nd stage according to the third embodiment are the same as the steps S310 to S380 of the 2nd stage according to the first embodiment shown in FIG. 9C.

After the Vth of the program destination of the Middle page and the Upper page is determined (step S1280), data is written to the Middle page and the Upper page using the determined Vth.

In the 2nd stage according to the third embodiment, when data is written to the Middle page and the Upper page, one or a plurality of program voltage pulses are applied to the memory cells in the areas D to G (step S1290). ). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read out to the areas D to G of the Middle page and the Upper page (step S1300).

Further, it is confirmed whether or not the number of fail bits of the data in the regions D to G on the Middle page and Upper page is smaller than that of the criteria (step S1310). When the number of fail bits of the data in the regions D to G on the Middle page and Upper page is equal to or greater than the criteria (steps S1310 and No), the processes of steps S1290 to S1310 are repeated.

Then, when the number of fail bits of the data in the areas D to G on the Middle page and the Upper page becomes smaller than the criteria (step S1310, Yes), writing to the areas A to C on the Middle page and the Upper page is performed. Specifically, when writing data to the Middle page and Upper page, a program voltage pulse is applied one to a plurality of times to the memory cells in the areas A to C (step S1320). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read out to the areas A to C of the Middle page and the Upper page (step S1330).

Further, it is confirmed whether or not the number of fail bits of the data in the regions A to C on the Middle page and Upper page is smaller than that of the criteria (step S1340). When the number of fail bits of the data in the regions A to C on the Middle page and Upper page is equal to or greater than the criteria (steps S1340 and No), steps S1320 to S1340 are repeated.

Then, when the number of fail bits of the data in the regions A to C on the Middle page and Upper page becomes smaller than the criteria (step S1350, Yes), the data becomes chip ready (step S1350).

In the present embodiment, the program of the Vth distribution state in the regions D to G is completed in the first half of the program of the 2nd stage, but the memory cell in the Vth distribution state in the regions D to G is completely completed. You don't have to end up with. In this case, the control unit 22 temporarily keeps the program up to the Vth distribution state of about the region D. After that, the control unit 22 sequentially executes the programs in the areas A to C and the programs in the areas D to G that were in the middle of the program.

FIG. 19 is a diagram for explaining a program modification example of the 2nd stage according to the third embodiment. FIG. 19 shows a transition method (modification example) of the Vth state in the 2nd stage. FIG. 19 (T31) shows the Vth distribution state after the program of the 1st stage is completed. Further, (T32) in FIG. 19 shows the Vth distribution state at the time when the program in the first half of the 2nd stage is completed. Further, (T33) in FIG. 19 shows the Vth distribution state at the time when the program in the latter half of the 2nd stage is completed.

When the 1st stage shown in FIG. 19 (T31) is completed, the control unit 22 of the present embodiment executes the program up to the Vth distribution state of about the region D as shown in FIG. 19 (T32). do. After that, the control unit 22 executes the programs of the regions A to C using the Vth distribution state of the region Er. Further, the control unit 22 executes the programs in the regions D to G using the Vth distribution state (Vth distribution state in the middle of the program) of about the region D.

Also in the case of the method shown in FIG. 19, as in the case of the method shown in FIG. 17, the timing at which the memory cells whose Lower page data is “1” and the memory cells whose Lower page data is “0” are mixed. Will not occur. Therefore, even if the power supply is cut off in the 2nd stage, the control unit 22 can read the Lower page data by using the read voltage of either Vr1 or Vr4.

In this way, the control unit 22 moves the threshold distribution to the memory cells that causes the Vth distribution state of the writing destination to be the area D or higher to a position that does not overlap the threshold areas from the areas Er to C. After that, the program to the memory cell to be made into the area Er to G is completed.

As described above, in the third embodiment, since the upper Vth distribution is programmed first when programming the 2nd stage, it is possible to prevent the entanglement destruction of the written data due to the unauthorized power cutoff, and as a result, this result. , It becomes possible to improve the reliability of the storage device.

In the first to third embodiments, the case where the same 1-3-3 data coding as that described with reference to FIG. 6 is used has been described, but other 1-3-3 data coding may be used. .. However, in 1-3-3 data coding, there is a condition that the lower page data has one boundary.

FIG. 20 is a diagram showing another example of 1-3-3 data coding. In the 1-3-3 data coding modification 1 shown in FIG. 20 (A), the relationship between the threshold voltage and the data value is as shown below.
-The memory cell whose threshold voltage is in the Er region is in a state of storing "111".
-The memory cell whose threshold voltage is in the A region is in a state of storing "011".
-The memory cell whose threshold voltage is in the B region is in a state of storing "001".
A memory cell whose threshold voltage is in the C region is in a state of storing "101".
A memory cell whose threshold voltage is in the D region is in a state of storing "100".
-The memory cell whose threshold voltage is in the E region is in a state of storing "110".
-The memory cell whose threshold voltage is in the F region is in a state of storing "010".
-The memory cell whose threshold voltage is in the G region is in a state of storing "000".

In the 1-3-3 data coding modification 2 shown in FIG. 20 (B), the relationship between the threshold voltage and the data value is as shown below.
-The memory cell whose threshold voltage is in the Er region is in a state of storing "110".
A memory cell whose threshold voltage is in the A region is in a state of storing "100".
-The memory cell whose threshold voltage is in the B region is in a state of storing "000".
-The memory cell whose threshold voltage is in the C region is in a state of storing "010".
-The memory cell whose threshold voltage is in the D area is in a state of storing "011".
-The memory cell whose threshold voltage is in the E region is in a state of storing "111".
A memory cell whose threshold voltage is in the F region is in a state of storing "101".
-The memory cell whose threshold voltage is in the G region is in a state of storing "001".

In the 1-3-3 data coding modification 3 shown in FIG. 20 (C), the relationship between the threshold voltage and the data value is as shown below.
-The memory cell whose threshold voltage is in the Er region is in a state of storing "110".
-The memory cell whose threshold voltage is in the A region is in a state of storing "010".
-The memory cell whose threshold voltage is in the B region is in a state of storing "000".
A memory cell whose threshold voltage is in the C region is in a state of storing "100".
A memory cell whose threshold voltage is in the D region is in a state of storing "101".
-The memory cell whose threshold voltage is in the E region is in a state of storing "111".
-The memory cell whose threshold voltage is in the F region is in a state of storing "011".
-The memory cell whose threshold voltage is in the G region is in a state of storing "001".

(Fourth Embodiment)
Next, a fourth embodiment will be described with reference to FIG. In the fourth embodiment, the 1st stage is a lower / middle page program, and the 2nd stage is an upper page program.

FIG. 21 is a diagram showing the threshold distribution after the program in the fourth embodiment. FIG. 21 shows the threshold distribution after each program stage for the memory cells. FIG. 21 (T41) shows the threshold distribution of the erased state, which is the initial state before the program. FIG. 21 (T42) shows the threshold distribution after the program of the 1st stage. FIG. 21 (T43) shows the threshold distribution after programming the 2nd stage.

As shown in FIG. 21 (T41), all the memory cells of the NAND memory cell array 23 are in the state of distribution Er in the unwritten state. As shown in (T42) of FIG. 21, the control unit 22 of the non-volatile memory 2 keeps the distribution Er for each memory cell according to the bit value written in the Lower / Middle page in the program of the 1st stage. Alternatively, a charge is injected to move the distribution above the distribution Er. As a result, the memory cell is programmed to the quaternary level by the Lower / Middle page data.

Further, as shown in FIG. 21 (T43), in the 2nd stage program, one page of the Upper page is required for writing data. The control unit 22 of the non-volatile memory 2 adds the data of the Upper page as the 2nd stage to the data of the 1st stage. In this way, the control unit 22 programs the threshold distribution after the program of the 2nd stage so that each adjacent distribution has an 8-value level in the final state in which it is separated.

The threshold level when programming to the 4-value level of the 1st stage is, for example, as follows. The control unit 22 controls the second threshold level from the bottom to have the same distribution as the area A in view of allocating the transition to the area A and the area B in the program of the 2nd stage. Further, the control unit 22 controls so that the third threshold level from the bottom falls between Vr3 and Vr5 in view of allocating the transition to the area D and the area E in the program of the 2nd stage. Further, the control unit 22 controls so that the highest threshold level is placed between Vr5 and Vr7 in view of allocating the highest threshold level so as to transition to the area E and the area F in the program of the 2nd stage. After that, the control unit 22 programs the 4 values of the 1st stage to the 8 value level of the 2nd stage.

The programs are executed in the same order as shown in FIG. 8B in order to reduce the influence of interference between adjacent memory cells. That is, two different program stages are not executed consecutively on the same word line WLi. In order to reduce the interference between adjacent memory cells between word line WLi, it is effective to reduce the fluctuation amount of the threshold value of adjacent word line WLi after the program up to the 2nd stage of word line WLi is completed. .. In the sequence shown in FIG. 8B, since the program stage of the adjacent word line WLi is only the 2nd stage after the program up to the 2nd stage of the word line WLi is completed, the influence of interference between adjacent memory cells can be reduced.

Here, the writing procedure according to the fourth embodiment will be described. Since the procedure for writing the entire block according to the fourth embodiment is the same as the procedure for writing the entire block according to the first embodiment (FIG. 9A), the description thereof will be omitted. In the present embodiment as well, as in the first embodiment, the program stage is advanced while straddling the word line WLi in a discontinuous order. The program is executed as a unit.

FIG. 22A is a sub-flow chart showing a writing procedure in the 1st stage according to the fourth embodiment, and FIG. 22B is a sub-flow chart showing a writing procedure in the 2nd stage according to the fourth embodiment. Of the processes shown in FIG. 22A, the same processes as those shown in FIG. 9B will be omitted. Further, among the processes shown in FIG. 22B, the same processes as those shown in FIG. 9C will be omitted.

As shown in FIG. 22A, in the 1st stage program, first, a lower page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S1410). Then, the Lower page data is input from the memory controller 1 to the non-volatile memory 2 (step S1420).

Further, a middle page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S1430). Then, the data of the Middle page is input from the memory controller 1 to the non-volatile memory 2 (step S1440).

Then, the program execution command of the 1st stage is input from the memory controller 1 to the non-volatile memory 2 (step S1450), which makes the chip busy (step S1460).

After that, the Vth of the program destination of the 2nd stage is determined based on the Lower page data and the Middle page data (step S1470). After that, data is written to the Lower page and the Middle page using the determined Vth.

When writing data to the Lower page and the Middle page, one or more program voltage pulses are applied (step S1480). Then, reading is performed to confirm whether or not the memory cell has moved beyond the threshold boundary level (step S1490). Further, it is confirmed whether or not the number of fail bits of the data on the Lower page and the Middle page is smaller than the criteria (determination criterion) (step S1500). When the number of fail bits of the data is equal to or greater than the criteria (steps S1500, No), the processes of steps S1480 to S1500 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S1500, Yes), the data becomes chip ready (step S1510).

As shown in FIG. 22B, in the 2nd stage program, first, the upper page data input start command is input from the memory controller 1 to the non-volatile memory 2 (step S1610). Then, the data of the Upper page is input from the memory controller 1 to the non-volatile memory 2 (step S1620). Next, the program execution command of the 2nd stage is input from the memory controller 1 to the non-volatile memory 2 (step S1630), which makes the chip busy (step S1640).

After that, the Lower page data which is the IDL is read out (step S1650). Further, the middle page data which is the IDL is read (step S1660). Then, the Vth of the program destination of the Upper page is determined based on the Lower page data and the Middle page data (step S1670). After that, data is written to the Upper page using the determined Vth.

Further, the control unit 22 can read a plurality of times in order to improve the reliability of the read data of the IDL, take a majority decision of the read result in the page buffer 24 in the chip, and use it as the next write data. Is. Of course, the control unit 22 can read a plurality of times in a normal read operation, take a majority vote of the read result in the chip, and use it as read data to the outside.

When writing data to the Upper page, program voltage pulses are applied one to more than once (step S1680). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data reading of the Upper page is performed (step S1690).

Further, it is confirmed whether or not the number of fail bits of the data on the Upper page is smaller than that of the criteria (step S1700). When the number of fail bits of the data on the Upper page is equal to or greater than the criteria (steps S1700, No), the processes of steps S1680 to S1700 are repeated. Then, when the number of fail bits of the data becomes smaller than the criteria (step S1700, Yes), the data becomes chip ready (step S1710).

Here, a modified example of the writing procedure shown in FIG. 22B will be described. FIG. 22C is a sub-flow chart showing a modified example of the writing procedure in the 2nd stage according to the fourth embodiment. In the processing procedure shown in FIG. 22C, the processing procedure of steps S161 to S1710 is the same as that of FIG. 22B, except that the processing of steps S1650 and S1670 described in FIG. 22B is not performed.

In the case of the processing procedure shown in FIG. 22C, the processing of steps S1601 to S1609 is performed before step S1610. Specifically, first, the lower page and middle page read commands are input from the memory controller 1 to the non-volatile memory 2 (step S1601), which makes the chip busy (step S1602).

After that, the control unit 22 reads the Lower page data and the Middle page data, which are IDLs, at the threshold voltages of Vr1, Vr3, Vr5, and Vr7. Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1, Vr3, Vr5, and Vr7 (step S1603). After that, it becomes chip ready (step S1604).

When the lower page data and the middle page data read by the control unit 22 are output (step S1605), the lower page data and the middle page data are transmitted to the ECC circuit 14 (step S1606). As a result, the ECC circuit 14 ECC corrects the Lower page data and the Middle page data (step S1607).

Then, the input start command of the lower page data and the middle page data is input from the memory controller 1 to the non-volatile memory 2 (step S1608). As a result, the ECC circuit 14 inputs the data of the Lower page and Middle page data to the non-volatile memory 2 (step S1609).

After that, the processes of steps S161 to S1710 are performed. In step S1670, the Vth of the program destination of the Middle page and Upper page is determined based on the Lower page data and the Middle page data from the ECC circuit 14.

As described above, in the present embodiment, the data input in the 2nd stage program is only one page of the Upper page. However, in this 2nd stage, Vth, which is the destination of the memory cell program, requires data for 3 pages including the Lower / Middle page. Therefore, in this 2nd stage program, Lower page data and Middle page data are first read as preprocessing. Then, the Vth of the program destination of the Upper page is determined by synthesizing the read data and the input Upper page data.

FIG. 23 is a diagram showing an example of a sequence of external program commands according to the fourth embodiment. FIG. 23 (A) shows a sequence of external program commands in the 1st stage according to the fourth embodiment, and FIG. 24 (B) shows a sequence of external program commands in the 2nd stage according to the fourth embodiment. Shown.

As shown in FIG. 23 (A), in the 1st stage, after the program start command (80h) is input, the address of the program target block page (Lower page address) is input, and then the program of the Lower page. Data is entered. After that, the concatenation command (1Ah) of the program command is input, and the program data of the Middle page is input this time in the same sequence. Finally, when the program execution command (10h) is input, the chip becomes busy and the operation of the program is started inside the memory chip. By inputting such a program command, the Lower page and the Middle page are programmed. The input order of the program data on the Lower page and the program data on the Middle page may come first.

As shown in FIG. 23 (B), in the 2nd stage, after the program start command (80h) is input, the address of the program target block page (Upper page address) is input, and then the program of the Upper page. Data is entered. Finally, when the program execution command (10h) is input, the chip becomes busy and the operation of the program is started inside the memory chip. By inputting such a program command, the Lower page and the Middle page as the IDL are read, and the Upper page is programmed.

Here, the page reading process will be described. The method of reading the page differs depending on whether the program for the word line WLi including the page to be read is before the writing of the 2nd stage or after the completion of the 2nd stage.

In the case of the word line WLi before writing the 2nd stage, the lower page and the middle page are valid for the recorded data. Therefore, the control unit 22 reads data from the memory cell when the read page is the Lower page or the Middle page. Then, in the case of the Upper page, the control unit 22 does not perform the memory cell read operation, but controls to forcibly output all "1" as read data.

On the other hand, in the case of the word line WLi completed up to the 2nd stage, the control unit 22 reads the memory cell regardless of whether the read page is the Upper / Middle / Lower page. In this case, since the required read voltage differs depending on which page is read, the control unit 22 executes only the required read according to the selected page.

According to the coding shown in FIG. 6, since there is only one boundary between the threshold states in which the Lower page data changes, the control unit 22 sets the threshold value in any of the two ranges separated by the boundary. The data is determined by the location of.

Further, since there are three boundaries between the threshold states in which the data on the Middle page or Upper page changes, the control unit 22 positions the threshold value in any of the four ranges separated by those boundaries. Determine the data by doing.

Hereinafter, a specific processing procedure for reading the page will be described. FIG. 24A is a flowchart showing a processing procedure of reading a page with a word line before writing the 2nd stage in the storage device according to the fourth embodiment. FIG. 24B is a flowchart showing a processing procedure of reading a page with a word line in which the program is completed up to the 2nd stage in the storage device according to the fourth embodiment. Of the processes shown in FIG. 24A, the same processes as those shown in FIG. 12A will be omitted. Further, among the processes shown in FIG. 24B, the same processes as those shown in FIG. 12B will be omitted.

As shown in FIG. 24A, in the case of the word line WLi before writing in the 2nd stage, the control unit 22 selects the read page (step S1810). When the read page is the Lower page (step S1810, Lower), the control unit 22 reads out at the threshold voltage of Vr3 (step S1820). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr3 (step S1830).

When the read page is a middle page (step S1810, Middle), the control unit 22 reads at the threshold voltages of Vr1, Vr3, and Vr5 (steps S1840, S1850, S1860). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1, Vr3, and Vr5 (step S1870).

When the read page is an Upper page (step S1810, Upper), the control unit 22 controls to forcibly output "1" as the output data of the memory cell (step S1880).

Further, as shown in FIG. 24B, in the case of the word line WLi whose program has been completed up to the 2nd stage, the control unit 22 selects the read page (step S1910). When the read page is the Lower page (step S1910, Lower), the control unit 22 reads out at the threshold voltage of Vr4 (step S1920). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr4 (step S1930).

When the read page is a middle page (step S1910, Middle), the control unit 22 reads at the threshold voltages of Vr1, Vr3, and Vr6 (steps S1940, S1950, S1960). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1, Vr3, and Vr6 (step S1970).

When the read page is the Upper page (step S1910, Upper), the control unit 22 reads at the threshold voltages of Vr2, Vr5, and Vr7 (steps S1980, S1990, S2000). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr2, Vr5, and Vr7 (step S2010).

As described above, in the threshold program control as shown in FIG. 21, Vr3 is used as the read level capable of separating the four levels into two upper and lower levels in the case of reading the Lower page data. Further, in the case of reading Middle page data, since the data allocation is such that the data cannot be determined unless one of the four levels is specified, it is necessary to read three levels of Vr1, Vr3, and Vr5 as the read level. Become.

On the other hand, in the case of the word line WLi completed up to the 2nd stage, the read page reads the memory cell regardless of whether it is Upper / Middle / Lower, but the required read voltage differs depending on which page is read, so it is selected. Only the necessary reads are performed according to the page.

The memory controller 1 can manage and identify whether the program for the word line WLi is completed in the 1st stage or the 2nd stage. Since the memory controller 1 controls the program, if the memory controller 1 records the progress status, the memory controller 1 can easily determine which address of the non-volatile memory 2 is in what program state. You can refer to it. In this case, when reading from the non-volatile memory 2, the memory controller 1 identifies what kind of program state the word line WLi including the target page address is in, and issues a read command according to the identified state. ..

FIG. 25 is a diagram showing an example of a sequence of external read commands according to the fourth embodiment. FIG. 25 (A) shows a sequence of external read commands on the word line WLi in which the program is completed up to the 1st stage in the storage device according to the fourth embodiment, and FIG. 25 (B) shows the fourth. The sequence of the external read command on the word line WLi in which the program is completed up to the 2nd stage in the storage device according to the embodiment is shown.

As shown in FIG. 25 (A), in the case of the word line WLi before writing the 2nd stage, a command (2Dh) indicating the state before writing the 2nd stage is first input as a command to execute the read operation. After that, the read start command (00h) is input, and then the address of the block page to be read (the address of the Lower page, the Middle page, or the Upper page) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation is started inside the memory chip. By inputting such a program command, data is read from the Lower page, Middle page, or Upper page. After that, the chip becomes ready and the read data is output.

On the other hand, as shown in FIG. 25 (B), in the case of the word line WLi in which the program is completed up to the 2nd stage, a command (25h) indicating the completion state up to the 2nd stage is first input as a command to execute the read operation. Will be done. After that, the read start command (00h) is input, and then the address of the block page to be read (the address of the Lower page, the Middle page, or the Upper page) is input. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation is started inside the memory chip. By inputting such a program command, data is read from the Lower page, Middle page, or Upper page. After that, the chip becomes ready and the read data is output.

A modification similar to the modification of the second embodiment with respect to the first embodiment may be applied to the present embodiment. That is, also in this embodiment, the program of the 2nd stage of the word line WLn-1 and the program of the 1st stage of the word line WLn may be collectively performed.

Further, in the present embodiment, the 1-3-3 data coding type does not require the restriction that the number of boundaries at Lower is 1. Therefore, 1-3-3 data coding other than 1-3-3 data coding used in the first to third embodiments may be applied. Specific states of 1-3-3 data coding of the present embodiment are shown in FIGS. 5 to 8, 12 to 15, 18, 20, 22, 24, 28 to 30 of Japanese Patent Application Laid-Open No. 2015-19571 and the like. It is a thing.

As described above, in the fourth embodiment, similarly to the first embodiment, when programming the non-volatile memory 2 (3 bit / Cell NAND memory having a three-dimensional structure or a two-dimensional structure), 1-3 -3 Data coding was adopted, and the program was a two-stage system. Since the program is programmed in a two-stage system in this way, the amount of data input during the data program is reduced, and the amount of write buffer required for the memory controller 1 can be suppressed. In addition, the bias of the bit error rate between the pages of the non-volatile memory 2 can be reduced, and the cost of ECC can be reduced.

(Fifth Embodiment)
Next, the fifth embodiment will be described with reference to FIGS. 26 to 30. In the fifth embodiment, it is recorded in the memory cell (flag cell) whether the program for the word line WLi is completed in the 1st stage or the 2nd stage, and when the data is read, the information recorded in the flag cell is recorded. Appropriately control the read sequence based on.

In this embodiment as well, a case where the same data coding as that described with reference to FIG. 6 of the first embodiment is used will be described. Further, in the following description, a memory cell array for storing data may be referred to as a data storage cell. In addition, information indicating which of the 1st stage and the 2nd stage has been completed may be referred to as completion information. In the present embodiment, when the 2nd stage is completed, the data is written in the flag cell, so that the data is the completion information indicating that the 2nd stage has been completed. On the other hand, when the 2nd stage is not completed, the data is not written in the flag cell, so that the unwritten data is the completion information indicating that the 2nd stage has not been completed.

FIG. 26 is a diagram for explaining the configuration of the flag cell. Also in this embodiment, a memory cell array having the same configuration as the memory cell array described with reference to FIG. 3 of the first embodiment is used. Note that FIG. 26 shows the memory cell transistor MT and the like connected to the select gate line SGD0, and the memory cell transistor MT and the like connected to the select gate lines SGD1 to 3 are not shown.

A dummy cell DC and a flag cell FC are arranged next to the memory cell transistor (data storage cell) MT connected to the bit lines BL0 to BLm-1. The dummy cell DC and the flag cell FC have the same configuration as the memory cell transistor MT. Specifically, the dummy cell DC is connected to the select gate line SGD0, the word line WL0 to WL7, the select gate line SGS, the source line SL, the dummy cell bit line DBL, and the like. Further, the flag cell FC is connected to the select gate line SGD0, the word line WL0 to WL7, the select gate line SGS, the source line SL, the flag cell bit lines FBL0 to FBLk-1 and the like. In other words, a part of the memory cells in the block BLK is used as data storage, and the remaining part is used as a dummy cell DC and a flag cell FC.

In the first to fifth embodiments, the memory controller 1 manages and identifies whether the program for the word line WLi is completed in the 1st stage or the 2nd stage. Then, when reading data, the memory controller 1 issues a read command according to the completion state of the program.

On the other hand, in the present embodiment, the control unit 22 records the completion information indicating whether the 1st stage or the 2nd stage is completed in the flag cell FC of the non-volatile memory 2. Then, at the time of data reading, the control unit 22 controls the reading sequence based on the completion information recorded in the flag cell FC.

The flag cell FC is provided in word line units. That is, a part of the plurality of memory cells in the word line WLi is used as the flag cell FC. The number of flag cells FC may be one for each word line WLi, but it is preferable to have a plurality of flag cells FC in order to improve the reliability of data by multiplexing. Further, in order to suppress the influence of reliability deterioration due to interference between adjacent cells, it is preferable that the data storage cell for storing data and the flag cell FC are not physically adjacent to each other. For example, it is preferable to arrange a dummy cell DC or the like that is not used as a data recording area between the data storage cell and the flag cell FC.

The completion information recorded in the flag cell FC is binary information as to whether or not the 2nd stage program has been performed. The control unit 22 writes the completion information indicating that the program of the 2nd stage is completed in the flag cell FC in the same word line WLi at the time of programming the 2nd stage. The control unit 22 writes the completion information in the flag cell FC, for example, at the D level or higher. The state of change in the threshold distribution at this time will be described.

FIG. 27A is a diagram for explaining a program for the flag cell according to the fifth embodiment. FIG. 27A shows a method of transitioning the Vth state in the flag cell FC, which is performed during the 2nd stage program.

FIG. 27A (T51) shows the Vth distribution state in the flag cell FC in the erased state, which is the initial state before the program. Further, (T52) in FIG. 27A shows the Vth distribution state at the time when the program of the 1st stage is completed. Further, (T53) in FIG. 27A shows the Vth distribution state at the time when the program of the 2nd stage is completed. When the 2nd stage is completed, the control unit 22 of the present embodiment sets the flag cell FC so that the Vth distribution state of the writing destination becomes the region D or more (Vr4 or more) as shown in (T53) of FIG. 27A. Program.

The flag cell FC is written at the same time as the data cell at the 2nd stage, but the transition of the threshold value including the flag cell FC is larger than that of the data cell. Therefore, when the reliability of the data cell adjacent to the flag cell FC deteriorates, a dummy cell DC is provided between the flag cell FC and the data cell. Further, the dummy cell DC may be written from Er to A or B or C at the time of the 2nd stage as shown in FIG. 27B.

FIG. 27B is a diagram for explaining a program for a dummy cell according to a fifth embodiment. FIG. 27B shows a method of transitioning the Vth state in the dummy cell DC, which is performed during the 2nd stage program.

FIG. 27B (T61) shows the Vth distribution state in the dummy cell DC in the erased state, which is the initial state before the program. Further, (T62) in FIG. 27B shows the Vth distribution state at the time when the program of the 1st stage is completed. Further, (T53) in FIG. 27A shows the Vth distribution state at the time when the program of the 2nd stage is completed. When the 2nd stage is completed, the control unit 22 of the present embodiment sets the dummy cell DC so that the Vth distribution state of the writing destination becomes region C or less (Vr4 or less) as shown in (T63) of FIG. 27B. Program.

FIG. 28 is a flowchart showing a writing procedure in the 2nd stage according to the fifth embodiment. The same processing as that described with reference to FIG. 9C will be omitted. The steps S210 to S2180 of the 2nd stage according to the fifth embodiment are the same as the steps S310 to S380 of the 2nd stage according to the first embodiment shown in FIG. 9C.

In the present embodiment, after the Vth of the program destination to the Middle page, Upper page and flag cell FC is determined (step S2180), the determined Vth is used to determine the data storage cell (Middle page, Upper page) and the flag cell FC. Data is written to.

In the 2nd stage according to the fifth embodiment, one or a plurality of program voltage pulses are applied when writing data to the Middle page, Upper page, and flag cell FC. (Step S2190). Then, in order to confirm whether or not the memory cell has moved beyond the threshold boundary level, data is read out to the Middle page, Upper page, and flag cell FC (step S2200).

Further, it is confirmed whether or not the number of fail bits of the data on the Middle page and the Upper page is smaller than the criteria (step S2210). When the number of fail bits of data on the Middle page and Upper page is equal to or greater than the criteria (steps S2210, No), the processes of steps S2190 to S2210 are repeated. In this case, the processing of steps S2190 and S2210 for the flag cell FC is omitted.

Then, when the number of fail bits of the data on the Middle page and the Upper page is smaller than the criteria (step S2210, Yes), it is confirmed whether or not the number of fail bits of the data in the flag cell FC is smaller than the criteria (step S2220). ..

When the number of fail bits of data in the flag cell FC is equal to or greater than the criteria (steps S2220, No), the processes of steps S2190 to S2220 are repeated. In this case, the processing of steps S2190 to S2210 for the Middle page and Upper page is omitted.

Then, when the number of fail bits of the data in the flag cell FC becomes smaller than the criteria (step S2220, Yes), the data becomes chip ready (step S2230).

As described above, in step S2190 (step of applying the program voltage pulse) of the present embodiment, the program voltage pulse is simultaneously applied to the flag cell FC in addition to the data storage cell for writing the data. Then, also in the subsequent data reading, the data in the data storage cell and the data (completion information) in the flag cell FC are read out in order to confirm whether or not the data storage cell and the flag cell FC are programmed.

After that, the data read from the data storage cell and the flag cell FC and the criteria corresponding to the expected value are compared. At this time, the number of failed bits is counted, but the data failed in the data storage cell and the data failed in the flag cell FC are counted separately and compared with their respective criteria. If neither of them satisfies the criteria, the procedure for applying the program voltage pulse is returned again. If the criteria are met in any of the comparisons, the chip is considered ready and the process ends.

In the page reading in the first embodiment, different processing orders were used depending on whether the program for the word line WLi including the page to be read was completed in the 1st stage or the 2nd stage. Then, which processing procedure to carry out was determined based on the external read command. However, in the present embodiment, which of the 1st stage and the 2nd stage is completed is not instructed by the command from the memory controller 1, but is determined according to the completion information in the flag cell FC. That is, when the control unit 22 receives the read command from the memory controller 1, the control unit 22 first reads the completion information which is the data in the flag cell FC. Then, the control unit 22 determines whether the 1st stage or the 2nd stage is completed depending on whether or not the flag cell FC has been written.

As described above, in the present embodiment, the writing level to the flag cell FC is set to D level or higher. Therefore, the reading of the flag cell FC is possible with any one reading voltage of Vr1, Vr2, Vr3 or Vr4. Therefore, the control unit 22 uses the lowest read level of the plurality of read levels required when the program of the 2nd stage is completed regardless of whether the read target page is the Lower page, the Middle page, or the Upper page. Then, the flag cell FC can be read. Then, if it is determined that the flag cell FC has been written, the control unit 22 determines that the program of the 2nd stage has been completed, and reads from the memory cells other than the flag cell FC at the remaining read level. Run.

On the other hand, when the flag cell FC is determined to be unwritten and the Lower page is the read target, the control unit 22 rereads the data with Vr1. If the Middle / Upper page is the read target, the control unit 22 determines that subsequent reading is unnecessary, and forcibly sets the output data to "1".

When determining whether or not the flag cell FC has been written from the read result (completion information) of the flag cell FC, the control unit 22 determines whether or not the cell itself has been written if there is only one flag cell FC. Should be determined. Further, a plurality of flag cell FCs may be provided in order to increase the reliability of the data of the flag cell FCs. In this case, the control unit 22 has written the flag cell FC, for example, when the completion information indicating that more than the number of cells of the criteria have been written is read from a certain flag cell FC among the plurality of flag cell FCs. Judge that.

Here, a specific processing procedure for reading the page will be described. FIG. 29 is a flowchart showing a page reading processing procedure according to the fifth embodiment. Of the processes shown in FIG. 29, the same processes as those shown in FIGS. 12A or 24A will be omitted.

As shown in FIG. 29, the control unit 22 selects a read page (step S2310). When the read page is the Lower page (step S2310, Lower), the control unit 22 reads out at the threshold voltage of Vr4 (step S2320).

Then, the control unit 22 determines whether or not the completion information is written in the flag cell FC (step S2330). When the completion information has not been written in the flag cell FC (step S2330, No), the control unit 22 reads out at the threshold voltage of Vr1 (step S2340). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1 (step S2350).

On the other hand, when the completion information has already been written in the flag cell FC (step S2330, Yes), the control unit 22 sets the value of the read data to “0” or “” based on the read result at the threshold voltage of Vr4. It is determined to be 1 ”(step S2360).

When the read page is a middle page (step S2310, Middle), the control unit 22 reads at the threshold voltage of Vr1 (step S2370). Then, the control unit 22 determines whether or not the completion information is written in the flag cell FC (step S2380). When the completion information has not been written in the flag cell FC (step S2380, No), the control unit 22 controls to forcibly output "1" as the output data of the data storage cell (Middle page) (step S2390). ..

On the other hand, when the completion information has already been written in the flag cell FC (steps S2380, Yes), the control unit 22 reads out at the threshold voltages of Vr3 and Vr6 (steps S2400, S2410). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr1, Vr3, and Vr6 (step S2420).

When the read page is the Upper page (step S2430, Upper), the control unit 22 reads at the threshold voltage of Vr2 (step S2370). Then, the control unit 22 determines whether or not the completion information is written in the flag cell FC (step S2440). When the completion information has not been written in the flag cell FC (step S2440, No), the control unit 22 controls to forcibly output "1" as the output data of the data storage cell (Upper page) (step S2450). ..

On the other hand, when the completion information has already been written in the flag cell FC (step S2440, Yes), the control unit 22 reads out at the threshold voltages of Vr5 and Vr7 (steps S2460, S2470). Then, the control unit 22 determines the value of the read data to be “0” or “1” based on the read result at the threshold voltage of Vr2, Vr5, and Vr7 (step S2780).

FIG. 30 is a diagram showing an example of a sequence of external read commands according to the fifth embodiment. In this embodiment, there is only one type of read command. As shown in FIG. 30, a read start command (00h) is input as a command to execute the read operation, and then the address of the block page to be read (the address of the Lower page, the Middle page, or the Upper page) is input. .. Finally, when the read execution command (30h) is input, the chip becomes busy and the read operation is started inside the memory chip. By inputting such a program command, data is read from the Lower page, Middle page, or Upper page. After that, the chip becomes ready and the read data is output.

As described above, in the fifth embodiment, since the completion information is stored in the flag cell FC, it is possible to read the page data in the same processing order regardless of whether the 1st stage or the 2nd stage is completed. Become.

(Sixth Embodiment)
Next, the sixth embodiment will be described with reference to FIGS. 31 to 36. In the sixth embodiment, page-by-page writing is performed in two stages on the non-volatile memory 2 of a 4-bit / Cell (QLC: Quadruple Level Cell) having a three-dimensional structure or a two-dimensional structure.

FIG. 31 is a diagram showing an example of the threshold value region of the sixth embodiment. FIG. 31 shows an example of the threshold distribution of the 4-bit / Cell non-volatile memory 2. The 16 distributions described as Er1, A1, B1, C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, O1 in FIG. 31 have 16 thresholds. Each threshold distribution within the region is shown. As described above, each memory cell of the present embodiment has a threshold distribution partitioned by 15 boundaries. The horizontal axis of FIG. 31 shows the threshold voltage, and the vertical axis shows the distribution of the number of memory cells (number of cells).

In the present embodiment, the region where the threshold voltage is Vr11 or less is called region Er1, the region where the threshold voltage is larger than Vr11 and Vr12 or less is called region A1, and the threshold voltage is larger than Vr12 and Vr13 or less. The region where the threshold voltage is greater than Vr13 and Vr14 or less is referred to as region C1. Further, in the present embodiment, the region where the threshold voltage is larger than Vr14 and Vr15 or less is called a region D1, and the region where the threshold voltage is larger than Vr15 and Vr16 or less is called a region E1. The region where the threshold voltage is larger than Vr16 and Vr17 or less is called a region F1, and the region where the threshold voltage is larger than Vr17 and Vr18 or less is called a region G1.

Further, in the present embodiment, the region where the threshold voltage is larger than Vr18 and Vr19 or less is called region H1, the region where the threshold voltage is larger than Vr19 and Vr20 or less is called region I1, and the threshold voltage is called region I1. The region where the threshold voltage is larger than Vr20 and Vr21 or less is called region J1, and the region where the threshold voltage is larger than Vr21 and Vr22 or less is called region K1. Further, in the present embodiment, the region where the threshold voltage is larger than Vr22 and Vr23 or less is called a region L1, and the region where the threshold voltage is larger than Vr23 and Vr24 or less is called a region M1. The region larger than Vr24 and equal to or less than Vr25 is called a region N1, and the region where the threshold voltage is larger than Vr25 is called a region O1.

Further, the threshold distributions corresponding to the regions Er1, A1, B1, C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, O1 are distributed respectively Er1, A1, B1, respectively. It is called C1, D1, E1, F1, G1, H1, I1, J1, K1, L1, M1, N1, O1 (the first to 16th distributions). Vr11 to Vr25 are threshold voltages that serve as boundaries between regions.

Figures 32, 34, and 36 below show the threshold distribution after each program stage for 4-bit / Cell memory cells. Further, the threshold distribution shown in FIG. 32 and the data coding shown in FIG. 33 correspond to 1-4-5-5 coding. In 1-4-5-5 coding, the number of boundaries for determining the bit value is 1, 4, 5, 5 for the Lower page, Middle page, Upper page, and Higher page, respectively.

FIG. 32 is a diagram of a first example showing the threshold distribution after the program in the sixth embodiment. FIG. 32 (T71) shows the threshold distribution of the erased state, which is the initial state before the program. FIG. 32 (T72) shows the threshold distribution after the program of the 1st stage. FIG. 32 (T73) shows the threshold distribution after programming the 2nd stage.

As shown in FIG. 32 (T71), all the memory cells of the NAND memory cell array 23 have a distribution Er in the unwritten state. As shown in (T72) of FIG. 32, the control unit 22 of the non-volatile memory 2 keeps the distribution Er for each memory cell according to the bit value written to the Lower page and the Middle page in the program of the 1st stage. , Or charge is injected to move it to a distribution above the distribution Er. As a result, the memory cells are programmed to the quaternary level by the Lower page data and the Middle page data.

Further, as shown in FIG. 32 (T73), in the 2nd stage program, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the non-volatile memory 2 programs the threshold distribution after the program of the 2nd stage so that each adjacent distribution has a level of 16 values in the final state in which the adjacent distributions are separated. In this case, all page data can be read.

FIG. 33 is a diagram showing data coding corresponding to the threshold distribution shown in FIG. In the data coding shown in FIG. 33, for example, the memory cell whose threshold voltage is in the Er1 region stores "1111" as the data value of the bit corresponding to the Upper, Middle, Lower, and Higher pages. be. Further, the memory cell whose threshold voltage is in the A1 region is in a state of storing "1011".

Further, the threshold distribution shown in FIG. 34 and the data coding shown in FIG. 35 correspond to the 1-6-4-4 coding. In 1-6-4-4 coding, the number of boundaries for determining the bit value is 1, 6, 4, and 4, respectively, on the Lower page, Middle page, Upper page, and Higher page.

FIG. 34 is a diagram of a second example showing the post-programmed threshold distribution in the sixth embodiment. FIG. 34 (T81) shows the threshold distribution of the erased state, which is the initial state before the program. FIG. 34 (T82) shows the threshold distribution after the program of the 1st stage. FIG. 34 (T83) shows the threshold distribution after programming the 2nd stage.

As shown in FIG. 34 (T81), all the memory cells of the NAND memory cell array 23 have a distribution Er in the unwritten state. As shown in (T82) of FIG. 34, the control unit 22 of the non-volatile memory 2 keeps the distribution Er for each memory cell according to the bit value written to the Lower page and the Middle page in the program of the 1st stage. , Or charge is injected to move it to a distribution above the distribution Er. As a result, the memory cells are programmed to the quaternary level by the Lower page data and the Middle page data.

Further, as shown in FIG. 34 (T83), in the 2nd stage program, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the non-volatile memory 2 programs the threshold distribution after the program of the 2nd stage so that each adjacent distribution has a level of 16 values in the final state in which the adjacent distributions are separated. In this case, all page data can be read.

FIG. 35 is a diagram showing data coding corresponding to the threshold distribution shown in FIG. 34. In the data coding shown in FIG. 35, for example, the memory cell whose threshold voltage is in the Er1 region stores "1111" as the data value of the bit corresponding to the Upper, Middle, Lower, and Higher pages. be. Further, the memory cell whose threshold voltage is in the A1 region is in a state of storing "0111".

Further, the threshold distribution shown in FIG. 36 and the data coding shown in FIG. 37 correspond to the 1-2-6-6 coding. In the 1-2-6-6 coding, the number of boundaries for determining the bit value is 1, 2, 6, and 6 on the Lower page, Middle page, Upper page, and Higher page, respectively.

FIG. 36 is a diagram of a third example showing the threshold distribution after the program in the sixth embodiment. FIG. 36 (T91) shows the threshold distribution of the erased state, which is the initial state before the program. FIG. 36 (T92) shows the threshold distribution after the program of the 1st stage. FIG. 36 (T93) shows the threshold distribution after programming the 2nd stage.

As shown in FIG. 36 (T91), all the memory cells of the NAND memory cell array 23 have a distribution Er in the unwritten state. As shown in (T92) of FIG. 36, the control unit 22 of the non-volatile memory 2 keeps the distribution Er for each memory cell according to the bit value written to the Lower page and the Middle page in the program of the 1st stage. , Or charge is injected to move it to a distribution above the distribution Er. As a result, the memory cells are programmed to the quaternary level by the Lower page data and the Middle page data.

Further, as shown in FIG. 36 (T93), in the 2nd stage program, two pages, an Upper page and a Higher page, are required for writing data. Then, the control unit 22 of the non-volatile memory 2 programs the threshold distribution after the program of the 2nd stage so that each adjacent distribution has a level of 16 values in the final state in which the adjacent distributions are separated. In this case, all page data can be read.

FIG. 37 is a diagram showing data coding corresponding to the threshold distribution shown in FIG. In the data coding shown in FIG. 37, for example, the memory cell whose threshold voltage is in the Er1 region stores "1111" as the data value of the bit corresponding to the Upper, Middle, Lower, and Higher pages. be. Further, the memory cell whose threshold voltage is in the B1 region is in a state of storing "0011".

Also in this embodiment, the program is executed and the page data is read by the same processing as in the first to fifth embodiments.

As described above, in the sixth embodiment, since the page-by-page writing is performed in two stages to the 4-bit / Cell non-volatile memory 2 having the three-dimensional structure or the two-dimensional structure, the first to fifth embodiments are performed. It is possible to obtain the same effect as the form.

The first to sixth embodiments may be combined. For example, at least one of the second to fourth embodiments may be combined with the fourth embodiment or the fifth embodiment.

Further, in the first to sixth embodiments, the case where the non-volatile memory 2 is configured by using the NAND memory has been described, but other types of memories may be used. Further, in the first to fifth embodiments, the case where the non-volatile memory 2 applies the 1-3-3 coding has been described, but the coding applied to the non-volatile memory 2 is limited to the 1-3-3 coding. No. For example, the non-volatile memory 2 may apply 1-2-4 coding or 2-3-2 coding.

The read levels (Vr1, Vr4) before and after the 2nd stage write described in FIGS. 7, 12, 17, 19, and 29 are the read levels (T3) after the 2nd stage write. It may be slightly different from Vr1 and Vr4). Further, the read levels (Vr1, Vr3, Vr5, Vr7) before the 2nd stage write and after the 2nd stage write described with reference to FIGS. 21 and 24 are the read levels (Vr1, Vr3, Vr5) after the 2nd stage write (T3). , Vr7) may be slightly different.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Memory controller, 2 ... Non-volatile memory, 11 ... RAM, 12 ... Processor, 22 ... Control unit, 23 ... NAND memory cell array, FC ... Flag cell, MT ... Memory cell transistor.

Claims (6)

A first threshold area indicating an erased state in which data has been erased, and a second to eighth threshold area indicating a write state in which data is written at a higher voltage level than the first threshold area, respectively. The nth threshold region, which is a threshold region including the threshold region, has a higher voltage level than the (n-1) threshold region (n is 2 or more and 8 or less). Non-volatile memory having a plurality of memory cells capable of storing 3-bit data represented by 1st to 3rd bits by 8 threshold areas (natural number), and
The first program command provided with a buffer and designating the data of the first bit stored in the buffer is transmitted to the non-volatile memory, and after the first program command is transmitted, the first program stored in the buffer is transmitted. A memory controller configured to delete 1-bit data and transmit a second program command specifying the 2nd bit and 3rd bit data stored in the buffer to the non-volatile memory.
With
The non-volatile memory is
In response to the transmitted first program command, the threshold area in the memory cell indicates the erased state in which the data has been erased according to the data of the designated first bit. The threshold area is one of the value area and the tenth threshold area indicating the writing state in which the data is written because the voltage level is higher than the ninth threshold area. It is configured to execute the first program on the memory cell.
In response to the transmitted command for the second program, the data of the first bit is read from the memory cell in which the first program is executed, and the read data of the first bit and the designated second are used. Based on the bit and the data of the third bit, the tenth threshold is moved from the ninth threshold area to any one of the first to fourth threshold areas. A control unit configured to execute a second program on the memory cell so that the value area becomes one of the fifth to eighth threshold areas is provided. ,
Of the first to seventh boundaries existing between adjacent threshold areas in the first to eighth threshold areas, the number of boundaries used for determining the value of the data of the first bit is 1, the number of boundary used for determination of the second bit of the data value is 3, the number of boundary used for determination of the third-bit data values are three der,
In the second program, the control unit reads the data of the first bit a plurality of times from the memory cell in which the first program is executed, and reads the result of the majority decision regarding the read result, the first read. memory system to use as bit data. The fourth boundary is used to determine the value of the first bit of data.
The first boundary, the third boundary, and the sixth boundary are used to determine the value of the second bit of data.
The memory system according to claim 1 , wherein the second boundary, the fifth boundary, and the seventh boundary are used for determining the value of the data of the third bit. The memory system according to claim 1 or 2 , wherein the voltage level in the tenth threshold region falls between the first boundary and the fourth boundary. The memory controller
The command for the first program for executing the first program for the first memory cell group electrically connected to the first word line of the plurality of memory cells is transmitted, and the command for the first program is transmitted.
To execute the first program for a second memory cell group electrically connected to a second word line among the plurality of memory cells after the first program for the first memory cell group. Send the command for the first program of
From claim 1, the second program command for executing the second program for the first memory cell group is transmitted after the first program for the second memory cell group. The memory system according to any one of claims 3. The memory system according to claim 4 , wherein the memory cells of the first memory cell group and the memory cells of the second memory cell group are connected in series. The memory controller
After executing the first program for the first memory cell group of the first string, the command for the first program for executing the first program for the first memory cell group of the second string is issued. Send and
The command for the second program for executing the second program for the first memory cell group of the first string after the execution of the first program for the first memory cell group of the second string. The memory system according to claim 4 or 5 , wherein the memory system is configured to transmit.

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