JP6947685B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Conventionally, the semiconductor device described in Japanese Patent Application Laid-Open No. 2003-218356 (Patent Document 1) is known. The semiconductor device described in Patent Document 1 includes a semiconductor substrate, an embedded insulating film, a silicon layer, and a gate electrode. A contact impurity region is formed on the semiconductor substrate. The embedded insulating film and silicon layer on the contact impurity region have been removed. The silicon layer is formed with an active layer, a source impurity region, and a drain impurity region. The gate electrode formed on the source impurity region, the drain impurity region, the active layer sandwiched between the source impurity region and the drain impurity region, and the active layer sandwiched between the source impurity region and the drain impurity region A transistor is formed. The threshold voltage of the transistor is adjusted by applying a voltage to the contact impurity region.

Japanese Unexamined Patent Publication No. 2003-218356

However, it is not clear from Patent Document 1 how to detect the cause of the poorly formed transistor in the semiconductor device having the above structure.

Other issues and novel features will become apparent from the description and accompanying drawings herein.

The semiconductor device according to one embodiment includes a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and a first test pattern. The semiconductor substrate has a base material layer, an insulating layer formed on the base material layer, and a semiconductor layer formed on the insulating layer. The first test pattern includes a first wiring pattern formed on the interlayer insulating film, a plurality of second wiring patterns formed on the interlayer insulating film, a third wiring pattern formed on the interlayer insulating film, and a base material layer. A first active region formed in, a plurality of second active regions formed in a semiconductor layer, a first contact plug formed in an interlayer insulating film on the first active region, and a plurality of second active regions. It has a pair of second and third contact plugs formed in the interlayer insulating film above each.

The plurality of second active regions are arranged on a virtual line including one end and the other end in a plan view. The first active region is arranged next to the third active region on one end of the virtual line among the plurality of second active regions in a plan view.

The first contact plug is connected to the first active region without interposing the insulating layer and the semiconductor layer. The pair of second contact plugs and third contact plugs are each connected to a plurality of second active regions. The first wiring pattern is connected to each of the first contact plug and the second contact plug connected to the third active region. Each of the plurality of second wiring patterns is electrically connected to two second active regions arranged adjacent to each other among the plurality of second active regions via the second contact plug and the third contact plug. Has been done. The third wiring pattern is connected to a third contact plug that is electrically connected to the fourth active region on the other end of the virtual line of the plurality of second active regions.

According to the semiconductor device according to the embodiment, it is possible to detect the cause of the poorly formed transistor.

It is a top view of the semiconductor wafer WF in 1st Embodiment. It is a top view of the semiconductor wafer WF in the modification of 1st Embodiment. It is a top view of the 1st test pattern TP1 in 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment. It is a top view of the 1st test pattern TP1 in the modification of 1st Embodiment. It is a process drawing of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing of the semiconductor apparatus which concerns on 1st Embodiment in the element separation membrane forming step S1. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in a removal step S2. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in 1st ion implantation process S3. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in a gate insulating film forming step S4. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in a gate electrode forming step S5. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in the epitaxial growth step S6. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in 2nd ion implantation process S7. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in a sidewall spacer forming process S8. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in 3rd ion implantation process S9. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in the silicide film forming step S10. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in the interlayer insulating film forming step S11. It is sectional drawing of the semiconductor device which concerns on 1st Embodiment in a contact plug forming step S12. It is an equivalent circuit diagram of the 1st test pattern TP1 when all the 2nd contact plug CP2 and the 3rd contact plug CP3 are formed normally. It is an equivalent circuit diagram of the 1st test pattern TP1 in the case where any 2nd contact plug CP2 and 3rd contact plug CP3 are not formed normally. It is a top view of the 1st test pattern TP1 in 2nd Embodiment. FIG. 2 is a cross-sectional view taken along the line XXII-XXII of FIG. It is sectional drawing in XXIII-XXIII of FIG. It is a schematic top view of the test area TEG in the third embodiment.

Details of the embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and duplicate explanations will not be repeated.

(First Embodiment)
The configuration of the semiconductor device according to the first embodiment will be described below.

As shown in FIG. 1, the semiconductor device according to the first embodiment has a semiconductor substrate SUB. The semiconductor substrate SUB is formed by cutting a semiconductor wafer WF. That is, the semiconductor substrate SUB in this embodiment is a part of the semiconductor wafer WF. More specifically, the semiconductor wafer WF has a chip region CH and a scribe region SC in a plan view. The chip region CH is a region in which a semiconductor element is formed.

The chip region CH is surrounded by the scribe region SC in a plan view. From another point of view, the scribe region SC is arranged between two chip region CHs adjacent to each other. The test region TEG is arranged in the chip region CH in a plan view. The test region TEG is a region in which the first test pattern TP1, which will be described later, is formed. As shown in FIG. 2, the test region TEG may be arranged in the scribe region SC in a plan view. The semiconductor wafer WF is cut along the scribe region SC.

As shown in FIGS. 3 and 4, the semiconductor device according to the first embodiment further has an interlayer insulating film ILD and a first test pattern TP1. The interlayer insulating film ILD is formed on the semiconductor substrate SUB. The interlayer insulating film ILD is formed of, for example, silicon oxide (SiO ₂ ).

The semiconductor substrate SUB has a base material layer BULK, an insulating layer BOX, and a semiconductor layer SOI. The insulating layer BOX is formed on the base material layer BULK. The semiconductor layer SOI is formed on the insulating layer BOX. The base material layer BULK is formed of, for example, single crystal silicon (Si). The insulating layer BOX is formed of, for example, a silicon oxide. The semiconductor layer SOI is formed of, for example, single crystal silicon.

The first test pattern TP1 has a first active region AR1 and a plurality of second active regions AR2. The first active region AR1 is formed in the base material layer BULK. The second active region AR2 is formed in the semiconductor layer SOI. More specifically, the first active region AR1 is formed in the base material layer BULK located in the first region R1 of the semiconductor substrate SUB. The second active region AR2 is formed in the semiconductor layer SOI located in the third region R3 of the semiconductor substrate SUB. The first region R1 and the third region R3 are included in the test region TEG. As described above, since the test region TEG is included in the chip region CH, the first region R1 and the third region R3 are also located in the chip region CH. On the first active region AR1, the insulating layer BOX and the semiconductor layer SOI have been removed. Each of the first active region AR1 and the second active region AR2 is insulated and separated by being surrounded by the device separation membrane ISL. The device separation membrane ISL is, for example, STI (Shallow Trench Isolation) formed of silicon oxide.

The second active region AR2 is arranged on the virtual line L in a plan view. The virtual line L is a straight line. However, the virtual line L is not limited to a straight line. The virtual line L may meander as shown in FIG. The virtual line L has one end and the other end. In the following, the second active region AR2 on one end may be referred to as a third active region AR3. Further, in the following, the second active region AR2 on the other end may be referred to as a fourth active region AR4. The first active region AR1 is arranged next to the third active region AR3 in a plan view.

The first test pattern TP1 further includes a first wiring pattern WP1, a plurality of second wiring patterns WP2, and a third wiring pattern WP3. The first wiring pattern WP1, the second wiring pattern WP2, and the third wiring pattern WP3 are formed on the interlayer insulating film ILD.

The first test pattern TP1 further has a first contact plug CP1, a pair of second contact plugs CP2, and a third contact plug CP3. The first contact plug CP1 is formed in the interlayer insulating film ILD on the first active region AR1. The second contact plug CP2 and the third contact plug CP3 are formed in the interlayer insulating film ILD on the second active region AR2.

The first contact plug CP1 is electrically connected to the first active region AR1 without passing through the insulating layer BOX and the semiconductor layer SOI. The pair of second contact plug CP2 and third contact plug CP3 are each electrically connected to a plurality of second active regions AR2.

The first wiring pattern WP1 is electrically connected to the second contact plug CP2 electrically connected to the first contact plug CP1 and the third active region AR3. The plurality of second wiring patterns WP2 are electrically connected to two second active regions AR2 arranged adjacent to each other in a plan view via the second contact plug CP2 and the third contact plug CP3, respectively. .. The third wiring pattern WP3 is electrically connected to the third contact plug CP3 which is electrically connected to the fourth active region AR4.

The first wiring pattern WP1, the second wiring pattern WP2, and the third wiring pattern WP3 are formed of, for example, aluminum (Al), an aluminum alloy, copper (Cu), a copper alloy, or the like. The first contact plug CP1, the second contact plug CP2, and the third contact plug CP3 are made of, for example, tungsten (W).

As shown in FIG. 4, the semiconductor device according to the first embodiment further includes a transistor Tr. The transistor Tr is, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The transistor Tr is formed in the chip region CH. The transistor Tr is composed of a source region SR, a drain region DRA, a well region WR, a gate insulating film GO, and a gate electrode GE.

The source region SR and the drain region DRA are formed in the semiconductor layer SOI located in the second region R2 of the semiconductor substrate SUB. The second region R2 is located in the chip region CH. The semiconductor layer SOI of the portion sandwiched between the source region SR and the drain region DRA constitutes the channel region of the transistor Tr. The well region WR is formed in the base material layer BULK located in the second region R2 of the semiconductor wafer WF. The conductive type of the source region SR and the conductive type of the drain region DRA are the first conductive types. On the other hand, the conductive type of the well region WR is the second conductive type. The second conductive type is the opposite conductive type of the first conductive type. For example, when the first conductive type is n type, the second conductive type is p type.

The gate insulating film GO is formed on the channel region. The gate electrode GE is formed on the gate insulating film GO. The gate insulating film GO is formed of, for example, a silicon oxide. The gate electrode GE is made of, for example, polycrystalline silicon doped with impurities.

The source region SR has a first portion SRa and a second portion SRb. The drain region DRA has a first portion DRAa and a second portion DRAb. The first portion SRa is formed on the channel region side with respect to the second portion SRb. The first portion DRAa is formed on the channel region side with respect to the second portion DRAb. The impurity concentration in the first portion SRa is lower than the impurity concentration in the second portion SRb. The impurity concentration in the first portion DRAa is lower than the impurity concentration in the second portion DRAb. That is, an LDD structure (Lightly Doped Diffusion) is formed in the source region SR and the drain region DRA.

A sidewall spacer SWS is formed on the side of the gate electrode GE and above the first portion SRa and the first portion DRAa. The sidewall spacer SWS is made of, for example, a silicon oxide. The sidewall spacer SWS may be formed by laminating a film of silicon oxide and a film of silicon nitride.

A contact plug electrically connected to the source region SR is formed in the interlayer insulating film ILD on the source region SR, and a drain is formed in the interlayer insulating film ILD on the drain region DRA. A contact plug is formed that is electrically connected to the region DRA.

Hereinafter, the method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the process diagram (process flow) shown in FIG.

First, as shown in FIG. 7, in the element separation membrane forming step S1, the element separation membrane ISL is formed. In the element separation film forming step S1, first, a groove is formed on the surface of the semiconductor wafer WF (substrate) by an anisotropic etching process. The anisotropic etching process is, for example, dry etching or RIE (Reactive Ion Etching) using a photoresist pattern as a mask. In the element separation membrane forming step S1, secondly, the material constituting the element separation membrane ISL is embedded in the groove. In the device separation membrane forming step S1, the material constituting the device separation membrane ISL protruding from the groove is removed by CMP (Chemical Mechanical Polishing) or the like.

Next, as shown in FIG. 8, in the removal step S2, the insulating layer BOX and the semiconductor layer SOI on the base material layer BULK on which the first active region AR1 is formed are removed in a later step. The removal of the base material layer BULK and the insulating layer BOX is performed, for example, by an isotropic etching process. The isotropic etching process is, for example, wet etching.

Next, as shown in FIG. 9, in the first ion implantation step S3, with respect to the base material layer BULK on which the gate electrode GE constituting the transistor Tr is formed above the first ion implantation step S3 (second region). Well region WR is formed on the substrate layer BULK located at R2). The formation of the well region WR is performed, for example, by ion implantation using a photoresist pattern (not shown) as a mask. When the conductive type of the well region WR is p type, for example, boron (B) is implanted by ion implantation. On the other hand, when the conductive type of the well region is n-type, for example, arsenic (As) and phosphorus (P) are implanted by ion implantation.

Next, as shown in FIG. 10, in the gate insulating film forming step S4, the gate insulating film GO is formed. The gate insulating film GO is formed, for example, by thermally oxidizing the surface of the semiconductor wafer WF.

Next, as shown in FIG. 11, in the gate electrode forming step S5, the gate electrode GE is formed. The gate electrode GE is formed on the gate insulating film GO on the surface of the semiconductor layer SOI located in the second region R2. In the gate electrode forming step S5, first, a material constituting the gate electrode GE is formed on the gate insulating film GO. In the gate electrode forming step S5, secondly, the material constituting the formed gate electrode GE is patterned by photolithography and anisotropic etching (here, dry etching). As described above, the material constituting the gate electrode GE is, for example, polycrystalline silicon doped with impurities. Further, the gate insulating film GO is patterned using the patterned gate electrode GE as a mask.

Next, as shown in FIG. 12, in the epitaxial growth step S6, the epitaxial growth method was used on the surface of the portion of the semiconductor layer SOI located in the second region R2 exposed from the gate electrode GE. An epitaxial layer EPI is formed. Further, in the epitaxial growth step S6, the epitaxial layer EPI is also formed on the surface of the semiconductor layer SOI located in the first region R1 by using the epitaxial growth method. In the subsequent steps, the epitaxial layer EPI forms part of the semiconductor layer SOI.

After the gate electrode forming step S5 and before the epitaxial growth step S6, a dummy sidewall spacer DSW is formed on the side of the gate electrode GE. The dummy sidewall spacer DSW is shown by a dotted line in FIG. The dummy sidewall spacer DSW is removed after the epitaxial growth step S6 and before the second ion implantation step S7.

As shown in FIG. 13, in the second ion implantation step S7, the first portion SRa and the first portion DRAa are formed. Further, in the second ion implantation step S7, the impurity region IR is formed. The impurity region IR is mainly formed in the epitaxial layer EPI located in the third region R3. The formation of the first portion SRa, the first portion DRAa and the impurity region IR is performed by ion implantation using the gate electrode GE as a mask. This ion implantation is performed on the epitaxial layer EPI and the semiconductor layer SOI located in the second region R2 and the epitaxial layer EPI and the semiconductor layer SOI located in the third region R3. That is, impurities are injected into the second region R2 and the third region R3 with the first region R1 covered with a mask (not shown). When the conductive type of the first portion SRa, the first portion DRAa and the impurity region IR is n-type, for example, arsenic and phosphorus are implanted by ion implantation. On the other hand, when the conductive type of the first portion SRa, the first portion DRAa and the impurity region IR is p-type, for example, boron is implanted by ion implantation.

Next, as shown in FIG. 14, in the sidewall spacer forming step S8, the sidewall spacer SWS is formed. In the sidewall spacer forming step S8, first, a material (insulating member) constituting the sidewall spacer SWS is formed by CVD or the like so as to cover the gate insulating film GO and the gate electrode GE. As described above, the material constituting the sidewall spacer SWS is, for example, a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film. In the formation of the sidewall spacer SWS, secondly, the material constituting the deposited sidewall spacer SWS is etched back so that the upper surface of the gate electrode GE is exposed.

Next, as shown in FIG. 15, in the third ion implantation step S9, the first active region AR1, the second active region AR2, the second portion SRb, and the second portion DRAb are formed. The first active region AR1, the second active region AR2, the second portion SRb, and the second portion DRAb are formed by ion implantation using the gate electrode GE and the sidewall spacer SWS as masks. This ion implantation is performed on the base material layer BULK located in the first region R1, the epitaxial layer EPI and the semiconductor layer SOI located in the second region R2, and the epitaxial layer EPI and the semiconductor layer SOI located in the third region R3. Is done. When the conductive type of the second portion SRb, the second portion DRAb, the first active region AR1 and the second active region AR2 is n-type, for example, arsenic and phosphorus are implanted by ion implantation. On the other hand, when the conductive type of the second portion SRb, the second portion DRAb, the first active region AR1 and the second active region AR2 is p type, for example, boron is implanted by ion implantation. Further, the concentration of impurities implanted in the third ion implantation step S9 is higher than the concentration of impurities implanted in the second ion implantation step S7.

Next, as shown in FIG. 16, in the silicide film forming step S10, the silicide film SIL is formed. In the formation of the silicide film SIL, first, titanium (Ti), cobalt (Co) and the like are formed on the semiconductor wafer WF. Second, heat treatment is performed on the formed film of titanium, cobalt, or the like. As a result, the silicon contained in the semiconductor layer SOI, the base material layer BULK, and the gate electrode GE reacts with titanium, cobalt, and the like, and the silicide film SIL is on the first active region AR1, the second active region AR2, and the source region SR. Above, on the drain region DRA and on the gate electrode GE. Unreacted titanium, cobalt, etc. are removed by etching.

Although not shown, a contact stopper film is formed on the semiconductor wafer WF after the silicide film forming step S10 and before the interlayer insulating film forming step S11. The contact stopper film is formed by forming a material constituting the contact stopper film by CVD or the like. The contact stopper film is made of, for example, silicon nitride.

Next, as shown in FIG. 17, in the interlayer insulating film forming step S11, the interlayer insulating film ILD is formed. In the interlayer insulating film forming step S11, first, a material constituting the interlayer insulating film ILD is formed on the semiconductor wafer WF by CVD or the like. In the interlayer insulating film forming step S11, secondly, the material constituting the formed interlayer insulating film ILD is flattened by CMP or the like. As described above, the material constituting the interlayer insulating film ILD is, for example, a silicon oxide.

Next, as shown in FIG. 18, in the contact plug forming step S12, the first contact plug CP1, the second contact plug CP2, and the third contact plug CP3 are formed. In the contact plug forming step S12, first, contact holes are formed in the interlayer insulating film ILD by dry etching or anisotropic etching such as RIE. In the contact plug forming step S12, secondly, the materials (conductive members) constituting the first contact plug CP1 to the third contact plug CP3 are embedded in the contact hole. As described above, the material constituting the first contact plug CP1 to the third contact plug CP3 is, for example, tungsten. In the contact plug forming step S12, thirdly, the materials constituting the first contact plug CP1 to the third contact plug CP3 protruding from the contact hole are removed by CMP or the like.

In the contact plug forming step S12, the contact plug electrically connected to the source region SR and the contact plug connected to the drain region DRA are similarly formed.

Next, in the wiring pattern forming step S13, the first wiring pattern WP1, the second wiring pattern WP2, and the third wiring pattern WP3 are formed. In the wiring pattern forming step S13, first, the materials constituting the first wiring pattern WP1 to the third wiring pattern WP3 are formed. In the wiring pattern forming step S13, secondly, the material constituting the first wiring pattern WP1 to the third wiring pattern WP3 formed is patterned by, for example, photolithography and dry etching or anisotropic etching such as RIE. Be etched.

As a result, the structure of the semiconductor device shown in FIG. 4 is formed. That is, the semiconductor wafer WF on which the first test pattern TP1 and the transistor Tr are formed is prepared.

In the inspection step S14, a non-defective product of the transistor Tr is determined. In the inspection step S14, first, the resistance value of the first test pattern TP1 is measured by passing a current between the first wiring pattern WP1 and the third wiring pattern WP3.

In the inspection step S14, secondly, the measured resistance value of the first test pattern TP1 and the reference range are compared. The reference range is, for example, a range of 97% or more and 103% or less of the resistance value when all the second contact plug CP2 and the third contact plug CP3 are normally formed.

If the measured resistance value of the first test pattern TP1 is within the reference range, it is determined that the transistor Tr is normally formed. On the other hand, if the measured resistance value of the first test pattern TP1 is out of the reference range, it is determined that the transistor Tr has not been formed normally.

In the cutting step S15, the semiconductor wafer WF is cut. Cutting of the semiconductor wafer WF is performed using, for example, a dicing blade or a laser. As described above, the semiconductor wafer WF is fragmented into a plurality of semiconductor devices according to the first embodiment.

The effects of the semiconductor device according to the first embodiment will be described below.
The second contact plug CP2 (third contact plug CP3) may be formed so as to penetrate the semiconductor layer SOI and the insulating layer BOX and reach the base material layer BULK when the growth failure of the epitaxial layer EPI occurs. be.

The second contact plug CP2 (third contact plug CP3) formed so as to reach the base material layer BULK is electrically connected to the first contact plug CP1 via the base material layer BULK. Therefore, when the second contact plug CP2 (third contact plug CP3) is formed so as to reach the base material layer BULK, the resistance value of the first test pattern TP1 is the second contact plug CP2 (third contact plug CP3). Is different from the resistance value of the first test pattern TP1 when is normally formed.

When the second contact plug CP2 (third contact plug CP3) is formed so as to reach the base layer BULK, the contact plug connected to the source region SR and the drain region DRA also reaches the base layer BULK. It is highly possible that it is formed in. Therefore, according to the semiconductor device according to the first embodiment, it is possible to determine whether or not the transistor Tr is normally formed by measuring the resistance value of the first test pattern TP1 and comparing it with the reference range. can.

Further, in the semiconductor device according to the first embodiment, by measuring the resistance value of the first test pattern TP1, which second contact plug CP2 (third contact plug CP3) is formed so as to reach the base material layer BULK. It can be determined whether or not it is done.

This will be specifically described below with the number of the second active region AR2 being 5. A wiring pattern connected to the second contact plug CP2 (third contact plug CP3), the second contact plug CP2 (third contact plug CP3), and the second contact plug CP2 (third contact plug CP3). It is assumed that the unit resistance is formed by the second active region AR2.

_{The unit resistance is R 1 to} R _{10 in} order from one end side of the virtual line L. The resistance value between the second contact plug CP2 (third contact plug CP3) formed so as to reach the base material layer BULK and the first contact plug CP1 is defined as R _BULK .

The equivalent circuit of the first test pattern TP1 when all the second contact plugs CP2 and the third contact plugs CP3 are normally formed is shown in FIG. An equivalent circuit when the 2 contact plug CP2) is formed so as to reach the base material layer BULK is shown in FIG.

When the l-th (natural number of l: 10 or less) contact plug from one end of the virtual line L is formed so as to reach the base material layer BULK, the resistance value of the first test pattern TP1, R _TP1, is as follows. It can be expressed by an expression.

In the above equation, when R _{1 to} R ₁₀ are calculated as 50 Ω and R _{BULK is calculated as 2000 Ω, the resistance value shown in Table 1 is obtained as R TP 1} , which is the resistance value of the first test pattern TP1 (hereinafter, this is described). Such a table is called a reference table).

As shown in Table 1, the resistance values of the first test pattern TP1 differ from each other depending on which second contact plug CP2 (third contact plug CP3) is formed so as to reach the base material layer BULK. Is shown. Therefore, by preparing a reference table as shown in Table 1 in advance and comparing the resistance value of the first test pattern TP1 with it, which second contact plug CP2 (third contact plug CP3) becomes the base material layer BULK. It is possible to identify whether it is formed to reach. Therefore, according to the semiconductor device according to the first embodiment, the defective portion can be easily identified.

In the above description, the case where either the second contact plug CP2 or the third contact plug CP3 is formed so as to reach the base material layer BULK has been described as an example, but two or more contact plugs are formed in the base material layer BULK. Even in the case of being formed so as to reach the above, it is possible to identify the defective part by performing the same calculation and creating a reference table in advance.

In the semiconductor device according to the first embodiment, when the virtual line L meanders, the first test pattern TP1 can be formed in a relatively narrow space.

(Second Embodiment)
The configuration of the semiconductor device according to the second embodiment will be described below. It should be noted that the points different from the configuration of the semiconductor device according to the first embodiment will be mainly described, and the duplicated description will not be repeated.

The semiconductor device according to the second embodiment includes a semiconductor substrate SUB, an interlayer insulating film ILD, a first test pattern TP1, and a transistor Tr. In this respect, the configuration of the semiconductor device according to the second embodiment is common to the configuration of the semiconductor device according to the first embodiment.

However, as shown in FIGS. 21 to 23, in the semiconductor device according to the second embodiment, the meandering first test pattern TP1 shown in FIG. 5 includes a fifth active region AR5 and a sixth active region AR6. , The fourth contact plug CP4, the fifth contact plug CP5, the fourth wiring pattern WP4, and the fifth wiring pattern WP5 are further provided. In this respect, the configuration of the semiconductor device according to the second embodiment is different from the configuration of the semiconductor device according to the first embodiment.

The fifth active region AR5 and the sixth active region AR6 are formed in the base material layer BULK. The insulating layer BOX and the semiconductor layer SOI are removed on the fifth active region AR5 and the sixth active region AR6. The fifth active region AR5 and the sixth active region AR6 are insulated and separated by being surrounded by the device separation membrane ISL.

The fifth active region AR5 is a second active region AR2 (hereinafter, the second active region AR2 is referred to as a seventh active region AR7) located between one end and the other end of the virtual line L in a plan view. Is located next to). The sixth active region AR6 is a second active region AR2 other than the seventh active region AR7 located between one end and the other end of the virtual line L in a plan view (hereinafter, this second active region AR2 is referred to as a second active region AR2. It is located next to the 8th active region (sometimes called AR8).

The fourth contact plug CP4 is formed in the interlayer insulating film ILD on the seventh active region AR7. The fifth contact plug CP5 is formed in the interlayer insulating film ILD on the eighth active region AR8. The fourth contact plug CP4 is electrically connected to the seventh active region AR7. The fifth contact plug CP5 is electrically connected to the eighth active region AR8.

The fourth wiring pattern WP4 and the fifth wiring pattern WP5 are formed on the interlayer insulating film ILD. The fourth wiring pattern WP4 is electrically connected to the second contact plug CP2 which is electrically connected to the seventh active region AR7. The fifth wiring pattern WP5 is electrically connected to the second contact plug CP2 which is electrically connected to the eighth active region AR8.

The fourth contact plug CP4 and the fifth contact plug CP5 are made of the same material as the first contact plug CP1 to the third contact plug CP3. The fourth wiring pattern WP4 and the fifth wiring pattern WP5 are formed of the same material as the first wiring pattern WP1 to the third wiring pattern WP3.

The method of manufacturing the semiconductor device according to the second embodiment will be described below. It should be noted that the points different from the method for manufacturing the semiconductor device according to the first embodiment will be mainly described, and the duplicated description will not be repeated.

The method for manufacturing the semiconductor device according to the second embodiment includes an element separation film forming step S1, a removing step S2, a first ion implantation step S3, a gate insulating film forming step S4, a gate electrode forming step S5, and epitaxial growth. It has a step S6, a second ion implantation step S7, a sidewall spacer forming step S8, and a third ion implantation step S9. The method for manufacturing the semiconductor device according to the first embodiment includes a silicide film forming step S10, an interlayer insulating film forming step S11, a contact plug forming step S12, a wiring pattern forming step S13, an inspection step S14, and a cutting step S15. And have more. In this respect, the method for manufacturing the semiconductor device according to the second embodiment is common to the method for manufacturing the semiconductor device according to the first embodiment.

However, the method for manufacturing the semiconductor device according to the second embodiment describes the details of the removal step S2, the third ion implantation step S9, the contact plug forming step S12, and the wiring pattern forming step S13 with respect to the details of the semiconductor device according to the first embodiment. It is different from the manufacturing method.

In the method for manufacturing a semiconductor device according to the second embodiment, in the removal step S2, the insulating layer BOX and the semiconductor layer SOI on the base material layer BULK on which the fifth active region AR5 and the sixth active region AR6 are formed in a later step. Is also removed at the same time. In the third ion implantation step S9, the fifth active region AR5 and the sixth active region AR6 are also formed.

Further, in the method for manufacturing a semiconductor device according to the second embodiment, the fourth contact plug CP4 and the fifth contact plug CP5 are also formed in the contact plug forming step S12. In the method for manufacturing a semiconductor device according to the second embodiment, the fourth wiring pattern WP4 and the fifth wiring pattern WP5 are also formed in the wiring pattern forming step S13.

The effects of the semiconductor device according to the second embodiment will be described below. It should be noted that the points different from the effects of the semiconductor device according to the first embodiment will be mainly described, and the duplicated description will not be repeated.

In the semiconductor device according to the second embodiment, the first test between the fourth wiring pattern WP4 and the third wiring pattern WP3 is performed by passing a current between the fourth wiring pattern WP4 and the third wiring pattern WP3. The resistance value of the pattern TP1 (hereinafter, may be referred to as the first resistance value) can be measured. Further, in the semiconductor device according to the second embodiment, by passing a current between the fifth wiring pattern WP5 and the third wiring pattern WP3, the fifth wiring pattern WP5 and the third wiring pattern WP3 are connected. The resistance value of one test pattern TP1 (hereinafter, may be referred to as a second resistance value) can be measured.

The first resistance value is compared with the first reference range. The first reference range is the second contact plug CP2 and the third contact plug CP3 electrically connected to the seventh active region AR7, the second contact plug CP2 and the second contact plug CP2 electrically connected to the fourth active region AR4. 3 The contact plug CP3 and the second contact plug CP2 and the third contact plug CP3 electrically connected to the second active region AR2 between the fourth active region AR4 and the seventh active region AR7 are all normally formed. In this case, the range is 97% or more and 103% or less of the resistance value of the first test pattern TP1 between the fourth wiring pattern WP4 and the third wiring pattern WP3.

When the first resistance value is within the first reference range, it is electrically connected to the second contact plug CP2, the third contact plug CP3, and the fourth active region AR4, which are electrically connected to the seventh active region AR7. The second contact plug CP2 and the third contact plug CP3 connected to the second contact plug CP2 and the second contact plug CP2 electrically connected to the second active region AR2 between the fourth active region AR4 and the seventh active region AR7. It can be determined that all the third contact plugs CP3 are normally formed. On the other hand, when the first resistance value is outside the first reference range, the second contact plug CP2 and the third contact plug CP3, which are electrically connected to the seventh active region AR7, and the fourth active region AR4 The second contact plug CP2 and the third contact plug CP3 electrically connected to the second contact plug CP3 and the second contact electrically connected to the second active region AR2 between the fourth active region AR4 and the seventh active region AR7. It can be determined that either the plug CP2 or the third contact plug CP3 is formed so as to reach the base material layer BULK.

Similarly, the second resistance value is compared to the second reference range. The second reference range is the second contact plug CP2 and the third contact plug CP3 electrically connected to the eighth active region AR8, the second contact plug CP2 and the second contact plug CP2 electrically connected to the fourth active region AR4. 3 The contact plug CP3 and the second contact plug CP2 and the third contact plug CP3 electrically connected to the second active region AR2 between the fourth active region AR4 and the eighth active region AR8 are all normally formed. In this case, the range is 97% or more and 103% or less of the resistance value of the first test pattern TP1 between the fifth wiring pattern WP5 and the third wiring pattern WP3.

When the second resistance value is within the second reference range, it is electrically connected to the second contact plug CP2 and the third contact plug CP3, which are electrically connected to the eighth active region AR8, and the fourth active region AR4. The second contact plug CP2 and the third contact plug CP3, and the second contact plug CP2 and the third contact plug CP2 and the third contact plug CP2 electrically connected to the second active region AR2 between the fourth active region AR4 and the eighth active region AR8. It can be determined that all the contact plugs CP3 are normally formed. On the other hand, when the second resistance value is outside the second reference range, the second contact plug CP2 and the third contact plug CP3, which are electrically connected to the eighth active region AR8, and the fourth active region AR4 The second contact plug CP2 and the third contact plug CP3 electrically connected to the second contact plug CP3 and the second contact electrically connected to the second active region AR2 between the fourth active region AR4 and the eighth active region AR8. It can be determined that either the plug CP2 or the third contact plug CP3 is formed so as to reach the base material layer BULK.

As described above, according to the semiconductor device according to the second embodiment, the approximate position of the second contact plug CP2 (third contact plug CP3) in which the poor formation occurs can be easily specified.

(Third Embodiment)
The configuration of the semiconductor device according to the third embodiment will be described below. It should be noted that the differences between the configuration of the semiconductor device according to the first embodiment and the configuration of the semiconductor device according to the second embodiment will be mainly described, and duplicate explanations will not be repeated.

The semiconductor device according to the third embodiment includes a semiconductor substrate SUB, an interlayer insulating film ILD, a first test pattern TP1, and a transistor Tr. In this respect, the configuration of the semiconductor device according to the third embodiment is common to the configuration of the semiconductor device according to the first embodiment.

However, as shown in FIG. 24, the semiconductor device according to the third embodiment further includes a second test pattern TP2 and a switch unit SW. In this respect, the semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment.

The second test pattern TP2 has the same configuration as the first test pattern TP1. The first test pattern TP1 of the semiconductor device according to the third embodiment may be the same as the first test pattern TP1 in the semiconductor device according to the first embodiment, and the first test pattern TP1 of the semiconductor device according to the second embodiment may be the same. 1 It may be the same as the test pattern TP1.

The second test pattern TP2 is arranged next to the first test pattern TP1 in a plan view. The switch unit SW is connected to the first test pattern TP1 and the second test pattern TP2. The switch unit SW is composed of, for example, a transistor.

More specifically, the switch unit SW is connected to the third wiring pattern WP3 of the first test pattern TP1 in the first state, and is connected to the third wiring pattern WP3 of the second test pattern TP2 in the second state. The switch unit SW can switch between the first state and the second state. The first wiring pattern WP1 of the first test pattern TP1 and the first wiring pattern WP1 of the second test pattern TP2 are electrically connected to each other.

The unit structure US including the pair of the first test pattern TP1 and the second test pattern TP2 and the switch unit SW is arranged in a matrix in a plan view. Each unit structure US is configured to be individually selectable by, for example, an address decoder circuit (not shown).

The method for manufacturing the semiconductor device according to the third embodiment will be described below. As described above, since the configuration of the second test pattern TP2 is the same as that of the first test pattern TP1, the method for manufacturing the semiconductor device according to the third embodiment is the method for manufacturing the semiconductor device according to the first embodiment. It is the same as the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. However, the method for manufacturing the semiconductor device according to the third embodiment is different from the method for manufacturing the semiconductor device according to the first embodiment and the method for manufacturing the semiconductor device according to the second embodiment with respect to the inspection step S14.

In the method for manufacturing a semiconductor device according to the third embodiment, in the inspection step S14, first, the switch unit SW selects the first test pattern TP1. Secondly, in the first test pattern TP1, the resistance value of the first test pattern TP1 is measured by passing a current between the first wiring pattern WP1 and the third wiring pattern WP3. Third, the switch unit SW selects the second test pattern TP2. Fourth, in the second test pattern TP2, the resistance value of the second test pattern TP2 is measured by passing a current between the first wiring pattern WP1 and the third wiring pattern WP3. Fifth, the measured resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 are compared.

The first to fifth steps described above are repeated for all unit structure US. As a result, when the resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 match for all the unit structures US, it is determined that the transistor Tr is normally formed. On the other hand, if the resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 do not match in at least one of the unit structures US, it is determined that the transistor Tr has not been formed normally. Will be done.

When the resistance value of the first test pattern TP1 is 97% or more and 103% or less of the resistance value of the second test pattern TP2, the resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 are different. It may be considered as a match.

Of all the unit structure US, the unit structure US in which the absolute value of the difference between the resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 is the largest is the second contact plug CP2 (third contact plug). It may be determined that the poor formation of CP3) has occurred.

Absolute value of the difference between the resistance value of the first test pattern TP1 and the reference resistance value in the unit structure US in which the absolute value of the difference between the resistance value of the first test pattern TP1 and the resistance value of the second test pattern TP2 is the largest. And by comparing the absolute value of the difference between the resistance value of the second test pattern TP2 and the reference resistance value, the second contact plug CP2 (third contact plug) can be applied to either the first test pattern TP1 or the second test pattern TP2. It may be determined whether or not there is a poor formation of CP3). More specifically, when the former is large, it is determined that the first test pattern TP1 has a poor formation of the second contact plug CP2 (third contact plug CP3), and when the latter is large, the second test pattern TP2 is determined. It may be determined that the second contact plug CP2 (third contact plug CP3) is poorly formed.

Here, the reference resistance value is the resistance value of the first test pattern TP1 (second test pattern TP2) when all the second contact plug CP2 and the third contact plug CP3 are normally formed.

The effects of the semiconductor device according to the third embodiment will be described below. In addition, the difference between the effect of the semiconductor device according to the first embodiment and the effect of the semiconductor device according to the second embodiment will be mainly described, and the duplicated description will not be repeated.

Since the first test pattern TP1 and the second test pattern TP2 have the same configuration and are arranged next to each other, if both are normally formed, they show substantially the same resistance value. Therefore, by measuring and comparing the resistance values of the first test pattern TP1 and the second test pattern TP2 that are adjacent to each other, it is easy to detect the presence or absence of poor formation of the second contact plug CP2 (third contact plug CP3). It becomes possible.

In addition, a part of the contents described in the above-described embodiment will be described below.
[Appendix 1]
Manufacturing method of semiconductor device including the following steps:
(A) The base material layer, the insulating layer formed on the base material layer, the semiconductor layer formed on the insulating layer, and the semiconductor layer and the insulating layer so that a part thereof reaches the base material layer. A step of preparing a substrate having a groove penetrating and an insulating film formed in the groove and having a first region, a second region, and a third region;
(B) After the step (a), the step of removing the semiconductor layer in the first region and the insulating layer in the first region to expose the base material layer in the first region;
(C) After the step (b), a step of forming a gate electrode on the semiconductor layer in the second region via a gate insulating film;
(D) After the step (c), by the epitaxial growth method, on the surface of the portion of the semiconductor layer in the second region exposed from the gate electrode, and on the surface of the semiconductor layer in the third region. , The process of forming the epitaxial layer;
(E) After the step (d), the ion implantation method is applied to each of the base material layer in the first region, the epitaxial layer in the second region, and the epitaxial layer in the third region. Step of forming a conductive impurity region;
(F) A step of forming an interlayer insulating film on the substrate after the step (e);
(G) After the step (f), the interlayer insulating film in the first region has a first contact hole reaching the impurity region in the first region, and the interlayer insulating film in the second region has the second region. A pair of second contact holes and a third contact hole reaching the impurity region in the above, and a pair of fourth contact holes and a fifth contact hole reaching the impurity region in the third region on the interlayer insulating film in the third region, respectively. The process of forming each contact hole;
(H) After the step (g), a conductive member is provided inside each of the first contact hole, the second contact hole, the third contact hole, the fourth contact hole, and the fifth contact hole. A process of forming a first contact plug, a second contact plug, a third contact plug, a fourth contact plug, and a fifth contact plug by embedding;
(I) After the step (h), the first wiring pattern and the second wiring pattern are formed on the interlayer insulating film, and the first contact plug straddles the first contact plug and the fourth contact plug. And the step of connecting the first wiring pattern to the fourth contact plug and connecting the second wiring pattern to the fifth contact plug;
(J) After the step (i), the first of the test patterns including the first contact plug, the fourth contact plug, the fifth contact plug, the first wiring pattern, and the second wiring pattern. A step of measuring the resistance value of the test pattern by passing a current between the one wiring pattern and the second wiring pattern of the test pattern;
(K) After the step (j), the resistance value of the test pattern measured in the step (j) is compared with another value, and the gate electrode, the gate insulating film, and the said in the second region. A step of inspecting a MISFET composed of an epitaxial layer.

[Appendix 2]
In the method for manufacturing a semiconductor device described in Appendix 1,
The substrate has a plurality of chip regions and a scribe region located between two chip regions adjacent to each other in the plurality of chip regions.
The second region is located within the chip region and
The first region and the third region are located in the scribe region.

[Appendix 3]
In the method for manufacturing a semiconductor device described in Appendix 1,
The substrate has a plurality of chip regions and a scribe region located between two chip regions adjacent to each other in the plurality of chip regions.
The first region to the third region is located in the chip region.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

AR1 1st active region, AR2 2nd active region, AR3 3rd active region, AR4 4th active region, AR5 5th active region, AR6 6th active region, AR7 7th active region, AR8 8th active region, BOX insulating Membrane, BULK substrate layer, CH chip area, CP1 1st contact plug, CP2 2nd contact plug, CP3 3rd contact plug, CP4 4th contact plug, CP5 5th contact plug, DSW dummy sidewall spacer, DRA drain area , DRAa 1st part, DRAb 2nd part, EPI epitaxial layer, GE gate electrode, GO gate insulating film, ILD interlayer insulating film, ISL element separating film, IR impurity region, L virtual line, R1 1st region, R2 2nd Region, R3 3rd region, S1 element separation film forming step, S2 removal step, S3 1st ion injection step, S4 gate insulating film forming step, S5 gate electrode forming step, S6 epitaxial growth step, S7 2nd ion injection step, S8 Sidewall spacer forming step, S9 third ion injection step, S10 VDD film forming step, S11 interlayer insulating film forming step, S12 contact plug forming step, S13 wiring pattern forming step, S14 inspection step, S15 cutting step, SOI semiconductor layer, SC screen area, SR source area, SRa 1st part, SRb 2nd part, SUB semiconductor substrate, SW switch part, SWS sidewall spacer, TEG test area, TP1 1st test pattern, TP2 2nd test pattern, Tr transistor, US unit structure, WF semiconductor wafer, WP1 first wiring pattern, WP2 second wiring pattern, WP3 third wiring pattern, WP4 fourth wiring pattern, WP5 fifth wiring pattern, WR well area.

Claims (17)

A base material layer, an insulating layer formed on the base material layer, and a semiconductor substrate having a semiconductor layer formed on the insulating layer,
The interlayer insulating film formed on the semiconductor substrate and
A first wiring pattern formed on the interlayer insulating film, a plurality of second wiring patterns formed on the interlayer insulating film, a third wiring pattern formed on the interlayer insulating film, and formed on the base material layer. The first active region formed, the plurality of second active regions formed on the semiconductor layer, the first contact plug formed in the interlayer insulating film on the first active region, and the plurality of second active regions. A first test pattern having a pair of second and third contact plugs formed in the interlayer insulating film above each of the regions.
With
The plurality of second active regions are arranged on a virtual line including one end and the other end in a plan view.
The first active region is arranged next to the third active region on the one end of the virtual line among the plurality of second active regions in a plan view.
The first contact plug is connected to the first active region without passing through the insulating layer and the semiconductor layer.
The pair of second contact plugs and the third contact plugs are connected to the plurality of second active regions, respectively.
The first wiring pattern is connected to each of the first contact plug and the second contact plug connected to the third active region.
Each of the plurality of second wiring patterns is arranged adjacent to each other in the plurality of second active regions via the second contact plug and the third contact plug. Is electrically connected to
The third wiring pattern is a semiconductor that is electrically connected to the third contact plug connected to the fourth active region on the other end of the virtual line among the plurality of second active regions. Device. The semiconductor device according to claim 1, wherein the semiconductor layer has a first region in which the plurality of second active regions are formed and a second region in which a source and a drain constituting a MISFET are formed. The semiconductor device according to claim 2, wherein the virtual line meanders in a plan view. The first test pattern is
A sixth active region formed on the base material layer and arranged next to a fifth active region between the one end and the other end in a plan view among the plurality of second active regions. ,
A fourth contact plug formed in the interlayer insulating film on the sixth active region and connected to the sixth active region without interposing the insulating layer and the semiconductor layer.
A fourth wiring pattern formed on the interlayer insulating film and connected to the fifth active region and connected to each of the second contact plug and the fourth contact plug.
The semiconductor device according to claim 3 , further comprising. The semiconductor device according to claim 2, wherein a second test pattern having the same configuration as the first test pattern is arranged next to the first test pattern in a plan view. The semiconductor device according to claim 5, wherein the pair of the first test pattern and the second test pattern arranged adjacent to each other are arranged in a matrix in a plan view. A process of preparing a semiconductor wafer having a MISFET and a first test pattern,
A step of determining a non-defective product of the MISFET using the first test pattern, and
With
The semiconductor wafer includes a base material layer, an insulating layer formed on the base material layer, a semiconductor substrate having a semiconductor layer formed on the insulating layer, and an interlayer insulating film formed on the semiconductor substrate. Have,
The first test pattern includes a first wiring pattern formed on the interlayer insulating film, a plurality of second wiring patterns formed on the interlayer insulating film, and a third wiring pattern formed on the interlayer insulating film. It was formed in the wiring pattern, the first active region formed on the base material layer, the plurality of second active regions formed on the semiconductor layer, and the interlayer insulating film on the first active region. It has a first contact plug and a pair of second contact plugs and a third contact plug formed in the interlayer insulating film on each of the plurality of second active regions.
The plurality of second active regions are arranged on a virtual line including one end and the other end in a plan view.
The first active region is arranged next to the third active region on the one end of the virtual line among the plurality of second active regions in a plan view.
The first contact plug is connected to the first active region without passing through the insulating layer and the semiconductor layer.
The pair of second contact plugs and the third contact plugs are connected to the plurality of second active regions, respectively.
The first wiring pattern is connected to the first contact plug and the second contact plug connected to the third active region.
Each of the plurality of second wiring patterns is arranged adjacent to each other in the plurality of second active regions via the second contact plug and the third contact plug. Is electrically connected to
The third wiring pattern is connected to the third contact plug connected to the fourth active region on the other end of the virtual line among the plurality of second active regions.
The source and drain of the MISFET are formed in the semiconductor layer, and the source and drain of the MISFET are formed in the semiconductor layer.
The gate electrode of the MISFET is formed on the semiconductor layer, and is formed on the semiconductor layer.
The step of determining the non-defective product includes a step of measuring the resistance value of the first test pattern by passing a current between the first wiring pattern and the third wiring pattern, and a step of preparing the resistance value in advance. A method for manufacturing a semiconductor device, which comprises a step of comparing the resistance value with a reference range. The step of determining the non-defective product includes a step of measuring the resistance value of the first test pattern and then comparing the measured resistance value with a reference range prepared in advance.
When the compared resistance value is within the reference range, the MISFET is determined to be a non-defective product, while when the compared resistance value is outside the reference range, the MISFET is determined to be defective. The method for manufacturing a semiconductor device according to claim 7. The method for manufacturing a semiconductor device according to claim 8, wherein the virtual line meanders in a plan view. The first test pattern is
A sixth active region formed on the base material layer and arranged next to a fifth active region between the one end and the other end in a plan view, among the second active regions.
A fourth contact plug formed in the interlayer insulating film on the sixth active region and connected to the sixth active region.
A fourth wiring pattern formed on the interlayer insulating film and connected to the fifth active region and connected to each of the second contact plug and the fourth contact plug.
The method for manufacturing a semiconductor device according to claim 9 , further comprising. The semiconductor wafer has a chip region and a scribe region surrounding the chip region in a plan view.
The MISFET is arranged in the chip region, and the MISFET is arranged in the chip region.
The method for manufacturing a semiconductor device according to claim 8, wherein the first test pattern is arranged in the scribe region. The semiconductor wafer has a chip region and a scribe region surrounding the chip region in a plan view.
The method for manufacturing a semiconductor device according to claim 8, wherein each of the MISFET and the first test pattern is arranged in the chip region. In a plan view, a second test pattern having the same configuration as the first test pattern is arranged next to the first test pattern.
The step of determining a non-defective product is
(A1) A step of measuring the first resistance value of the first test pattern by passing a current between the first wiring pattern and the third wiring pattern of the first test pattern.
(A2) A step of measuring the second resistance value of the second test pattern by passing a current between the first wiring pattern and the third wiring pattern of the second test pattern.
(A3) After the step (a2), a step of comparing the measured first resistance value and the second resistance value, and
Have,
When the first resistance value and the second resistance value match, the MISFET is determined to be a non-defective product, while when the first resistance value and the second resistance value are different, the MISFET is determined to be a non-defective product. The method for manufacturing a semiconductor device according to claim 7, which is determined to be defective. The method for manufacturing a semiconductor device according to claim 13, wherein the pair of the first test pattern and the second test pattern arranged adjacent to each other are arranged in a matrix in a plan view. After the step (a1), the switch provided between the third wiring pattern of the first test pattern and the third wiring pattern of the second test pattern is switched, and then the step (a2) is performed. The method for manufacturing a semiconductor device according to claim 13. The semiconductor wafer has a chip region and a scribe region surrounding the chip region in a plan view.
The MISFET is arranged in the chip region, and the MISFET is arranged in the chip region.
The method for manufacturing a semiconductor device according to claim 15, wherein the first test pattern is arranged in the scribe region. The semiconductor wafer has a chip region and a scribe region surrounding the chip region in a plan view.
The method for manufacturing a semiconductor device according to claim 15, wherein each of the MISFET and the first test pattern is arranged in the chip region.

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