JP6932439B2 - Digital signal processor - Google Patents

Description

The present invention relates to a digital signal processing device using ΔΣ modulation.

As a technology for expressing linear signals with high efficiency with a nonlinear amplifier used in digital radios, etc., linear amplification is performed using a saturation amplifier by LINK (Linear Amplifier with Nonlinear Components), and phase control type orthogonal modulation. Those that perform linear amplification using a device are known. The phase-controlled quadrature modulation method can eliminate spurious at low amplitude, which is a problem of the LINK method, but has a problem that the circuit scale is increased by the D / A converter. Further, as a problem common to the LINK method and the phase control type quadrature modulation method, there is a problem that a wide band cannot be supported. This is because switching is performed at the transmission frequency, and it is necessary to switch the LPF (Low Pass Filter) when the transmission frequency is significantly changed.

A delta-sigma modulator is known as one of the digital signal processing devices that solves the problems of the LINK system and the phase control type orthogonal modulation system (see, for example, Patent Document 1). This ΔΣ modulator has a circuit configuration similar to that of the ΔΣ modulator 100 shown in FIG. 10A, and mainly includes a loop filter circuit 101 and a quantizer 102, and an input signal U (z) is input. Then, the amplitude information is expanded in the time axis direction of a specific sampling space, and the output signal V (z), which is a discrete signal expressed by the density of the discrete-time signal, is output.

The loop filter circuit 101 has a circuit configuration for inputting an input signal U (z) and feeding back an output signal V (z) output from the quantizer 102 to perform subtraction processing and the like. The signal Y (z) output from the filter circuit 101 is configured to be input to the quantizer 102. The loop filter circuit 101 is composed of, for example, elements such as a delay element and a subtractor. The quantizer 102 is connected to the output side of the loop filter circuit 101 so that the signal Y (z) output from the loop filter circuit 101 is input, and the output signal V (z) is output. , A loop filter circuit 101 is connected to the output side thereof so that feedback input is performed.

An example of the input signal U (z) of the ΔΣ modulator 100 is shown in the waveform L11 of FIG. 10 (b), and an example of the output signal V (z) is shown in FIG. 10 (c). The ΔΣ modulator 100 can expand the amplitude information in the time axis direction and control it by the density of the discrete-time signal, as shown in the output signal V (z) shown in FIG. 10 (c). It also has a noise shaving function that pushes noise out of the band. It is a modulator that can eliminate spurious emissions at low amplitude with high efficiency and can also widen the bandwidth of the input signal.

However, in order to perform signal processing using such a delta-sigma modulator 100 with practical accuracy, that is, with an accuracy that can comply with the regulations of the Radio Law and the like, sampling of several times to several hundred times the frequency of the output signal is performed. It is necessary to operate at a frequency, and it has been an issue to realize a configuration for performing such high-speed processing.

Further, as a technique for speeding up a filter circuit having a closed loop structure, Scattered Look-Ahead is known (see, for example, Non-Patent Document 1). This Scattered Look-Ahead is one of the pipeline feedback processes for high-speed calculation of a filter circuit having a closed loop structure.

Japanese Unexamined Patent Publication No. 2014-230113

K. K. Parhi (Dept.of Electr.Eng, Minnesota Univ, Minneapolis, MN, USA..) Al., "Pipeline Interleaving and Parallelism in Recursive Digital Filter-Part I: Pipelining Using Scattered Look-Ahead and Decomposition" IEEE Transactions on Acoustics, Speech, and Signal Processing (Vol. 37, IEEE: 7, Jul. 1989)

Generally, in order to speed up a signal processing system, a method of parallelizing circuits and executing a large number of operations at one time is used. However, since the delta-sigma modulator has a closed loop structure, parallelization is difficult. This is because in a closed-loop circuit, the output signal V (t) at a certain time t depends on the output V (t−Δt) before the discrete time step Δt, and no output can be obtained unless the output result one step before the time is confirmed. Because. Therefore, how to reduce the delay in the closed loop circuit has been an issue.

Therefore, an object of the present invention is to provide a digital signal processing apparatus that suppresses the latency associated with the loop processing of delta-sigma modulation and realizes high-speed signal processing.

In order to solve the above problems, the invention according to claim 1 is a digital signal processing device including a quantization device that converts an input signal into a discrete signal having a desired number of bits, and the input signal is input. A feedback processing unit that combines the first calculation result signal that is output after performing a predetermined calculation with the input signal and outputs the first combined signal, and a signal that is input to the quantizer. Is fed back, the second calculation result signal that is output after performing a predetermined calculation is combined with the first composite signal, and the second composite signal is output. A storage element in which an output signal output from the quantizer is fed back and a plurality of types of third calculation result signals, which are calculation results obtained by performing predetermined calculations in advance for all the output patterns of the output signals, are stored. The third calculation result signal corresponding to the output signal is read from the storage element and output, and the output third calculation result signal is combined with the second composite signal to obtain the above. The first feedback processing unit includes a second feedback processing unit that outputs a third composite signal input to the quantizer, and the first feedback processing unit is a predetermined transfer function (specifically, the equation 5 described later). ) .

In the present invention, a storage element is provided in the second feedback processing unit, and a plurality of types of third calculation result signals in which predetermined calculations are performed in advance for all the output patterns of the output signals output from the quantizer are provided. Be remembered. The third calculation result signal is read out and output corresponding to the output signal.

The invention according to claim 2 is a digital signal processing apparatus including a quantization device that converts an input signal into a discrete signal having a desired number of bits, and the input signal is input and a predetermined calculation is performed. The feed-forward processing unit, in which the first calculation result signal output is combined with the input signal and the first combined signal is output, and the signal input to the quantizer are feedback-input to perform a predetermined calculation. Is performed and the second calculation result signal output is combined with the first composite signal to output the second composite signal. The first feedback processing unit and the output output from the quantizer. It is provided with a storage element in which a plurality of types of third calculation result signals, which are calculation results obtained by inputting a signal as feedback input and performing predetermined calculations in advance for all the output patterns of the output signal, are provided, and corresponds to the output signal. The third calculation result signal is read from the storage element and output, and the output third calculation result signal is combined with the second composite signal and input to the quantizer. A second feedback processing unit for outputting the combined signal of 3 is provided, and the first feedback processing unit is assumed to have a predetermined transmission function (specifically, the equation 5 described later). A first delay element that delays the composite signal of 1 by one clock, _{a first multiplier that multiplies the output result of the first delay element by a constant − (a 0} + a 1), and the first composite signal. A second delay element that delays 2 clocks, a second multiplier that multiplies the output result of the second delay element by a constant a ₀ a ₁ , the output result of the first multiplier, and the second A feed forward composed of a first adder for adding the output result of the multiplier and a second adder for adding the output result of the first adder and the first composite signal. A third delay element that includes a processing unit and delays the second composite signal by one clock, and a third delay element that multiplies _{the output result of the third delay element by a constant − (a 0} ² + a ₁ ^2). A multiplier, a fourth delay element that delays the third composite signal by two clocks, a fourth _{multiplier that multiplies the output result of the fourth delay element by a constant a 0} ² a ₁ ² , and the above. A fifth delay element that delays the output result of the third multiplier by one clock, a sixth delay element that delays the output result of the fourth multiplier by one clock, and an output result of the fifth delay element. And the output result of the sixth delay element are added together and output as the second calculation result signal. The adder is provided with a fourth adder that negatively feeds back the second calculation result signal and synthesizes the output result of the second adder .

The inventor of the present application has obtained the output signal of the feedback input and the output signal of the output value selected from the output candidate values calculated in advance by the experiment using the model circuit of the digital signal processing device using the above-mentioned ΔΣ modulator. It was confirmed that it was possible to suppress the latency associated with the loop processing.

According to the invention of claim 1, a plurality of types in which a storage element is provided in the second feedback processing unit and predetermined calculations are performed in advance for all the output patterns of the output signals output from the quantizer. Since the third calculation result signal is stored and read out corresponding to the output signal and output, it is possible to select and read the output value from the storage element when the output one step before in the closed loop circuit is determined. Since this is possible, the latency associated with the loop processing of delta-sigma modulation can be suppressed. This makes it possible to provide a digital signal processing device that realizes high-speed signal processing.

According to the second aspect of the present invention, the transfer function representing the first feedback processing unit is subjected to pipeline feedback processing that transforms the transfer function so that only a predetermined delay element appears, so that the processing in the closed loop circuit is further speeded up. It becomes possible to do.

It is a block diagram which shows the transfer function of the digital signal processing apparatus 1 which concerns on embodiment of this invention. It is a block diagram which shows the state which the 2nd feedback processing part 4 of FIG. 1 was converted to output the output value calculated in advance. It is a block diagram which shows the state which replaced the adder 421, 422, ..., 42n and a selector 43 in the 2nd feedback processing part 4A of FIG. 2 with a storage element 44 and an adder 42. FIG. 3 is a block diagram showing a state in which the transfer function of the first feedback processing unit 3 in FIG. 3 is converted into the feedback processing unit 3C. FIG. 3 is a block diagram showing a state in which the transfer function of the first feedback processing unit 3C of FIG. 4 is converted into the feedback processing unit 3D. FIG. 5 is a block diagram showing a state in which the transfer function of the first feedback processing unit 3D in FIG. 5 is converted into the feedback processing unit 3E. It is a block diagram which shows the digital signal processing apparatus 1F which is the model circuit for verifying the operation of the transfer function of the digital signal processing apparatus 1B of FIG. It is a block diagram which shows the digital signal processing apparatus 1G which is the model circuit for verifying the operation of the transfer function of the digital signal processing apparatus 1B of FIG. It is a graph which shows the operation verification result of the transfer function of the digital signal processing apparatus 1F of FIG. It is an example which shows the ΔΣ modulator 100 of the conventional example, the circuit block diagram (a) which shows the ΔΣ modulator 100, the graph (b) which shows the waveform L11 of the input signal input to the ΔΣ modulator 100, and the ΔΣ modulator. It is a graph (c) which shows the waveform L12 of the pulse output signal output from 100.

Hereinafter, the present invention will be described based on the illustrated embodiment.

The transfer function of the digital signal processing device 1 according to the embodiment of the present invention is represented by a block diagram as shown in FIG. First, a method of deriving the transfer function of the digital signal processing device 1 will be described below.

In order to suppress the latency (delay time) of the closed loop of the ΔΣ modulator 100 as shown in FIG. 10A, it is effective to reduce the processing load by moving the arithmetic processing inside the loop to the outside. be. This ΔΣ modulator 100 is considered as a primary 1-bit ΔΣ modulator. At this time, since the output value of the output signal V (z) is either +1 or -1, the loop filter circuit is used for each case of V (z) = + 1 and V (z) = -1. The value of the signal Y (z) output from 101 is calculated in advance, and when the output value of the output signal V (z) is determined, one of the calculated values is selected in advance. Conceivable. With this configuration, the latency of the closed loop is suppressed, so that the processing load can be reduced.

Consider the case where the above method is applied to an nth-order 1-bit ΔΣ modulator. Assuming that the transfer function of the ΔΣ modulator is STF (z), the noise transfer function of the ΔΣ modulator is NTF (z), and the quantization error is E (z) = V (z) −Y (z), the output signal V (Z) is represented by the following formula 1.

とすると、ループフィルタ回路１０１から出力される信号Ｙ（ｚ）は以下の数式３により表される。

here,

Then, the signal Y (z) output from the loop filter circuit 101 is expressed by the following mathematical formula 3.

The transfer function at this time is represented by a block diagram such as the digital signal processing device 1 shown in FIG. The digital signal processing device 1 mainly includes a feedforward processing unit 2, a first feedback processing unit 3, a second feedback processing unit 4, and a quantizer 5.

The feed-forward processing unit 2 receives an input signal U (z), processes the transmission function A (z), which is a predetermined operation on this signal, by the operator 21, and the first operation result is the first operation. This is a place where the calculation result signal A (z) U (z) and the input signal U (z) are added by the adder 22 and the first combined signal X (z) is output.

In the first feedback processing unit 3, a signal (third composite signal Y (z) described later) input to the quantizer 5 is fed back and input, and a transfer function B (z) which is a predetermined operation for this signal. Is performed by the operator 31, and the second calculation result signal B (z) Y (z), which is the calculation result, is negatively fed back by the adder 32 to be combined with the first composite signal X (z). This is the location where the composite is performed and the second composite signal W (z) is output.

In the second feedback processing unit 4, the output signal V (z) is input, the processing of the transmission function C (z), which is a predetermined calculation for this signal, is performed by the operator 41, and the signal which is the calculation result is performed. This is a place where C (z) V (z) is positively fed back by the adder 42, combined with the second combined signal W (z), and the third combined signal Y (z) is output.

The quantizer 5 is a device substantially similar to the quantizer 102 shown in FIG. 10 (a).

In Equation 3, since the transfer function A (z) and the transfer function B (z) are nth-order polynomials, the transfer function C (z) is also an nth-order polynomial, and the signal C (z) V (z) The calculation result has 2 ⁿ kinds of values. Therefore, in the digital signal processing device 1 shown in FIG. 1, ^{a block configuration is conceivable in which 2 n} types of calculations are performed in advance and the results are selected in later processing. The transfer function configured in this way is represented by a block diagram such as the digital signal processing device 1A shown in FIG.

This digital signal processing device 1A is different from the digital signal processing device 1 shown in FIG. 1 in that it includes a second feedback processing unit 4A instead of the second feedback processing unit 4 shown in FIG. The second feedback processing unit 4A receives the output signal V (z) output from the quantizer 5 and delays the signal by 1, 2, ..., N clocks, delay elements 411, 421, ... The adders 421, 422, ... , 42n and a selector 43 that selects an input signal based on the delay signal output from the delay elements 411, 421, ..., 41n.

In the second feedback processing unit 4A, the output signal V (z) output from the quantizer 5 is output to the selector 43 as a delay signal by the delay elements 411, 421, ..., 41n. Further, the third calculation result signal C (z) Vp (z) calculated in advance is added by the adders 421, 422, ..., 42n. Then, in the selector 43, one value is selected from n third calculation result signals C (z) Vp (z) based on the delay signal, and the quantizer 5 is used as the third composite signal Y (z). Is output to. This makes it possible to suppress the latency of the closed loop.

In the configuration of the digital signal processing device 1A of FIG. 2, n adders are required. Therefore, by providing a storage element that stores the third calculation result signal C (z) Vp (z) calculated in advance, it is possible to reduce the hardware resources. The transfer function configured in this way is represented by a block diagram such as the digital signal processing device 1B shown in FIG.

The digital signal processing device 1B replaces the adders 421, 422, ..., 42n and the selector 43 of the second feedback processing unit 4A shown in FIG. 2 with a pre-calculated third calculation result signal C ( A second feedback process including a storage element 44 that stores z) Vp (z) and an adder 42 that adds the third calculation result signal C (z) Vp (z) stored in the storage element 44. The part 4B is provided.

The output signal V (z) output from the quantizer 5 is output to the storage element 44 as a delay signal by the delay elements 411, 421, ..., 41n. Then, one value is selected from the n third calculation result signals C (z) Vp (z) stored in the storage element 44 based on the delay signal, and is positively fed back by the adder 42 to be quantized. It is output to the vessel 5. This also makes it possible to reduce closed-loop latency and reduce hardware resources.

この伝達関数を有する第１のフィードバック処理部３の例として、第１のフィードバック処理部３Ｃを図４に示す。この第１のフィードバック処理部３Ｃは、図１に示す第１のフィードバック処理部３の演算子３１に代えて、第３の合成信号Ｙ（ｚ）が入力され、１及び２クロックだけ信号を遅延させる遅延素子３１１，３１２と、定数ａ_０＋ａ_１を乗算する乗算器３３１と、定数ａ_０ａ_１を乗算する乗算器３３２と、乗算器３３１の出力結果と乗算器３３２の出力結果とを加算する加算器３４とを備えている点において、図１に示す第１のフィードバック処理部３と異なる。 Next, a case where the above-mentioned Scattered Look-Ahead, which is one of the pipeline feedback processes, is performed in order to speed up the closed loop in the first feedback processing unit 3 of the digital signal processing device 1 shown in FIG. 1 will be described. .. Here, it is assumed that the first feedback processing unit 3 has a transfer function as shown in the following mathematical formula 4.

As an example of the first feedback processing unit 3 having this transfer function, the first feedback processing unit 3C is shown in FIG. In the first feedback processing unit 3C, a third composite signal Y (z) is input instead of the operator 31 of the first feedback processing unit 3 shown in FIG. 1, and the signal is delayed by 1 and 2 clocks. The delay elements 311, 312, the multiplier 331 that multiplies the _{constant a 0} + a _{1 , the multiplier 332 that multiplies the constant a 0} a ₁ , and the output result of the multiplier 331 and the output result of the multiplier 332 are added. It differs from the first feedback processing unit 3 shown in FIG. 1 in that it is provided with an adder 34.

すると、分母の項にｚ^−１が現れない形に変形することができる。このような伝達関数を有する第１のフィードバック処理部３の例として、第１のフィードバック処理部３Ｄを図５に示す。この第１のフィードバック処理部３Ｄは、図４に示す第１のフィードバック処理部３Ｃの遅延素子３１１，３１２に代えて、第３の合成信号Ｙ（ｚ）が入力され、２及び４クロックだけ信号を遅延させる遅延素子３１１Ｄ，３１２Ｄを、乗算器３３１，３３２に代えて、定数−（ａ_０ ^２＋ａ_１ ^２）を乗算する乗算器３３１Ｄ、及び定数ａ_０ ^２ａ_１ ^２を乗算する乗算器３３２Ｄを備え、新たに１及び２クロックだけ信号を遅延させる遅延素子３５１，３５２と、定数−（ａ_０＋ａ_１）を乗算する乗算器３６１と、定数ａ_０ａ_１を乗算する乗算器３６２と、乗算器３６１の出力結果と乗算器３６２の出力結果とを加算する加算器３７１と、加算器３７１の出力結果と第１の合成信号Ｘ（ｚ）とを加算する加算器３７２とから構成されるフィードフォワード処理部を備えている点において、図４に示す第１のフィードバック処理部３Ｃと異なる。 Here, the above formula 4 is converted as in the following formula 5.

Then, it can be transformed into a form in ^{which z -1} does not appear in the denominator term. As an example of the first feedback processing unit 3 having such a transfer function, the first feedback processing unit 3D is shown in FIG. The first feedback processing unit 3D receives a third composite signal Y (z) in place of the delay elements 311, 312 of the first feedback processing unit 3C shown in FIG. 4, and signals only 2 and 4 clocks. a delay element 311D delaying, the 312D, in place of the multipliers 331 and 332, the constant _{^{- (a 0 2 + a 1}} 2) multiplier 331D for multiplying, and a multiplier for multiplying the constants _a ^{0 2} _a ¹ 2 332D A delay element 351,352 that newly delays the signal by 1 and 2 clocks, a multiplier 361 that multiplies the _{constant − (a 0} + a ₁ ), and a multiplier 362 that multiplies the _{constant a 0} a _1. It is composed of an adder 371 that adds the output result of the multiplier 361 and the output result of the multiplier 362, and an adder 372 that adds the output result of the adder 371 and the first composite signal X (z). It differs from the first feedback processing unit 3C shown in FIG. 4 in that it includes a feed-forward processing unit.

Further, as an example of optimizing the above equation 5, the first feedback processing unit 3E is shown in FIG. The first feedback processing unit 3E receives a second combined signal W (z) instead of the delay elements 311D and 312D of the first feedback processing unit 3D shown in FIG. 5, and delays the signal by one clock. Delay element 311E to delay the signal, delay element 312E to delay the signal by 2 clocks when the third combined signal Y (z) is input, and delay element to delay the signal by 1 clock when the output result of the multiplier 331D is input. It differs from the first feedback processing unit 3D shown in FIG. 5 in that it includes a 313E and a delay element 314E in which the output result of the multiplier 332D is input and the signal is delayed by one clock. With such a transfer function configuration, the feedforward processing unit is not a closed loop, so high speed can be achieved by performing parallel processing, and in the closed loop as in the delay elements 312E, 313E, and 314E. By reducing the processing performed in, the processing speed can be increased.

The inventor of the present application has calculated in advance the output signal V (z) input as feedback by an experiment using the digital signal processing device 1F shown below, which is a model circuit of the digital signal processing device 1B shown in FIG. It was confirmed that the output signals of the third calculation result signal C (z) Vp (z) match, and it is possible to suppress the latency associated with the loop processing. This result will be described below with reference to FIGS. 7 to 9.

The digital signal processing device 1F and the digital signal processing device 1G, which are model circuits for verifying the operation of the transfer function of the digital signal processing device 1B of FIG. 3, are shown in FIGS. 7 and 8. The digital signal processing device 1F shown in FIG. 7 is composed of a calculation unit 21F in which the feed forward processing unit 2 of FIG. 3 is composed of eight delay elements and eight multipliers, and is a first feedback processing unit. 3 is composed of a calculation unit 31F composed of eight delay elements and four multipliers. Further, the second feedback processing unit 4B is composed of a calculation unit 41F composed of eight delay elements and eight multipliers. Further, it is provided with a quantizer 5F.

The digital signal processing device 1G shown in FIG. 8 includes a calculation unit 21G and a calculation unit 31G having the same configuration as the calculation unit 21F and the calculation unit 31F of the digital signal processing device 1F shown in FIG. 7. Further, the second feedback processing unit 4B is composed of a storage unit 44G in which the calculation result of the transfer function C (z) is stored, and a LUT (LookUp Table) 45 for comparing the calculation results of the eight delay elements. Has been done.

FIG. 9 shows the result of operation verification comparing the output result of the digital signal processing device 1F and the output result of the digital signal processing device 1G. The waveform L1 shown in FIG. 9 is a graph showing the third calculation result signal C (z) Vp (z) by the digital signal processing device 1G of FIG. 8, and the waveform L2 is based on the digital signal processing device 1F of FIG. It is a graph which shows the signal C (z) V (z), and the waveform L3 is a graph which shows the difference between the 3rd calculation result signal C (z) Vp (z) and the signal C (z) V (z). be. As shown in the waveform L3, a difference occurs immediately after the start, but the difference becomes 0 after a lapse of a predetermined time. From this, since the third calculation result signal C (z) Vp (z) and the signal C (z) V (z) are in agreement, the output signal output from the quantizer 5 in FIG. 3 is shown. Instead of using V (z) as a delay signal via the delay elements 411, 421, ..., 41n, the third calculation result signal C (z) Vp (z) stored in the storage unit 44. It can be said that it is possible to use. This also makes it possible to reduce closed-loop latency and reduce hardware resources.

As described above, according to the digital signal processing device 1B, when the delay elements 411, 421, ..., 41n output as a delay signal, the third calculation result signal C (stored in the storage unit 44) ( z) One value is selected from Vp (z) and output to the quantizer 5. As a result, the output value is read out from the storage element and output when the output one step before in the closed loop circuit is determined without waiting for the elapse of the sampling cycle of the output signal V (z), so that the latency of the closed loop is reached. It is also possible to reduce hardware resources. This makes it possible to provide a digital signal processing device that realizes high-speed signal processing.

Further, according to the digital signal processing device 1B, since the storage unit 44 stores the third calculation result signal C (z) Vp (z), as shown in FIG. 9, the signal C (z) V It is possible to output an accurate third calculation result signal C (z) Vp (z) having no difference from (z). Further, since the first feedback processing unit 3E performs Scattered Look-Ahead, which is one of the pipeline feedback processing, the processing in the closed loop circuit can be further speeded up.

Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above-described embodiment, and even if there is a design change or the like within a range that does not deviate from the gist of the present invention. Included in the invention. For example, in the above embodiment, an eighth-order 1-bit digital signal processing device is used as a model circuit, but the present embodiment is not limited to this embodiment.

1,1A, 1B Digital signal processor 2 Feed forward processing unit 3 First feedback processing unit 4, 4A Second feedback processing unit 5 Quantifier 21 Operator 22 Adder 31 Operator 32 Adder 41 Operator 42 Adders 311, 312, 311D, 312D, 311E, 312E,
313E, 314E Delay element 331, 332, 331D, 332D Multiplier 34 Adder 351,352 Delay element 361,362 Multiplier 371,371 Adder 411,421, ..., 41n Delay element 421,422 ... , 42n adder 43 selector 44 storage element 100,100A ΔΣ modulator 101, 101a, 101b loop filter circuit 102 quantizer 103 selector 104 delay element

Claims (2)

A digital signal processor equipped with a quantizer that converts an input signal into a discrete signal with a desired number of bits.
A feedforward processing unit in which an input signal is input, a predetermined calculation is performed, and the first calculation result signal is combined with the input signal and the first combined signal is output.
The signal input to the quantizer is fed back input, the second calculation result signal output after performing a predetermined calculation is combined with the first composite signal, and the second composite signal is output. The first feedback processing unit and
A storage in which an output signal output from the quantizer is input back and a plurality of types of third calculation result signals, which are calculation results obtained by performing predetermined calculations in advance for all the output patterns of the output signals, are stored. The third calculation result signal corresponding to the output signal is read from the storage element and output, and the output third calculation result signal is combined with the second composite signal. A second feedback processing unit for outputting a third composite signal input to the quantizer is provided .
The first feedback processing unit
It has a transfer function as in Equation 1 below.

However, a signal delayed by ^{z -1: 1 clock,}
z ^-2 : Signal delayed by 2 clocks,
z ^-4 : Signal delayed by 4 clocks,
-(A ₀ + a ₁ ): constant,
a ₀ a ₁ : A digital signal processing device characterized by a constant. A digital signal processor equipped with a quantizer that converts an input signal into a discrete signal with a desired number of bits.
A feedforward processing unit in which an input signal is input, a predetermined calculation is performed, and the first calculation result signal is combined with the input signal and the first combined signal is output.
The signal input to the quantizer is fed back input, the second calculation result signal output after performing a predetermined calculation is combined with the first composite signal, and the second composite signal is output. The first feedback processing unit and
A storage in which an output signal output from the quantizer is input back and a plurality of types of third calculation result signals, which are calculation results obtained by performing predetermined calculations in advance for all the output patterns of the output signals, are stored. The third calculation result signal corresponding to the output signal is read from the storage element and output, and the output third calculation result signal is combined with the second composite signal. A second feedback processing unit for outputting a third composite signal input to the quantizer is provided.
The first feedback processing unit
It is assumed that it has a transfer function as shown in Equation 2 below.

However, a signal delayed by ^{z -1: 1 clock,}
z ^-2 : Signal delayed by 2 clocks,
z ^-4 : Signal delayed by 4 clocks,
-(A ₀ + a ₁ ): constant,
a ₀ a ₁ : Constant
A first delay element that delays the first composite signal by one clock, and
A first multiplier that multiplies the output result of the first delay element by a constant − (a ₀ + a _{1), and}
A second delay element that delays the first composite signal by two clocks,
A second multiplier that multiplies the output result of the second delay element by a constant a ₀ a _1.
A first adder that adds the output result of the first multiplier and the output result of the second multiplier, and
It is provided with a feedforward processing unit including a second adder that adds the output result of the first adder and the first combined signal, and a feedforward processing unit.
A third delay element that delays the second composite signal by one clock, and
A third multiplier that multiplies the output result of the third delay element by a constant − (a ₀ ² + a ₁ ^{2), and}
A fourth delay element that delays the third composite signal by two clocks, and
A fourth multiplier that multiplies the output result of the fourth delay element by a constant a ₀ ² a ₁ ^2.
A fifth delay element that delays the output result of the third multiplier by one clock, and
A sixth delay element that delays the output result of the fourth multiplier by one clock, and
A third adder that adds the output result of the fifth delay element and the output result of the sixth delay element and outputs it as the second calculation result signal.
A fourth adder that negatively feeds back the second calculation result signal and combines it with the output result of the second adder is provided.
It features and to Lud digital signal processor that.

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