JP6927863B2 - Register optimizer and register optimization method - Google Patents

Description

The present invention relates to a register optimization device and a register optimization method for optimizing a set value of a register inside a microprocessor.

In the system (embedded system) development process in recent years, design modularization and model-based development are progressing. Therefore, while the difficulty of system development is increasing, it is becoming relatively easy to design. However, as the functionality of the system increases, the number of registers that can be controlled by hardware and software continues to increase. As a result, a great deal of cost is required to find the optimum value of the register in design and evaluation.

In general, there are two methods for creating a hardware / software test pattern: an all-pair method and a method using an orthogonal array. The all-pair method is a method in which a test pattern for a combination of all parameters is created and a test is performed based on the test pattern. In this case, if an attempt is made to cover all combinations of parameters, the test pattern becomes enormous, and the test time also takes an enormous amount of time. On the other hand, the orthogonal array is an allocation table characterized in that all combinations of the levels appear the same number of times for any two factors. In the method using this orthogonal array, the number of parameter combinations can be significantly reduced.

For example, in Patent Document 1, a test is performed so that the coverage rate of a combination of values that can be taken between factors of a test object (for example, the test object may be hardware such as a digital circuit or software) becomes a predetermined value. A test device, a test method, etc. that generate a pattern, supply the test pattern to the test object, and execute the test are described. An algorithm using an orthogonal array is used as a method of obtaining a combination of values such that the coverage rate becomes a predetermined value.

JP 2015-121994

As described above, the apparatus and the like described in Patent Document 1 reduce the number of combination test patterns by using an orthogonal array. However, when testing register settings, there is a desire to reduce the number of tests (number of experiments) and a desire to test the number of registers and the number of bits of registers more, so the number of tests is calculated using an orthogonal array. Reduction alone is not enough and there is room for improvement.

The present invention has been made in view of the above circumstances, and is a register optimization device and a register optimization method capable of reducing the number of tests and testing a larger number of registers and the number of bits of the registers. The purpose is to provide.

In order to achieve the above object, the present invention is a register optimization device that optimizes the set value of a register inside the microprocessor of the system, and a register extraction unit that extracts registers related to the function of the system. , At least one of the predetermined unit bits having a predetermined number of bits in the register extracted by the register extraction unit as one unit is extracted, and the bits are assigned to one factor to determine the level of all levels between any two factors. The system operation is affected based on the test results of the first orthogonal table creation unit that creates the orthogonal table in which the combination appears, the first test execution unit that executes the test for the combination of the orthogonal tables, and the first test execution unit. A first factor specifying unit that specifies the factors that are specified, a second orthogonal table creating unit that creates an orthogonal table by allocating bits in a predetermined unit bit including the factor specified by the first factor specifying unit to one factor, and The second test execution unit that executes the test again for the combination of the orthogonal tables, and the second factor identification unit that identifies the bits of the factors affecting the operation of the system based on the test results of the second test execution unit. , A setting unit for changing the set value of the bit specified by the second factor specifying unit, and a determining unit for determining whether or not the set value of the bit set in the setting unit is within the standard value range are provided. , When the determination unit determines that the bit setting value is not within the standard value range, the first orthogonal table creation unit, the first test execution unit, the first factor identification unit, the second orthogonal table creation unit, and the second The test execution unit, the second factor identification unit, and the setting unit each provide a register optimization device characterized by executing processing.

In addition, the first orthogonal array creation unit allocates the corresponding bit of the register to one factor for a register without a range specification, and allocates a bit of the predetermined unit bits of the register to one factor for a register with a range specification. It may be configured to create an orthogonal array.

Further, the predetermined unit bit may be 4 bits, 1 byte, or 1 word.

In addition, it is equipped with a function extraction unit that extracts the functions of the system under development based on the system specifications, and the register extraction unit is also configured to extract the registers related to the system functions extracted by the function extraction unit. good.

Further, the present invention is a register optimization method for optimizing the set value of a register inside a system microprocessor, which is extracted by a register extraction step for extracting registers related to a system function and a register extraction step. Extract at least one bit of a predetermined unit bit having a predetermined number of bits in a register as one unit, assign the bit to one factor, and create an orthogonal table in which all level combinations between any two factors appear. Identify the factors that influence the operation of the system based on the test results of the first orthogonal table creation step to be created, the first test execution step that executes the test for the combination of the orthogonal tables, and the first test execution step. For the combination of the first factor identification step, the second orthogonal table creation step of allocating the bits in the predetermined unit bit including the factor specified in the first factor identification step to one factor to create an orthogonal table, and the orthogonal table. Based on the test results of the second test execution step and the second test execution step , the second factor identification step and the second factor identification step of identifying the bits of the factors affecting the operation of the system are performed. A setting step for changing the bit setting value specified in step 1 and a determination step for determining whether or not the bit setting value set in the setting step is within the standard value range are provided, and the bit setting value is determined in the determination step. When it is determined that the set value is not within the standard value range, the first orthogonal table creation step, the first test execution step, the first factor identification step, the second orthogonal table creation step, the second test execution step, and the second Provided is a register optimization method characterized by executing the processing of a factor identification step and a setting step.

Further, in the first orthogonal array creation step, for a register without a range specification, the corresponding bit of the register is assigned to one factor, and for a register with a range specification, a bit out of a predetermined unit bit of the register is assigned to one factor. It may be configured to create an orthogonal array.

Further, the predetermined unit bit may be 4 bits, 1 byte, or 1 word.

In addition, a function extraction step for extracting the functions of the system under development is provided based on the system specifications, and in the register extraction step, the registers related to the system functions extracted in the function extraction step are extracted. good.

According to the present invention, the number of tests can be reduced, and more registers and the number of bits of the registers can be tested.

It is a block diagram which shows the structure of the register optimization apparatus which concerns on embodiment of this invention. It is a block diagram which shows the configuration example of the system to be tested. It is a flowchart which shows the process of the register optimization method which concerns on embodiment of this invention. It is a flowchart which shows the 1st orthogonal array creation process of the register optimization method shown in FIG. It is a flowchart which shows the 2nd orthogonal array creation process of the register optimization method shown in FIG. It is a figure which shows the allocation of a factor and a level in an orthogonal array. It is a figure which shows the bit position of the register assigned to the orthogonal array. It is a figure which shows the example of the orthogonal array. It is a figure which shows the example of the register A, B, C assigned to an orthogonal array. It is a figure which shows the 1st orthogonal array and the concrete example of a register expansion. It is a figure which shows the specific example of the 2nd orthogonal array. It is a figure which shows the specific example of a register optimization result.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to this. Further, in the drawings, in order to explain the embodiment, the scale may be changed as appropriate, such as drawing a part in a large or emphasized manner.

FIG. 1 is a block diagram showing a configuration of a register optimization device 1 according to an embodiment of the present invention. The register optimization device 1 shown in FIG. 1 is a device that optimizes the value (parameter) of a register inside a microprocessor of a system (for example, an embedded system). Here, as the system to be tested, for example, a system configured by combining various devices is assumed. Optimization means setting the register value to an appropriate value so that each device or the like operates normally as a system.

In the case of a system that controls a microprocessor that is hardware, it is necessary to set the register range, for example, to issue a command when the register value reaches a predetermined range. In this case, there are a huge number of register combinations, and it takes a huge amount of time to find the optimum value of each register. Therefore, in the present embodiment, we propose a method for efficiently finding a defective register (a register in which an appropriate value is not set as a set value) using an orthogonal array.

FIG. 2 is a block diagram showing a configuration example of the system 100 to be tested (test target). The system 100 shown in FIG. 2 is a SoC (System On a Chip) system in which all the functions necessary for the operation of a device or the like are mounted on one semiconductor chip. The register optimization device 1 is a device that optimizes the register value of the system 100 as shown in FIG. 2, for example. The system 100 is an example, and the system to be optimized for the register by the register optimization device 1 is not limited to the system shown in FIG. For example, register setting between devices in an embedded board is also targeted.

Returning to the description of FIG. 1, the register optimization device 1 is realized by, for example, a computer having a CPU (Central Processing Unit) (for example, a personal computer). As shown in FIG. 1, the register optimization device 1 includes a function identification unit 11, a register extraction unit 12, an orthogonal array creation unit 13 (first orthogonal array creation unit, second orthogonal array creation unit), and a test execution unit 14. It has (first test execution unit, second test execution unit), factor identification unit 15 (first factor identification unit, second factor identification unit), setting unit 16, and storage unit 20. The function specifying unit 11, the register extraction unit 12, the orthogonal array creation unit 13, the test execution unit 14, the factor identification unit 15, and the setting unit 16 in the register optimization device 1 are controlled by the CPU based on a program. Corresponds to processing.

The function specifying unit 11 is a processing unit that extracts the functions of the system under development based on the system specifications. The register extraction unit 12 is a processing unit that extracts registers related to the function extracted by the function specifying unit 11. The orthogonal array creation unit 13 is a processing unit that creates an orthogonal array with a predetermined bit of the register extracted by the register extraction unit 12 as one factor and a level of 2. Specifically, the orthogonal table creation unit 13 has a predetermined unit bit (for example, 4 bits, 1 byte (8 bits)) and 1 word (for example, 4 bits, 1 byte (8 bits)) having a predetermined number of bits in the register extracted by the register extraction unit 12 as one unit. At least one bit out of 32 bits)) is extracted, the extracted bits are assigned to one factor, and an orthogonal table (first orthogonal table) having a level of 2 is created. The orthogonal array creation unit 13 that performs such processing is referred to as a first orthogonal array creation unit. Further, the orthogonal array creation unit 13 allocates each bit in a predetermined unit bit including the factor specified by the factor identification unit 15 described later to one factor, and creates an orthogonal array (second orthogonal array) having a level of 2. .. The orthogonal array creation unit 13 that performs such processing is referred to as a second orthogonal array creation unit.

The test execution unit 14 is a processing unit that executes a test on a combination (test pattern) of orthogonal arrays created by the orthogonal array creation unit 13. The test execution unit 14 that executes a test on the combination of the first orthogonal array created by the first orthogonal array creation unit is called the first test execution unit, and the combination of the second orthogonal array created by the second orthogonal array creation unit. The test execution unit 14 that executes a test on the subject is referred to as a second test execution unit.

The factor identification unit 15 is a processing unit that identifies factors affecting the operation of the system based on the test results of the test execution unit 14. The factor identification unit 15 that identifies the factors affecting the operation of the system based on the test results of the first test execution unit is called the first factor identification unit, and the system operation is based on the test results of the second test execution unit. The factor identification unit 15 that identifies the factors that influence the factors is called the second factor identification unit. The setting unit 16 is a processing unit that sets the value of the register and changes the value of the register specified by the factor specifying unit 15. The determination unit 17 is a processing unit that determines whether or not the register value set by the setting unit 16 is within the range of the specified value.

The storage unit 20 is a device such as a memory that stores various types of information. The information stored in the storage unit 20 includes information in the system specifications (including information on the function under development and registers related to the function), a program for controlling the register optimization device 1, and the like. include. The information stored in the storage unit 20 includes a function extracted by the function specifying unit 11, a register extracted by the register extraction unit 12, an orthogonal array created by the orthogonal array creation unit 13, and a test execution by the test execution unit 14. As a result, the information of the factor specified by the factor specifying unit 15 is also included.

The register optimization device 1 is used in a process of determining a register setting value between devices or within a device, which occurs in a normal system development work. In other words, in system development, system direction, systemization plan, requirements definition, system requirements definition, software requirements definition, programming, software qualification test, system qualification test, requirements test, evaluation, etc. are performed in this order. It is said. The register optimization device 1 is used, for example, in the steps of software requirement definition (design stage) and software qualification test (test stage).

Next, the operation of the register optimization device 1 (register optimization method) will be described with reference to FIGS. 3 to 12.

FIG. 3 is a flowchart showing the processing of the register optimization method according to the embodiment of the present invention. FIG. 4 is a flowchart showing the first orthogonal array creation process (step S3) of the register optimization method shown in FIG. FIG. 5 is a flowchart showing a second orthogonal array creation process (step S6) of the register optimization method shown in FIG.

In the process shown in FIG. 3, the function specifying unit 11 of the register optimization device 1 automatically extracts the functions and conditions of the system under development based on the system specifications (step S1). The functions / conditions extracted by the function specifying unit 11 are determined by the system environment (temperature, etc.), operation mode, hardware configuration, and the like. In the present embodiment, the function specifying unit 11 is configured to automatically extract the functions / conditions of the system under development based on the system specifications, but the developer manually extracts the functions / conditions based on the system specifications. The functions and conditions of the system under development may be extracted.

Next, the register extraction unit 12 is related to a predetermined condition among the registers related to the functions extracted by the function specifying unit 11 and the functions extracted by the function specifying unit 11 based on the system specifications. Extract the register (step S2). Then, the orthogonal array creation unit 13 extracts a predetermined bit from the predetermined unit bits of the register extracted by the register extraction unit 12, allocates the predetermined bit to one factor, and creates an orthogonal array (first orthogonal array). (Step S3).

FIG. 6 is a diagram showing the allocation of factors and levels in an orthogonal array. The orthogonal array is an allocation table for a test (experiment) in which all combinations of the levels appear the same number of times for any two factors (columns). In general, in a multi-dimensional test, the number of tests is required at least by the product of the number of levels of factors, and the number of tests becomes enormous as the number of factors increases. If the required interaction is small, the orthogonal array can be used to test many factors in a relatively small number of times.

As shown in FIG. 6, as a factor (parameter) in the orthogonal array, a register (function A in the example shown in FIG. 6) extracted by the register extraction unit 12 and related to a function / condition implemented in a system or device (function A in the example shown in FIG. 6). In the example shown in FIG. 6, the bits (Bits) included in the registers A, B, C ...) Are allocated (allocated). The level (set value for the parameter) in the orthogonal array is 0 or 1 of "2". The rows of the orthogonal array are the test numbers. (Number of tests, number of combinations). The orthogonal array is created by the orthogonal array creation unit 13 for each function / condition. For example, when the registers related to function A are registers A, B, C, the bits contained in those registers A, B, C are allocated as factors, and the registers related to function B are registers C, D, E. In this case, the bits contained in those registers C, D, and E are allocated as factors.

The size of the orthogonal array is determined from the relationship between the number and type of items (factors) to be tested, test time, cost, and so on. It can also be calculated from the formula of orthogonal array size = Σ (factor level + 1) + 1. The larger the orthogonal array, the longer the man-hours required for the test, and the longer it takes to derive the optimum value, but the accuracy of the test improves. The size of the orthogonal array is determined in consideration of these man-hours and accuracy.

FIG. 7 is a diagram showing bit positions of registers assigned to the orthogonal array. The register shown in FIG. 7 is a 24-bit register (0th bit, 1st bit, 2nd bit, ..., 23rd bit). The bits of the register assigned to the orthogonal array are the recurrence formula difference sequence type arithmetic progression A. It is performed using P (Arithmetic Progression). That is, the orthogonal array creation unit 13 specifies the position of the register bit by the calculated sequence an = a + (n-1) d. In the example shown in FIG. 7, a is 0,1,2,3, n is 1,2,3,4,5, and d is 4. In this case, the 24 bits of the register are divided into units of 4 bits. That is, the 24 bits are "0,1,2,3", "4,5,6,7", "8,9,10,11", "12,13,14,15", "16,17,18,19". It is divided into "20,21,22,23". The unit of 4 bits is a predetermined unit bit. The predetermined unit bit is changed according to the value of d. For example, when d is 8, the 24-bit register is a unit of 8 bits, that is, "0,1,2,3,4,5,6,7", "8,9,10,11,12". , 13, 14, 15 ”and“ 16, 17, 18, 19, 20, 21, 22, 23 ”.

FIG. 8 is a diagram showing an example of an orthogonal array. FIG. 8A is an orthogonal array of two levels L8, and FIG. 8B is an orthogonal array of two levels L16. In this way, the value (level) assigned to each factor (each parameter) and the number of test executions are predetermined according to the size of the orthogonal array.

Next, the contents of the process (first orthogonal array creation process) of step S3 of FIG. 3 will be described with reference to FIG. As shown in FIG. 4, in the first orthogonal array creation process (step S3), the orthogonal array creation unit 13 is a register in which the register (register related to the function / condition) extracted by the register extraction unit 12 has a range designation. Whether or not it is determined (step S3A). Here, the register having no specified range is a register in which the enable bit, the activate bit, and the like are set. The enable bit is a bit that is fixed in the enable register, there is no range specification, and the function starts when this bit is reached. A register having a specified range is a register in which a value is set in each bit of the specified range among each bit of the register (each bit of a 16-bit, 24-bit, 32-bit, or 64-bit register). When the orthogonal array creation unit 13 determines that the register does not have a range specification (that is, determines that the register does not have a range specification) (NO in step S3A), the corresponding bit (enable bit, etc.) of the register is set to 1. Assign to a factor (step S3B). On the other hand, when the orthogonal array creation unit 13 determines that the register has a range designation (YES in step S3A), the orthogonal array creation unit 13 allocates a predetermined bit among the predetermined unit bits within the designated range of the register to one factor (step S3C). ..

FIG. 9 is a diagram showing an example of registers A, B, and C assigned to the orthogonal array. It is assumed that the registers A, B and C shown in FIG. 9 are registers related to the function / condition A of the system. Register A is a register in which the enable bit is set, that is, a register having no specified range. “EN” in register A indicates an enable bit. Register B and register C are registers having a specified range (0th to 7th bits). The register B and the register C have a predetermined unit bit of 4 bits. That is, in the register B and the register C, the 4 bits from the 0th bit to the 3rd bit are set as predetermined unit bits, and the 4 bits from the 4th bit to the 7th bit are set as predetermined unit bits. The initial values of register B and register C are All0 (all bit values are 0), All1 (all bit values are 1), and the predetermined unit bit value is hexadecimal 5h (4-bit value is 2). The base number "0101") or the value of the predetermined unit bit is the hexadecimal number Ah (the 4-bit value is the binary number "1010").

In FIG. 9, the bits marked with ◯ are the bits assigned to the orthogonal array. In addition, the bits marked with x are bits that cannot be assigned to the orthogonal array. In the case of register A, the 0th bit (enable bit) is assigned to the orthogonal array. In the case of register B, the 3rd bit and the 7th bit (predetermined bit of the predetermined unit bit) are assigned to the orthogonal array. In the case of register C as well, the 3rd bit and the 7th bit (predetermined bit of the predetermined unit bit) are assigned to the orthogonal array. The bits assigned in the registers B and C are the bits specified by the arithmetic progression described in FIG. 7.

FIG. 10 is a diagram showing a first orthogonal array and a specific example of register expansion. The orthogonal array (first orthogonal array) shown in the upper left figure of FIG. 10 is an orthogonal array to which the bits of the registers A, B, and C related to the condition A are assigned. The orthogonal array creation unit 13 includes the 0th bit (enable bit) of the register A, the 3rd bit (B0 in FIG. 10) and the 7th bit (B1 in FIG. 10) of the register B, and the 3rd bit of the register C (FIG. 10). 10 C0) and the 7th bit (C1 in FIG. 10) are assigned to the orthogonal array to create a first orthogonal array with a level of 2. This first orthogonal array is a two-level L8 orthogonal array, and the test is No. 0-No. It is executed up to 7.

Returning to the explanation of FIG. 3, the test execution unit 14 executes the test on the combination of the first orthogonal array created by the orthogonal array creation unit 13 (No. 0 to No. 7 of the first orthogonal array in FIG. 10). (Step S4). The result of the test is output as a characteristic value. In parameter design, characteristic values that reasonably express functional quality are required. In the characteristic value output determination, as shown in the upper right figure of FIG. 10, the double circle is the characteristic value of 100%, the circle (◯) is the characteristic value of 90%, and the triangle (Δ) is the characteristic of 80%. It is a value, a square (□) is a characteristic value of 50%, a square (◇) is a characteristic value of 30%, and a cross (x) is a characteristic value of 0%. In the above example, the larger the characteristic value, the better the characteristic.

Next, the factor specifying unit 15 identifies the factors affecting the operation of the system based on the test result (characteristic value output determination) of the test execution unit 14 (step S5). In the example shown in FIG. 10, the factor specifying unit 15 is No. It is determined that the characteristic value output determination of 5 is a factor affecting the system. Then, the factor identification unit 15 is set to No. 1 in the orthogonal array. The "1" of the register division name B1 (7th bit of the register B) of the register B in 5 is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter position "3" in the lower figure of FIG. "0" is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter positions "2", "1", and "0" in the figure below. The value (Hex) on the orthogonal array of the register partition name B1 is "8". The factor identification unit 15 is No. 1 in the orthogonal array. The "0" of the register division name B0 (third bit of the register B) of the register B in 5 is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter position "3" in the lower figure of FIG. "0" is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter positions "2", "1", and "0" in the figure below. The value (Hex) on the orthogonal array of the register partition name B0 is "0". The factor identification unit 15 is No. 1 in the orthogonal array. The "1" of the register division name C1 (7th bit of the register C) of the register C in 5 is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter position "3" in the lower figure of FIG. "0" is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter positions "2", "1", and "0" in the figure below. The value (Hex) on the orthogonal array of the register partition name C1 is "8". The factor identification unit 15 is No. 1 in the orthogonal array. The "0" of the register division name C0 (third bit of the register C) of the register C in 5 is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter position "3" in the lower figure of FIG. "0" is assigned to the value (bin) on the orthogonal array corresponding to the Bit delimiter positions "2", "1", and "0" in the figure below. The value (Hex) on the orthogonal array of the register partition name C0 is "0".

Next, the orthogonal array creation unit 13 allocates bits in a predetermined unit bit including the factor specified by the factor identification unit 15 to one factor, and creates an orthogonal array (second orthogonal array) having a level of 2. Step S6). The contents of the process (second orthogonal array creation process) of step S6 of FIG. 3 will be described with reference to FIG.

As shown in FIG. 5, in the second orthogonal array creation process (step S6), the orthogonal array creation unit 13 determines whether or not the register containing the factor specified by the factor identification unit 15 is a register having a range designation (step S6). Step S6A). When the orthogonal array creation unit 13 determines that the register does not have a range specification (that is, determines that the register does not have a range specification) (NO in step S6A), the corresponding bit (enable bit, etc.) of the register is set to 1. Assign to a factor (step S6B). On the other hand, when the orthogonal array creation unit 13 determines that the register has a range designation (YES in step S6A), the orthogonal array creation unit 13 allocates a bit in a predetermined unit bit included in the influencing factor in the register to one factor (step). S6C).

FIG. 11 is a diagram showing a specific example of the second orthogonal array. The orthogonal table creation unit 13 converts the bits (6th bit, 5th bit, and 4th bit of the register B) of the bit delimiter positions “2”, “1”, and “0” of the register division name B1 in the lower figure of FIG. 10 into an orthogonal table. The bits of the bit delimiter positions "2", "1", and "0" of the register division name B0 in the lower figure of FIG. 10 (the second bit, the first bit, and the 0th bit of the register B) are assigned to the orthogonal table. Bits of the bit delimiter positions "2", "1", and "0" of the register division name C1 in the lower figure of FIG. 10 (6th bit, 5th bit, and 4th bit of the register C) are assigned to the orthogonal table, and in the lower figure of FIG. A second orthogonal table in which the bits (2nd bit, 1st bit, and 0th bit of register C) of the bit delimiter positions "2", "1", and "0" of the register division name C0 are assigned to the orthogonal table and the level is 2. To create. This second orthogonal array is a two-level L16 orthogonal array, and the test is No. 0-No. It is executed up to 15. The value of the bit (7th bit of register B) of the bit delimiter position "3" of the register division name B1 in the lower figure of FIG. 10 is fixed to "1", and the bit delimiter of the register division name B0 in the lower figure of FIG. The value of the bit at position "3" (third bit of register B) is fixed to "0", and the bit at the bit delimiter position "3" of the register division name C1 in the lower figure of FIG. 10 (seventh bit of register C). The value of is fixed to "1", the value of the bit (third bit of register C) of the bit delimiter position "3" of the register division name C0 in the lower figure of FIG. 10 is fixed to "0", and further, the value of register A is fixed. Run the test under the condition that the value is fixed.

The test execution unit 14 executes the test again for the combination of the second orthogonal array created by the orthogonal array creation unit 13 (Nos. 0 to No. 15 of the second orthogonal array in FIG. 11) (step S7). The result of the test is output as a characteristic value.

Next, the factor specifying unit 15 identifies bits (influence factor bits) of factors affecting the operation of the system based on the test result (characteristic value output determination) of the test execution unit 14 (step S8). In the example shown in FIG. 11, the factor specifying unit 15 is No. It is determined that the characteristic value output determination of 14 is a bit of a factor affecting the system.

FIG. 12 is a diagram showing a specific example of the register optimization result. The factor identification unit 15 is No. 1 in the orthogonal array. "1" is assigned to the value (bin) on the orthogonal table corresponding to the bit delimiter position "3" of the register division name B1 of the register B in 14 and the orthogonal table corresponding to the bit delimiter position "2" of the register division name B1. Allocate "1" to the above value (bin), assign "0" to the value (bin) on the orthogonal table corresponding to the Bit delimiter position "1" of the register division name B1, and assign the Bit delimiter position of the register division name B1. "0" is assigned to the value (bin) on the orthogonal table corresponding to "0". The value (Hex) on the orthogonal array of the register partition name B1 is "C". This value is the optimum value.

The factor identification unit 15 is No. 1 in the orthogonal array. "0" is assigned to the value (bin) on the orthogonal table corresponding to the bit delimiter position "3" of the register division name B0 of the register B in 14, and the orthogonal table corresponding to the bit delimiter position "2" of the register division name B0. Allocate "1" to the above value (bin), assign "0" to the value (bin) on the orthogonal table corresponding to the Bit delimiter position "1" of the register division name B0, and assign the Bit delimiter position of the register division name B0. "1" is assigned to the value (bin) on the orthogonal table corresponding to "0". The value (Hex) on the orthogonal array of the register division name B0 is "5". This value is the optimum value.

The factor identification unit 15 is No. 1 in the orthogonal array. "1" is assigned to the value (bin) on the orthogonal table corresponding to the bit delimiter position "3" of the register division name C1 of the register C in 14, and the orthogonal table corresponding to the bit delimiter position "2" of the register division name C1 is assigned. Allocate "1" to the above value (bin), assign "0" to the value (bin) on the orthogonal table corresponding to the Bit delimiter position "1" of the register division name C1, and assign the Bit delimiter position of the register division name C1. "1" is assigned to the value (bin) on the orthogonal table corresponding to "0". The value (Hex) on the orthogonal array of the register partition name C1 is "D". This value is the optimum value.

The factor identification unit 15 is No. 1 in the orthogonal array. "0" is assigned to the value (bin) on the orthogonal table corresponding to the bit delimiter position "3" of the register division name C0 of the register C in 14, and the orthogonal table corresponding to the bit delimiter position "2" of the register division name C0. "0" is assigned to the upper value (bin), "0" is assigned to the value (bin) on the orthogonal table corresponding to the bit delimiter position "1" of the register division name C0, and the bit delimiter position of the register division name C0. "1" is assigned to the value (bin) on the orthogonal table corresponding to "0". The value (Hex) on the orthogonal array of the register division name C0 is "1". This value is the optimum value.

Returning to the description of FIG. 3, the setting unit 16 sets (changes) the optimum value of the register shown in FIG. 12 (step S9). Next, the determination unit 17 determines whether or not the optimum value (set value) set in step S9 is within the range of the standard value (specified value) in the specification (step S10). If the determination unit 17 determines that the set value is not within the standard value (NO in step S10), the process returns to the process of step S3, and the processes of steps S3 to S10 are repeatedly executed. On the other hand, when the determination unit 17 determines that the standard value is within the standard value (YES in step S10), it determines that the optimization of the register related to the predetermined function has been completed, and processes the function. To finish. When optimizing other functions, it is executed from step S1.

As described above, in the present embodiment, the number of tests can be reduced, and more registers and the number of bits of the registers can be tested.

Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be made to the above embodiments without departing from the spirit of the present invention. In addition, one or more of the requirements described in the above embodiments may be omitted. Such modifications, improvements, or omitted forms are also included in the technical scope of the present invention. Further, it is also possible to appropriately combine and apply the configurations of the above-described embodiments and modifications.

For example, in the second orthogonal array shown in FIG. 11, B1 “2” “1” “0”, B0 “2” “1” “0”, C1 “2” “1” “0”, C0 "2" "1" "0" was assigned, but B1 "3" "2" "1" "0", B0 "3" "2" "1" "0", C1 "3" "2" "1" "0", C0 "3" "2" "1" "0" may be assigned. Further, a bit of register A may be assigned to the second orthogonal array.

Further, as an example of the register to be optimized, 16-bit, 24-bit, 32-bit, and 64-bit registers are used, but the register is not limited to these-bit registers, and for example, 128-bit, 256-bit registers and the like. There may be.

1 Register optimizer 11 Function specification unit 12 Register extraction unit 13 Orthogonal array creation unit (1st orthogonal array creation unit, 2nd orthogonal array creation unit)
14 Test execution unit (1st test execution unit, 2nd test execution unit)
15 Factor identification part (1st factor identification part, 2nd factor identification part)
16 Setting unit 17 Judgment unit 100 System

Claims (8)

A register optimizer that optimizes register settings inside the system's microprocessor.
A register extractor that extracts registers related to the function of the system,
At least one bit of a predetermined unit bit having an arbitrary number of bits in the register as one unit extracted by the register extraction unit is extracted, the bit is assigned to one factor, and between any two factors. The first orthogonal array creation unit that creates an orthogonal array in which all levels of combinations appear,
A first test execution unit that executes a test on the combination of the orthogonal arrays,
Based on the test results of the first test execution unit, the first factor identification unit that identifies the factors affecting the operation of the system, and the first factor identification unit.
A second orthogonal array creation unit that creates an orthogonal array by allocating bits in the predetermined unit bit including the factor specified by the first factor identification unit to one factor.
A second test execution unit that executes the test again for the combination of the orthogonal arrays,
Based on the test results of the second test execution unit, the second factor identification unit that specifies the bits of the factors affecting the operation of the system, and the second factor identification unit.
A setting unit that changes the setting value of the bit specified by the second factor identification unit, and a setting unit that changes the setting value of the bit.
A determination unit for determining whether or not the set value of the bit set by the setting unit is within the standard value range is provided.
When the determination unit determines that the set value of the bit is not within the standard value range, the first orthogonal array creation unit, the first test execution unit, the first factor identification unit, and the second orthogonal array unit. The table creation unit, the second test execution unit, the second factor identification unit, and the setting unit are register optimization devices, each of which executes the processing. The first orthogonal array creation unit assigns the corresponding bit of the register to one factor for a register without a range designation, and assigns the bit of the predetermined unit bits of the register to one factor for a register with a range designation. The register optimizer according to claim 1, which allocates and creates an orthogonal array. The register optimization device according to claim 1 or 2, wherein the predetermined unit bit is 4 bits, 1 byte, or 1 word. It is equipped with a function extraction unit that extracts the functions of the system under development based on the specifications of the system.
The register optimization device according to any one of claims 1 to 3, wherein the register extraction unit extracts registers related to the function of the system extracted by the function extraction unit. A register optimization method that optimizes register settings inside the system's microprocessor.
A register extraction step that extracts registers related to the function of the system, and
At least one bit of a predetermined unit bit having an arbitrary number of bits in the register as one unit extracted in the register extraction step is extracted, the bit is assigned to one factor, and between any two factors. The first orthogonal array creation step to create an orthogonal array in which all levels of combinations appear,
A first test execution step of executing a test on the combination of orthogonal arrays, and
Based on the test results of the first test execution step, the first factor identification step for identifying the factors influencing the operation of the system, and the first factor identification step.
A second orthogonal array creation step in which bits in the predetermined unit bit including the factor specified in the first factor identification step are assigned to one factor to create an orthogonal array, and a second orthogonal array creation step.
A second test execution step in which the test is executed again for the combination of the orthogonal arrays, and
Based on the test result of the second test execution step , the second factor specifying step for specifying the bits of the factors affecting the operation of the system, and the second factor specifying step.
A setting step for changing the set value of the bit specified in the second factor specifying step, and a setting step for changing the set value of the bit.
A determination step for determining whether or not the set value of the bit set in the setting step is within the standard value range is provided.
When it is determined in the determination step that the set value of the bit is not within the range of the standard value, the first orthogonal array creation step, the first test execution step, the first factor identification step, and the second orthogonal array are performed. A register optimization method comprising executing the processing of the table creation step, the second test execution step, the second factor identification step, and the setting step. In the first orthogonal array creation step, for a register without a range designation, the corresponding bit of the register is assigned to one factor, and for a register with a range designation, the bit of the predetermined unit bits of the register is assigned to one factor. The register optimization method according to claim 5, wherein an orthogonal array is created by allocating. The register optimization method according to claim 5 or 6, wherein the predetermined unit bit is 4 bits, 1 byte, or 1 word. A function extraction step for extracting the functions of the system under development based on the specifications of the system is provided.
The register optimization method according to any one of claims 5 to 7, wherein in the register extraction step, the registers related to the functions of the system extracted in the function extraction step are extracted.

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