JP6915359B2 - Information processing equipment and printing equipment - Google Patents

Description

The present invention relates to an information processing device and a printing device.

In a printing device such as a laser printer, for example, a photoconductor drum or a developing roller has a cylindrical shape. Further, the photoconductor drum or the developing roller or the like is attached to the housing so as to maintain a parallel relationship with the other drum or the roller or the like.

However, due to variations in mounting accuracy or changes over time, the ideal cylindrical shape may be slightly distorted with respect to the photoconductor drum or the like, and the parallel relationship may be deviated. In this case, for example, even if a solid image which is a monochromatic image having a uniform density as a whole is printed, printing unevenness occurs periodically along the sub-scanning direction which is the moving direction of the printed matter. Such printing unevenness may be tolerated in general office printing equipment. However, it becomes unacceptable in commercial printing equipment where high print quality is expected.

For this reason, many commercial printing devices are provided with a calibration function capable of reducing printing unevenness. For example, in the case of the image forming apparatus disclosed in Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-228201), the print density is calibrated based on the density value of the toner image detected by the sensor. Printing unevenness is reduced.

The parameters used in the calibration process are generated by acquiring data indicating the degree of printing unevenness, data indicating the tendency of printing unevenness, and the like for a predetermined time, digitizing them, and performing an inverse transformation process. When generating this parameter value, when a finite number of data are arranged in ascending order, the intermediate value (median value), which is the value located at the center, is used. For example, a full-time technician at a printing factory adjusts the optimum calibration pattern and parameter values at the time of printing while checking the intermediate values of arithmetic processing. The more intermediate values that can be obtained, the finer the adjustment becomes possible.

On the other hand, since the calibration process is required to have a high speed, the calibration function is often realized by an integrated circuit (LSI: Large Scale Integration). There is an upper limit to the number of external terminals that can be installed in an LSI due to restrictions such as mounting area and packaging cost. Further, the LSI has an upper limit on the transition speed of the external signal from the viewpoint of reducing current consumption and noise. Therefore, when acquiring an intermediate value from an LSI, a storage unit such as an SRAM (Static Random Access Memory) is provided inside the LSI, the intermediate value is temporarily stored in this storage unit, and the intermediate value is read out after the predetermined information processing is completed. To get.

Here, the SRAM used as the storage unit for the intermediate value has one input port, and the number of intermediate values that can be written in one cycle is one. For this reason, the calibration processing unit that supplies input information to the data processing systems of a plurality of channels and performs data processing in parallel in each data processing system is subjected to "arbitration" for controlling data processing of intermediate values that occur at the same time. A "circuit" is provided.

For example, when an intermediate value is generated at the same time in the first data processing system and the second data processing system, the arbitration circuit separates the intermediate value to be output and the intermediate value temporarily stored in the SRAM. Then, the arbitration circuit stores the intermediate value of the non-output side in a storage unit such as SRAM. As a result, even if a plurality of intermediate values are generated at the same time in the calibration processing unit in which the SRAM is used as the storage unit, one intermediate value is output and the other intermediate value is stored in the SRAM. By reading from, it is possible to obtain both intermediate values that occur at the same time. Therefore, it is possible to obtain more intermediate values.

However, the arbitration circuit has a high degree of design difficulty and requires man-hours for design and verification. Further, the circuit scale of the calibration LSI is increased by the amount of the arbitration circuit provided. Therefore, there is a problem that the manufacturing cost of the calibration LSI increases.

The present invention has been made in view of the above-mentioned problems, and information capable of acquiring more intermediate values without providing an arbitration circuit, reducing the circuit scale, and reducing the manufacturing cost. An object of the present invention is to provide a processing device and a printing device.

In order to solve the above-mentioned problems and achieve the object, the present invention provides output information at different timings for a plurality of information processing units that process input information with predetermined information processing and output output information. Multiple channels of a timing control unit that controls to output information, a write control unit that controls writing output information from each information processing unit to a storage unit, and an information processing system in which a plurality of information processing units are connected in series. The minute, preparation, and timing control units perform delay processing for a predetermined delay time on a plurality of input information supplied in parallel, and supply the information processing system of each channel with the plurality of delay processing units. , Set a predetermined delay time for each delay processing unit that supplies input information to the information processing system of each channel so that the output information is output from the information processing system of each channel at different timings. It has a delay setting unit .

According to the present invention, it is possible to obtain more intermediate values without providing an arbitration circuit, and it is possible to reduce the circuit scale and the manufacturing cost.

FIG. 1 is a diagram showing an internal configuration of a printing apparatus according to a first embodiment. FIG. 2 is a block diagram of a calibration system including an arbitration circuit. FIG. 3 is a diagram for explaining the inconvenience that two or more intermediate values occur at the same time. FIG. 4 is a block diagram of a calibration system provided in the printing apparatus of the first embodiment. FIG. 5 is a diagram showing how the calibration system provided in the printing apparatus of the first embodiment prevents the inconvenience of generating intermediate values at the same time in each arithmetic processing unit. FIG. 6 is a flowchart showing the flow of the calibration process in the printing apparatus of the first embodiment. FIG. 7 is a block diagram of a calibration system provided in the printing apparatus of the second embodiment. FIG. 8 is a block diagram of a calibration system provided in the printing apparatus of the third embodiment.

Hereinafter, embodiments will be described with reference to the drawings.

[First Embodiment]
(Configuration of printing device)
FIG. 1 is a diagram showing an internal configuration of the printing apparatus 100 according to the first embodiment. In this printing device 100, a print server 110 is connected to the main body 100. The print data is stored in the print server 110, and is transmitted to the main body 120 according to an instruction from the user.

The main body 120 includes an optical device 121, a photoconductor drum 122, a developing roller 123, a transfer roller 124, a transfer belt 125, a transfer roller 126, a fixing device 127, a transfer device 131, a paper tray 132, a transfer path 133, a paper discharge tray 134, and the like. The calibration system 200 is provided. The main body 120 performs processing such as color correction, density conversion, and reduction in value on the print data, and finally supplies the binarized print data to the optical device 121. The optical device 121, the photoconductor drum 122, the developing roller 123, the transfer roller 124, the transfer belt 125, the transfer roller 126, the fixing device 127, the transfer device 131, the paper tray 132, and the transfer path 133 provided in the main body 120. , The output tray 134, the calibration system 200, and the like are examples of the printing unit.

The optical device 121 uses a laser diode or the like as a laser light source, and irradiates the uniformly charged photoconductor drum 122 with a laser beam according to print data. The surface of the photoconductor drum 122 is irradiated with a laser beam corresponding to the print data in a uniformly charged state, so that the electric charge disappears only at the portion irradiated with the laser beam. As a result, a latent image corresponding to the print data is formed on the surface of the photoconductor drum 122. The latent image formed here moves in the direction of the corresponding developing roller 123 as the photoconductor drum 122 rotates.

The developing roller 123 rotates and adheres the toner supplied from the toner cartridge to the surface thereof. Then, the developing roller 123 attaches the toner adhering to the surface to the latent image formed on the surface of the photoconductor drum 122. As a result, the developing roller 123 visualizes the latent image formed on the surface of the photoconductor drum 122 and forms a toner image on the surface of the photoconductor drum 122.

The toner image formed on the surface of the photoconductor drum 122 is transferred onto the transfer belt 125 between the photoconductor drum 122 and the transfer roller 124. As a result, a toner image is formed on the transfer belt 125. In the example shown in FIG. 1, the optical device 121, the photoconductor drum 122, the developing roller 123, and the transfer roller 124 have four printing colors (yellow (Y), cyan (C), magenta (M), and key plate (M)). K: ≈ black))). Therefore, a toner image of each print color is formed on the transfer belt 125.

The transport device 131 delivers the recording paper 135 from the paper tray 132 to the transport path 133. The recording paper 135 sent out to the transport path 133 is transported between the transfer belt 125 and the transfer roller 126. As a result, the toner image of each printing color formed on the transfer belt 125 is transferred to the recording paper 135 between the transfer belt 125 and the transfer roller 126. After that, heat and pressure are applied to the recording paper 135 by the fixing device 127, and the toner image is fixed on the recording paper 135. Then, the recording paper 135 on which the toner image is fixed is conveyed to the output tray 134.

The printing apparatus 100 configured in this way includes a calibration system 200 described later. The calibration system 200 generates calibration data for making the print density uniform based on the density value of the calibration pattern and various parameters detected by the plurality of density sensors 203A to 200E shown in FIG. .. As a result, the printing apparatus 100 can eliminate printing unevenness caused by a defect of the rotating body (for example, the photoconductor drum 122, the developing roller 123, etc.). In particular, the calibration system 200 of the embodiment can acquire more intermediate values without providing an arbitration circuit, and can reduce the circuit scale and the manufacturing cost. Hereinafter, this point will be specifically described.

(Calibration system with arbitration circuit)
First, as a comparative example, a calibration system provided with an arbitration circuit will be described. FIG. 2 is a block diagram of a calibration system including an arbitration circuit. As shown in FIG. 2, the calibration system provided with the arbitration circuit includes a plurality of density sensors 500A to 500D, an analog-to-digital converter (ADC) 501, a calibration LSI 502, and a control CPU 503.

The calibration LSI 502 is an integrated circuit and has a calibration processing unit 504 and a control CPU interface (control CPUIF) 505. The control CPU 503 is connected to the calibration processing unit 504 via the control CPU IF 505.

The calibration processing unit 504 includes a sensor input unit 511, data processing systems 521 to 515 of the first to fourth channels, a result output unit 515, an arbitration circuit 516, and a storage unit 517. In the case of a printing device capable of color printing, it is necessary to automatically execute the calibration process for each color. Therefore, in the case of the calibration system of the example of FIG. 2, data processing systems 521 to 515 for each channel for Y, C, M, and K are provided. The data processing systems 521 to 515 of each channel have first to third arithmetic processing units 521 to 523, respectively.

As the density sensors 500A to 500D, for example, a photodiode or the like is used, and they are provided at positions facing the transfer belt 125, respectively. The print data includes calibration pattern data formed between the toner image transferred to the recording paper 135 and the next toner image transferred to the next recording paper 135 on the transfer belt 125. It has been. Each of the density sensors 500A to 500D detects the density value of the calibration pattern transferred to the transfer belt 125 and supplies the density value to the sensor input unit 511 of the calibration processing unit 504 via the ADC 501.

The sensor input unit 511 divides and supplies the density values of the calibration patterns detected by the density sensors 500A to 500D into the data processing systems 521 to 515 of the first to fourth channels in order to process them in parallel. .. The data processing systems 521 to 515 of each of the first to fourth channels are subjected to the first arithmetic processing unit 521 to the third arithmetic processing unit 523, respectively, based on the density value of the calibration pattern and predetermined parameters. Generate calibration data for adjusting the shade of print density.

Specifically, the parameters include, for example, a reference voltage setting for converting a density value into a toner adhesion amount, a speed setting of the photoconductor drum 122, the number of data to be calibrated, the number of laps, an effective image position setting, and various corrections. It contains various values such as coefficients. The data processing system 521 to 515 of each channel calculates the amount of toner of the calibration pattern transferred to the transfer belt 125 based on the density value of the calibration pattern detected by the density sensors 500A to 500D. Then, the data processing system 521 to 515 of each channel determines the shading of the print density by comparing the calculated toner amount with the desired value of the toner amount. Further, the data processing system 521 to 515 of each channel generates calibration data for adjusting the shading of the print density according to the determination result of the shading of the print density.

The result output unit 515 integrates and processes the calibration data generated by the data processing systems 521 to 515 of each channel, and supplies the calibration data to the next processing block 520 in the subsequent stage. The next processing block 520 adjusts the luminous flux amount of the laser beam output from the optical device 121, the charge amount of the photoconductor drum 122, and the like based on the calibration data from the result output unit 515, thereby adjusting the print density. Adjust the shade. As a result, it is possible to prevent the occurrence of printing unevenness in the printing apparatus 100.

Here, various intermediate values are generated in the arithmetic processing of the data processing systems 521 to 515 of each channel at the time of generating the calibration data. For example, a full-time technician at a printing factory adjusts the optimum calibration pattern and parameter values at the time of printing while checking the intermediate values of arithmetic processing. Specifically, for example, as intermediate values for calculating the frequency component and the phase component of printing unevenness, comparison data of the charging current and the amount of toner adhered is acquired. Then, based on the acquired comparison data, the amount of current corresponding to the toner component used for printing can be calculated and set as a design value.

On the other hand, when the calibration data is generated in parallel by the data processing systems 521 to 515 of each channel as shown in FIG. 2, two or more intermediate values may be generated at the same time as shown in FIG. In FIG. 3, FIG. 3A shows a system clock having a predetermined frequency, and FIGS. 3B to 3E show the first arithmetic processing of the data processing system 521 to 515 of each channel. The generation timing of the intermediate value generated by the unit 521, the second arithmetic processing unit 522, and the third arithmetic processing unit 523 is shown. That is, in FIGS. 3B to 3E, the high-level signal is effectively output from the first arithmetic processing unit 521 to the third arithmetic processing unit 523 at the timing when a valid intermediate value is generated. Indicates a notification signal (valid). In the example of FIG. 3, in the data processing systems 521 to 515 of each channel, it is shown that valid intermediate values are simultaneously generated in the first arithmetic processing units 521 to the third arithmetic processing units 523.

Normally, the SRAM used for storing data has one input port, and the number of data that can be written in one cycle is one. Therefore, when two or more intermediate values are generated at the same time, the arbitration circuit 516 shown in FIG. The intermediate value that is not written is temporarily stored and controlled in the storage unit. The intermediate value written in the storage unit is read out by the control CPU 503 via the control CPU IF 505 at a predetermined timing. As a result, even when an SRAM is provided as a storage unit, it is possible to acquire a plurality of intermediate values generated at the same time. Therefore, it is possible to make finer calibration adjustments by using more intermediate values.

However, the arbitration circuit has a high degree of design difficulty and requires man-hours for design and verification. Further, the circuit scale of the calibration LSI is increased by the amount of the arbitration circuit provided. Therefore, there is a problem that the manufacturing cost of the calibration LSI increases.

(Configuration of Calibration System of First Embodiment)
Therefore, the printing apparatus of the first embodiment shown in FIG. 1 can acquire more intermediate values in the calibration system without providing an arbitration circuit as described below. By doing so, it is possible to reduce the circuit scale and the manufacturing cost.

That is, the printing apparatus of the first embodiment has a calibration system 200 as shown in FIG. As shown in FIG. 4, the calibration system 200 includes a plurality of density sensors 200A to 200D, an analog-to-digital converter (ADC) 204, a calibration LSI 202, and a control CPU 203.

The calibration LSI 202 is an integrated circuit and has a calibration processing unit 220 and a control CPU interface (control CPUIF) 221. The control CPU 203 is connected to the calibration processing unit 220 via the control CPU IF 221.

The calibration processing unit 220 includes a sensor input unit 231, an input selection unit 232, a data generation unit 233, a result output unit 271, a storage unit 272, and a storage control unit 273. Each of the data generation units 233 is an example of an information processing unit, and each has a first arithmetic processing unit 261 to a third arithmetic processing unit 263 connected in series, and is detected by each density sensor 200A to 200D. Based on the density value of the read calibration pattern (an example of input information) and a predetermined parameter set by the control CPU 203, calibration data for adjusting the shading of the print density is generated. The first arithmetic processing unit 261 is an input terminal arithmetic processing unit. The third arithmetic processing unit 263 is an arithmetic processing unit at the output end. The first arithmetic processing units 261 to the third arithmetic processing units 263 perform arithmetic processing in order based on the density value and output an intermediate value.

The storage control unit 273, which is an example of the write control unit, has first to third AND gates 241 to 243, a first OR gate 251 and a second OR gate 252. The first AND gate 241 is connected to the first arithmetic processing unit 261 and keeps a high level while the intermediate value supplied from the first arithmetic processing unit 261 and a valid intermediate value are output. Outputs the logical sum with the valid notification signal (valid). The second AND gate 242 is connected to the second arithmetic processing unit 262, and while the intermediate value supplied from the second arithmetic processing unit 262 and the valid intermediate value are output, the level is high. Outputs the logical sum with the valid notification signal (valid). The third AND gate 243 is connected to the third arithmetic processing unit 263, and while the intermediate value supplied from the third arithmetic processing unit 263 and the effective intermediate value are output, the high level is set. Outputs the logical sum with the valid notification signal (valid). The "intermediate value" is an example of output information.

The first OR gate 251 is connected to the first to third arithmetic processing units 261 to 263, and outputs the logical product of the valid notification signals (valid) supplied from the arithmetic processing units 261 to 263. The second OR gate 252 outputs the logical sum of the outputs (logical product described above) from the first to third AND gates 241 to 243. As will be described later, the output of the second OR gate 252 becomes a high level at the timing when a valid intermediate value is output from any one of the first to third arithmetic processing units 261 to 263 (intermediate value). It is supplied to the storage unit 272. Further, the output of the first OR gate 251 becomes high level at the timing when a high level valid notification signal (valid) is supplied from any one of the first to third arithmetic processing units 261 to 263, and is written. It is supplied to the storage unit 272 as a control signal.

The intermediate value supplied to the storage unit 272 from any of the first to third AND gates 241 to 243 is stored in the storage unit 272 based on the write control signal supplied from the first OR gate 251. .. The intermediate value stored in the storage unit 272 is read out by the control CPU 203 at a predetermined timing and used for generating calibration data. As an example, SRAM (Static Random Access Memory) can be used as the storage unit 272. As the storage unit 272, another storage unit such as a flip-flop may be used.

(Operation of calibration system)
Next, the operation of the calibration system 200 having such a configuration will be described. Each density sensor 200A to 200D reads the density value of the calibration pattern transferred to the transfer belt 125. The density values from the density sensors 200A to 200D are binarized (digitized) by the ADC 204 and supplied to the input selection unit 232 via the sensor input unit 231.

The input selection unit 232 selects each concentration value supplied via the sensor input unit 231 in a predetermined order, and supplies it to the data generation unit 233 provided with only one channel as an example. That is, in the case of this calibration system 200, the input selection unit 232 selects the density values detected in parallel by the density sensors 200A to 200D in a predetermined order to the data generation unit 233. Is supplied in series. As a result, the density value supplied to the data generation unit 233 is supplied in the order of the first arithmetic processing unit 261 → the second arithmetic processing unit 262 → the third arithmetic processing unit 263. The input selection unit 232 selects the density value to be processed next at the timing when the calculation processing for each density value is completed in each calculation processing unit 261 to 263, and the first calculation process serving as the input end. Supply to unit 261.

Each arithmetic processing unit 261 to 263 calculates the amount of toner of the calibration pattern transferred to the transfer belt 125 based on the density value of the calibration pattern detected by the density sensors 200A to 200D. Further, each arithmetic processing unit 261 to 263 determines the shading of the print density by comparing the calculated toner amount with the desired value of the toner amount. Then, each arithmetic processing unit 261 to 263 generates calibration data for adjusting the shading of the print density according to the determination result of the shading of the print density, and supplies the calibration data to the result output unit 271. The result output unit 271 supplies the calibration data to the next processing block 280 in the subsequent stage. The next processing block 280 adjusts the luminous flux amount of the laser beam output from the optical device 121, the charge amount of the photoconductor drum 122, and the like based on the calibration data from the result output unit 271 to obtain the print density. Adjust the shade. As a result, it is possible to prevent the occurrence of printing unevenness in the printing apparatus 100.

In such a calibration system 200, the density values detected in parallel by the density sensors 200A to 200D are processed by the data generation unit 233 of one channel. Therefore, intermediate values do not occur at the same time in the data generation units of a plurality of channels. Further, in the calibration system 200, the arithmetic processing units 261 to 263 of the data generation unit 233 do not simultaneously process the density value data, and the arithmetic processing units 261 to 263 sequentially process the density value data. I do. As a result, as shown in FIG. 5, it is possible to prevent the inconvenience that intermediate values are generated at the same time in the arithmetic processing units 261 to 263.

That is, FIG. 5A shows a system clock having a predetermined frequency, and FIG. 5B shows data generators in which the first to fourth density values detected in parallel by the density sensors 200A to 200D are the data generation units. The intermediate value (high level) generated when the processing is sequentially performed in 233 is shown. The horizontal axis of FIGS. 5A and 5B is the time axis.

In the calibration system 200, the first to fourth density values detected in parallel by the density sensors 200A to 200D are sequentially processed by the data generation unit 233 of one channel. Therefore, it is possible to prevent the inconvenience that an intermediate value is generated at the same time between the data generation units of a plurality of channels. Further, the first to fourth density values detected in parallel by the density sensors 200A to 200D are sequentially processed by the arithmetic processing units 261 to 263 of the data generation unit 233. Therefore, as shown in FIG. 5B, even in the arithmetic processing units 261 to 263, the intermediate values generated when the first to fourth density values are data-processed are generated at different timings. Therefore, it is possible to prevent the inconvenience that an intermediate value is generated at the same time between the arithmetic processing units 261 to 263.

(Median memory control)
Next, such an intermediate value is temporarily stored and controlled by the storage unit 272 of the SRAM or the like by the storage control unit 273, read out at a predetermined timing by the control CPU 203, and used for the calibration process or the like.

Specifically, the first arithmetic processing unit 261 of the data generation unit 233 supplies the intermediate value (high level) generated in the arithmetic processing to the first AND gate 241 and outputs a valid intermediate value. Meanwhile, a high level valid notification signal (valid) is supplied to the first AND gate 241. Further, the second arithmetic processing unit 262 supplies an intermediate value of arithmetic processing to the second AND gate 242, and while outputting a valid intermediate value, a high-level effective notification signal (valid) is output. It is supplied to the second AND gate 242. Further, the third arithmetic processing unit 263 supplies an intermediate value of arithmetic processing to the third AND gate 243, and while outputting a valid intermediate value, a high-level valid notification signal (valid) is output. It supplies to the third AND gate 243.

The first AND gate 241 outputs a logical product of an intermediate value supplied from the first arithmetic processing unit 261 and a valid notification signal (valid). As a result, the first AND gate 241 outputs a high-level intermediate value while the valid notification signal (valid) is at a high level. Similarly, the second AND gate 242 outputs the logical product of the intermediate value supplied from the second arithmetic processing unit 262 and the valid notification signal (valid). As a result, the second AND gate 242 outputs a high-level intermediate value while the valid notification signal (valid) is at a high level. Similarly, the third AND gate 243 outputs the logical product of the intermediate value supplied from the third arithmetic processing unit 263 and the valid notification signal (valid). As a result, the third AND gate 243 outputs a high-level intermediate value while the valid notification signal (valid) is at a high level.

The second OR gate 252 outputs the logical sum of the first AND gate 241 to the third AND gate 243 to supply the intermediate value supplied from any of the AND gates to the storage unit 272. Further, the first OR gate 251 is used while a high-level valid notification signal (valid) is being supplied from any of the first arithmetic processing units 261 to the third arithmetic processing unit 263. , A high-level write control signal is supplied to the storage unit 272. As a result, the intermediate value supplied to the storage unit 272 is write-controlled to the storage unit 272 based on the write control signal.

That is, as described above, since the first to third arithmetic processing units 261 to 263 sequentially perform arithmetic processing based on the density value, as shown in FIG. 5B, each arithmetic processing unit 261 to 263 In 263, intermediate values are generated at different timings. Further, since the timing at which the intermediate value is generated is different, the timing at which the high-level valid notification signal (valid) is generated from the first to third arithmetic processing units 261 to 263 is also different. Since the valid notification signal (valid) is output in synchronization with the intermediate value, by using this valid notification signal (valid) as a write control signal, the intermediate value is supplied to the storage unit 272 at the timing when the intermediate value is supplied. Can be written in the storage unit 272.

As a result, all the intermediate values generated in the arithmetic processing units 261 to 263 can be used via the storage unit 272 without being wasted. Therefore, more intermediate values can be used for the calibration process and the like, and more accurate calibration process and the like can be performed.

(Flow of calibration process)
Next, the flow of the calibration process will be described with reference to the flowchart of FIG. First, the control CPU 203 sets print data including calibration pattern data in a print control unit (not shown) (step S1). As a result, a calibration pattern is formed between the recording paper 135 and the next recording paper 135 (step S2), and is read by the density sensors 200A to 200D. The sensor input unit 231 and the input selection unit 232 shown in FIG. 4 acquire the density values of the calibration pattern from the density sensors 200A to 200D (step S3), and sequentially supply them to the data generation unit 233.

The data generation unit 233 compares the density value of the calibration pattern read by the density sensors 200A to 200D with the ideal density value (step S4). The result output unit 271 supplies this comparison result to the next processing block 280 in the subsequent stage as calibration data for performing calibration adjustment. The next processing block 280 adjusts the luminous flux amount of the laser beam output from the optical device 121, the charge amount of the photoconductor drum 122, and the like based on the calibration data from the result output unit 271 to obtain the print density. The shade is adjusted (step S5). As a result, it is possible to prevent the occurrence of printing unevenness in the printing apparatus 100.

(Effect of the first embodiment)
As is clear from the above description, in the printing apparatus 100 of the first embodiment, the input selection unit 232 sequentially selects the density values of the calibration patterns read in parallel by the density sensors 200A to 200D. Then, it is supplied to the data generation unit 233 provided with only one channel. As a result, the density values of the calibration patterns read in parallel by the density sensors 200A to 200D can be supplied to the data generation unit 233 provided with only one channel in a time-division manner. Therefore, in the data generation unit 233, after the intermediate value is generated in the calculation process of the first density value, when the calculation process of the second density value is performed, the second density value is calculated. It is possible to generate an intermediate value in a time-divided manner, such as when an intermediate value corresponding to arithmetic processing is generated.

Further, also in the first to third arithmetic processing units 261 to 263 of the data generation unit 233, the arithmetic processing of the second arithmetic processing unit 262 is started after the arithmetic processing of the first arithmetic processing unit 261 is completed. Each arithmetic processing unit 261 to 263 sequentially performs a predetermined arithmetic processing using the density value. Therefore, each arithmetic processing unit 261 to 263 can also generate an intermediate value in a time-division manner.

Therefore, it is possible to prevent the inconvenience that a plurality of intermediate values are generated at the same time in the data generation unit 233 or the first to third arithmetic processing units 261 to 263. Therefore, it is possible to eliminate the need for an "arbitration circuit" that controls the storage of intermediate values generated at the same time, and it is possible to reduce the circuit scale of the calibration LSI 202. In addition, the manufacturing cost of the calibration LSI 202 can be reduced.

(Second Embodiment)
Next, the printing apparatus of the second embodiment will be described. In the printing apparatus 100 of the first embodiment described above, the input selection unit 232 is used for calibration in which the input selection unit 232 is read in parallel by the density sensors 200A to 200D with respect to the data generation unit 233 provided with only one channel. This was an inconvenient example in which a plurality of intermediate values were generated at the same time by supplying the density value of the pattern in a time division manner. On the other hand, in the printing apparatus of the second embodiment, delay processing for a predetermined delay time is performed on the density values of the calibration patterns read in parallel by the density sensors 200A to 200D. This is an example in which the density value is supplied to the data generation units of a plurality of channels in a time-division manner.

It should be noted that the first embodiment described above and the second embodiment described below differ only in this respect. Therefore, hereinafter, only the difference between the two will be explained, and the duplicate explanation will be omitted.

FIG. 7 shows a block diagram of the calibration system 200 of the second embodiment. In FIG. 7, the parts showing the same operation as in FIG. 4 are designated by the same reference numerals. As shown in FIG. 7, in the case of the calibration system 200 of the second embodiment, data generation units 31 to 314 of the first to fourth channels are provided. Further, in the calibration system 200, first to fourth delay circuits 301 to 304, which are examples of delay processing units, are provided in the input stages of the data generation units 31 to 314. The sensor input unit 231 supplies the density values supplied in parallel from the density sensors 200A to 200D to the data generation units 31 to 314 via the delay circuits 301 to 304, respectively.

In this example, it is assumed that the timing at which the intermediate value is output from each data generation unit 31 to 314 is known in advance. The delay adjustment circuit 305, which is an example of the delay setting unit, is based on the output timing of the intermediate value known in advance, and is such that the intermediate values output from the data generation units 31 to 314 do not overlap each other. The delay time of 301 to 304 is adjusted and set.

As an example, the delay adjustment circuit 305 sets a delay time (no delay time) of "0 seconds" for the first delay circuit 302. As a result, the first data generation unit 311 starts the calculation process for calibration immediately after the concentration value is supplied from the sensor input unit 231. It is assumed that it takes "1 second" for the first data generation unit 311 to complete the arithmetic processing. In this case, in the first data generation unit 311 the intermediate value is generated between the time when the concentration value is supplied from the sensor input unit 231 and the time when one second elapses.

That is, in the case of this example, the first data generation unit 311 has the first to third arithmetic processing units 321 to 223. The first to third arithmetic processing units 321 to 223 perform arithmetic processing for calibration in order using the density value. As a result, intermediate values are sequentially generated in the first to third arithmetic processing units 321 to 223 between the time when the concentration value is supplied to the first data generation unit 311 and one second elapses.

Next, since the delay adjustment circuit 305 requires a time of "1 second" for the first data generation unit 311 to complete the arithmetic processing, the delay time of "1 second" with respect to the second delay circuit 302. To set. As a result, the second data generation unit 312 starts the calculation process of the density value at the timing when the calculation process of the first data generation unit 311 is completed. When the second data generation unit 312 takes "1 second" to complete the arithmetic processing, the second data generation unit 312 completes the arithmetic processing of the first data generation unit 311. An intermediate value will be generated from 1 second to 1 second.

That is, in the case of this example, the second data generation unit 312 has the first to third arithmetic processing units 331 to 333. The first to third arithmetic processing units 331 to 333 perform arithmetic processing for calibration in order using the density value. As a result, intermediate values are sequentially generated in the first to third arithmetic processing units 331 to 333 between the time when the concentration value is supplied to the second data generation unit 312 and one second elapses.

Similarly, in the delay adjustment circuit 305, it takes "1 second" for the second data generation unit 312 to complete the arithmetic processing, so that the delay time is "2 seconds" with respect to the third delay circuit 303. To set. As a result, the third data generation unit 313 starts the calculation process of the density value at the timing when the calculation process of the second data generation unit 312 is completed. When the third data generation unit 313 takes "1.5 seconds" to complete the arithmetic processing, the third data generation unit 313 completes the arithmetic processing of the second data generation unit 312. An intermediate value will be generated between the time when 1.5 seconds have passed.

That is, in the case of this example, the third data generation unit 313 has the first to third arithmetic processing units 341 to 343. The first to third arithmetic processing units 341 to 343 perform arithmetic processing for calibration in order using the density value. As a result, intermediate values are sequentially generated in the first to third arithmetic processing units 341 to 343 within 1.5 seconds after the concentration value is supplied to the third data generation unit 313. ..

Similarly, in the delay adjustment circuit 305, it takes "1.5 seconds" for the third data generation unit 313 to complete the arithmetic processing, so that the delay adjustment circuit 305 takes "3.5 seconds" with respect to the fourth delay circuit 304. Set the delay time. As a result, the fourth data generation unit 314 starts the calculation process of the density value at the timing when the calculation process of the third data generation unit 313 is completed. When it takes "1.7 seconds" for the fourth data generation unit 314 to complete the arithmetic processing, the arithmetic processing of the third data generation unit 313 is completed in the fourth data generation unit 314. An intermediate value will be generated between the time when 1.7 seconds have passed and the time when 1.7 seconds have passed.

That is, in the case of this example, the fourth data generation unit 314 has the first to third arithmetic processing units 351 to 353. The first to third arithmetic processing units 351 to 353 perform arithmetic processing for calibration in order using the density value. As a result, intermediate values are generated in order in the first to third arithmetic processing units 351 to 53 before 1.7 seconds have elapsed since the concentration value was supplied to the fourth data generation unit 314. ..

In this way, the delay adjustment circuit 305 is based on the arithmetic processing time of each data generation unit 31 to 314 so that the intermediate values are generated from each data generation unit 31 to 314 without overlapping by a predetermined time difference. The delay time of 301 to 304 is adjusted and set. This prevents the inconvenience that intermediate values are generated from each data generation unit 31 to 314 at the same time without providing an arbitration circuit even when the arithmetic processing for calibration adjustment is performed in parallel by each data generation unit 31 to 314. can.

The intermediate values generated from the data generation units 31 to 314 with a predetermined time difference pass through the first to third AND gates 241 to 243 and the second OR gate 252, as in the first embodiment described above. Is supplied to the storage unit 272 and is written to the storage unit 272 based on the write control signal generated by the first OR gate 251. Then, the intermediate value written in the storage unit 272 is read out by the control CPU 203 at a predetermined timing and used for calibration adjustment and the like.

(Effect of the second implementation)
As is clear from the above description, in the printing apparatus of the second embodiment, the density values detected by the density sensors 200A to 200D can be processed in parallel by the first to fourth data generation units 31 to 314. Moreover, it is possible to prevent the inconvenience that intermediate values are generated from each of the data generation units 31 to 314 at the same time without providing an arbitration circuit. Therefore, since the density values can be processed in parallel in each of the data generation units 31 to 314, the processing speed of the concentration values can be improved, and the same effect as that of the first embodiment described above can be obtained. be able to.

(Third Embodiment)
Next, the printing apparatus of the third embodiment will be described. In the printing apparatus of the second embodiment described above, the delay adjusting circuit 305 sets the delay time in each of the delay circuits 301 to 304 based on the arithmetic processing time of each of the data generation units 31 to 314 known in advance. It was an example. On the other hand, in the printing apparatus of the third embodiment described below, the delay adjustment circuit detects the generation timing of the intermediate value of each data generation unit 31 to 314 and adjusts based on the detection result. This is an example of setting the delay time for each delay circuit.

It should be noted that each of the above-described embodiments and the third embodiment described below differ only in this respect. Therefore, hereinafter, only the difference between the two will be explained, and the duplicate explanation will be omitted.

FIG. 8 shows a block diagram of the calibration system 200 of the third embodiment. In FIG. 8, the parts showing the same operation as those in FIGS. 4 and 7 are designated by the same reference numerals. As shown in FIG. 8, in the case of the calibration system 200 of the third embodiment, the delay adjustment circuit 400 that sets the delay time for each of the delay circuits 301 to 304 is an example of the timing difference measuring unit. It has a timing difference measurement sequencer 401.

The timing difference measurement sequencer 401 is output while valid intermediate values are output from the arithmetic processing units 321-23, 331-333, 341-343, and 351-353 of each data generation unit 31 to 314. The generation timing difference of the high-level valid notification signal (valid) is measured. When the generation timing difference of the valid notification signal (valid) detected by the timing difference measurement sequencer 401 is "0 (simultaneous)", the delay adjustment circuit 400 changes and sets the delay time of the delay circuit of the corresponding channel. The timing difference measurement sequencer 401 remeasures the generation timing difference of the valid notification signal (valid) of the delay circuit whose delay time has been changed, and the generation timing difference of the valid notification signal (valid) is "0 (simultaneous)". Check if it exists.

In the delay adjustment circuit 400, intermediate values are generated at different timings from the arithmetic processing units 321-23, 331-333, 341-343, and 351-353 of the data generation units 31 to 314 (at the same time, the intermediate values). The delay time is set in each of the delay circuits 301 to 304 based on the detection result of the timing difference measurement sequencer 401 described above.

(Effect of the third embodiment)
As a result, the delay circuits 301 to 304 are generated so that intermediate values are generated at different timings from the arithmetic processing units 321-23, 331-333, 341-343, and 351-353 of the data generation units 31 to 314. Delay time can be adjusted. Further, after adjusting the delay time of each of the delay circuits 301 to 304 once, the timing difference measurement sequencer 401 continuously monitors the generation timing difference of the valid notification signal (valid), so that the generation timing of the intermediate value is real-time. Can be modified with. Therefore, for example, it is possible to prevent the inconvenience that the intermediate values are generated at the same time due to aging or the like, it is possible to store more intermediate values in the storage unit 272, and the same effect as that of each of the above-described embodiments is obtained. be able to.

The timing difference measurement sequencer 401 may detect the generation timing difference of the valid notification signal (valid) at all times while the printing device is energized. For example, when the printing device is started, the timing specified by the administrator, Alternatively, it may be executed at an arbitrary timing such as when the operation is suspended for a predetermined time or longer.

Finally, each of the above embodiments is presented as an example and is not intended to limit the scope of the invention. Each of the novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. Moreover, each embodiment and the modification of each embodiment are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalent scope thereof.

100 Printing device 200 Calibration system 200A Density sensor 200B Density sensor 200C Density sensor 200D Density sensor 202 Calibration LSI
203 control CPU
204 Analog / Digital Converter (ADC)
220 Calibration processing unit 221 Control CPU interface 231 Sensor input unit 232 Input selection unit 233 Data generation unit 241 First AND gate 242 Second AND gate 243 Third AND gate 251 First OR gate 252 Second OR Gate 261 First arithmetic processing unit 262 Second arithmetic processing unit 263 Third arithmetic processing unit 271 Result output unit 272 Storage unit 273 Storage control unit 280th processing block 301 First delay circuit 302 Second delay circuit 303 3rd delay circuit 304 4th delay circuit 305 Delay adjustment circuit 311 1st channel data generation unit 312 2nd channel data generation unit 313 3rd channel data generation unit 314 4th channel data generation unit Part 400 Delay adjustment circuit 401 Timing difference measurement sequencer

Japanese Unexamined Patent Publication No. 2003-228201

Claims (8)

A timing control unit that controls a plurality of information processing units that process input information with predetermined information processing and output output information so as to output the output information at different timings.
A write control unit that controls writing of the output information from each information processing unit to a storage unit,
An information processing system in which a plurality of the above-mentioned information processing units are connected in series is provided for a plurality of channels.
The timing control unit
A plurality of delay processing units that perform delay processing for a predetermined delay time on each of the plurality of input information supplied in parallel and supply the information processing system of each channel, respectively.
A predetermined delay is given to each delay processing unit that supplies the input information to the information processing system of each channel so that the output information is output from the information processing system of each channel at different timings. Having a delay setting unit that sets the time
An information processing device characterized by. Each of the information processing units is connected in series to form an information processing system for at least one channel, and the input is sequentially described from the information processing unit that is the input end to the information processing unit that is the output end. The information is processed and output as specified, and then output.
The information processing apparatus according to claim 1, wherein the timing control unit sequentially selects a plurality of the input information supplied in parallel and supplies the information processing unit as the input end. .. The timing control unit selects the input information to be processed next at the timing when the information processing for the input information is completed in each information processing unit and supplies it to the information processing unit serving as the input end. The information processing apparatus according to claim 2, wherein the information processing device is characterized by the above. A timing difference measuring unit for measuring the output timing difference of the output information output from the information processing system of each channel is further provided.
The delay setting unit is claimed from claim 1 , wherein a predetermined delay time is set for each delay processing unit based on the output timing difference measured by the timing difference measurement unit. Item 3. The information processing apparatus according to any one of items 3. While the valid output information is being output from each of the information processing units, the write control unit writes and controls the output information to the storage unit at the timing of the discrimination information output from each of the information processing units. The information processing apparatus according to any one of claims 1 to 4, wherein the information processing apparatus is characterized in that. Claims 1 to 5 are characterized in that the output information is an intermediate value which is an information processing result located at the center when a finite number of information processing results in each information processing unit are arranged in ascending order. The information processing apparatus according to any one of the above. The information processing apparatus according to any one of claims 1 to 6, wherein the timing control unit and the write control unit are integrated circuits. The information processing apparatus according to any one of claims 1 to 7.
A printing device having a printing unit that performs a calibration process for reducing printing unevenness based on the output information stored in the storage unit of the information processing device and prints a predetermined printed matter.

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