JP6885801B2 - Bank dual port memory - Google Patents

Description

The present invention relates to a method of exchanging data between two microprocessors in a computer system composed of two microprocessors and a dual port memory.

Microprocessors are widely used in industrial control equipment and are responsible for the production of many products. And because of the increasingly complex and sophisticated functions, multiple microprocessors are used to perform distributed processing.

For example, in a PLC (Programmable Logic Controller) device, it is widely practiced to use a microprocessor suitable for each process for execution of a ladder program, signal input / output processing, positioning control, and the like. Further, in the inverter device for driving the motor, a control microprocessor suitable for the inverter drive of the motor is used, for example, a communication microprocessor is used for data transmission / reception with another general monitoring device. ing. Here, the microprocessor is also referred to as an MPU below.

A dual-port memory (hereinafter, the dual-port memory is also referred to as DPM) is often used for exchanging data between MPUs, and FIG. 12 shows an example of using MPU and DPM which is normally carried out. Will be shown and this will be explained.

In FIG. 12, 1 and 2 are microprocessors MPUA and MPUB, and 3 is a dual port memory DPM. The MPUA1 and the MPUB2 exchange a plurality of data via the DPM3, and the MPUA1 and the DPM3 are connected by a control bus 11, an address bus 12, a data bus 13, and a busy signal 14, and similarly, the MPUB2. And DPM3 are connected by a control bus 21, an address bus 22, a data bus 23, and a busy signal 24, and the control buses 11 and 21 include a read signal and a write signal.

Similarly, in FIG. 12, if the address buses 12 and 22 indicate different addresses, the DPM 3 can access the read or write from the MPUA1 and the MPUB2 at the same time, but at the same time, the DPM3 indicates the same address (this can be seen). When the DPM3 is arbitrated by the built-in arbitration function, for example, the busy signal 14 to the MPUA1 that allows access is made inactive, and the busy signal 14 to the MPUB2 that does not allow access is made inactive. The signal 24 is activated. As a result, the MPUA1 can access the DPM3, but the MPUB2 is in a waiting state until the address conflict state disappears and the busy signal 24 becomes inactive.
Here, in FIG. 12, the synchronization signal 15 is intended to synchronize the program execution of the MPUA1 and the MPUB2, which will be described later.

Many inventions have been conventionally made regarding such a method of using the dual port memory. For example, in Patent Document 1, the flag A by hardware is used between two microprocessors without using the arbitration function built in the dual port memory. And the invention in which the connection of the flag B is provided and the mediation is performed by software is disclosed. When using the dual port memory, it is important to surely perform the processing in the race condition, and it is considered that Patent Document 1 pays attention to this.

Further, in Patent Document 2, when two microprocessors try to transfer a large amount of data via the dual port memory, time is spent only in the data transfer process to the dual port memory, and the main functions and performances are related. It cites the problem of running out of processing time. Then, in order to solve this problem, an invention is disclosed in which an interrupt signal is connected by hardware between two microprocessors and the problem is solved by synchronous access and asynchronous access.

Next, Patent Document 3 cites the problem of guaranteeing data simultaneity and ensuring high-speed data transfer in writing and reading data between two microprocessors. To solve this problem, an invention that solves the problem is disclosed by providing a write area selection signal generation circuit by hardware between two microprocessors.

Japanese Unexamined Patent Publication No. 5-250250 Japanese Unexamined Patent Publication No. 2000-242610 Japanese Unexamined Patent Publication No. 2007-328647

The problem to be solved by the present invention is to prevent a race condition from occurring and the processing time of the MPU from becoming long when two MPUs exchange a plurality of data via the DPM. The purpose is to ensure the simultaneity of the above, and to eliminate the need to add new hardware even for different types of DPM. Next, the contents of these problems will be described in more detail with reference to FIGS. 12 and 13 and 14.

First, FIG. 13 illustrates the synchronous operation of the conventional DPM usage example of FIG. 12, and FIGS. 13A, 13B, and 13C each process the MPUA1. , The processing of the synchronization signal 15, and MPUB2 is shown with the passage of time.
Then, in FIG. 13A, it is assumed that the MPUA1 sequentially executes the processes of a1, a2, a3, and a4 at the times Ta1, Ta2, Ta3, and Ta4 in the cycle ta. The ta11 shown in white in the process a1 represents the job time for executing a predetermined job without the MPUA1 competing with the MPUB2, and the shaded ta13 indicates that the MPUA1 competes with the MPUB2. It represents the total waiting time that was waited for by waiting. Further, ta12 in the figure is a margin time, and the waiting time ta13 needs to be shorter than the margin time ta12.

Here, if the description is added in the process a1, the waiting of the MPUA1 can occur in the entire range of the time (ta11 + ta13), and the fact that the processing time becomes longer due to the occurrence of the waiting is added to the ta13. It should be noted that it is represented.
Further, also in the processes a2, a3, and a4, the shaded portion represents the total waiting time of each.

Next, the synchronization signal 15 of FIG. 12 is a flag output when the MPUA1 starts processing as shown in FIG. 13B. Then, as shown in FIG. 13 (c), the MPUB 2 sequentially executes the processes of b1, b2, b3, and b4 in synchronization with the synchronization signal 15. Here, in the processes b1 to b4, the white portion and the shaded portion are the total of the job time and the waiting time of the MPUB2, respectively.

As described above with reference to FIG. 13, a waiting time occurs when the MPUA1 and the MPUB2 exchange data via the DPM3. Then, to give a specific example, when the MPUA1 controls an inverter device for driving a motor and the MPUB2 controls communication such as PROFIBUS, the waiting time of the MPUA1, that is, the length of the processing time is caused by the operation of the MPUB2. Will be affected. However, the MPUA1 controls the power element of the inverter, and unexpected influences such as a change in the length of the processing time should be eliminated.
Thereby, the first object of the present invention is to eliminate the race condition due to DPM so that the waiting time does not occur in the MPU.

Next, the second problem of the present invention will be described again with reference to FIG. When the MPUB2 receives data from the MPUA1, the timing of the process a2 of FIG. 13A and the process b2 of FIG. 13C will be described. The MPUA1 transfers all the data to the DPM3 in the process a2. The light is completed at the time Ta2E. In other words, the data that the MPUA1 has written to the DPM3 from the time Ta2 to the time Ta2E is a mixture of the processing a1 and the processing a2.

Therefore, the MPUB2 reads the mixed data of the processes a1 and a2 in the process b2. This is an obstacle because the MPUB2 loses simultaneity when it tries to receive the current, voltage, or torque command of the inverter at the same time, for example. Further, even when a plurality of data are used as one physical quantity, the data obtained by the processes a1 and a2 are mixed and a problem occurs. Thereby, the second object of the present invention is to ensure the simultaneity of a plurality of data.

Next, a third object of the present invention is to eliminate the hardware connection of the busy signals 14, 15 and the synchronization signal 15 in FIG. This eliminates the need to design the timing of weighting of the microprocessor by busy signals, and enables the same dual-port memory to be used regardless of the DPM supplier or type, realizing a simple DPM system. Can be done.

Next, FIG. 14 illustrates the asynchronous operation in the conventional DPM usage example, and is the case where the synchronization signal 15 is not used in FIG. (A) and (c) of FIG. 14 represent the processing of the MPUA1 and the processing of the MPUB2 with the passage of time, respectively. The a1 to a4, ta11, and ta13 shown in the process of (a) MPUA1 in FIG. 14 are the same as those having the same reference numerals in (a) of FIG. 13, and the description thereof will be omitted. Further, b1 to b4, tb11, and tb13 shown in the process of (c) MPUB2 in FIG. 14 are the same as those having the same reference numerals in (c) of FIG. 13, and the description thereof will be omitted.
As shown in FIG. 14, the MPDUA1 and MPDUB2 are not synchronized and the processing is repeated in each cycle.

Further, in a1 to a4 and b1 to b4 of FIG. 14, the white portion represents the job time and the shaded portion represents the total waiting time. Although weighting also occurs in FIG. 14, the first problem of the present invention is to eliminate the race condition due to DPM so that the waiting time does not occur in the MPU even in the case of the asynchronous type.

Next, regarding the simultaneity of the data in FIG. 14, the case where the MPUA1 receives the data from the MPUB2 will be described. First, in the processes b2 and a2, the time T1 is the time when the process b2 ends, and the time T2 is the time when the process b3 starts. Then, in the process a2, the contents of the data received by the MPUA1 from the MPUB2 via the DPM3 are summarized as shown in Table 1, and in the worst case, the data of the processes b1 to b3 are mixedly received. Therefore, even in the case of the asynchronous type, the second object of the present invention is to ensure the simultaneity of a plurality of data.
(Table 1)

Further, also in the asynchronous type FIG. 14, the third problem is to eliminate the hardware connection of the busy signals 14 and 15.

In the present invention, the above problems are solved as follows.
(1) In a microprocessor system composed of two microprocessors MPUA1 and MPUB2 and a dual port memory, the MPUA1 and MPUB2 exchange a plurality of data via the dual port memory.
Then, a bank A pointer, a bank A memory, a bank B pointer, and a bank B memory are provided in the dual port memory, and the MPUA1 sends a plurality of data to the MPUB2 using the bank A pointer and the bank A memory. The MPUB2 has a function of sending a plurality of data to the MPUA1 by using the bank B pointer and the bank B memory.
Here, the bank A memory is composed of banks A0 to banks A (n-1) and n of the banks, with memory areas of a plurality of consecutive addresses as one bank, and the bank A pointer is the same. A value from 0 to (n-1) is set in MPUA1 to specify one of the n banks.
Then, the MPUA1 writes a plurality of data to the bank designated by the bank A pointer in order to send the plurality of data to the MPUB2 via the bank A memory of the dual port memory for each process. Next, the MPUA1 updates the value of the bank A pointer by 1 in the range of 0 to (n-1) after the write is completed.
Further, when the MPUB2 receives a plurality of data from the MPUA1 via the bank A memory of the dual port memory for each process, the MPUB2 has a plurality of data from the bank one before the bank specified by the bank A pointer. Is sequentially read according to the progress of processing.
On the other hand, the bank B memory is composed of banks B0 to bank B (n-1) and n of the banks, with the memory areas of a plurality of consecutive addresses as one bank, and the bank B pointer is the MPUB2. In, a value from 0 to (n-1) is set to specify one of the n banks.
Then, the MPUB 2 writes a plurality of data to the bank designated by the bank B pointer in order to send the plurality of data to the MPUA 1 via the bank B memory of the dual port memory for each process. Next, the MPUB2 updates the value of the bank B pointer by 1 in the range of 0 to (n-1) after the write is completed.
Further, when the MPUA1 receives a plurality of data from the MPUB2 via the bank B memory of the dual port memory for each process, the MPUA1 receives a plurality of data from the bank one before the bank specified by the bank B pointer. This is a bank-type dual-port memory characterized in that the memory is sequentially read according to the progress of processing.

(2) In the above (1), the MPUA1 and the MPUB2 include a temporary memory A and a temporary memory B, respectively.
When the MPUB2 receives a plurality of data from the MPUA1 via the bank A memory of the dual port memory for each process, the MPUB2 receives a plurality of data from the bank one before the bank specified by the bank A pointer. After reading continuously and saving in the temporary memory B in a batch, data is read from the temporary memory B sequentially according to the progress of the process.
Further, when the MPUA1 receives a plurality of data from the MPUB2 via the bank B memory of the dual port memory for each process, the MPUA1 receives a plurality of data from the bank one before the bank specified by the bank B pointer. This is a bank-type dual-port memory characterized in that data is continuously read from the temporary memory A, and then data is sequentially read from the temporary memory A according to the progress of processing.

As explained above, when two microprocessors send and receive multiple data via the dual port memory, the conflict state of the dual port memory is resolved and the microprocessor operates stably without falling into the waiting state. As a result, the reliability of control by the microprocessor is improved.
It also guarantees the simultaneity of data exchanged between the two microprocessors, enabling accurate data control execution and tracing of various data.
The number of signal connections between the microprocessor and the dual-port memory is minimized, and various dual-port memories can be used with the minimum connection with the microprocessor regardless of the supplier and type. It is a thing.

It is a figure (the 1) explaining the structure of Example 1 of the bank type DPM by this invention. It is a figure (the 2) explaining the structure of Example 1 of the bank type DPM by this invention. It is a figure (the 1) explaining the data transfer of Example 1. FIG. It is a figure (the 2) explaining the data transfer of Example 1. FIG. It is a figure (the 3) explaining the data transfer of Example 1. FIG. It is a figure (the 4) explaining the data transfer of Example 1. FIG. It is a figure (the 1) explaining the structure of Example 2 of the bank type DPM by this invention. It is a figure (the 2) explaining the structure of Example 2 of the bank type DPM by this invention. It is a figure (the 1) explaining the data transfer of Example 2. FIG. It is a figure (the 2) explaining the data transfer of Example 2. FIG. FIG. 3 is a diagram (No. 3) for explaining the data transfer of the second embodiment. It is a figure explaining the use example of the conventional DPM. It is a figure (synchronous type) explaining the operation of the conventional DPM. It is a figure (asynchronous type) explaining the operation of the conventional DPM.

Hereinafter, the present invention will be described with reference to diagrams of examples. FIG. 1 shows Example 1 of the present invention, FIGS. 2, 3, 4, 5, and 6 supplementarily explain the operation of FIG. 1, and FIG. 7 shows Example 2 of the present invention. 8, FIG. 9, FIG. 10, and FIG. 11 supplementarily explain the operation of FIG. 7.

FIG. 1 is a diagram illustrating a configuration of a first embodiment of a bank type dual port memory according to the present invention. In FIG. 1, the MPUA 1, the control bus 11, the address bus 12, the data bus 13, and the MPUB 2, the control bus 21, the address bus 22, and the data bus 23 have the same functions as those having the same reference numerals in FIG. I will omit the explanation of this. Further, the DPM3 has the same dual port memory function as the DPM3 of FIG. 12, but the present invention is characterized by the internal configuration of the DPM3.

In DPM3 of FIG. 1, 31 and 32 are a bank A pointer and a bank A memory, respectively, and these are for sending data from the MPUA1 to the MPUB2. The bank A memory 32 is composed of banks A0, banks A1 to banks A (n-1), and n banks, with memory areas of a plurality of consecutive addresses as one bank. Here, each of banks A0 to A (n-1) is collectively referred to as bank A.

Further, to simplify the explanation, if a numerical example is shown, when the physical data size of the DPM3 is 1 word, the size of the bank A pointer 31 is 1 word, and the bank A0 to the bank A (n−). The size of each bank A in 1) is, for example, 40 words of consecutive addresses. At this time, the size of the bank A memory 32 is (40 × n) words.
Then, the bank A pointer 31, the bank A memory 32, and the bank A0 to the bank A (n-1) are memory-mapped in the DPM3.

Next, a procedure in which the MPUA1 sends a plurality of data to the MPUB2 via the DPM3 will be described with reference to a to e shown in FIG.
a: The MPUA1 reads the bank A pointer 31 at the beginning of processing.
b: The MPUA1 is among the banks A0 to A (n-1).
No. indicated by the bank A pointer 31. In bank A of
Write a plurality of data to be sent to the MPUB2.
c: The MPUA1 adds the value of the bank A pointer 31 by 1 at the end of processing. However, if the value becomes n or more as a result of the addition, 0 is written to the bank A pointer 31.

d: The MPUB 2 reads the bank A pointer 31 at the beginning of processing.
e: The MPUB2 is among the banks A0 to A (n-1).
When the bank A pointer 31 is 1 to (n-1), the NO. From Bank A of
When the bank A pointer 31 is 0, from bank A (n-1),
Multiple data are read sequentially according to the progress of processing.

Here, the MPUA1 and the MPUB2 execute their respective processes asynchronously with each other. Further, in c, the value of the bank A pointer 31 is added to the rotary up counter by adding 1, but instead of this, the value of the bank A pointer 31 may be subtracted by 1 to be used as the rotary down counter.

In this way, when the MPUA1 sends a plurality of data to the MPUB2 via the DPM3, the bank A written by the MPUA1 and the bank A read by the MPUB2 are based on the bank A pointer 31. Since they are always different, a race condition does not occur in the DPM3, so that the MPUA1 and the MPUB2 do not fall into a waiting state.
Further, since the MPUB2 always reads data from the bank A in which the MPUA1 has completed writing, the simultaneity of a plurality of data is ensured.
Further, as shown in FIG. 1, there is no hardware connection between the MPUA1 and the MPUB2, which eliminates the need for timing design of the weighting of the microprocessor by a busy signal.

Next, a configuration and a procedure for sending data from the MPUB2 to the MPUA1 will be described. In DPM3 of FIG. 1, 33 and 34 are a bank B pointer and a bank B memory, respectively, and these are for sending data from the MPUB2 to the MPUA1. The bank B memory 34 is composed of banks B0, banks B1 to banks B (n-1), and n banks, with memory areas of a plurality of consecutive addresses as one bank. Here, each of bank B0 to bank B (n-1) is collectively referred to as bank B.

Further, to simplify the explanation, if a numerical example is shown, when the physical data size of the DPM3 is 1 word, the size of the bank B pointer 33 is 1 word, and the size of the bank B0 to the bank B (n-). The size of each bank B in 1) is, for example, 40 words of consecutive addresses. At this time, the size of the bank B memory 34 is (40 × n) words.
Then, the bank B pointer 33, the bank B memory 34, and the bank B0 to the bank B (n-1) are memory-mapped in the DPM3.

Next, in FIG. 2, a procedure in which the MPUB2 sends a plurality of data to the MPUA1 via the DPM3 will be described. In FIG. 2, f, g, and h indicate a procedure in which the MPUB2 writes data to the DPM3, and i and j indicate a procedure in which the MPUA1 reads data from the DPM3. Those having a reference numeral other than f to j have the same function as those having the same reference numeral in FIG. 1, and the description thereof will be omitted.

Next, it will be described from f to j shown in FIG.
f: The MPUB 2 reads the bank B pointer 33 at the beginning of processing.
g: The MPUB2 is among the banks B0 to B (n-1) from the bank B0.
No. indicated by the bank B pointer 33. In bank B of
Write a plurality of data to be sent to the MPUA1.
h: The MPUB 2 adds the value of the bank B pointer 33 by 1 at the end of processing. However, if the value becomes n or more as a result of the addition, 0 is written to the bank B pointer 33.

i: The MPUA1 reads the bank B pointer 33 at the beginning of processing.
j: The MPUA1 is among the banks B0 to B (n-1).
When the bank B pointer 33 is 1 to (n-1), the NO. From Bank B
When the bank B pointer 33 is 0, from bank B (n-1),
Multiple data are read sequentially according to the progress of processing.

Here, the MPUB2 and the MPUA1 execute their respective processes asynchronously with each other. Further, in h, the value of the bank B pointer 33 is added to the rotary up counter by adding 1, but instead of this, the value of the bank B pointer 33 may be subtracted by 1 to be used as the rotary down counter.

In this way, when the MPUB2 sends a plurality of data to the MPUA1 via the DPM3, the bank B written by the MPUB2 and the bank B read by the MPUA1 are transferred based on the bank B pointer 33. Since they are always different, no race condition occurs in the DPM3, so that the MPUB2 and the MPUA1 do not fall into the waiting state.
Further, since the MPUA1 always reads data from the bank B in which the MPUB2 has completed writing, the simultaneity of a plurality of data is ensured.
Further, as shown in FIG. 2, there is no hardware connection between the MPU B2 and the MPU A1, which eliminates the need for timing design of the weighting of the microprocessor by the busy signal.

The configuration and procedure for sending data from the MPUA1 to the MPUB2 in FIG. 1 and from the MPUB2 to the MPUA1 in FIG. 2 have been described. Although both of these are similar operations, the temporal transition of each state with respect to FIG. 1 is shown in FIGS. 3, 4, 5, and 6, and the first embodiment of the present invention will be described. ..

First, in FIG. 3, (a) and (b) represent the process executed by the MPUA1 in FIG. 1, and the time transition of the value of the bank A pointer 31, respectively. Then, as shown in (a) of FIG. 3, the MPUA1 sequentially executes the processing A1, the processing A2, the processing A3, and the processing A4 at a predetermined cycle, and the way shown in the (a) of FIG. There is no ting time. Further, the times TA1, TA2, TA3, and TA4 in the figure represent the times when the processes A1 to A4 are completed, respectively.

Next, in FIG. 1, the bank A memory 32 is composed of n banks, and is shown in FIG. 3 when n is 4. Then, the bank A pointer 31 of FIG. 3 (b) specifies the bank A2 until the time TA1, and in (a) of FIG. 3, the MPUA1 sequentially outputs data according to the progress of the process A1. Light to bank A2. Then, at the time TA1 at the end of the process A1, the bank A pointer 31 of FIG. 3 (b) is added by 1 to obtain 3. Subsequently, the bank A pointer 31 of FIG. 3 (b) transitions to 0, 1, and 2, respectively, at the times TA2, TA3, and TA4.

Next, (c) and (d) of FIG. 3 represent the process executed by the MPUB 2 of FIG. 1, and the temporal transition of the bank A accessed (read) by the MPUB 2, respectively. First, as shown in (c) of FIG. 3, the MPUB2 sequentially executes processing B1, processing B2, processing B3, and processing B4 at a predetermined cycle, and the way shown in (c) of FIG. 13 There is no ting time. Further, the times TB1, TB2, TB3, and TB4 in the figure represent the times when the processes B1 to B4 start, respectively.

Next, FIG. 3D shows the transition of the bank A that the MPUB2 leads, and which bank A leads the bank A is determined at the start of the process. Further explaining this with reference to FIGS. 3 (c) and 3 (d), the MPUB 2 reads the value 3 of the bank A pointer 31 when the process B1 is started, and subtracts this by 1, that is, the bank. Leads are taken from A2, and the leads are sequentially read according to the progress of the process B1. Similarly, in the MPUB2, at the times TB2, TB3, and TB4, the banks A that are read in the processes B2, B3, and B4 are designated as banks A3, bank A0, and bank A0, respectively.

Here, when (b) and (d) of FIG. 3 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different. As a result, the race condition between the MPUA1 and the MPUB2 does not occur in the DPM3, and both the MPUA1 and the MPUB2 do not fall into the waiting state.
Further, since the MPUB2 always reads data from the bank A in which the MPUA1 has completed writing, the simultaneity of a plurality of data is ensured.
Further, since the arbitration by software is performed by the bank A pointer 31, it is not necessary to connect and arbitrate by hardware between the MPUA1 and the MPUB2.

Here, FIG. 3 assumes a case where the MPUA1 and the MPUB2 operate asynchronously and their processing times are substantially equal. Further, the shading following the time TB4 in FIG. 3D indicates that the bank A0 led by the MPUB2 continues from the previous time TB3.

The time transition of each state in FIG. 1 has been described with reference to FIG. 3, and then the transition with reference to FIG. 4 will be described. (A), (b), (c), and (d) of FIG. 4 represent the temporal transition of the same item as that of FIG. 3, and those having a reference numeral in FIG. 4 are shown in FIG. Those with the same reference numerals have the same functions and roles, and their explanations are omitted.

The difference from FIG. 3 shows the time transition when the processing time of the MPUA1 shown in FIG. 4A is longer than the processing time of the MPUB2 shown in FIG. 4C. .. At this time, when (b) and (d) of FIG. 4 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different. As a result, the object of the present invention can be achieved without causing a race condition between the MPUA1 and the MPUB2 in the DPM3.
Here, the shading in FIG. 4D indicates that the bank A led by the MPUB 2 continues from the processing one cycle before.

Further, the temporal transition of each state in FIG. 1 will be described with reference to FIG. 5 following FIGS. 3 and 4. (A), (b), (c), and (d) of FIG. 5 represent the temporal transition of the same item as that of FIG. Those with the same code have the same function and role, and the explanation is omitted.

The difference between FIGS. 3 and 4 and FIG. 5 is that the processing time of the MPUA1 shown in FIG. 5A is shorter than the processing time of the MPUB2 shown in FIG. 5C. It shows the transition.

Here, when (b) and (d) of FIG. 5 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 should always be different, but the same bank A3 is obtained from time TA8 to TB4. ing. As a result, in the DPM3, a race condition can occur between the MPUA1 and the MPUB2, which hinders the achievement of the object of the present invention. As a countermeasure against this, the number of banks A may be increased, which will be described with reference to FIG.

Here, the TA8 is the time at which the process A8 ends in (a) of FIG. Further, the shaded bank A in FIG. 5B represents a bank A in which the MPDUB2 does not lead even if the MPDUA1 writes to the bank A.

Although the number of banks A was 4 in FIG. 5, a case where this is set to 5 will be described with reference to FIG. (A), (b), (c), and (d) of FIG. 6 represent the temporal transition of the same item as that of FIG. 5, and those having a reference numeral in FIG. 6 are shown in FIG. It has the same function and role as those with the same code, and the explanation is omitted.

In FIG. 6B, the bank A pointer 31 transitions in the range of 0 to 4. Comparing (b) and (d) in FIG. 6, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different not only from time TA8 to TB4 but also in all periods. ..

In this way, when the MPUA1 sends a plurality of data to the MPUB2 via the DPM3, the bank A written by the MPUA1 and the bank A read by the MPUB2 are based on the bank A pointer 31. Since they are always different, a race condition does not occur in the DPM3, so that the MPUA1 and the MPUB2 do not fall into a waiting state.
Further, since the MPUB2 always reads data from the bank A in which the MPUA1 has completed writing, the simultaneity of a plurality of data is ensured.
Further, as shown in FIG. 1, there is no hardware connection between the MPUA1 and the MPUB2, which eliminates the need for weighting and interrupt timing design of the microprocessor by a busy signal.

Up to this point, the temporal transition of the configuration for transmitting data from the MPUA1 in FIG. 1 to the MPUB2 has been described with reference to FIGS. 3 to 6. The time transition when data is sent from the MPUB 2 to the MPUA 1 shown in FIG. 2 is also the same as in FIGS. 3 to 6.

Next, FIG. 7 is a diagram illustrating the configuration of the second embodiment of the bank type dual port memory according to the present invention. In FIG. 7, those having the same reference numerals as those in FIG. 1 have the same functions, and the description thereof will be omitted. And in FIG. 7, 16 is a temporary memory A which the MPUA1 is built in or is arranged outside. Similarly, reference numeral 26 denotes a temporary memory B built in or externally provided by the MPUB 2.

First, a procedure in which the MPUA1 sends a plurality of data to the MPUB2 via the DPM3 will be described with reference to a to f shown in FIG. 7.

a: The MPUA1 reads the bank A pointer 31 at the beginning of processing.
b: The MPUA1 is among the banks A0 to A (n-1).
No. indicated by the bank A pointer 31. In bank A of
Write a plurality of data to be sent to the MPUB2.
c: The MPUA1 adds the value of the bank A pointer 31 by 1 at the end of processing. However, if the value becomes n or more as a result of the addition, 0 is written to the bank A pointer 31.

d: The MPUB 2 reads the bank A pointer 31 at the beginning of processing.
e: The MPUB2 is among the banks A0 to A (n-1).
When the bank A pointer 31 is 1 to (n-1), the NO. From Bank A of
When the bank A pointer 31 is 0, from bank A (n-1),
Read all the data at once at the beginning of the process.

f: The MPUB2 collectively reads all the data read in the above e.
Saved in the temporary memory B26,
The data from the MPUA1 is sequentially read from the temporary memory B26 according to the progress of the processing.

Here, the MPUA1 and the MPUB2 execute their respective processes asynchronously with each other. Further, in c, the value of the bank A pointer 31 is added to the rotary up counter by adding 1, but instead of this, the value of the bank A pointer 31 may be subtracted by 1 to be used as the rotary down counter.

In this way, when the MPUA1 sends a plurality of data to the MPUB2 via the DPM3, the bank A written by the MPUA1 and the bank A read by the MPUB2 are based on the bank A pointer 31. Since they are always different, a race condition does not occur in the DPM3, so that the MPUA1 and the MPUB2 do not fall into a waiting state.
Further, since the MPUB2 always reads data from the bank A in which the MPUA1 has completed writing, the simultaneity of a plurality of data is ensured.
Further, as shown in FIG. 7, there is no hardware connection between the MPUA1 and the MPUB2, which eliminates the need for timing design of the weighting of the microprocessor by the busy signal.

Next, in FIG. 8, a procedure in which the MPUB2 sends a plurality of data to the MPUA1 via the DPM3 will be described. In FIG. 8, h, i, and j indicate a procedure in which the MPUB2 writes data to the DPM3, and k, m, and n indicate a procedure in which the MPUA1 reads data from the DPM3. Those having a reference numeral other than h to n have the same function as those having the same reference numerals in FIG. 7, and the description thereof will be omitted.

Then, it will be described from h to n shown in FIG.
h: The MPUB 2 reads the bank B pointer 33 at the beginning of processing.
i: The MPUB2 is among the banks B0 to B (n-1).
No. indicated by the bank B pointer 33. In bank B of
Write a plurality of data to be sent to the MPUA1.
j: The MPUB 2 adds the value of the bank B pointer 33 by 1 at the end of processing. However, if the value becomes n or more as a result of the addition, 0 is written to the bank B pointer 33.

k: The MPUA1 reads the bank B pointer 33 at the beginning of processing.
m: The MPUA1 is among the banks B0 to B (n-1).
When the bank B pointer 33 is 1 to (n-1), the NO. From Bank B
When the bank B pointer 33 is 0, from bank B (n-1),
Read all the data at once at the beginning of the process.

n: The MPUA1 collectively reads all the data read in m above.
Save to the temporary memory A16,
The data from the MPUB 2 is sequentially read from the temporary memory A16 according to the progress of the processing.

Here, the MPUB2 and the MPUA1 execute their respective processes asynchronously with each other. Further, in the above j, the value of the bank B pointer 33 is set as a rotary up counter by adding only 1, but instead of this, it may be used as a rotary down counter by subtracting only 1.

In this way, when the MPUB2 sends a plurality of data to the MPUA1 via the DPM3, the bank B written by the MPUB2 and the bank B read by the MPUA1 are transferred based on the bank B pointer 33. Since they are always different, no race condition occurs in the DPM3, so that the MPUB2 and the MPUA1 do not fall into the waiting state.
Further, since the MPUA1 always reads data from the bank B in which the MPUB2 has completed writing, the simultaneity of a plurality of data is ensured.
Further, as shown in FIG. 8, there is no hardware connection between the MPU B2 and the MPU A1, which eliminates the need for timing design of the weighting of the microprocessor by the busy signal.

Regarding Example 2 of the present invention, the configuration and procedure for sending data from the MPUA1 to the MPUB2 according to FIG. 7 and from the MPUB2 to the MPUA1 according to FIG. 8 have been described. Although both of these operations are similar, the temporal transition of each state is shown in FIGS. 9, 10 and 11 as a representative of FIG. 7, and the second embodiment of the present invention will be described.

First, FIG. 9 will be described, which corresponds to FIG. 3 of the first embodiment. By the way, in FIG. 9, (a) and (b) represent the process executed by the MPUA1 of FIG. 7, respectively, and the temporal transition of the value of the bank A pointer 31. Then, as shown in (a) of FIG. 9, the MPUA1 sequentially executes the processing A1, the processing A2, the processing A3, and the processing A4 at a predetermined cycle, and the way shown in the (a) of FIG. There is no ting time. Further, the times TA1, TA2, TA3, and TA4 in the figure represent the times when the processes A1 to A4 are completed, respectively.

Next, in FIG. 7, the bank A memory 32 is composed of n banks, and is shown in FIG. 9 when n is 4. Then, the bank A pointer 31 of FIG. 9 (b) specifies the bank A2 until the time TA1, and in (a) of FIG. 9, the MPUA1 sequentially outputs data according to the progress of the process A1. Light to bank A2. Then, at the time TA1 at the end of the process A1, the bank A pointer 31 of FIG. 9 (b) is added by 1 to obtain 3. Subsequently, the bank A pointer 31 of FIG. 9 (b) transitions to 0, 1, and 2, respectively, at the times TA2, TA3, and TA4.

Next, (c) and (d) of FIG. 9 represent the process executed by the MPUB 2 of FIG. 7, respectively, and the temporal transition of the bank A accessed (read) by the MPUB 2. Then, as shown in FIG. 9 (c), the MPUB 2 sequentially executes the processes B1, the process B2, the process B3, and the process B4 at a predetermined cycle, and the waiting shown in the figure 13 (c). There is no time. Further, the times TB1, TB2, TB3, and TB4 in the figure represent the times when the processes B1 to B4 start, respectively.

Next, FIG. 9D shows the transition of the bank A that the MPUB2 leads, and which bank A leads the bank A is determined at the start of the process. Further explaining this with reference to FIGS. 9 (c) and 9 (d), the MPUB 2 reads the value 3 of the bank A pointer 31 when the process B1 is started, and subtracts this by 1, that is, the bank. The read is performed from A2, all the data in the bank A2 is read at the beginning of the process B1, and all the data in the temporary memory 26 is saved. Then, the MPUB 2 sequentially reads the data of the MPUA 1 from the temporary memory 26 according to the progress of the process B1.

Similarly, in the MPUB2, at the times TB2, TB3, and TB4, the banks A that are collectively read in the processes B2, B3, and B4 are set as banks A3, bank A0, and bank A0, respectively, and are saved in the temporary memory 26. To do. Here, in each process of FIG. 9C, the shaded portion is a short time that simulates the time that the MPUB 2 collectively reads from the bank A and saves it in the temporary memory 26. That is, in the second embodiment of the present invention, the time for the MPUB 2 to use the bank A is shortened.

Here, when (b) and (d) of FIG. 3 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different. As a result, the race condition between the MPUA1 and the MPUB2 does not occur in the DPM3, and both the MPUA1 and the MPUB2 do not fall into the waiting state.
Further, since the MPUB2 always reads data from the bank A in which the MPUA1 has completed writing, the simultaneity of a plurality of data is ensured.
Further, since the arbitration by software is performed by the bank A pointer 31, it is not necessary to connect and arbitrate by hardware between the MPUA1 and the MPUB2.

Here, FIG. 9 assumes a case where the MPUA1 and the MPUB2 operate asynchronously and their processing times are substantially equal. Further, the shading following the time TB4 in FIG. 9D indicates that the bank A0 led by the MPUB2 continues from the previous time TB3.

The time transition of each state in FIG. 7 has been described with reference to FIG. Subsequently, a description will be given with reference to FIG. 10, which corresponds to FIG. 4 of the first embodiment. By the way, (a), (b), (c), and (d) of FIG. 10 represent the temporal transition of the same item as that of FIG. It has the same function and role as the one with the same code, and the explanation is omitted.

The difference from FIG. 9 shows the time transition when the processing time of the MPUA1 shown in FIG. 10A is longer than the processing time of the MPUB2 shown in FIG. 10C. .. At this time, when (b) and (d) of FIG. 10 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different. As a result, the object of the present invention can be achieved without causing a race condition between the MPUA1 and the MPUB2 in the DPM3.
Here, the shading in FIG. 10D indicates that the bank A led by the MPUB 2 continues from the processing one cycle before.

Further, the temporal transition of each state in FIG. 7 will be described with reference to FIG. 11 following FIGS. 9 and 10, but FIG. 11 corresponds to FIG. 5 of the first embodiment. By the way, (a), (b), (c), and (d) of FIG. 11 represent the temporal transition of the same item as that of FIG. 9, and the reference numeral is attached to FIG. Those with the same reference numerals have the same functions and roles, and their explanations are omitted.

The difference between FIGS. 9 and 10 and FIG. 11 is that the processing time of the MPUA1 shown in FIG. 11A is shorter than the processing time of the MPUB2 shown in FIG. 9C. It shows the transition.

Here, when (b) and (d) of FIG. 11 are compared, the bank A written by the MPUA1 and the bank A led by the MPUB2 are always different, and the time at which the problem occurs in FIG. 5 Bank A is also different between TA8 and TB4.
Here, the TA8 is the time at which the process A8 ends in (a) of FIG. Further, the shaded bank A in FIG. 11B represents a bank A in which the MPDUB2 does not lead even if the MPDUA1 writes to the bank A.

As described above, in the second embodiment of the present invention, by providing the temporary memories in each of the two microprocessors, it is possible to solve the problem that a conflict state is surely generated in the dual port memory when the two microprocessors exchange data. Is what you do.
Also, since one microprocessor always reads data from the dual-port memory that the other microprocessor has completed writing, the simultaneity of a plurality of data is ensured.
Furthermore, there is no connection such as an interrupt signal or a busy signal between the two microprocessors, which realizes simpler hardware.

Inverters, PLCs, and other control equipment used in industrial manufacturing equipment are equipped with a plurality of microprocessors, and the processing suitable for each is shared and executed. Data transfer between microprocessors is important, but by using the bank-type dual-port memory of the present invention, simple and reliable data transfer can be realized.
As a result, not only the hardware of the microprocessor system but also the software of a plurality of microprocessors that do not interfere with each other can be embedded.

1 MPUA
2 MPUB 11, 21 Control bus 12, 22 Address bus 13, 23 Data bus 14, 24 Busy signal 15 Synchronous signal 16 Temporary memory A
26 Temporary memory B
3 DPM, or dual port memory
31 Bank A pointer 32 Bank A memory 33 Bank B pointer 34 Bank B memory

Claims (2)

In a microprocessor system composed of two microprocessors MPUA1 and MPUB2 and a dual port memory, the MPUA1 and MPUB2 exchange a plurality of data via the dual port memory.
A bank A pointer, a bank A memory, a bank B pointer, and a bank B memory are provided in the dual port memory, and the MPUA1 sends a plurality of data to the MPUB 2 using the bank A pointer and the bank A memory. The MPUB2 has a function of sending a plurality of data to the MPUA1 using the bank B pointer and the bank B memory.
The bank A memory is composed of banks A0 to bank A (n-1) and n of the banks, with memory areas of a plurality of consecutive addresses as one bank.
The bank A pointer is set with a value from 0 to (n-1) in the MPUA1 to specify one of the n banks.
The MPUA1 writes a plurality of data to the bank designated by the bank A pointer in order to send the plurality of data to the MPUB2 via the bank A memory of the dual port memory for each process. Then, after the write is completed, the MPUA1 updates the value of the bank A pointer by 1 in the range of 0 to (n-1).
When the MPUB2 receives a plurality of data from the MPUA1 via the bank A memory of the dual port memory for each process, the MPUB2 has a plurality of data from the bank one before the bank specified by the bank A pointer. Is sequentially read according to the progress of processing.
Next, the bank B memory is composed of banks B0 to bank B (n-1) and n of the banks, with the memory areas of a plurality of consecutive addresses as one bank.
The bank B pointer is set with a value from 0 to (n-1) in the MPUB2 to specify one of the n banks.
The MPUB2 writes a plurality of data to the bank designated by the bank B pointer in order to send the plurality of data to the MPUA1 via the bank B memory of the dual port memory for each process. Then, after the write is completed, the MPUB2 updates the value of the bank B pointer by 1 in the range of 0 to (n-1).
When the MPUA1 receives a plurality of data from the MPUB2 via the bank B memory of the dual port memory for each process, the MPUA1 receives a plurality of data from the bank one before the bank specified by the bank B pointer. A bank-type dual-port memory characterized by sequentially reading according to the progress of processing.
In claim 1,
The MPUA1 and MPUB2 include a temporary memory A and a temporary memory B, respectively.
When the MPUB2 receives a plurality of data from the MPUA1 via the bank A memory of the dual port memory for each process, the MPUB2 receives a plurality of data from the bank one before the bank specified by the bank A pointer. After reading continuously and saving in the temporary memory B in a batch, data is read from the temporary memory B sequentially according to the progress of the process.
When the MPUA1 receives a plurality of data from the MPUB2 via the bank B memory of the dual port memory for each process, the MPUA1 receives a plurality of data from the bank one before the bank specified by the bank B pointer. A bank-type dual-port memory characterized in that data is read continuously from the temporary memory A after being continuously read and collectively saved in the temporary memory A, and then sequentially read from the temporary memory A according to the progress of processing.

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