JP6833149B2 - Signal sorting circuit, signal sorting method and distortion compensation circuit - Google Patents

Description

The present invention relates to a signal sorting circuit for sorting acquired signals, a signal sorting method, and a distortion compensation circuit.

The wireless transmitter amplifies the power of the transmission signal using a power amplifier, and transmits the amplified transmission signal to the transmission partner using an antenna. At this time, if the power amplifier has a non-linear characteristic, a distortion component is added to the transmitted signal in which the power is amplified, and the signal quality deteriorates. Therefore, in the conventional wireless transmitter, the distortion component added to the transmission signal is reduced by compensating the non-linear characteristics of the power amplifier by using the distortion compensation circuit.

The distortion compensation circuit calculates the distortion compensation coefficient by using the transmission signal before the power is amplified by the power amplifier and the feedback signal obtained by feeding back the transmission signal whose power is amplified by the power amplifier.
For example, the distortion compensation circuit stores the signal input to the power amplifier and the signal output from the power amplifier in a memory, and calculates the distortion compensation coefficient representing the non-linear characteristics of the power amplifier using the signal stored in the memory. To do.

Further, the transmission signal may have an intermittent transmission pattern. In the intermittent transmission pattern, a signal mainly composed of a noise component exists in a section where there is no transmission signal (hereinafter, referred to as a no-signal section). Therefore, even if the distortion compensation coefficient is calculated using the signal in the non-signal section, the distortion compensation coefficient does not become the correct distortion compensation coefficient. Therefore, conventionally, a technique for selecting signals transmitted in an intermittent transmission pattern has been proposed.

For example, the sampling circuit described in Patent Document 1 samples signals at predetermined intervals on the premise that signals are transmitted in an intermittent transmission pattern having regularity, and if signal sampling fails, Sampling is performed again at a different interval than before. As a result, the sampling circuit described in Patent Document 1 can return to the interval at which signal sampling succeeds even if signal sampling fails.

International Publication No. 2011/030672

As described above, the sampling circuit described in Patent Document 1 is premised on an intermittent transmission pattern having regularity. Therefore, when a signal is transmitted in a transmission pattern in which the non-signal section is irregular, the sampling method described in Patent Document 1 does not always succeed in sampling the signal, and the signal is selected excluding the non-signal section. Could not be done.

The present invention solves the above problems, and an object of the present invention is to obtain a signal selection circuit, a signal selection method, and a distortion compensation circuit capable of selecting signals even if no signal sections occur irregularly.

The signal sorting circuit according to the present invention is a value indicating a signal level for each sector by dividing the signal stored in the memory into three or more continuous sectors and a signal acquisition unit that acquires the signal and stores it in the memory. A calculation unit that calculates, and a determination unit that determines whether or not the value calculated by the calculation unit satisfies the determination condition for each sector, and confirms whether or not three or more sectors satisfying the determination condition are consecutive. The determination unit outputs a signal of a sector excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition, and the signal acquisition unit has 3 sectors satisfying the determination condition. If one or more are not continuous, the signal is acquired again.

According to the present invention, when three or more sectors in which the value indicating the signal level for each sector satisfies the determination condition are consecutive, the signal of the sector excluding the first sector and the last sector is output and the determination condition is set. If three or more sectors to be satisfied are not consecutive, the signal is acquired again. As a result, signals can be selected even if non-signal sections occur irregularly.

It is a block diagram which shows the structure of the signal sorting circuit which concerns on Embodiment 1. FIG. It is a flowchart which shows the signal selection method which concerns on Embodiment 1. FIG. 3A is a graph showing the relationship between the signal number and the signal amplitude when there is no no-signal section. FIG. 3B is a graph showing the relationship between the signal number and the signal amplitude when one sector includes a non-signal section. FIG. 3C is a graph showing the relationship between the signal number and the signal amplitude when the two sectors include a non-signal section. FIG. 4A is a block diagram showing a hardware configuration that realizes the function of the signal sorting circuit according to the first embodiment. FIG. 4B is a block diagram showing a hardware configuration for executing software that realizes the function of the signal sorting circuit according to the first embodiment. It is a block diagram which shows the signal sorting circuit and distortion compensation circuit which concerns on Embodiment 2, and the power amplifier which is the object of distortion compensation. It is a block diagram which shows the structure of the signal sorting circuit which concerns on Embodiment 2. It is a block diagram which shows the structure of the distortion compensation circuit which concerns on Embodiment 2. It is a flowchart which shows the signal selection method which concerns on Embodiment 2. It is a block diagram which shows the signal sorting circuit and distortion compensation circuit which concerns on Embodiment 3, and the power amplifier which is the object of distortion compensation. It is a block diagram which shows the structure of the signal sorting circuit which concerns on Embodiment 3.

Hereinafter, in order to explain the present invention in more detail, a mode for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a signal sorting circuit 1 according to the first embodiment. The signal sorting circuit 1 is a circuit that sorts signals, and includes a signal acquisition unit 10, a memory 11, a calculation unit 12, and a determination unit 13. The signal acquisition unit 10 acquires a signal and stores the acquired signal in the memory 11. The signal acquired by the signal acquisition unit 10 is a signal transmitted irregularly and intermittently, and examples thereof include a time-divided duplex (TDD) signal and a burst signal.
The non-signal section where there is no transmission signal includes signal components that are not subject to selection, such as noise components. In the following description, a signal component that is not subject to selection in the non-signal section is described as a non-signal component.

The memory 11 stores the signal acquired by the signal acquisition unit 10. For example, the memory 11 sequentially stores digital signals acquired from analog signals by the signal acquisition unit 10 at regular acquisition intervals. Each digital signal is given, for example, a signal number that is a serial number in the order of being stored in the memory 11.

Although FIG. 1 shows a signal sorting circuit 1 including the memory 11, the memory 11 may be provided with an external device provided separately from the signal sorting circuit 1. That is, the signal sorting circuit 1 according to the first embodiment does not have to include the memory 11. In this case, the signal sorting circuit 1 communicates with the external device and exchanges signals with the memory 11.

The calculation unit 12 divides the signal stored in the memory 11 into three or more consecutive sectors, and calculates a value indicating the signal level for each sector. The value indicating the signal level for each sector includes, for example, the average value of the power or the average value of the amplitudes of the plurality of signals divided for each sector. In addition to the average value of power and the average value of amplitude, the value indicating the signal level for each sector may be the maximum value of power or amplitude, or other statistical value regarding power or amplitude. Good.

A sector is a unit that divides a signal at regular intervals. For example, when the signal is a plurality of digital signals acquired by the signal acquisition unit 10 at a fixed cycle and the plurality of digital signals are stored in the memory 11 in a time series in the order of signal numbers, the sector is a plurality of digital signals. It is a range of signal numbers that divides the time series at regular intervals. When the range of 256 signal numbers n is regarded as one sector, the range of signal numbers n from 1 to 256 is the first sector, and the range of signal numbers n of 257 to 512 is the second sector. The sector having a signal number n of 513 to 768 is the third sector, and the sector having a signal number n of 769 to 1024 is the fourth sector.

The determination unit 13 determines for each sector whether or not the value calculated by the calculation unit 12 satisfies the determination condition, and confirms whether or not three or more sectors satisfying the determination condition are consecutive. The determination condition is a condition for determining whether or not a sector contains a certain or more signal sections based on the signal level of each sector when the section including the signal to be sorted is set as the signal section. .. For example, if the value indicating the signal level for each sector is the average value of the amplitudes of a plurality of signals divided for each sector, is the average value of the signal amplitudes for each sector equal to or greater than the threshold value for the signal amplitude? Whether or not it may be a determination condition.

The determination unit 13 determines that the sector signal satisfies the determination condition if the average value of the signal amplitude for each sector is equal to or more than the threshold value, and if the average value of the signal amplitude for each sector is smaller than the threshold value, the sector It is determined that the signal of is not satisfying the determination condition. This also applies when the value indicating the signal level for each sector is the average value of the power of a plurality of signals divided for each sector, and if the average value of the power is equal to or more than the threshold value, the value of that sector It is determined that the signal satisfies the determination condition, and if the average value of the power is smaller than the threshold value, the signal of the sector is determined not to satisfy the determination condition.

The determination unit 13 outputs a signal of a sector excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition. For example, when four sectors from the first to the fourth sector satisfy the determination condition in succession, the determination unit 13 is the second sector excluding the first sector and the fourth sector. And outputs the signal contained in both or one of the third sectors.

When four sectors from the first to the fourth sector satisfy the judgment condition in succession, the first sector does not satisfy the judgment condition, that is, the immediately preceding sector is a no-signal section. The fourth sector is a non-signal section in which the immediately following sector does not satisfy the determination condition. Therefore, even if the first sector and the fourth sector satisfy the determination condition, there is a high possibility that these sectors include a non-signal section. Therefore, the determination unit 13 excludes the first sector and the last sector from the three or more consecutive sectors determined to satisfy the determination condition, so that the output signal does not include the no-signal component in the no-signal section. I am doing it.

The signal acquisition unit 10 acquires a signal again when three or more sectors satisfying the determination condition are not consecutive. When the number of consecutive sectors satisfying the determination condition is two or less, there is a high possibility that the sector includes a non-signal section. Therefore, the signal acquisition unit 10 acquires the signal again and stores the acquired signal in the memory 11. The signal acquisition process by the signal acquisition unit 10 is repeated until the determination unit 13 confirms that three or more sectors satisfying the determination condition are continuous.

Next, the operation will be described.
FIG. 2 is a flowchart showing the signal selection method according to the first embodiment, and it is assumed that the value indicating the signal level for each sector is the amplitude average value of the signal.
The signal acquisition unit 10 acquires the signal and stores the acquired signal in the memory 11 (step ST1). For example, the signal acquisition unit 10 acquires signals transmitted irregularly and intermittently at regular cycles, and stores a plurality of digital signals acquired for each cycle in the memory 11. As a result, a plurality of digital signals are stored in the memory 11 in a time series in the order of signal numbers.

Next, the calculation unit 12 divides the signal stored in the memory 11 into three or more consecutive sectors, and calculates the average value of the signal amplitudes for each sector (step ST2). For example, the calculation unit 12 divides the time series of the most recently acquired 1024 digital signals among the signals stored in the memory 11 into four sectors (1) to (4). Then, the calculation unit 12 calculates the average value of the signal amplitude for each sector (hereinafter referred to as the amplitude average value) according to the following equations (1) to (4), and the calculated amplitude average of the signal for each sector. The value is output to the determination unit 13. In the following equations (1) to (4), n (n = 1, 2, ..., 1024) is a signal number, and A (n) is a signal number out of 1024 digital signals. The amplitude of the digital signal. abs is a function for finding the absolute value of the amplitude A (n). _Savg (1) is the amplitude average value of the signal of the sector (1), _Savg (2) is the amplitude average value of the signal of the sector (2), and _Savg (3) is the sector (3). ) Is the amplitude average value of the signal, and _Savg (4) is the amplitude average value of the signal of the sector (4).

The determination unit 13 determines for each sector whether or not the amplitude average value of the signal input from the calculation unit 12 is equal to or greater than the threshold value (step ST3). For example, when the signal stored in the memory 11 is a time series of 1024 digital signals, and the sector is in the range of signal numbers n for 256, the signal stored in the memory 11 is calculated by the calculation unit 12. It is divided into four consecutive sectors. The determination unit 13 extracts the amplitude average value of the sector signals in ascending order of the signal numbers from the amplitude average values of the signals of the four sectors, and the amplitude average value of each sector is equal to or higher than the threshold value for all four sectors. It is determined whether or not it is.

Subsequently, the determination unit 13 confirms whether or not three or more sectors having an average signal amplitude equal to or greater than the threshold value are continuous as a result of the determination process in step ST3 (step ST4). FIG. 3A is a graph showing the relationship between the signal number n and the signal amplitude when there is no no-signal section. In FIG. 3A, the signal is a time series of 1024 digital signals most recently acquired by the signal acquisition unit 10 among the digital signals stored in the memory 11. When the sector is in the range of 256 signal numbers n, as shown in FIG. 3A, the signal is divided into four consecutive sectors such as sector (1), sector (2), sector (3) and sector (4). Divided.

When three or more sectors having an average signal amplitude equal to or greater than the threshold value are consecutive (step ST4; YES), the determination unit 13 shifts to the process of step ST5. In the example shown in FIG. 3A, _S avg of the sector (1) (1), sector (2) _S avg (2) of the sector _{S avg} (3) (3) and sector (4) _S avg (4) of All are above the threshold. In this case, the determination unit 13 determines that the amplitude average value of the signal is equal to or greater than the threshold value, and is the first sector (1), sector (2), sector (3), and sector (4) of the series. The signal contained in the sector (2) and / or one of the sector (2) and the sector (3) excluding the 1) and the final sector (4) is output (step ST5).

FIG. 3B is a graph showing the relationship between the signal number n and the signal amplitude when one sector includes a non-signal section. In FIG. 3B, the signal is divided into four consecutive sectors such as sector (1), sector (2), sector (3) and sector (4), as in FIG. 3A. The sector (1) includes a non-signal section, and the amplitude average value _Savg (1) of the signal of the sector (1) is smaller than the threshold value. The _Savg (2) of the sector (2), the _Savg (3) of the sector (3), and the Savg (4) of the sector (4) are _{equal to} or higher than the threshold value. In this case, the determination unit 13 determines the first sector (2) and the last sector (4) of the consecutive sectors (2), sectors (3) and sectors (4) whose average signal amplitude is equal to or greater than the threshold value. ) Is excluded, and the signal included in the sector (3) is output (step ST5).

FIG. 3C is a graph showing the relationship between the signal number n and the signal amplitude when the two sectors include a non-signal section. In FIG. 3C, the signal is divided into four consecutive sectors such as sector (1), sector (2), sector (3) and sector (4), as in FIG. 3A. A non-signal section is included in the sector (1) and the sector (2). In this case, since the signal amplitude average value _Savg (1) and the amplitude average value _Savg (2) are smaller than the threshold value, three or more sectors in which the signal amplitude average value is equal to or more than the threshold value are not consecutive (step ST4; NO). The determination unit 13 notifies the signal acquisition unit 10 that three or more sectors whose amplitude average value of the signal is equal to or greater than the threshold value are not continuous. Returning to the process of step ST1, the signal acquisition unit 10 acquires the signal again.

For example, in FIG. 3C, when the signal amplitude average value _Savg (2) of the sector (2) is equal to or greater than the threshold value, the determination unit 13 determines that the continuous sector (2) in which the signal amplitude average value is equal to or greater than the threshold value. ), Sector (3) and sector (4), excluding the first sector (2) and the last sector (4), the signal included in the sector (3) is output (step ST5).

As described above, the sector whose immediately preceding sector (for example, the sector (1) in FIG. 3C) includes a non-signal section at least at the end thereof (for example, the sector (2) in FIG. 3C) has a threshold value of the signal amplitude average value. Even with the above, as shown in FIG. 3C, there is a high possibility that a non-signal component is contained. This is also the case when the sector immediately after the sector includes a non-signal section at least at the start portion thereof. Here, for a plurality of consecutive sectors in which the amplitude average value of the signal determined by the determination unit 13 is equal to or greater than the threshold value, among the plurality of sectors, the sector immediately before the first sector and the sector immediately after the last sector Are all likely to be sectors in which the average amplitude of the signal is less than the threshold. Then, a sector in which the average amplitude value of the signal is less than the threshold value may contain a non-signal component in the end portion or the start portion thereof. Therefore, the determination unit 13 outputs a signal included in the sectors excluding the first sector and the last sector among three or more consecutive sectors in which the average amplitude value of the signal is equal to or greater than the threshold value. As a result, the signal sorting circuit 1 can sort signals while suppressing the output of the non-signal component even if the non-signal section occurs irregularly.

Next, the hardware configuration that realizes the function of the signal sorting circuit 1 will be described.
The functions of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1 are realized by the processing circuit. That is, the signal sorting circuit 1 includes a processing circuit for executing the processing of steps ST1 to ST5 shown in FIG. The processing circuit may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in the memory.

FIG. 4A is a block diagram showing a hardware configuration that realizes the function of the signal sorting circuit 1. FIG. 4B is a block diagram showing a hardware configuration for executing software that realizes the function of the signal sorting circuit 1. In FIGS. 4A and 4B, the input interface 100 is an interface that relays the acquisition of signals by the signal acquisition unit 10 shown in FIG. The storage device 101 is a storage device that functions as a memory 11. The output interface 102 is an interface that relays the output of the signal from the determination unit 13 included in the signal sorting circuit 1.

When the processing circuit is the processing circuit 103 of the dedicated hardware shown in FIG. 4A, the processing circuit 103 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, or an ASIC (Application Specific Integrated Circuitd). Circuit), FPGA (Field-Programmable Gate Array), or a combination thereof is applicable. The functions of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1 may be realized by separate processing circuits, or these functions may be collectively realized by one processing circuit. ..

When the processing circuit is the processor 104 shown in FIG. 4B, the functions of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1 are realized by software, firmware, or a combination of software and firmware. Will be done. The software or firmware is described as a program and stored in the memory 105.

The processor 104 realizes the functions of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1 by reading and executing the program stored in the memory 105. That is, the signal sorting circuit 1 includes a memory 105 for storing a program in which the processes from steps ST1 to ST5 in the flowchart shown in FIG. 2 are executed as a result when executed by the processor 104. These programs cause the computer to execute the procedure or method of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1. The memory 105 may be a computer-readable storage medium in which a program for causing the computer to function as a signal acquisition unit 10, a memory 11, a calculation unit 12, and a determination unit 13 in the signal selection circuit 1 is stored.

The memory 105 is, for example, a non-volatile semiconductor such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrolytically Magnetic Memory), or an EPROM (Electrically-EPROM). This includes discs, flexible discs, optical discs, compact discs, mini discs, DVDs, and the like.

Some of the functions of the signal acquisition unit 10, the memory 11, the calculation unit 12, and the determination unit 13 in the signal selection circuit 1 may be realized by dedicated hardware, and some may be realized by software or firmware. For example, the signal acquisition unit 10 and the memory 11 realize the functions by the processing circuit 103 which is the dedicated hardware, and the calculation unit 12 and the determination unit 13 read and execute the program stored in the memory 105 by the processor 104. By doing so, the function is realized. As described above, the processing circuit can realize the above-mentioned functions by hardware, software, firmware or a combination thereof.

As described above, the signal sorting circuit 1 according to the first embodiment excludes the first sector and the last sector when three or more sectors in which the value indicating the signal level for each sector satisfies the determination condition are consecutive. The signal of the sector is output, and if three or more sectors satisfying the determination condition are not consecutive, the signal is acquired again. As a result, signals can be selected even if non-signal sections occur irregularly. The signal sorting circuit 1 according to the first embodiment can also be used when no signal section occurs regularly.

Embodiment 2.
FIG. 5 is a block diagram showing the signal sorting circuit 1A and the distortion compensation circuit 2 according to the second embodiment and the power amplifier 3 to be distortion-compensated. The signal sorting circuit 1A, the distortion compensation circuit 2, and the power amplifier 3 are components of the wireless transmitter. The signal sorting circuit 1A selects the first signal used for calculating the distortion compensation coefficient from the output signal of the distortion compensation circuit 2, and the second signal used for calculating the distortion compensation coefficient from the output signal of the power amplifier 3. Sort signals. The distortion compensation circuit 2 calculates a distortion compensation coefficient using the first signal and the second signal selected by the signal selection circuit 1A, and compensates for the non-linear characteristics of the power amplifier 3 using the calculated distortion compensation coefficient. .. The power amplifier 3 amplifies the power of the transmission signal of the wireless transmitter. The transmission signal whose power is amplified by the power amplifier 3 is transmitted from the wireless transmitter.

FIG. 6 is a block diagram showing the configuration of the signal sorting circuit 1A. As shown in FIG. 6, the signal sorting circuit 1A includes a first signal acquisition unit 10A-1, a second signal acquisition unit 10A-2, a first memory 11A-1, a second memory 11A-2, and a second. A calculation unit 12A-1 of 1, a second calculation unit 12A-2, a first determination unit 13A-1, and a second determination unit 13A-2 are provided.

The first signal acquisition unit 10A-1 acquires the first signal and stores the acquired first signal in the first memory 11A-1. For example, the first signal acquisition unit 10A-1 acquires the output signal of the distortion compensation circuit 2 as the first signal, and stores the acquired first signal in the first memory 11A-1. The second signal acquisition unit 10A-2 acquires the second signal and stores the acquired second signal in the second memory 11A-2. For example, the second signal acquisition unit 10A-2 acquires the output signal of the power amplifier 3 as the second signal, and stores the acquired second signal in the second memory 11A-2.

The first memory 11A-1 stores the first signal acquired by the first signal acquisition unit 10A-1. For example, the first memory 11A-1 sequentially stores the output signals of the distortion compensation circuit 2. The output signal of the distortion compensation circuit 2 is a digital signal acquired by the first signal acquisition unit 10A-1 at regular intervals, and is, for example, a serial number in the order of being stored in the first memory 11A-1. A signal number is given.

The second memory 11A-2 stores the second signal acquired by the second signal acquisition unit 10A-2. For example, the second memory 11A-2 sequentially stores the output signals of the power amplifier 3. The output signal of the power amplifier 3 is a digital signal acquired by the second signal acquisition unit 10A-2 at regular intervals, and is, for example, a signal having a serial number in the order stored in the second memory 11A-2. A number is given.

Note that FIG. 6 shows a signal sorting circuit 1A including the first memory 11A-1 and the second memory 11A-2, but the first memory 11A-1 and the second memory 11A-2 are shown. An external device provided separately from the signal sorting circuit 1A may be provided. That is, the signal sorting circuit 1A according to the second embodiment does not have to include the first memory 11A-1 and the second memory 11A-2. In this case, the signal sorting circuit 1A communicates with an external device and exchanges signals between the first memory 11A-1 and the second memory 11A-2.

The first calculation unit 12A-1 divides the first signal stored in the first memory 11A-1 into three or more consecutive sectors, and calculates a value indicating the level of the first signal for each sector. To do. The second calculation unit 12A-2 divides the second signal stored in the second memory 11A-2 into three or more consecutive sectors, and calculates a value indicating the level of the second signal for each sector. To do.

Similar to the first embodiment, the value indicating the level of the first signal for each sector includes, for example, the average value of the power or the average value of the amplitudes of the plurality of first signals divided for each sector. .. Further, the value indicating the level of the first signal for each sector may be the maximum value of power or amplitude in addition to the average value of power and the average value of amplitude, or other statistical values regarding power or amplitude. There may be. This also applies to the sector of the second signal. A sector is a unit that divides a signal at regular intervals. For example, a sector is a range of signal numbers that divides a time series of a plurality of digital signals at regular intervals.

The first determination unit 13A-1 determines for each sector whether or not the value calculated by the first calculation unit 12A-1 satisfies the determination condition, and three or more sectors satisfying the determination condition are continuous. Check if it is. Similarly, the second determination unit 13A-2 determines for each sector whether or not the value calculated by the second calculation unit 12A-2 satisfies the determination condition, and there are three sectors that satisfy the determination condition. Check if the above is continuous.

Similar to the first embodiment, the determination condition in the first determination unit 13A-1 determines whether or not the sector includes a certain or more signal sections based on the level of the first signal for each sector. It is a condition for. For example, when the value indicating the level of the first signal for each sector is the amplitude average value of a plurality of first signals divided for each sector, the amplitude average value of the first signal for each sector is the amplitude of the signal. The determination condition may be whether or not it is equal to or greater than the threshold value for.
Further, the determination condition in the second determination unit 13A-2 is a condition for determining whether or not the sector includes a certain or more signal sections based on the level of the second signal for each sector. For example, when the value indicating the level of the second signal for each sector is the amplitude average value of a plurality of second signals divided for each sector, the amplitude average value of the second signal for each sector is the amplitude of the signal. The determination condition may be whether or not it is equal to or greater than the threshold value for.

Each of the first determination unit 13A-1 and the second determination unit 13A-2 determines that the sector signal satisfies the determination condition if the amplitude average value of the signal for each sector is equal to or more than the threshold value, and for each sector. If the amplitude average value of the signal of is smaller than the threshold value, it is determined that the sector signal does not satisfy the determination condition. This also applies when the value indicating the signal level for each sector is the average value of the power of a plurality of signals divided for each sector, and if the average value of the power is equal to or more than the threshold value, the signal of that sector Is determined to satisfy the determination condition, and if the average value of the power is smaller than the threshold value, it is determined that the signal of the sector does not satisfy the determination condition.

The first determination unit 13A-1 and the second determination unit 13A-2 output signals of sectors excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition, respectively. .. For example, in the signal stored in the first memory 11A-1, four sectors from the first to the fourth consecutively satisfy the determination condition and are stored in the second memory 11A-2. In the signal, when the third sector from the second to the fourth sector continuously satisfies the determination condition, the first determination unit 13A-1 excludes the first sector and the fourth sector. , Outputs the signal contained in both or one of the second sector and the third sector. The second determination unit 13A-2 outputs a signal included in the third sector excluding the second sector and the fourth sector.

For example, when four sectors from the first to the fourth sector satisfy the judgment condition in succession, the first sector includes a non-signal section in the immediately preceding sector, and the fourth sector is , The sector immediately after may include a non-signal section. Therefore, even if the first sector and the fourth sector satisfy the determination conditions, there is a high possibility that these sectors contain no signal components. Therefore, in the signal sorting circuit 1A, by removing the first sector and the last sector from three or more consecutive sectors determined to satisfy the determination condition, there is a possibility that the output signal contains a non-signal component. It is low.

Further, the first signal acquisition unit 10A-1 and the second signal acquisition unit 10A-2 have the first signal and the second signal acquired most recently when three or more sectors satisfying the determination condition are not consecutive. Since there is a high possibility that both or one of the signals contains a non-signal component, the first signal and the second signal are acquired again.

FIG. 7 is a block diagram showing the configuration of the distortion compensation circuit 2. The distortion compensation circuit 2 is a circuit that reduces the distortion component applied to the transmission signal due to the non-linear characteristics of the power amplifier 3, and includes a coefficient calculation unit 20 and a compensation processing unit 21. The coefficient calculation unit 20 uses the first signal output from the first determination unit 13A-1 included in the signal sorting circuit 1A and the second signal output from the second determination unit 13A-2 to distort. Calculate the compensation factor. A well-known method can be used as a method for calculating the strain compensation coefficient.

The compensation processing unit 21 executes distortion compensation processing on the transmission signal input to the power amplifier 3 by using the distortion compensation coefficient calculated by the coefficient calculation unit 20. For example, the coefficient calculation unit 20 uses the first signal selected from the output signal of the distortion compensation circuit 2 by the first determination unit 13A-1 and the output signal of the power amplifier 3 by the second determination unit 13A-2. Using the selected second signal, a distortion compensation coefficient representing the inverse characteristic of the power amplifier 3 is calculated. The compensation processing unit 21 performs distortion compensation processing on the transmission signal using the distortion compensation coefficient calculated by the coefficient calculation unit 20. It should be noted that this configuration is a well-known configuration called Direct Learning Architecture.

Next, the operation will be described.
FIG. 8 is a flowchart showing the signal selection method according to the second embodiment, and it is assumed that the value indicating the signal level for each sector is the amplitude average value of the signal.
First, the first signal acquisition unit 10A-1 acquires the output signal of the distortion compensation circuit 2 as the first signal, stores the acquired first signal in the first memory 11A-1, and second. The signal acquisition unit 10A-2 acquires the output signal of the power amplifier 3 as a second signal, and stores the acquired second signal in the second memory 11A-2 (step ST1a).

In the first memory 11A-1, for example, the output signals of the distortion compensation circuit 2 acquired by the first signal acquisition unit 10A-1 at regular intervals are sequentially stored. The output signal of the distortion compensation circuit 2 is a complex signal. Further, in the second memory 11A-2, for example, the output signals of the power amplifier 3 acquired by the second signal acquisition unit 10A-2 at regular intervals are sequentially stored.

Next, the first calculation unit 12A-1 is the first signal acquired most recently by the first signal acquisition unit 10A-1 among the first signals stored in the first memory 11A-1. The time series of is divided into three or more consecutive sectors, and the average value of the amplitude of the first signal for each sector is calculated. Similarly, the second calculation unit 12A-2 is the second signal acquired most recently by the second signal acquisition unit 10A-2 among the second signals stored in the second memory 11A-2. The time series of is divided into three or more consecutive sectors, and the average value of the amplitude of the second signal for each sector is calculated (step ST2a). For example, the first calculation unit 12A-1 has four consecutive sectors (4 consecutive sectors) of the time series of the 1024 digital signals acquired most recently among the first signals stored in the first memory 11A-1. Divide into 1) to (4). Then, the first calculation unit 12A-1 calculates the amplitude average value of the first signal for each sector according to the above equations (1) to (4), and the calculated amplitude average of the first signal for each sector. The value is output to the first determination unit 13A-1. Similarly, the second calculation unit 12A-2 divides the second signal into four sectors (1) to (4), and according to the above equations (1) to (4), the second signal is for each sector. The amplitude average value of the above is calculated, and the amplitude average value of the calculated second signal for each sector is output to the second determination unit 13A-2.

The first determination unit 13A-1 determines for each sector whether or not the amplitude average value of the first signal input from the first calculation unit 12A-1 is equal to or greater than the threshold value, and the second determination unit 13A-2 determines for each sector whether or not the amplitude average value of the second signal input from the second calculation unit 12A-2 is equal to or greater than the threshold value (step ST3a). For example, when the first signal is a time series of 1024 digital signals and the sector is in the range of signal numbers n for 256 signals, the first calculation unit 12A-1 sets four first signals. Divide into consecutive sectors. The first determination unit 13A-1 extracts the amplitude average value of the sector signals in ascending order of the signal numbers from the amplitude average values of the signals of the four sectors, and is the first of each sector for all four sectors. It is determined whether or not the amplitude average value of the signal of is equal to or greater than the threshold value. Similarly, when the second signal is a time series of 1024 digital signals and the sector is in the range of signal numbers n for 256, the second calculation unit 12A-2 sets the second signal to 4. Divide into two consecutive sectors. The second determination unit 13A-2 extracts the amplitude average value of the sector signals in ascending order of the signal numbers from the amplitude average values of the signals of the four sectors, and the second determination unit 13A-2 of each sector for all four sectors. It is determined whether or not the amplitude average value of the signal of is equal to or greater than the threshold value. In the description so far, the 1024 digital signals are divided into sectors for each 256, but these are examples, and may be increased or decreased depending on the non-linearity of the power amplifier.

Subsequently, the first determination unit 13A-1 confirms as a result of the determination process in step ST3a whether or not three or more sectors in which the amplitude average value of the first signal is equal to or greater than the threshold value are continuous (step ST4a). ). This determination process is the first determination process. The first determination unit 13A-1 notifies the second determination unit 13A-2 when three or more sectors in which the amplitude average value of the first signal is equal to or greater than the threshold value are consecutive (step ST4a; YES). To do. Upon receiving the above notification from the first determination unit 13A-1, the second determination unit 13A-2 has three sectors in which the amplitude average value of the second signal is equal to or greater than the threshold value as a result of the determination process in step ST3a. It is confirmed whether or not the above is continuous (step ST5a). This determination process is the second determination process.

The second determination unit 13A-2 notifies the first determination unit 13A-1 when three or more sectors in which the amplitude average value of the second signal is equal to or greater than the threshold value are consecutive (step ST5a; YES). To do. At this time, the first determination unit 13A-1 is the first sector of the sector excluding the first sector and the last sector among three or more consecutive sectors in which the amplitude average value of the first signal is equal to or greater than the threshold value. The signal is output to the distortion compensation circuit 2, and the second determination unit 13A-2 selects the first sector and the last sector among three or more consecutive sectors in which the amplitude average value of the second signal is equal to or greater than the threshold value. The second signal of the removed sector is output to the distortion compensation circuit 2 (step ST6a). As a result, the signal sorting circuit 1A is unlikely to contain a non-signal component among the output signal of the distortion compensation circuit 2 and the output signal of the power amplifier 3 even if the non-signal section is irregularly generated. The signal and the second signal are selected, and the selected first signal and the second signal can be output to the distortion compensation circuit 2.

For example, the first calculation unit 12A-1 divides the first signal stored in the first memory 11A-1 into four consecutive sectors, and _save (1) to _Save (4) are calculated. When the _save (1), the _save (2), the _save (3), and the _save (4) are equal to or higher than the threshold value, the first determination unit 13A-1 is set to the sector (2). ) And the first signal included in each of the sectors (3) may be output, only the first signal included in the sector (2) may be output, or the first signal included in the sector (3) may be output. Only the first signal may be output. That is, if the first signal output to the distortion compensation circuit 2 is continuous, the first sector and the last sector in three or more consecutive sectors in which the amplitude average value of the first signal is equal to or more than the threshold value are excluded. The first signal of any sector may be output.

On the other hand, when the first determination unit 13A-1 does not have three or more consecutive sectors in which the amplitude average value of the first signal is equal to or greater than the threshold value (step ST4a; NO), the first signal acquisition unit 13A-1 determines this. Notify 10A-1 and the second determination unit 13A-2. When the second determination unit 13A-2 receives the above notification of the first determination unit 13A-1, the second determination unit 13A-2 notifies the second signal acquisition unit 10A-2 of the above notification.

Upon receiving the above notification from the first determination unit 13A-1, the first signal acquisition unit 10A-1 returns to the process of step ST1a and acquires the output signal of the distortion compensation circuit 2 again. Similarly, when the second signal acquisition unit 10A-2 receives the above notification from the first determination unit 13A-1, the second signal acquisition unit 10A-2 returns to the process of step ST1a and acquires the output signal of the power amplifier 3 again.

Further, when the second determination unit 13A-2 does not have three or more consecutive sectors in which the amplitude average value of the second signal is equal to or greater than the threshold value (step ST5a; NO), the second determination unit 13A-2 determines this as the second signal acquisition unit. Notify 10A-2 and the first determination unit 13A-1. When the first determination unit 13A-1 receives the above notification from the second determination unit 13A-2, the first determination unit 13A-1 notifies the first signal acquisition unit 10A-1 of the above notification.

Upon receiving the above notification from the second determination unit 13A-2, the second signal acquisition unit 10A-2 returns to the process of step ST1a and acquires the output signal of the power amplifier 3 again. Similarly, when the first signal acquisition unit 10A-1 receives the above notification from the second determination unit 13A-2, it returns to the process of step ST1a and acquires the output signal of the distortion compensation circuit 2 again.

In FIG. 8, following the first determination process (step ST4a) by the first determination unit 13A-1, the second determination process (step ST5a) by the second determination unit 13A-2 is executed. Although the case has been shown, the first determination process and the second determination process may be performed in parallel by the first determination unit 13A-1 and the second determination unit 13A-2.

Next, the hardware configuration that realizes the function of the signal sorting circuit 1A will be described.
In the signal sorting circuit 1A, the first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, the first memory 11A-1, the second memory 11A-2, and the first calculation unit 12A-1. , The functions of the second calculation unit 12A-2, the first determination unit 13A-1, and the second determination unit 13A-2 are realized by the processing circuit. That is, the signal sorting circuit 1A includes a processing circuit for executing the processing of steps ST1a to ST6a shown in FIG. The processing circuit may be dedicated hardware, or may be a CPU that executes a program stored in the memory.

When the processing circuit is the processing circuit 103 of the dedicated hardware shown in FIG. 4A, the processing circuit 103 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or A combination of these is applicable. The first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, the first memory 11A-1, the second memory 11A-2, the first calculation unit 12A-1, in the signal selection circuit 1A, The functions of the second calculation unit 12A-2, the first determination unit 13A-1 and the second determination unit 13A-2 may be realized by separate processing circuits, and these functions may be combined into one processing circuit. It may be realized by.

When the processing circuit is the processor 104 shown in FIG. 4B, the first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, the first memory 11A-1, and the second in the signal selection circuit 1A. The functions of the memory 11A-2, the first calculation unit 12A-1, the second calculation unit 12A-2, the first determination unit 13A-1, and the second determination unit 13A-2 are software, firmware, or software. It is realized by the combination of and firmware. The software or firmware is described as a program and stored in the memory 105.

The processor 104 reads the program stored in the memory 105 and executes the program to read and execute the first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, and the first memory 11A in the signal selection circuit 1A. -1, 2nd memory 11A-2, 1st calculation unit 12A-1, 2nd calculation unit 12A-2, 1st determination unit 13A-1 and 2nd determination unit 13A-2 To do. That is, the signal sorting circuit 1A includes a memory 105 for storing a program in which the processes from steps ST1a to ST6a in the flowchart shown in FIG. 8 are executed as a result when executed by the processor 104. These programs include a first signal acquisition unit 10A-1, a second signal acquisition unit 10A-2, a first memory 11A-1, a second memory 11A-2, and a first calculation in the signal selection circuit 1A. Have the computer execute the procedure or method of the unit 12A-1, the second calculation unit 12A-2, the first determination unit 13A-1, and the second determination unit 13A-2. The memory 105 uses the computer as a first signal acquisition unit 10A-1, a second signal acquisition unit 10A-2, a first memory 11A-1, a second memory 11A-2, and a first signal selection circuit 1A. A computer-readable storage medium in which a program for functioning as the calculation unit 12A-1, the second calculation unit 12A-2, the first determination unit 13A-1, and the second determination unit 13A-2 is stored. May be good.

In the signal sorting circuit 1A, the first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, the first memory 11A-1, the second memory 11A-2, and the first calculation unit 12A-1. , The functions of the second calculation unit 12A-2, the first determination unit 13A-1 and the second determination unit 13A-2 are partially realized by dedicated hardware and partly realized by software or firmware. You may. For example, the first signal acquisition unit 10A-1, the second signal acquisition unit 10A-2, the first memory 11A-1 and the second memory 11A-2 function in the processing circuit 103, which is dedicated hardware. The processor 104 of the first calculation unit 12A-1, the second calculation unit 12A-2, the first determination unit 13A-1 and the second determination unit 13A-2 is stored in the memory 105. The function is realized by reading and executing the program. As described above, the processing circuit can realize the above-mentioned functions by hardware, software, firmware or a combination thereof.

As described above, since the signal sorting circuit 1A according to the second embodiment has the components shown in FIG. 6, the output signal of the distortion compensation circuit 2 and / or the output signal of the power amplifier 3 are absent. Even if the signal section is irregularly generated, the output signal of the distortion compensation circuit 2 and the output signal of the power amplifier 3 which are unlikely to contain a non-signal component can be appropriately selected. As a result, a non-signal component inappropriate for calculating the distortion compensation coefficient is removed. Therefore, the distortion compensation circuit 2 calculates a distortion compensation coefficient capable of reducing the distortion component of the transmission signal, and uses the calculated distortion compensation coefficient. Appropriate distortion compensation can be applied to the transmitted signal.

Embodiment 3.
FIG. 9 is a block diagram showing the signal sorting circuit 1B and the distortion compensation circuit 2 according to the third embodiment and the power amplifier 3 to be distorted compensated. In FIG. 9, the same components as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted. The signal sorting circuit 1B, the distortion compensation circuit 2, and the power amplifier 3 are components of the wireless transmitter. The signal sorting circuit 1B selects the first signal used for calculating the distortion compensation coefficient from the output signal of the distortion compensation circuit 2, and the second signal used for calculating the distortion compensation coefficient from the input signal of the power amplifier 3. Sort the signal.

FIG. 10 is a block diagram showing the configuration of the signal sorting circuit 1B. As shown in FIG. 10, the signal sorting circuit 1B includes a first signal acquisition unit 10B-1, a second signal acquisition unit 10B-2, a first memory 11B-1, a second memory 11B-2, and a second. A calculation unit 12B-1 of 1, a second calculation unit 12B-2, a first determination unit 13B-1 and a second determination unit 13B-2 are provided.

The first signal acquisition unit 10B-1 acquires the first signal and stores the acquired first signal in the first memory 11B-1. For example, the first signal acquisition unit 10B-1 acquires the input signal of the distortion compensation circuit 2 as the first signal, and stores the acquired first signal in the first memory 11B-1. The second signal acquisition unit 10B-2 acquires the second signal and stores the acquired second signal in the second memory 11B-2. For example, the second signal acquisition unit 10B-2 acquires the output signal of the power amplifier 3 as the second signal, and stores the acquired second signal in the second memory 11B-2.

The first memory 11B-1 stores the first signal acquired by the first signal acquisition unit 10B-1. For example, the first memory 11B-1 sequentially stores the input signals of the distortion compensation circuit 2. The input signal of the distortion compensation circuit 2 is a digital signal acquired by the first signal acquisition unit 10B-1 at regular intervals, and is, for example, a serial number in the order of being stored in the first memory 11B-1. A signal number is given.

The second memory 11B-2 stores the second signal acquired by the second signal acquisition unit 10B-2. For example, the second memory 11B-2 sequentially stores the output signals of the power amplifier 3. The output signal of the power amplifier 3 is a digital signal acquired by the second signal acquisition unit 10B-2 at regular intervals, and is, for example, a signal having a serial number in the order stored in the second memory 11B-2. A number is given.

Although FIG. 10 shows a signal sorting circuit 1B including the first memory 11B-1 and the second memory 11B-2, the first memory 11B-1 and the second memory 11B-2 are shown. An external device provided separately from the signal sorting circuit 1B may be provided. That is, the signal sorting circuit 1B according to the third embodiment may not include the first memory 11B-1 and the second memory 11B-2. In this case, the signal sorting circuit 1B communicates with an external device and exchanges signals between the first memory 11B-1 and the second memory 11B-2.

The first calculation unit 12B-1 divides the first signal stored in the first memory 11B-1 into three or more consecutive sectors, and indicates a value indicating the level of the first signal for each sector. Is calculated. The second calculation unit 12B-2 divides the second signal stored in the second memory 11B-2 into three or more consecutive sectors, and indicates a value indicating the level of the second signal for each sector. Is calculated.
The value indicating the level of the first signal for each sector and the value indicating the level of the second signal for each sector are the same as those described in the second embodiment.

The first determination unit 13B-1 determines for each sector whether or not the value calculated by the first calculation unit 12B-1 satisfies the determination condition, and whether three or more sectors satisfying the determination condition are consecutive. Check if it is not. The second determination unit 13B-2 determines for each sector whether or not the value calculated by the second calculation unit 12B-2 satisfies the determination condition, and whether or not three or more sectors satisfying the determination condition are consecutive. Check if it is not. The determination conditions are the same as those described in the second embodiment.

For example, each of the first determination unit 13B-1 and the second determination unit 13B-2 determines that the sector signal satisfies the determination condition if the average value of the signal amplitudes for each sector is equal to or greater than the threshold value. If the average value of the signal amplitudes for each sector is smaller than the threshold value, it is determined that the sector signals do not satisfy the determination conditions. This also applies when the value indicating the signal level for each sector is the average value of the power of a plurality of signals divided for each sector, and if the average value of the power is equal to or more than the threshold value, the value of that sector It is determined that the signal satisfies the determination condition, and if the average value of the power is smaller than the threshold value, the signal of the sector is determined not to satisfy the determination condition.

The first determination unit 13B-1 and the second determination unit 13B-2 output signals of sectors excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition, respectively. .. For example, in the first signal stored in the first memory 11B-1, four sectors from the first to the fourth consecutively satisfy the determination condition and are stored in the second memory 11B-2. In the second signal, when the third sector from the second to the fourth sector continuously satisfies the determination condition, the first determination unit 13B-1 performs the first sector and the fourth sector. The first signal contained in both or one of the second sector and the third sector excluding the sector is output. The second determination unit 13B-2 outputs the second signal included in the third sector excluding the second sector and the fourth sector.

Further, when the first signal acquisition unit 10B-1 and the second signal acquisition unit 10B-2 do not have three or more consecutive sectors satisfying the determination condition, the first signal and the second signal acquired most recently are used. Since there is a high possibility that both or one of the signals contains a non-signal component, the first signal and the second signal are acquired again.

The distortion compensation circuit 2 is a circuit that reduces the distortion component applied to the transmission signal due to the non-linear characteristics of the power amplifier 3, and includes a coefficient calculation unit 20 and a compensation processing unit 21 as in FIG. 7. The coefficient calculation unit 20 distorts using the first signal output from the first determination unit 13B-1 included in the signal selection circuit 1B and the second signal output from the second determination unit 13B-2. Calculate the compensation factor. A well-known method can be used as a method for calculating the strain compensation coefficient.

The compensation processing unit 21 executes distortion compensation processing on the transmission signal input to the power amplifier 3 by using the distortion compensation coefficient calculated by the coefficient calculation unit 20. For example, the coefficient calculation unit 20 uses the first signal selected from the input signal of the distortion compensation circuit 2 by the first determination unit 13B-1 and the output signal of the power amplifier 3 by the second determination unit 13B-2. The distortion compensation coefficient that minimizes the error from the selected second signal is calculated. The compensation processing unit 21 uses the strain compensation coefficient calculated by the coefficient calculation unit 20 to select a first signal selected from the output signal of the distortion compensation circuit 2 and a first signal selected from the output signal of the power amplifier 3. Distortion compensation processing is performed on the transmitted signal so that the error with the signal of 2 is minimized.

The hardware configuration for realizing the function of the signal sorting circuit 1B is the same as that of the signal sorting circuit 1A described in the second embodiment.

As described above, since the signal sorting circuit 1B according to the third embodiment has the components shown in FIG. 10, there is no input signal of the distortion compensation circuit 2 and / or an output signal of the power amplifier 3. Even if the signal section is irregularly generated, the input signal of the distortion compensation circuit 2 and the output signal of the power amplifier 3 which are unlikely to contain a non-signal component can be appropriately selected. As a result, a non-signal component inappropriate for calculating the distortion compensation coefficient is removed. Therefore, the distortion compensation circuit 2 calculates a distortion compensation coefficient capable of reducing the distortion component of the transmission signal, and uses the calculated distortion compensation coefficient. Appropriate distortion compensation can be applied to the transmitted signal.

It should be noted that the present invention is not limited to the above-described embodiment, and within the scope of the present invention, any combination of the embodiments or any component of the embodiment may be modified or the embodiment. Any component can be omitted in each of the above.

Since the signal sorting circuit according to the present invention can sort signals even if no signal section occurs irregularly, it can be used as a distortion compensation circuit included in a wireless transmitter.

1,1A, 1B signal sorting circuit, 2 distortion compensation circuit, 3 power amplifier, 10 signal acquisition unit, 10A-1, 10B-1 first signal acquisition unit, 10A-2, 10B-2 second signal acquisition unit , 11 memory, 11A-1, 11B-1 first memory, 11A-2, 11B-2 second memory, 12 calculation unit, 12A-1, 12B-1 first calculation unit, 12A-2, 12B -2 Second calculation unit, 13 Judgment unit, 13A-1, 13B-1 First judgment unit, 13A-2, 13B-2 Second judgment unit, 20 coefficient calculation unit, 21 Compensation processing unit, 100 inputs Interface, 101 storage device, 102 output interface, 103 processing circuit, 104 processor, 105 memory.

Claims (7)

A signal acquisition unit that acquires signals and stores them in memory,
A calculation unit that divides the signal stored in the memory into three or more consecutive sectors and calculates a value indicating the signal level for each sector.
It is provided with a determination unit for determining whether or not the value calculated by the calculation unit satisfies the determination condition for each sector and confirming whether or not three or more sectors satisfying the determination condition are consecutive.
The determination unit outputs a signal of a sector excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition.
The signal acquisition unit is a signal selection circuit, characterized in that it acquires a signal again when three or more sectors satisfying the determination condition are not consecutive. The value indicating the signal level for each sector is the average value of the power or amplitude of the signal for each sector.
The signal sorting circuit according to claim 1, wherein the determination condition is whether or not the average value of the power or amplitude of the signal for each sector is equal to or greater than a threshold value. A first signal acquisition unit that acquires a first signal and stores it in a first memory,
A second signal acquisition unit that acquires a second signal and stores it in a second memory,
A first calculation unit that divides the first signal stored in the first memory into three or more consecutive sectors and calculates a value indicating the level of the first signal for each sector.
A second calculation unit that divides the second signal stored in the second memory into three or more consecutive sectors and calculates a value indicating the level of the second signal for each sector.
A first determination unit that determines for each sector whether or not the value calculated by the first calculation unit satisfies the determination condition, and confirms whether or not three or more sectors satisfying the determination condition are consecutive. When,
A second determination in which it is determined for each sector whether or not the value calculated by the second calculation unit satisfies the determination condition, and whether or not three or more sectors satisfying the determination condition are consecutive. With a department
The first determination unit and the second determination unit output signals of sectors excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition.
The first signal acquisition unit and the second signal acquisition unit are characterized in that, when three or more sectors satisfying the determination condition are not consecutive, the first signal and the second signal are acquired again. Signal sorting circuit. The value indicating the level of the first signal per sector is the average value of the power or amplitude of the first signal per sector.
The determination condition is whether or not the average value of the power or amplitude of the first signal for each sector is equal to or greater than the threshold value.
The value indicating the level of the second signal per sector is the average value of the power or amplitude of the second signal per sector.
The signal sorting circuit according to claim 3, wherein the determination condition is whether or not the average value of the power or amplitude of the second signal for each sector is equal to or greater than a threshold value. A distortion compensation circuit that performs distortion compensation processing on the signal input to the power amplifier.
Claim 3 or claim, wherein the first signal acquisition unit acquires the first signal output from the distortion compensation circuit, and the second signal acquisition unit acquires the second signal output from the power amplifier. A coefficient calculation unit that calculates a distortion compensation coefficient using the first signal and the second signal selected by the signal selection circuit according to Item 4.
A compensation processing unit that performs distortion compensation processing on a signal input to the power amplifier using the distortion compensation coefficient calculated by the coefficient calculation unit, and a compensation processing unit.
A distortion compensation circuit characterized by being equipped with. A distortion compensation circuit that performs distortion compensation processing on the signal input to the power amplifier.
Claim 3 or claim, wherein the first signal acquisition unit acquires a first signal input to the distortion compensation circuit, and the second signal acquisition unit acquires a second signal output from the power amplifier. A coefficient calculation unit that calculates a distortion compensation coefficient using the first signal and the second signal selected by the signal selection circuit according to Item 4.
A compensation processing unit that performs distortion compensation processing on a signal input to the power amplifier using the distortion compensation coefficient calculated by the coefficient calculation unit, and a compensation processing unit.
A distortion compensation circuit characterized by being equipped with. The step that the signal acquisition unit acquires the signal and stores it in the memory,
A step in which the calculation unit divides the signal stored in the memory into three or more consecutive sectors and calculates a value indicating the signal level for each sector.
A step in which the determination unit determines for each sector whether or not the value calculated by the calculation unit satisfies the determination condition, and confirms whether or not three or more sectors satisfying the determination condition are consecutive.
The determination unit outputs a signal of a sector excluding the first sector and the last sector among three or more consecutive sectors satisfying the determination condition.
A signal selection method, characterized in that the signal acquisition unit acquires a signal again when three or more sectors satisfying the determination condition are not consecutive.

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