JP6832116B2 - Memory control device, information processing device, and memory control method - Google Patents

Description

The present invention relates to a memory control device, an information processing device, and a memory control method.

In recent years, low-priced portable information devices or information devices such as smartphones and smart watches have become widespread. As such an information device, a device equipped with a low-capacity, low-performance eMMC (Embedded MultiMediaCard) has become widespread. However, when the remaining capacity of the eMMC is small, the storage area is fragmented and the writing performance is likely to deteriorate. When the writing performance deteriorates, problems such as freezing for a certain period of time may occur during operation. In addition to eMMC, it cannot be denied that the same problem may occur in other storage devices such as the Secure Digital memory card (SD card).

Usually, writing to a storage device such as an eMMC takes time, so a temporary storage device called a write cache is adopted. In the write cache, a high-speed SDRAM or the like is used, and once the data to be written is stored in the write cache, a completion response is returned to the write request source. Then, writing to the storage device is collectively executed under conditions such as the data stored in the write cache exceeding a predetermined amount of data. A storage device that employs a write cache improves the operating efficiency and responsiveness of an information device by such processing.

Japanese Unexamined Patent Publication No. 7-28690 Japanese Unexamined Patent Publication No. 2013-206307 Japanese Unexamined Patent Publication No. 2014-59850

By the way, in the case of a storage device such as eMMC whose writing performance varies depending on the state of the storage device exemplified by the remaining capacity or the like, if writing is performed to the storage device under the same conditions without considering the state of the storage device. , It may take a long time to write depending on the state of the storage device. As a result, the operating efficiency or responsiveness of the entire information device having the storage device is lowered. If such a decrease in operating efficiency or responsiveness occurs during the operation of the user, there is a problem that the information device appears to be frozen during that time.

On one aspect, an object of the present invention is to suppress fluctuations in operating efficiency and responsiveness in an information device that employs a storage device whose writing performance may fluctuate depending on the state of the storage device.

In one aspect, the invention is exemplified by a memory control device comprising a control unit that accesses the memory. This control unit stores the data written in the memory in the buffer circuit, writes the data in the buffer circuit to the memory when the amount of data stored in the buffer circuit reaches the reference value, and the data in the memory. The reference value is increased or decreased according to the writing performance of.

According to this memory control device, it is possible to suppress fluctuations in operating efficiency and responsiveness in an information device that employs a storage device whose write performance may fluctuate depending on the state of the storage device.

It is a figure which illustrates the structure of the mobile terminal. It is a figure which illustrates the structure of the memory control part. It is a block diagram which shows the functional structure of a control part. It is a flowchart which illustrates the process which concerns on Embodiment 1. It is a flowchart which illustrates the process which concerns on Embodiment 2. It is a block diagram which shows the functional structure which concerns on Embodiment 3.

Hereinafter, the memory control device according to the embodiment will be described with reference to the drawings. The configuration of the following embodiment is an example, and the memory control device is not limited to the configuration of the embodiment.
[Embodiment 1]

FIG. 1 illustrates the configuration of the mobile terminal 1 including the memory control unit 102 of the present embodiment. The memory control unit 102 is not limited to the mobile terminal 1, and can be applied to various information devices, information processing devices, and the like. As shown in FIG. 1, the mobile terminal 1 includes a CPU 101, a memory control unit 102, a storage unit 103, a touch panel 104, a display 105, a battery 106, a wireless communication unit 107, an antenna 111, and audio input / output. It has a unit 108, a speaker 109, and a microphone 110.

The CPU 101 accesses the storage unit 103 via the memory control unit 102. The CPU 101 executes the process as the mobile terminal 1 according to a computer program executably expanded in the storage unit 103. The CPU 101 is an example of a processor. The CPU 101 is also an example of a control unit.

The memory control unit 102 writes data to the storage unit 103 and reads data from the storage unit 103 in response to a command from the CPU 101. The memory control unit 102 is an example of a memory control device.

The storage unit 103 includes, for example, an eMMC 103A and a Synchronous Dynamic Random Access Memory (SDRAM) 103B. The storage unit 103 is not limited to the one having the eMMC 103A. For example, the storage unit 103 may include an SD card standard embedded memory card, a flash memory, or the like instead of the eMMC 103A. Further, another memory, for example, a Static RAM (SRAM) may be provided instead of the SRAM 103B. The eMMC103A of the storage unit 103, an SD card that replaces the eMMC103A, or the like is an example of the memory.

The touch panel 104 is mounted on the display 105, detects an operation on the graphics object on the display by the user, and notifies the CPU 101 of the detected operation. The display 105 displays graphics objects, characters, images, and other information generated according to the processing of the CPU 101.

The battery 106 is, for example, a secondary battery, and supplies electric power to each part of the mobile terminal 1. The audio input / output unit 108 reproduces sound from the digital sound data generated according to the processing of the CPU 101, and outputs the sound from the speaker 109. Further, the audio input / output unit 108 generates digital sound data from the sound input from the microphone 110 and supplies it to the CPU 101.

The communication unit 107 accesses the wireless communication network through the antenna 111, and processes communication data sent and received via the wireless communication network. The communication unit 107 is, for example, a communication device that accesses a mobile phone network, a communication device that accesses a wireless Local Area Network (LAN), or the like.

FIG. 2 illustrates the configuration of the memory control unit 102. In FIG. 2, the CPU 101 and the storage unit 103 connected to the memory control unit 102 are also illustrated. As shown in the figure, the memory control unit 102 includes a control unit 102A, a Read Only Memory (ROM) 102B, a CPU interface 102C, and a memory interface 102D.

The control unit 102A has a CPU or the like, and executes the processing of the memory control unit 102 according to the firmware stored in the ROM 102B. The control unit 102A is an example of the control unit. The ROM 102B stores the firmware executed by the memory control unit 102A. A Random Access Memory (RAM) may be provided in the memory control unit 102. The firmware in the ROM 102B may be loaded into the RAM. Further, the ROM 102B may be provided in the mobile terminal 1 outside the memory control unit 102. For example, when the power of the mobile terminal 1 is turned on, the CPU 101 may load the firmware into the RAM of the memory control unit 102.

The CPU interface 102C is an interface with a bus connected to the CPU 101. Further, the memory interface 102D is an interface with the storage unit 103. The memory interface 102D includes, for example, a control signal line between a data bus, an address bus, and a storage unit 103. In FIG. 2, one memory interface 102D is connected to the eMMC103A and the SDRAM 103B, but two memory interfaces 102D connected to each of the eMMC103A and the SDRAM 103B may be provided.

FIG. 3 is a block diagram showing a functional configuration of the control unit 102A in the memory control unit 102. In the figure, the CPU 101, the eMMC 103A, and the SDRAM 103B are illustrated together with the control unit 102A.

As shown in the figure, the control unit 102A executes the firmware as, for example, the memory input / output unit 12, the memory performance monitoring unit 13, and the memory performance determination unit 14. The memory input / output unit 12, the memory performance monitoring unit 13, and the memory performance determination unit 14 may be configured to correspond to the modules included in the firmware.

The memory input / output unit 12 executes data writing and reading to the eMMC 103A in response to a request from the CPU 101. At this time, a part of the SDRAM 103B is used as a write cache 17 which is a write buffer. The write cache 17 of the SDRAM 103B is an example of a buffer circuit. The memory input / output unit 12 controls the amount of data stored in the write cache 17 by using a threshold value set according to the processing of the memory performance monitoring unit 13 and the memory performance determination unit 14. For example, the memory input / output unit 12 temporarily stores the write data from the CPU 101 in the write cache 17 of the SDRAM 103B when writing to the eMMC 103A. Then, when the amount of data written to the write cache 17 exceeds a predetermined threshold value, the memory input / output unit 12 writes the data of the write cache 17 to the eMMC. Therefore, the threshold value determines the storage capacity of the write cache 17, that is, the storage data size. The threshold value is an example of a reference value. The processing of each part will be described below.

(1) When the memory performance determination unit 14 determines that the write performance of the eMMC 103A monitored by the memory performance monitoring unit 13 has deteriorated to a specific performance or less, the memory input / output unit 12 sets the threshold value of the write cache 17. Make it smaller.

(2) When the memory performance determination unit 14 determines that the write performance of the eMMC 103A monitored by the memory performance monitoring unit 13 has improved beyond a specific performance, the memory input / output unit 12 sets the threshold value of the write cache 17. Enlarge.

(3) The memory performance monitoring unit 13 measures the throughput when writing the data of the write cache 17 to the eMMC103A. However, the memory performance monitoring unit 13 may monitor the memory performance based on the information (referred to as the level) included in the background operation (BKOPS) request from the eMMC103A. BKOPS is a storage area rearranging process executed by the eMMC103A itself when the eMMC103A is in a performance deterioration state due to fragmentation of the storage area or the like.

When the eMMC103A determines that the fragmentation of the storage area has progressed to a predetermined limit, the eMMC103A notifies a higher-level device, for example, the memory control unit 102, the CPU 101, or the like of the BKOPS request. The BKOPS request is notified to the host device together with the response to the write request to the eMMC103A, for example. BKOPS requirements include information called levels that indicate the degree of storage fragmentation. When the host device receives the BKOPS request, it notifies the eMMC103A of the BKOPS execution command according to the level. The memory performance monitoring unit 13 may acquire the level included in the request of BKOPS.

(4) The memory performance determination unit 14 holds an index value for determining the quality of the throughput at the time of writing from the write cache 17 to the eMMC103A (hereinafter, write throughput). The initial value of the index value is set to the best value of the write throughput corresponding to the state in which the eMMC103A is initialized. Then, the memory performance determination unit 14 specifies the write throughput when the write throughput notified from the memory performance monitoring unit 13 is worse than a predetermined value (for example, 10% or more) from the index value of the held write throughput. It is judged that the performance has deteriorated below the performance of. In addition, the index value is updated with the write throughput at this time.

(5) On the other hand, when the write throughput notified from the memory performance monitoring unit 13 is improved by a predetermined value or more (for example, 10% or more) from the index value of the held write throughput, the write throughput becomes higher than the specific performance. Judge that it has improved. In addition, the index value is updated with the write throughput at this time.

(6) When the memory input / output unit 12 changes the threshold value of the write cache 17 due to the improvement or deterioration of the write throughput as described above, the index value of the write throughput is updated.
(7) When the BKOPS level notified from the memory performance monitoring unit 13 is 2 or 3, the memory performance determination unit 14 determines that the performance has deteriorated to a specific performance or less.

In the present embodiment, the CPU 101 or the CPU included in the control unit 102A of the memory control unit 102 is also called an MPU (Microprocessor). The CPU is not limited to a single processor, and may have a multiprocessor configuration. Further, a single CPU connected by a single socket may have a multi-core configuration.

At least a part of the processing of each part of the memory input / output unit 12, the memory performance monitoring unit 13, and the memory performance determination unit 14 is performed by a processor other than the CPU, for example, a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), or a numerical value. It may be performed by a dedicated processor such as an arithmetic processor, a vector processor, or an image processor. Further, at least a part of the processing of each of the above parts may be an integrated circuit (IC) or other digital circuit. Further, an analog circuit may be included in at least a part of each of the above parts. Integrated circuits include LSIs, application specific integrated circuits (ASICs), and programmable logic devices (PLDs). The PLD includes, for example, a Field-Programmable Gate Array (FPGA). Each of the above parts
It may be a combination of a processor and an integrated circuit. The combination is called, for example, a microcontroller (MCU), a SoC (System-on-a-chip), a system LSI, a chipset, or the like. Therefore, in the present embodiment, the term "control unit" includes any one of the above CPU, processor, digital circuit, analog circuit, ASIC, PLD, FPGA, MCU, SoC, or a combination of two or more thereof.

FIG. 4 is a flowchart illustrating the processing of the memory control unit 102. The process of FIG. 4 can also be said to be a memory control method. The control unit 102A of the memory control unit 102 executes the firmware stored in the ROM 102B, for example, as the memory input / output unit 12, the memory performance monitoring unit 13, and the memory performance determination unit 14 illustrated in FIG. In FIG. 4, the processes S1 to S4 are processes corresponding to the memory input / output unit 12. Before the start of the process of FIG. 4, the index value referred to in S6 and S7 is initially set to the best value (for example, the best value of throughput in the initialized state of eMMC13A).

The control unit 102A monitors whether or not the memory write of the CPU 101 occurs via the CPU interface 102C (S1). When the memory write occurs, the control unit 102A stores the write data in the write cache 17 of the SDRAM 103B (S2). The process of S2 is an example of storing the data written in the memory in the buffer circuit. Further, the control unit 102A determines whether or not the amount of data stored in the write cache 17 is equal to or greater than the threshold value (S3). Then, when the amount of data stored in the write cache 17 is not equal to or greater than the threshold value, the control unit 102A returns the process to S1. On the other hand, when the amount of data stored in the write cache 17 is equal to or greater than the threshold value, the control unit 102A writes the data of the write cache 17 to the eMMC 103A (S4). If YES in the determination of S3, it is an example that the amount of data stored in the buffer circuit reaches the reference value. The process of S4 is an example of writing the data stored in the buffer circuit to the memory when the amount of data stored in the buffer circuit reaches the reference value.
In FIG. 4, the process of S5 is a process corresponding to the memory performance monitoring unit 13. Further, the processes from S6 to S10 are processes corresponding to the memory performance determination unit 14.

At the time of writing to the eMMC 103A in S4, the control unit 102A measures the write throughput (S5). The process of S5 is also an example of measuring the write performance when writing the data of the buffer circuit to the memory.

Next, the control unit 102A determines whether or not the throughput measured this time is a value deteriorated by a predetermined value or more (for example, 10% or more) from the index value (S6). When the throughput measured this time is a value deteriorated by a predetermined value or more from the index value, the control unit 102A lowers the threshold value of the write cache 17 (S9). Then, the control unit 102A updates the index value with the throughput measured this time (S10). When YES in S6, it is an example when the writing performance deteriorates from the index value by a predetermined value or more. The processing of S9 and S10 is an example of reducing the reference value and updating the index value with the deteriorated writing performance. The process of S10 is also an example of storing the index value of the writing performance. The process of S9 is also an example of reducing the reference value when the writing performance deteriorates beyond a predetermined limit.

On the other hand, if the throughput measured this time is not a value deteriorated by a predetermined value or more from the index value in the determination of S6, the control unit 102A improves the throughput measured this time by a predetermined value or more (for example, 10% or more) from the index value. It is determined whether or not the value is the same (S7). When the throughput measured this time is a value improved from the index value by a predetermined value or more, the control unit 102A raises the threshold value of the write cache 17 (S8). Then, the control unit 102A updates the index value with the throughput measured this time (S10). Then, the control unit 102A returns the process to S1. When YES in S7, it is an example when the writing performance is improved by a predetermined value or more from the index value. The processing of S8 and S10 is an example of increasing the reference value and updating the index value with the improved writing performance. The processing of S6 to S9 is an example of increasing or decreasing the reference value according to the writing performance. The process of S8 is an example of increasing the reference value when the writing performance is improved beyond a predetermined limit. The determination of S6 and S7 can be said to be a process of determining the deterioration or improvement of the throughput based on the relative change value from the index value.

As described above, the memory control unit 102 of the present embodiment increases or decreases the capacity of the write cache 17, that is, the threshold value, according to the write throughput at the time of writing to the eMMC 103A. Therefore, the memory control unit 102 can set the capacity of the write cache 17 to an appropriate value according to the write throughput to the eMMC 103A.

When the write throughput deteriorates and it takes time to write to the eMMC 103A, the memory control unit 102 reduces the capacity of the write cache 17 and adjusts so that the write time from the write cache 17 to the eMMC 103A does not increase. As a result, when writing from the write cache 17 to the eMMC103A occurs, the possibility that the user feels a decrease in operability is suppressed. On the other hand, when the write throughput is improved and it does not take much time to write to the eMMC 103A, the memory control unit 102 increases the capacity of the write cache 17 and utilizes the write cache 17 as much as possible.

When the write throughput deteriorates by a predetermined value or more from the index value, the memory control unit 102 of the present embodiment lowers the threshold value of the write cache 17 and updates the index value with the current write throughput. Further, the memory control unit 102 of the present embodiment raises the threshold value of the write cache 17 and updates the index value with the current write throughput when the write throughput improves from the index value by a predetermined value or more. Therefore, the memory control unit 102 can relatively determine the quality of the write throughput according to the index value, suppress the fluctuation of the index value, and make a stable determination.

Further, as in S5, the memory control unit 102 measures the throughput at the time of writing from the write cache 17 to the eMMC103A. Therefore, the memory control unit 102 can set the threshold value of the write cache 17 according to the actual throughput of writing to the eMMC 103A.
[Embodiment 2]

FIG. 5 is a flowchart illustrating the process according to the second embodiment of the memory control unit 102. BKOPS is notified asynchronously from the eMMC103A to the control unit 102A. For example, the eMMC103A notifies the request of BKOPS as the response data when the data writing process is completed. Therefore, the control unit 102A of the memory control unit 102 may change the threshold value of the write cache 17 asynchronously when receiving the notification requesting BKOPS. FIG. 5 is an example of processing for asynchronously changing the threshold value of the write cache 17.

In this process, the control unit 102A determines whether or not there is a request for BKOPS from the eMMC103A (S21). The BKOPS request from the eMMC103A is input to, for example, the register of the control unit 102A. Upon receiving the request for BKOPS from the eMMC103A, the control unit 102A acquires the level of BKOPS from the request for BKOPS (S22). The level of BKOPS is defined according to the standard of eMMC103A. For example, level 0 is the highest level, that is, the eMMC103A has no discontinuous region. Level 3 is the worst level.

Next, the control unit 102A determines whether or not the level of BKOPS is equal to or higher than a specific value (S23). The determination in S23 can be said to be a process of determining the deterioration or improvement of the throughput based on the absolute value. When the level of BKOPS is less than a specific value, the control unit 102A raises the threshold value of the write cache 17 (S24). On the other hand, when the level of BKOPS is equal to or higher than a specific value, the control unit 102A lowers the threshold value of the write cache 17 (S25). Here, the specific value is a value 2 or a value 3 or the like at the level of BKOPS, which is a preset value.

The process of S23-S25 is an example of increasing or decreasing the reference value according to the writing performance. The process of S24 is also an example of increasing the reference value when the writing performance is improved beyond a predetermined limit. The process of S25 is also an example of reducing the reference value when the writing performance deteriorates beyond a predetermined limit. When YES in S23, since the level of BKOPS is equal to or higher than a specific value, it is an example when the writing performance deteriorates to a range of not less than a predetermined value. When NO in S23, the level of BKOPS is less than a specific value, which is an example when the writing performance is improved to a range exceeding a predetermined value. The process of S24 is an example of increasing the reference value. The processing of S25 is an example of reducing the reference value.

Then, the control unit 102A determines whether or not the amount of data stored in the write cache 17 is equal to or greater than the threshold value (S26). When the amount of data stored in the write cache 17 is equal to or greater than the threshold value, the control unit 102A writes the data in the write cache 17 to the eMMC (S27). After that, the control unit 102A returns the process to S21.

As described above, in the present embodiment, the control unit 102A of the memory control unit 102 can acquire the level of BKOPS from the eMMC 103A instead of measuring the write throughput. Further, the control unit 102A can determine whether the writing performance has deteriorated to a range below a predetermined value or improved to a range exceeding a predetermined value according to the level of BKOPS. That is, the control unit 102A can determine the write throughput by an absolute value, so to speak.

In the second embodiment, the control unit 102A of the memory control unit 102 increases or decreases the threshold value of the cache 17 based on the level of BKOPS. However, instead of such processing, the control unit 102A may measure the write throughput at the time of writing to the eMMC103A, as in the first embodiment. Then, the control unit 102A may increase or decrease the threshold value of the cache 17 depending on whether the measured write throughput is in the range of the predetermined value or less or the range exceeding the predetermined value. It can be said that such a process is a process of determining the deterioration or improvement of the throughput based on the absolute value of the throughput.
[Embodiment 3]

In the first and second embodiments, the memory control unit 102 interposed between the CPU 101 and the storage unit 103 updates the threshold value of the write cache 17, that is, the capacity, and writes the data stored in the write cache to the eMMC 103A. The processing was illustrated. In the third embodiment, instead of the memory control unit 102 in the first and second embodiments, the CPU 101 updates the threshold value of the write cache 17 and writes the data stored in the write cache 17 to the eMMC 103A. The components and actions of the third embodiment are the same as those of the first and second embodiments, except that the CPU 101 updates the threshold value of the write cache 17 and writes the data stored in the write cache 17 to the eMMC 103A. Therefore, among the components of the third embodiment, the same components as those of the first and second embodiments are designated by the same reference numerals as those of the first and second embodiments, and the description thereof will be omitted. In the third embodiment, the CPU 101 is an example of the control unit. The CPU 101 is also an example of a memory control device. The mobile terminal 1 is an example of an information processing device.

FIG. 6 is a diagram illustrating the configuration of the mobile terminal 1 according to the third embodiment. In FIG. 6, in addition to the memory input / output unit 12A, the memory performance monitoring unit 13A, and the memory performance determination unit 14C, which are processing units provided by the hardware CPU 101, the memory control unit 102 and the storage unit 103 are exemplified as hardware. ing.

The memory control unit 102 of the third embodiment has the CPU memory interface 102E but does not have the control unit 102A. That is, the memory control unit 102 of the third embodiment is an interface that provides an access route from the CPU to the storage unit 103. Since the configuration of the storage unit 103 of the third embodiment is the same as that of the first and second embodiments, the description thereof will be omitted.

In the third embodiment, the CPU 101 executes the process as the memory input / output unit 12A, the memory performance monitoring unit 13A, and the memory performance determination unit 14A according to the computer program executably deployed in the storage unit 103. The programs corresponding to the memory input / output unit 12A, the memory performance monitoring unit 13A, and the memory performance determination unit 14A are included in, for example, an operating system (OS) module executed by the CPU 101. The CPU 101 holds an OS including these modules in, for example, the eMMC103A. The CPU 101 may hold the OS including these modules in a ROM or the like other than the eMMC103A. When the power is turned on, the CPU 101 loads the OS from the eMMC103A or ROM into the SDRAM 103B to provide the function as the mobile terminal 1.

The processing of the memory input / output unit 12A, the memory performance monitoring unit 13A, and the memory performance determination unit 14A of the third embodiment is the same as that of the memory input / output unit 12, the memory performance monitoring unit 13, and the memory performance determination unit 14 of FIG. That is, the CPU 101 executes the process of FIG. 4 or the process of FIG. 5 in the same manner as the control unit 102A in the memory control unit 102 of FIG.

That is, in FIG. 4, the processes S1 to S4 are processes corresponding to the memory input / output unit 12A. Further, the process of S5 is a process corresponding to the memory performance monitoring unit 13A. Further, the processes from S6 to S10 are processes corresponding to the memory performance determination unit 14A.

Further, FIG. 5 can be said to be a processing example in which the threshold value of the write cache 17 is asynchronously changed when the CPU 101 receives a BKOPS request. The CPU 101 is asynchronously notified of the BKOPS request together with the response to the write request to the eMMC103A. In FIG. 5, S21 and S22 are processes corresponding to the memory performance monitoring unit 13A. S23 to S25 are processes corresponding to the memory performance determination unit 14A. Further, S26 to S27 are processes corresponding to the memory input / output unit 12A.

As described above, even when the control unit 102A of the memory control unit 102 illustrated in FIG. 2 is not provided, the CPU 101 executes the process of FIG. 4 or 5 to write to the eMMC 103A at the time of writing. The capacity of the write cache 17, that is, the threshold value is increased or decreased according to the throughput. Therefore, when the write throughput deteriorates and it takes time to write to the eMMC103A, the CPU 101 adjusts the capacity of the write cache 17 so as not to increase the write time from the write cache 17 to the eMMC103A. As a result, when writing from the write cache 17 to the eMMC103A occurs, the possibility that the user feels deterioration in operability or the like is suppressed.

The configurations of the above embodiments 1 to 3 are not limited to the mobile terminal 1, and information having a memory such as the eMMC103A whose writing performance varies depending on the state of the eMMC103A exemplified by the remaining capacity or the like. As long as it is a device, it can be applied to any information device.

12, 12A Memory input / output unit 13, 13A Memory performance monitoring unit 14, 14A Memory performance judgment unit 101 CPU
102 Memory control unit 102A Control unit 102B ROM
103 Storage unit 103A eMMC
103B SDRAM

Claims (5)

Equipped with a control unit to access memory
The control unit
The data written in the memory is stored in the buffer circuit, and when the amount of data stored in the buffer circuit reaches a reference value, the data stored in the buffer circuit is written to the memory.
The reference value is increased or decreased according to the performance of writing data to the memory, and
Increasing or decreasing the reference value
The index value of the writing performance is stored, and when the writing performance deteriorates from the index value by a predetermined value or more, the reference value is reduced and the index value is updated by the deteriorated writing performance. ,
A memory control device including increasing the reference value when the write performance is improved by a predetermined value or more from the index value and updating the index value with the improved write performance. The memory control device according to claim 1, wherein the control unit measures the write performance when writing data of the buffer circuit to the memory. The memory control device according to claim 1 or 2 , wherein the control unit acquires the write performance from the memory. With the processor
With memory,
The processor
The data written from the processor to the memory is stored in the buffer circuit, and when the amount of data stored in the buffer circuit reaches a reference value, the data stored in the buffer circuit is written to the memory.
The reference value is increased or decreased according to the performance of writing data to the memory, and
Increasing or decreasing the reference value
The index value of the writing performance is stored, and the writing performance deteriorates by a predetermined value or more from the index value.
When this is done , the reference value is reduced and the index value is updated with the deteriorated writing performance .
An information processing device including increasing the reference value when the writing performance is improved by a predetermined value or more from the index value and updating the index value with the improved writing performance. The processor
The data written from the processor to the memory is stored in the buffer circuit, and when the amount of data stored in the buffer circuit reaches a reference value, the data stored in the buffer circuit is written to the memory.
The reference value is increased or decreased according to the performance of writing data to the memory, and
Increasing or decreasing the reference value
The index value of the writing performance is stored, and when the writing performance deteriorates from the index value by a predetermined value or more, the reference value is reduced and the index value is updated by the deteriorated writing performance. ,
A memory control method comprising increasing the reference value when the writing performance is improved by a predetermined value or more from the index value and updating the index value with the improved writing performance.

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