JP6821313B2 - Data processing system and data processing method - Google Patents

Description

The present invention relates to a data processing system及beauty data processing method.

As a method for performing data processing at high speed, various methods have been proposed for hard disks, communication devices between CPUs (Central Processing Units), and the like. For example, the technique described in Patent Document 1 has been proposed as a conventional technique for high-speed data processing using a file stored in a storage device such as a hard disk. Patent Document 1 describes a technique for improving the speed of data processing by providing two storage devices having different speeds and storing frequently accessed file management information in a high-speed storage device. Further, in chip-to-chip communication such as CPU-to-CPU communication, a method of reducing the overhead of data processing by directly writing data to a memory in the destination chip domain via an inter-chip bus is common.

Japanese Unexamined Patent Publication No. 9-282103

Patent Document 1 attempts to improve the data processing capacity by storing frequently accessed file management information in a high-speed storage device, but when the reading speed of the storage device is slower than the writing speed, Relative processing power is reduced. In addition, in the general method used for chip-to-chip communication, when securing a data area from the memory in the chip domain of the other party, frequently accessed data such as data area management table information must be read via the chip-to-chip interface. I had to. It is known that a general chip-to-chip interface such as a PCI (Peripheral Component Interconnect) interface has a read speed slower than a write speed. From the above, in the above-mentioned conventional technology, the reading speed of frequently accessed data becomes a bottleneck, and the data processing capacity is reduced. The present invention has been made in view of such circumstances, and an object of the present invention is to improve communication performance between data processing blocks via an inter-block interface.

In the data processing system according to the present invention, a first data processing block and a second data processing block having a memory for writing data transmitted from the first data processing block are connected via a bus between the blocks. In a connected data processing system , the first data processing block is a storage means for storing a list of free areas including the start address and size of each free area of the memory of the second data processing block. When writing data to the memory, the start address and size of each free area in the free area list stored in the storage means are referred to in the memory based on the size of the data. Data is transferred to the data storage area of the memory secured by the management means via a management means for securing a data storage area for writing the data from a free area where the data can be written and a bus between the blocks. writing, and a transmitting means for receiving requests for information and the person the data indicating the address of the person the data storage area is transmitted to the second data processing block, the second data processing block, the first If the data processing block receives the reception request, the data storage based on the information indicating the address of the area to read out the data from the data storage area of the memory, after the completion of reception of the data first read have a receiving means for notifying the data processing block, the management unit of the first data processing block, said upon securing a data storage area, the size of the free space available write the data storing the data If it matches the size of the area, the free area is deleted from the free area list, and if the size of the free area is larger than the size of the data storage area, the start address of the free area is used in the free area list. When the size is updated based on the size of the data storage area and the management means of the first data processing block receives the notification of the completion of reception, the data storage area is followed by a free area. Updates the start address of the free area to the start address of the data storage area, increases the size of the free area by the size of the data storage area, and if the free area does not follow the data storage area. It is characterized in that the start address and size of the data storage area are registered in the free area list as the start address and size of a new free area .

According to the present invention, data can be written via the inter-block bus without reading via the inter-block bus, so that the communication performance between data processing blocks via the inter-block bus can be improved. ..

It is a figure which shows the configuration example of the data processing system in 1st Embodiment. It is a flowchart which shows the operation of 1st Embodiment. It is a figure for demonstrating the area management method by the area management table. It is a flowchart which shows the example of the area acquisition processing in step S203 of FIG. It is a figure which shows the example of the area management table and the memory pool after the update process. It is a flowchart which shows the example of the area release processing in step S203 of FIG. It is a figure which shows the example of the area management table and the memory pool after the update process. It is a figure which shows the structural example of the data processing system in 2nd Embodiment. It is a flowchart which shows the operation example of the data processing system in 2nd Embodiment. It is a figure which shows the structural example of the data processing system in 3rd Embodiment. It is a flowchart which shows the operation example of the data processing system in 3rd Embodiment. It is a figure which shows the structural example of the data processing system in 4th Embodiment. It is a figure which shows the structural example of the transmission control part in 4th Embodiment. It is a figure which shows the structural example of the reception control part in 4th Embodiment. It is a flowchart which shows the operation example of the data processing system in 4th Embodiment. It is a flowchart which shows the example of the area acquisition process in step S1502 of FIG. It is a figure which shows the example of the transmission packet area and the reply packet area.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment)
The first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration example of a data processing system according to the first embodiment. The data processing system according to the first embodiment includes a first data processing block 105, a second data processing block 109, and an inter-block bus 110. The first data processing block 105 and the second data processing block 109 are connected via the inter-block bus 110.

Here, the data processing block represents one domain composed of, for example, a CPU (Central Processing Unit) and peripheral devices such as a memory. Further, the inter-block bus represents, for example, an inter-chip bus represented by PCI (Peripheral Component Interconnect) or PCI Express, or a general-purpose bus used as an on-chip bus. The inter-block bus is, for example, a bus in which the data reading speed via the inter-block bus is slower than the data writing speed via the inter-block bus. The configuration of the data processing system shown in FIG. 1 includes, for example, a form in which data processing blocks arranged on different chips are connected via an inter-chip bus. Further, the configuration of the data processing system shown in FIG. 1 includes, for example, a form in which a plurality of data processing blocks arranged in one chip are connected via an on-chip bus.

The first data processing block 105 has a transmission activation unit 101, a transmission unit 102, a memory management unit 103 for inter-block communication, and an area management table 104 for inter-block communication. The second data processing block 109 has a reception notification unit 107, a reception unit 106, and a memory pool 108 for inter-block communication. The operation of the data processing system according to the first embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a flowchart showing an operation example of the data processing system according to the first embodiment.

First, in step S201, the transmission activation unit 101 issues a transmission start instruction to the transmission unit 102. At this time, the transmission activation unit 101 passes the transmission data storage area size and the transmission data information together to the transmission unit 102. Upon receiving the transmission start instruction, the transmission unit 102 sends a transmission area reservation request to the memory management unit 103 in step S202. At this time, the transmission data storage area size received in step S201 is also passed to the memory management unit 103.

In step S203, the memory management unit 103 analyzes the area management table 104 and secures a transmission data storage area of a required size on the memory pool 108. The process in step S203 will be described in detail with reference to FIGS. 3 to 5. FIG. 3 is a diagram for explaining an area management method using an area management table. FIG. 3A shows an example of the area management table 104 and the memory pool 108 in the state immediately after initialization, and FIG. 3B shows an example of the area management table 104 and the memory pool 108 in the operating state. Is shown. The area management table is area allocation information related to the memory pool, and includes, for example, information indicating whether or not data can be written in units of areas obtained by dividing the memory pool into areas of a predetermined size.

Here, it is assumed that the size of the memory pool 108 is Q bytes, and the minimum area acquisition unit in the memory pool 108 is N bytes. Therefore, the acquired area size is a multiple of N bytes. Also, for the sake of simplicity, it is assumed that Q is a multiple of N. The implementation of the area management table 104 can be considered in various forms, but here, it is assumed that it is a two-dimensional array represented by Table [Q / N] [3]. Table [Idx] [...] represents the state of the area starting from the address (N × Idx) of the memory pool 108, and its meaning is as follows.
Table [Idx] [1, 2, 3] = [Previous empty area Idx, Next empty area Idx, Idx area free size]

For example, the state of Idx = n having the values of the elements 305 to 307 of the area management table 104 shown in FIG. 3B is as follows. "A continuous area of Size_n bytes starting from the address (n × N) is free, the free area before this free area is Idx = p, and the free area after this free area is Idx = m. "It turns out that. When the value of Previous-Idx is "-1", it means that it is the beginning of the free space list, and when the value of Next-Idx is "-1", it means that it is the end of the free space list. It shall indicate that it is a tail. Further, when the value of the free area list head index 301 is "-1", it means that there is no free area at all.

Next, the operation when there is a request to acquire the E-byte area while in the operating state shown in FIG. 3B will be described with reference to the flowchart shown in FIG. FIG. 4 is a flowchart showing an example of the memory area acquisition process in step S203 of FIG. Unless otherwise specified, the memory management unit 103 performs the processing of FIG.

First, in step S401, the memory management unit 103 obtains a minimum multiple R of N that does not fall below E specified by the transmission data storage area size passed together with the transmission area reservation request from the transmission unit 102. Next, in step S402, the memory management unit 103 refers to the free area list top index 301 of the area management table 104 to obtain the top index of the free area. Next, in step S403, the memory management unit 103 determines whether or not the start index is “-1”, and if it is “-1”, there is no free area in the memory pool 108. Immediately proceed to step S408 and end with an error.

As a result of the determination in step S403, if the start index is not "-1", the memory management unit 103 obtains the size of the free area by referring to the information indicated by the start index in step S404. In the example shown in FIG. 4B, since the head index is “2”, the memory management unit 103 obtains the size of the free area by referring to the Table [p] [2] of the area management table 104.

Next, in step S405, the memory management unit 103 determines whether or not the size of the free area obtained in step S404 is equal to or greater than the R obtained in step S401. When the size of the free area obtained in step S404 is smaller than R, the memory management unit 103 obtains the index of the next free area by referring to Table [p] [1] in step S406. Here, if the index value of the next free area obtained is "-1", the memory management unit 103 determines in step S407 that there is no area satisfying the condition, and proceeds to step S408 to make an error. finish. On the other hand, if the index value of the next free area obtained in step S406 is not "-1", the memory management unit 103 returns to step S404 and repeats the loop process again.

If the size of the obtained free area is R or more as a result of the determination in step S405, the memory management unit 103 proceeds to step S409, and updates the area management table 104 in steps S409 to S411. If the index at this time is i, Pi = Table [i] [0], Ni = Table [i] [1], and Si = Table [i] [2]. The states of the area management table 104 and the memory pool 108 after the update process are as shown in FIG. 5, for example.

FIG. 5A shows the state of the area management table 104 and the memory pool 108 after the update process in step S410, which is performed when the size of the obtained free area is R. Further, FIG. 5B shows the states of the area management table 104 and the memory pool 108 after the update process in step S411, which is performed when the obtained free area size is different from R (larger than R). There is. In the processes of steps S410 and S411, when Pi or Ni is "-1", the corresponding list update process is omitted. For example, when Pi = -1, the table [Pi] [...] substitution process is not performed.

Returning to FIG. 4, when the processing of steps S409 to S411 is completed, in step S412, the memory management unit 103 determines whether or not the index i is the head of the free area list. If it is determined that the head is the head, the memory management unit 103 updates the free area list head index 301 of the area management table 104 in step S413. Finally, in step S414, the memory management unit 103 converts the index of the free area into the address of the memory pool and returns it. Note that the offset is a value in the IO space determined by the interface standard of the inter-block bus 110. For example, the address mapped to the PCI window in the address space of the CPU corresponds to this. This completes the detailed description of the process of step S203 shown in FIG.

Returning to FIG. 2, the processing after step S204 will be described. In step S204, the transmission unit 102 writes transmission data to the transmission data storage area on the memory pool 108 acquired in step S203. The transmission data to be written is the one passed by the transmission activation unit 101 to the transmission unit 102 in step S201. Further, the transmission data is written via the inter-block bus 110.

Next, in step S205, the transmission unit 102 notifies the reception notification unit 107 of the address of the transmission data storage area and the reception request notification. The address of the transmission data storage area and the notification of the reception request notification are notified via the inter-block bus 110. In step S206, the reception notification unit 107 notifies the reception unit 106 of the reception request from the received transmission unit 102 and the address of the data storage area. The data storage area address to be notified is converted into a value in an address space that can be interpreted by the receiving unit 106, and the transmitting unit 102 manages the offset between its own address space and the address space of the other party. It has these conversion functions.

Next, in step S207, the receiving unit 106 refers to the address of the data storage area and reads data from the memory pool 108. Here, various forms can be considered as the structure of the reception notification unit 107. For example, it can be composed of a communication register consisting of a scratch pad and an interrupt instruction bit. In this case, the transmission unit 102 writes the address of the transmission data storage area to the scratch pad of the reception notification unit 107 mapped to the inter-block bus 110, and further sets an interrupt instruction bit. As a result, the receiving unit 106 can receive the reception request and the address of the data storage area.

The receiving unit 106 can notify the transmitting side (data processing block 105 in this example) that the transmission data has been read. This method is not particularly limited, and for example, the read completion can be notified by setting the address of the transmission data storage area and the reception completion flag in a predetermined area of the memory on the transmitting side. Further, for example, the same notification can be performed by writing the result to a specific register on the transmitting side.

Next, in step S208, the transmission activation unit 101 instructs the transmission unit 102 to end transmission. Various methods can be considered for determining the timing at which the transmission start unit 101 gives the transmission end instruction to the transmission unit 102, but the present invention is not particularly limited. In step S209, the transmission unit 102 sends the start address and size of the transmission data storage area to the memory management unit 103, and instructs the memory management unit 103 to release the transmission data storage area.

Here, the transmission unit 102 can check whether or not the transmission data has been reliably read by the reception unit 106. The method is not particularly limited, but according to the example described in the description of step S207, there are a method of checking the reception completion flag on the memory, a method of checking a specific register, and the like. The transmission unit 102 can also select not to issue a release request for the transmission data storage area until, for example, reception is completed. By doing so, it is possible to prevent the data before reading from being destroyed.

In step S210, the memory management unit 103 operates the area management table 104 to release the transmission data storage area taken on the memory pool 108. Hereinafter, the process in step S210 will be described in detail mainly using the flowchart of FIG. 6 with reference to FIG. FIG. 6 is a flowchart showing an example of the memory area release process in step S210 of FIG. Unless otherwise specified, the memory management unit 103 performs the processing of FIG.

First, in step S601, the memory management unit 103 receives the address A of the area to be released and its size S. These values are passed to the memory management unit 103 by the transmission unit 102 in step S209. Next, in step S602, the memory management unit 103 converts the address A of the area to be released into the index of the free area list in the area management table 104. The offset is the same as that used for the conversion in step S414. The free area management method of the area management table 104 is as described above with reference to FIG.

Next, in step S603, the memory management unit 103 obtains Pi and Ni (Pi <i <Ni) sandwiching the index i obtained in step S602. This process is performed by searching the area management table 104 in a list. Next, in step S604, the memory management unit 103 determines whether or not the target index i is the end of the free area list. Here, the fact that Ni is "-1" indicates that the end of the free area list.

As a result of the determination in step S604, if Ni is "-1", it branches to step S607, and if Ni is not "-1", it proceeds to step S605. In step S605, the memory management unit 103 determines whether or not the area to be released should be connected to the next free area. If it is determined that the memory management unit 103 should be connected, the area management table 104 is updated in step S606, and if it is determined that the memory management unit 103 is not connected, the area management table 104 is updated in step S607. Update process. The states of the area management table 104 and the memory pool 108 after the update process are as shown in FIG. 7, for example. FIG. 7A shows the state of the area management table 104 and the memory pool 108 after the update process in step S606. Further, FIG. 7B shows the state of the area management table 104 and the memory pool 108 after the update process in step S607.

Returning to FIG. 6, after updating the list in the area management table 104 in steps S605 to S607, in step S608, the memory management unit 103 asks whether the index i to be released is the head of the free area list. Judge whether or not. Here, it means that Pi is "-1" at the beginning.

As a result of the determination in step S608, when Pi is "-1", the memory management unit 103 rewrites the free area list top index 301 to i in step S609. Since the process when the target index i in step S604 is the head of the free area list is the same as the process described above in step S607, the description thereof will be omitted. This completes the detailed description of the process of step S210 shown in FIG.
Returning to FIG. 2 again, when the process of step S210 is completed, all the processes are completed. This is the end of the operation description of the data processing system in the first embodiment.

According to the first embodiment, in the communication between the data processing blocks via the inter-block bus, the transmission source uses an area management table indicating the free area of the memory pool 108 of the second data processing block 109 as the transmission destination. A first data processing block 105 has. As a result, the data storage area in the second data processing block 109 can be determined and data communication can be performed without reading via the inter-block bus, and the data communication can be performed via the inter-block bus related to the data communication. It is possible to suppress the occurrence of reading. Therefore, it is possible to eliminate the bottleneck of the reading process in the data communication via the inter-block bus and improve the communication performance between the data processing blocks.

In the above-described embodiment, the first data processing block 105 is responsible for transmission and the second data processing block 109 is responsible for reception. However, both data processing blocks incorporate a transmission / reception system for bidirectional communication. Is possible.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. Regarding the drawings used for the description of the second embodiment, the same reference numerals will be given to the same components as those in the above-described embodiment, and the description will be omitted. FIG. 8 is a block diagram showing a configuration example of the data processing system according to the second embodiment. In FIG. 8, N second data processing blocks 805 to 807 on the receiving side (N is a natural number) are connected to the first data processing block 105 on the transmitting side via the inter-block bus 110. Has been done.

The most different points of the first data processing block 105 from the first embodiment are that the destination management unit 804 is added and the area management table 104 (area management table <1> to area management table) for inter-block communication. It has a plurality of <N>). The destination management unit 804 manages information between the area management table 104 corresponding to the destination and the reception notification unit 107.

The transmission activation unit 801 gives a transmission destination identifier indicating a data processing block of the transmission destination when giving a transmission start instruction or a transmission end instruction to the transmission unit 802. The destination identifier makes it possible to identify the data processing block of the destination (reception side). The transmission unit 802 sends the received destination identifier to the destination management unit 804 to acquire the information of the corresponding reception notification unit 107. Further, the transmission unit 802 gives a transmission destination identifier as additional information when requesting the memory management unit 803 to secure a transmission data storage area. The memory management unit 803 sends the received destination identifier to the destination management unit 804 to acquire the information of the corresponding area management table 104.

As described above, the first data processing block 105 in the second embodiment has an additional function of managing a plurality of destinations with respect to the function of the first embodiment. Next, the operation of the data processing system according to the second embodiment shown in FIG. 8 will be described with reference to FIG. FIG. 9 is a flowchart showing an operation example of the data processing system according to the second embodiment.

First, in step S901, the transmission start unit 801 issues a transmission start instruction to the transmission unit 802. At this time, the transmission activation unit 801 passes the transmission data storage area size and data contents to the transmission unit 802 together with the transmission data storage area, and also passes the transmission destination identifier to the transmission unit 802, as in the first embodiment. Next, in step S902, the transmission unit 802 issues a transmission area securing request to the memory management unit 803. Here, in addition to the size of the area to be acquired, the destination identifier received in step S901 is also passed to the memory management unit 803.

In step S903, the memory management unit 803 passes the destination identifier to the destination management unit 804, and acquires the information of the area management table 104 corresponding to the destination. Various methods can be considered for associating the destination identifier with the area management table information. For example, there is a method of statically managing the destination identifier and the address of the corresponding area management table. According to this method, the address acquired by the memory management unit 803 directly indicates the desired area management table 104 (any one of the area management table <1> to the area table <N>).

In step S904, the same processing as in steps S203 to S204 shown in FIG. 2 is performed. Next, in step S905, the transmission unit 802 passes the destination identifier to the destination management unit 804, and acquires the information of the reception notification unit 107 of the destination. Various methods can be considered as a method of associating the destination identifier with the reception notification unit 107 of each of the second data processing blocks 805 to 807. For example, when the reception notification unit 107 is configured as a communication register as described in the first embodiment, the identifier and the IO address of the reception notification unit may be managed in a static table.

The IO address referred to here is an address in the IO space determined by the interface standard of the inter-block bus 110, and corresponds to, for example, a map address on the PCI window. According to this method, the transmission unit 802 can access the desired reception notification unit 107 by accessing the acquired address. The management information of the destination management unit 804 is used in steps S903 and S905, and this information can be set at an arbitrary timing at the time of initialization. Various methods can be considered as the setting method, but the setting method is not particularly limited in this embodiment. Next, in step S906, the same processing as in steps S205 to S207 shown in FIG. 2 is performed, and the processing on the receiving side is completed.

Next, in step S907, the transmission start unit 801 issues a transmission end instruction to the transmission unit 802. Various methods can be considered for determining the timing at which the transmission start unit 801 gives the transmission end instruction to the transmission unit 802, but the method is not particularly limited here. In step S908, the transmission unit 802 adds a transmission destination identifier and requests the memory management unit 803 to release the transmission data storage area. The only difference between the processes in steps S907 to S908 and the processes in the first embodiment is that the destination identifier is passed as additional data as in the processes in steps S901 to S902.

Next, in step S909, the memory management unit 803 selects the area management table 104 to be released in the same manner as in step S903 described above. In the following step S910, the same processing as in step S210 shown in FIG. 2 is performed to complete the release of the transmission data storage area. This concludes the description of the operation of the data processing system according to the second embodiment shown in FIG.

According to the second embodiment, as in the first embodiment, the data storage area in the second data processing block on the receiving side is determined and the data is determined without reading via the inter-block bus. It becomes possible to communicate. Therefore, it is possible to suppress the occurrence of reading via the inter-block bus related to data communication, eliminate the bottleneck of reading processing in data communication, and improve the communication performance between data processing blocks. In the present embodiment, the first data processing block 105 is responsible for transmission, and the other data processing block groups 805 to 807 are responsible for reception. However, both data processing blocks incorporate a transmission / reception system. Forward communication is possible.

(Third Embodiment)
Next, a third embodiment of the present invention will be described. Regarding the drawings used for the description of the third embodiment, the same reference numerals will be given to the same components as those in the above-described embodiment, and the description will be omitted. FIG. 10 is a block diagram showing a configuration example of the data processing system according to the third embodiment. In FIG. 10, the components different from the first embodiment are the transmission client 1001 and the transmission notification unit 1003 of the first data processing block 105.

The transmission client 1001 controls the memory management unit 103 to acquire the transmission data storage area. Further, the transmission client 1001 directly writes the transmission data to the memory pool 108 for inter-block communication included in the second data processing block 109, and issues a transmission start instruction to the transmission notification unit 1003. Further, the transmission client 1001 instructs the memory management unit 103 to release the transmission data storage area. When the transmission notification unit 1003 receives the transmission start instruction from the transmission client 1001, the transmission notification unit 1003 notifies the reception notification unit 107 of the second data processing block 109 of the reception request.

Hereinafter, the operation of the data processing system according to the third embodiment will be described with reference to the flowchart shown in FIG. FIG. 11 is a flowchart showing an operation example of the data processing system according to the third embodiment. First, in step S1101, the transmission client 1001 requests the memory management unit 103 to secure the transmission data storage area. At this time, the transmission client 1001 also passes the size of the area to be acquired.

Next, in step S1102, the same processing as in steps S202 to S203 shown in FIG. 2 is performed, and the acquired address of the transmission data storage area is returned to the transmission client 1001. Next, in step S1103, the transmission client 1001 writes transmission data to the transmission data storage area of the memory pool 108 acquired in step S1102. The transmission data is written to the transmission data storage area via the inter-block bus 110.

Next, in step S1104, the transmission client 1001 issues a transmission start instruction to the transmission notification unit 1003. At this time, the address of the transmission data storage area in which the data is written is also passed to the transmission notification unit 1003. In step S1105, the same processing as in steps S205 to S207 shown in FIG. 2 is performed, and the data reception processing is completed. The transmission notification unit 1003 has a function of converting the address of the transmission data storage area performed by the transmission unit 102 in the first embodiment.

Next, in step S1106, the transmission client 1001 sends the start address and size of the transmission data storage area to the memory management unit 103, and gives an instruction to release the transmission data storage area. In the following step S1107, the same processing as in step S210 shown in FIG. 2 is performed to release the transmission data storage area. This concludes the description of the operation of the data processing system according to the third embodiment shown in FIG.

According to the third embodiment, it is possible to determine the data storage area in the second data processing block 109 and perform data communication without performing reading via the inter-block bus. Therefore, it is possible to suppress the occurrence of reading via the inter-block bus related to data communication, eliminate the bottleneck of reading processing in data communication, and improve the communication performance between data processing blocks. In the present embodiment, the first data processing block 105 is responsible for transmission and the second data processing block 109 is responsible for reception. However, both data processing blocks incorporate a transmission / reception system for bidirectional communication. Is possible. Further, in the present embodiment, the case where there is one transmitting side and one receiving side has been described, but if the destination management unit 804 is introduced as in the second embodiment, it is possible to deal with a plurality of receiving destinations.

(Fourth Embodiment)
Next, a fourth embodiment of the present invention will be described. Regarding the drawings used for the description of the fourth embodiment, the same reference numerals will be given to the same components as those in the above-described embodiment, and the description will be omitted. First, the configuration of the data processing system according to the fourth embodiment will be outlined, and then the operation will be described.

The configuration of the data processing system according to the fourth embodiment will be described with reference to FIGS. 12 to 14. FIG. 12 is a block diagram showing an overall configuration example of the data processing system according to the fourth embodiment. In FIG. 12, 1201 and 1211 are a plurality of data processing blocks for inter-block communication. The plurality of data processing blocks 1201 and 1211 are connected on the inter-block bus 110. As described in the first embodiment, the configuration of the data processing system includes a configuration composed of a plurality of data processing blocks arranged on different chips and a configuration composed of a plurality of data processing blocks arranged on one chip. including.

The data processing block 1201 has a plurality of communication clients 1202, a transmission control unit 1203, a reception control unit 1204, an internal memory pool 1205, and a memory pool 108 for inter-block communication. Although only the internal configuration of the data processing block 1201 is shown in FIG. 12, the plurality of data processing blocks 1201 and 1211 have the same internal configuration.

The transmission control unit 1203 receives a transmission data storage area securing instruction, a release instruction, and a transmission start instruction from the communication client 1202, and is in charge of overall transmission-related control. Upon receiving the instruction to secure the transmission data storage area, the transmission control unit 1203 secures the transmission data storage area from the memory pool 108 of the data processing block of the other party and secures the reply data storage area from the internal memory pool 1205. When the communication client 1202 finishes writing the transmission data to the transmission data storage area and issues a transmission start instruction, the transmission control unit 1203 issues a reception notification request to the data processing block of the other party. Further, when the transmission control unit 1203 receives the release instruction of the transmission data storage area, the transmission control unit 1203 releases the secured transmission data storage area and the reply data storage area.

The reception control unit 1204 notifies the communication client 1202 when it receives a reception notification request from another data processing block. The reception control unit 1204 interprets the command header of the address passed in the reception notification request and specifies the communication client 1202 to be notified and the received data type (reply or new transmission). Then, the reception control unit 1204 notifies the communication client 1202 of the reception data type and the reception data address, and issues a reception instruction. The communication client 1202 that has received the reception instruction from the reception control unit 1204 reads the data from the passed address.

Next, the configuration of the transmission control unit 1203 will be described with reference to FIG. FIG. 13 is a block diagram showing a configuration example of the transmission control unit 1203. In FIG. 13, 1301 is a transmission area management unit. The transmission area management unit 1301 handles the instruction for securing and releasing the transmission data storage area from the communication client 1202. The transmission area management unit 1301 passes the identifier (destination identifier) of the data processing block of the transmission destination and the area information to the memory management unit 803 for block communication to secure the transmission data storage area. Further, the transmission area management unit 1301 secures a reply data storage area from the internal memory pool 1205 by using the internal memory management unit 1302.

The reply data storage area is an area for the destination communication client to store the execution result and the like. Since the returned content is read by the communication client 1202 on the transmitting side, the reply data storage area is secured in the same data processing block (data processing block on the transmitting side). Various methods can be applied as the internal memory pool management method performed by the internal memory management unit 1302. For example, a commonly used link list-based free list management method can be considered, but the present invention is not limited thereto.

The address translation unit 1303 responds to the transmission start instruction instructed by the communication client 1202. Since the address requested by the communication client 1202 to be transmitted is an address inside the transmission data storage area, it is converted into the start address of the transmission data storage area and passed to the transmission notification unit 1305. Regarding the transmission processing operation in the transmission notification unit 1305, only the transmission destination selection operation performed by the transmission destination management unit 804 is added to the operation of the transmission notification unit 1003 in the third embodiment shown in FIG. Since this has already been described in the second embodiment and the third embodiment, the description thereof will be omitted.

Next, the configuration of the reception control unit 1204 will be described with reference to FIG. FIG. 14 is a block diagram showing a configuration example of the reception control unit 1204. In FIG. 14, the reception management unit 1401 receives the reception notification request and the reception data address from the reception notification unit 107. Since the reception notification unit 107 has already been described in the first embodiment, the description thereof will be omitted. The address received from the reception notification unit 107 is the address of the area included in either the memory pool 108 or the internal memory pool 1205.

The reception management unit 1401 reads the default command header by referring to the received address. The details will be described later in the operation description, but this command header includes an identifier that specifies the received data type (reply or new transmission) and the communication client. The reception management unit 1401 passes the reception data type and the communication client identifier to the client management unit 1402 together with the reception data address.

The client management unit 1402 manages the relationship between the communication client identifier and the corresponding communication client 1202, and delivers the information received from the reception management unit 1401 to the communication client 1202. Various methods can be applied as the communication client management method in the client management unit 1402, but the method is not particularly limited. For example, there is a method in which the communication client 1202 registers a callback function together with its own identifier at the time of initialization. According to this method, the client management unit 1402 can notify the target communication client 1202 of information by calling the callback function corresponding to the identifier.

Next, the operation of the data processing system according to the fourth embodiment will be described with reference to FIG. FIG. 15 is a flowchart showing an operation example of the data processing system according to the fourth embodiment. Unless otherwise specified in FIG. 15, the processes of steps S1501 to S1507 and steps S1515 to S1517 are operations in the data processing block (for example, data processing block 1201) on the side that started the transmission. Further, the processing of steps S1508 to S1514 is an operation in the data processing block on the receiving side (for example, the data processing block 1211).

It should be noted that the same reference code of the component used in the following description is used on both the transmitting side and the receiving side. Further, the roles of the transmitting side and the receiving side are provided for convenience of explanation, and all the data processing blocks (1201, 1211) connected to the inter-block bus 110 can be both the transmitting side and the receiving side. .. It should be noted that a data processing block that has only one of the functions of the transmitting side and the function of the receiving side and operates only as the transmitting side or the receiving side may be included.

In step S1501, the communication client 1202 registers its own identifier and the reception request notification method in the client management unit 1402 of the reception control unit 1204. As the reception request notification method, for example, the callback function as described above is used. For example, the C language prototype is as follows. The meaning of the argument will be described later in the description in the process of steps S151 to S1511.
void (* callback) (int chip_id, int client_id, int kind, void * sendBuf, int sendLength, void * respBuf, int respLength)
The process in step S1501 is generally performed at the time of system initialization, and is a process common to all data processing blocks (1201, 1211) regardless of whether it is the transmitting side or the receiving side.

Next, in step S1502, the communication client 1202 issues an instruction to secure the transmission data storage area to the transmission area management unit 1301 of the transmission control unit 1203. At this time, the communication client 1202 passes its own identifier, the destination identifier (data processing block identifier and communication client identifier), the transmission data size, and the reply data size together to the transmission area management unit 1301.

The process in step S1502 will be described in detail with reference to FIGS. 16 to 17. FIG. 16 is a flowchart showing an operation example of the transmission area management unit 1301 in step S1502. In step S1601, the transmission area management unit 1301 acquires the transmission packet area from the memory management unit 803. Since the method of acquiring the area has already been described in the third embodiment, the description thereof will be omitted, but here, the transmission packet area will be described.

In FIG. 17, 1701 represents the format of the transmission packet area. The transmission packet area 1701 is divided into a transmission command header unit 1702 and a transmission data storage area 1710. The transmission command header unit 1702 has a destination processing block identifier 1703, a destination client identifier 1704, a source processing block identifier 1705, a source client identifier 1706, a transmission data storage area size 1707, and a packet type 1708. Further, the transmission command header unit 1702 has a reply packet area start position 1709 and a reply data storage area size 1711.

The size of the transmission command header unit 1702 is Sh and is fixed. The size of the transmission data storage area 1710 is equal to the transmission data size given by the communication client 1202 in step S1502. Therefore, the size of the transmission packet area acquired by the transmission area management unit 1301 in step S1601 is the sum of Sh and the transmission data size. The address returned by the memory management unit 803 is an address for accessing via the inter-block bus 110. This is the result of conversion using the function of the area management table 104 as described in the first embodiment.

Returning to FIG. 16, in step S1602, the transmission area management unit 1301 determines whether or not the transmission packet area has been successfully secured. If the securing of the transmission packet area fails, the failure is notified in step S1608 and the process is completed. When the transmission packet area is successfully secured, the transmission area management unit 1301 acquires the reply packet area from the internal memory management unit 1302 in step S1603.

The format of the reply packet area is shown in 1721 of FIG. The reply packet area 1721 is divided into a reply data header unit 1722 and a reply data storage area 1730. The reply data header unit 1722 has a reply destination processing block identifier 1723, a reply destination client identifier 1724, a reply source processing block identifier 1725, a reply source client identifier 1726, a reply data storage area size 1727, and a packet type 1728. Further, the reply data header unit 1702 has a parent transmission packet area start position 1729. The area 1731 is a reserve area.

The size of the reply data header unit 1722 is Sh and fixed as in the transmission command header unit 1702. The size of the reply data storage area 1730 is equal to the size of the reply data given by the communication client 1202 in step S1502. Therefore, the size of the reply packet area acquired by the transmission area management unit 1301 in step S1603 is the sum of Sh and the reply data size. The reply packet area is secured in the internal memory pool 1205 on the transmitting side. This is because the data is written on the receiving side and the data is read on the transmitting side as described later. The address returned by the internal memory management unit 1302 is a value in the address space inside the data processing block. The method by which the internal memory management unit 1302 secures the memory from the internal memory pool 1205 in step S1603 is not particularly limited as described above.

Returning to FIG. 16 again, in step S1604, the transmission area management unit 1301 determines whether or not the reply packet area has been successfully secured. If the securing of the reply packet area fails, the failure is notified in step S1608 and the process ends. When the reply packet area is successfully secured, the transmission area management unit 1301 writes information to the transmission command header unit 1702 in step S1605. The information to be written is 1703 to 1709 and 1711 shown in FIG. The destination data processing block identifier 1703 and the destination client identifier 1704 are information that identifies the destination. The source data processing block identifier 1705 and the source client identifier 1706 are information that identifies the source. The transmission data storage area size 1707 is the size of the transmission data storage area 1710 in which the communication client 1202 actually writes the transmission data. The reply data storage area size 1711 is the size of the reply data storage area 1730 in which the destination client writes a reply. The packet type 1708 indicates whether this packet is a new transmission packet or a reply packet (reply to a new transmission packet). Here, it is a new transmission packet. Here, 1703 to 1707 and 1711 are all data given by the communication client 1202 in step S1501. On the other hand, the reply packet area start position 1709 represents the beginning of the reply packet area 1721, and the transmission area management unit 1301 dynamically determines when the area is acquired. The reply packet area start position 1709 is a value converted into the address space of the destination data processing block. The transmission area management unit 1301 has a function of converting the address of the internal memory pool 1205 in its own address space into a value for the destination data processing block to access via the inter-block bus 110.

Subsequently, in step S1606, the transmission area management unit 1301 writes information to the reply data header unit 1722. The information to be written is 1723 to 1729 in FIG. The reply destination data processing block identifier 1723 and the reply destination client identifier 1724 are information for specifying the reply destination. In other words, it is equal to the sender's identifier. The reply source data processing block identifier 1725 and the reply source client identifier 1726 are information for identifying the reply source. In other words, it is equal to the destination identifier. The reply data storage area size 1727 represents the size of the reply data storage area 1730. The packet type 1728 is the same as the packet type 1708, but the value here represents a reply packet. All of these 1723 to 1727 are the data given by the communication client 1202 in step S1501. On the other hand, the parent transmission packet area start position 1729 represents the head of the transmission packet area 1701, and the transmission area management unit 1301 dynamically determines when the area is acquired. The parent transmission packet area start position 1729 stores the value for accessing from the address space of the source data processing block as it is.

Next, in step S1607, the transmission area management unit 1301 returns the start address of the transmission data storage area 1710 and completes the process. This completes the description of the process in step S1502 shown in FIG.

Returning to FIG. 15, the processing after step S1503 will be described. In step S1503, the communication client 1202 writes the transmission data to the acquired transmission data storage area. Next, in step S1504, the communication client 1202 instructs the address translation unit 1303 of the transmission control unit 1203 to start transmission. Here, the communication client 1202 passes the data processing block identifier of the transmission destination and the start address of the transmission data storage area together to the address conversion unit 1303.

The address translation unit 1303 translates the start address of the received transmission data storage area into the start address of the transmission packet area. As is clear from FIG. 17, this conversion is performed by subtracting the header size Sh from the address of the transmission data storage area 1710. Then, the address translation unit 1303 sends the transmission packet start address to the transmission notification unit 1305 to relay the transmission start instruction. When the target is a reply packet, the address of the reply data storage area is converted into the address of the reply packet area by exactly the same processing.

Next, in step S1505, the same processing as in step S905 shown in FIG. 9 is performed, and the transmission notification unit 1305 specifies the reception notification unit 107 of the transmission destination. In step S1506, the transmission notification unit 1305 converts the address space of the transmission packet area address. Here, the address space of the data processing block on the transmitting side is converted into an address for the data processing block on the receiving side to access via the inter-block bus 110. The address space conversion is performed by the transmission notification unit 1305 as in the third embodiment.

In step S1507, the transmission notification unit 1305 notifies the transmission destination reception notification unit 107 of the transmission packet address and the reception request. In step S1508, the reception notification unit 107 relays the reception request to the reception management unit 1401. Here, the transmission packet address is also passed to the reception management unit 1401.

In step S1509, the reception management unit 1401 accesses the memory pool 108 in the own data processing block, analyzes the transmission command header unit 1702, and notifies the client management unit 1402. The data to be notified here is divided into transmission-related information and reply-related information. The transmission-related information includes a destination client identifier 1704, a transmission data storage area address 1707, and a size 1710. The reply-related information includes a reply destination data processing block identifier 1705 and a client identifier 1706, and a reply data storage area address 1709 and size 1711. The address of the reply data storage area is obtained by adding Sh to the reply packet area start position 1709.

Here, when the packet type represents a new transmission packet, all the transmission-related information and the reply-related information are notified. Since step S1509 deals with the case of a new transmission packet, all the information will be notified. If the packet type represents a reply packet, only transmission-related information is notified. In this case, the access destination is not the memory pool 108 but the internal memory pool 1205. The header to be analyzed is the reply data header unit 1722. Finally, the client management unit 1402 is notified including the selected data group and the packet type itself.

Next, in step S1510, the client management unit 1402 selects and calls the communication client 1202 corresponding to the received destination client identifier. If the above-mentioned callback function is used, the data processing block identifier of the reply destination is set in chip_id, and the client identifier of the reply destination is set in client_id. Further, the transmission packet type is set in kind, and the address and size of the transmission data storage area are set in sendBuf and sendLength, respectively. Then, the address and size of the reply data storage area are set in respBuf and respLength, respectively. When the packet type is reply packet, chip_id, client_id, respBuf and respLength are not set. Normally, when this callback function is called, the reception request is notified to the corresponding communication client, and at the same time, the data set in the argument is passed. The notification method shown here is an example, and other methods can be used.

The communication client 1202 that received the reception request in step S1510 accesses the memory pool 108 in the own data processing block in step S1511 and reads data from the transmission data storage area. Then, arbitrary processing is performed according to the transmission content. Next, in step S1512, the communication client 1202 writes the execution result and the like in step S1511 to the reply data storage area. The writing destination here is the internal memory pool 1205 on the data processing block side of the transmission source that accesses via the inter-block bus 110.

Next, in step S1513, the communication client 1202 instructs the address translation unit 1303 to start response transmission (transmission of a reply packet to a new transmission packet). Here, the communication client 1202 also passes the address of the reply data storage area to the address conversion unit 1303. In step S1514, the reception request is notified to the reception notification unit 107 in the original transmission packet transmission source by the same processing as in steps S1505 to S1507. Here, the address operation performed by the transmission notification unit 1305 on the reply packet transmission side is the same as that performed by the transmission notification unit 1305 of the transmission packet transmission source in steps S1505 to S1507.

Next, in step S1515, the same processing as in steps S1508 to S1510 is performed, and the communication client 1202 receives the reply packet. Next, in step S1516, the communication client 1202 instructs the transmission area management unit 1301 to release the transmission data storage area. However, the address passed here is the start address of the reply data storage area. It is assumed that the communication client 1202 confirms that the received packet is a reply packet, reads the reply data storage area, and confirms the contents. Based on the result, the communication client 1202 determines that a series of operations associated with the transmission packet initiated by itself has been completed, and instructs the release of the transmission data storage area.

Finally, in step S1517, the transmission area management unit 1301 releases the transmission packet area and the reply packet area. The transmission area management unit 1301 receives the start address of the reply data storage area 1730 as an address. Offsetting from this, the start address of the reply packet area 1721 is obtained, and further, the start address of the transmission packet area 1701 is obtained from the parent transmission packet area start position 1729 existing in the header. Then, the transmission packet area start address and the reply packet area start address are passed to the memory management unit 803 and the internal memory management unit 1302, respectively, to release the area. The release processing method in the memory management unit 803 is the same as the method described in the third embodiment. Further, since it is not necessary to limit the memory release method in the internal memory management unit 1302 as described above, the description thereof is omitted here.

In the description with reference to FIG. 15, a case where one transmission packet is generated and then the reply packet is transmitted to complete one communication context has been described. However, the life cycle of the communication context is arbitrary, and the above-mentioned exchange may be repeated many times without releasing the transmission area. For example, the area may be released by determining the completion of communication by receiving at least one reply after one transmission. Alternatively, after securing the transmission area, the transmission area may be released after receiving one or more transmissions and at least one reply for each transmission. It is clear that the present embodiment can handle such a case. This completes the description of the operation of the data processing system according to the fourth embodiment.

According to the fourth embodiment, in the communication between the data processing blocks including the reply packet for the transmission packet, the reply packet is secured from the memory pool in the source data processing block. As a result, each of the transmission destination and the transmission source can suppress reading via the inter-block bus, so that further improvement in data processing speed is expected.

(Other Embodiments of the present invention)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It is also possible to realize the processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

It should be noted that the above-described embodiments are merely examples of embodiment of the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

101, 801: Transmission activation unit 102, 802: Transmission unit 103, 803: Memory management unit 104: Area management table 105, 109, 805, 806, 807, 1201, 1211: Data processing block 106: Reception unit 107: Reception notification Unit 108: Memory pool 110: Inter-block bus 804: Destination management unit 1001: Transmission client 1003, 1305: Transmission notification unit 1202: Communication client 1203: Transmission control unit 1204: Reception control unit 1205: Internal memory pool 1301: Transmission area Management unit 1302: Internal memory management unit 1303: Address conversion unit 1401: Reception management unit 1402: Client management unit

Claims (6)

A data processing system in which a first data processing block and a second data processing block having a memory for writing data transmitted from the first data processing block are connected via a bus between the blocks. ,
The first data processing block is
A storage means for storing a list of free areas including the start address and size of each free area of the memory included in the second data processing block.
When writing data into said memory, with reference to the start address and size of each empty area in the free space list stored in the storage means based on the size of the data, Oite in the memory A management means for securing a data storage area for writing the data from a free area where the data can be written , and
Via the bus between the blocks, the write data in the data storage area of the memory reserved by the management unit, the second data reception request information and those the data indicating the address of the person the data storage area Has a transmission means to transmit to the processing block
The second data processing block is
If from the first data processing block receives the reception request, based on the information indicating the address of the data storage area to read out the data from the data storage area of the memory, the reception completion of the data after reading have a receiving means for notifying the first data processing block,
When the management means of the first data processing block secures the data storage area, if the size of the free area in which the data can be written matches the size of the data storage area, the free area is used. If it is deleted from the free area list and the size of the free area is larger than the size of the data storage area, the start address and size of the free area in the free area list are updated based on the size of the data storage area. And
When the management means of the first data processing block receives the notification of the completion of reception, if a free area follows the data storage area, the start address of the free area is set to the head of the data storage area. Update to the address, increase the size of the free area by the size of the data storage area, and if the free area does not follow the data storage area, the start address and size of the data storage area are newly freed. A data processing system characterized in that it is registered in the free area list as the start address and size of the area . The transmission means of the first data processing block is
A first transmission means for writing data to the data storage area of the memory secured by the management means, and
After writing data to said data storage area of the first transmission means it is performed, and transmits the received request information and those the data indicating the address of the person the data storage area in the second data processing block data processing system according to claim 1, wherein a second transmission means. The storage means of the first data processing block stores a list of free areas of the memory of each of the plurality of second data processing blocks connected via a bus between the blocks.
Wherein the management unit of the first data processing block, referring to the free space list of the memory of the second data processing block for writing data into said memory, those second data processing block The data processing system according to claim 1 or 2, wherein the data storage area is secured from the memory of the above. Free area list of the memory, according to claim 1 to 3, characterized in that the person said memory indicates a predetermined size start address and size in area units obtained by dividing the area of free space writable data The data processing system according to any one item. Claims 1 to 4 are characterized in that the bus between blocks is a bus in which the speed of reading data via the bus between blocks is slower than the speed of writing data via the bus between blocks. The data processing system according to any one of the above items. Data processing of a data processing system in which a first data processing block and a second data processing block having a memory for writing data transmitted from the first data processing block are connected via a bus between the blocks. It's a method
When the first data processing block writes data to the memory of the second data processing block, the memory stored in the first data processing block based on the size of the data. each free space with reference to the free space list including a start address and size of the data storage area in which the first data processing block writes the data from the free space writable Oite the data in the memory of Secure and
When the first data processing block secures the data storage area, if the size of the free area in which the data can be written matches the size of the data storage area, the free area is listed in the free area list. If the size of the free area is larger than the size of the data storage area, the start address and size of the free area in the free area list are updated based on the size of the data storage area.
To the first data processing block and the second data processing block, through said bus between blocks, writes data to the data storage area of the memory reserved, of those the data storage area transmitted the received request information and those the data indicating the address,
Said second data processing blocks receives the reception request from the first data processing block, Shi read out the data from the data storage area of the memory based on the information indicating the address of the data storage area After reading, the first data processing block is notified of the completion of receiving the data.
When the first data processing block receives the notification of the completion of reception, if a free area follows the data storage area, the start address of the free area is updated to the start address of the data storage area. , The size of the free area is increased by the size of the data storage area, and if the free area does not follow the data storage area, the start address and size of the data storage area are changed to the start address of the new free area. A data processing method characterized in that it is registered in the free area list as a size and a size .

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