JP6789828B2 - Switching power supply - Google Patents

Description

The present invention relates to a switching power supply device, and more particularly to a switching power supply device capable of detecting load power by calculating the excitation energy of an inductor and using it for controlling a switching transistor.

Patent Document 1 describes a method of calculating input power and output power for the purpose of detecting a power abnormality of a switching power supply device. Here, the abnormal power is obtained by taking in the data obtained by A / D converting the input power and the output power, calculating the excitation energy of the inductor of the switching power supply, and comparing the input power and the output power obtained by the calculation. Is determined and fed back to the control of the switching transistor. According to this, by adjusting the switching state by a program based on the comparison result, it can be applied to the protection operation including the normal control.

Japanese Unexamined Patent Publication No. 2001-78443

However, the method of digitizing the input power and output power by A / D conversion and calculating them requires a circuit that executes digital processing such as a processor that performs the main calculation, a memory, and a reference timing signal generator that operates the processor. Therefore, there is a problem that the circuit scale becomes large. In addition, there is a problem that the speed of arithmetic processing becomes high and the current consumption increases. Further, there is a problem that the cost of the switching power supply device becomes high because the processor is used.

An object of the present invention is to provide a switching power supply device including an arithmetic circuit capable of generating a control signal indicating load power with a small circuit scale, low current consumption, and low cost.

In order to achieve the above object, the invention according to claim 1 stores energy in the inductor by a current flowing by an input DC voltage during the ON period of the switching transistor, and the energy released from the inductor during the OFF period of the switching transistor. By rectifying and smoothing the voltage of, the input DC voltage is boosted or stepped down, and the DC voltage is output to the load, and the ON period and / or the OFF period of the switching transistor is controlled according to the state of the load. The switching power supply device includes an arithmetic circuit that calculates a load power to generate a control signal for controlling the ON period and / or the OFF period of the switching transistor, and the arithmetic circuit is the ON period of the switching transistor. The square circuit that generates a squared signal proportional to the square of the period and the period from the current ON start point to the next ON start point of the switching transistor or the period from the current OFF start point to the next OFF start point are shown. A cycle counter that generates a periodic signal proportional to the period, and a division circuit that divides the squared signal generated by the squared circuit and the periodic signal generated by the periodic counter to generate the control signal indicating the load power. It is characterized by having and.

According to the second aspect of the present invention, in the switching power supply device according to the first aspect, the squared circuit is updated every ON period of the switching transistor and charged according to the current flowing through the switching transistor. The first capacitor is characterized in that a squared voltage proportional to the square of the ON period of the switching transistor is generated corresponding to the squared signal.

The invention according to claim 3 is the switching power supply device according to claim 1, wherein the cycle counter is updated every period from the current ON start point of the switching transistor to the next ON start point, or this time. A second capacitor that is updated every period from the OFF start point to the next OFF start point and is charged with a constant current is provided, and a periodic voltage proportional to the period corresponds to the periodic signal in the second capacitor. It is characterized in that it is generated as a thing.

According to a fourth aspect of the present invention, in the switching power supply device according to the second aspect, the squared circuit holds a sample of the squared voltage charged in the first capacitor each time the switching transistor is turned off. A hold circuit and a first voltage / current conversion circuit that converts a voltage held by the first sample hold circuit into a current are provided, and the switching transistor is determined each time the switching transistor is turned off from the first voltage / current conversion circuit. It is characterized in that a squared signal is output.

According to a fifth aspect of the present invention, in the switching power supply device according to the third aspect, the periodic counter holds a sample of the periodic voltage charged in the second capacitor each time the switching transistor is turned off. A hold circuit and a second voltage / current conversion circuit that converts the voltage held by the second sample hold circuit into a current are provided, and the switching transistor is determined each time the switching transistor is turned off from the second voltage / current conversion circuit. It is characterized in that a periodic signal is output.

The invention according to claim 6 is the switching power supply device according to claim 1, wherein the division circuit has the squared signal output from the first voltage / current conversion circuit according to claim 4 and the squared signal according to claim 5. The control signal is generated by inputting the periodic signal output from the second voltage / current conversion circuit of the above and dividing the squared signal by the periodic signal or dividing the periodic signal by the squared signal. It is characterized by that.

According to the present invention, the excitation energy of the inductor is calculated and the load power is detected based on the detection of the ON / OFF cycle of the switching transistor and the detection of the ON period of the switching transistor, so that the integrated circuit that controls the switching power supply device is controlled. Since an analog arithmetic circuit that does not use a processor can be used, the circuit scale of the switching power supply can be reduced and the current consumption can be reduced. At this time, the number of circuits newly added to the conventional switching power supply device is small, and cost reduction can be realized.

It is a block diagram of the block of the step-up switching power supply device of 1st Example. It is a block diagram of the composition circuit of the arithmetic circuit of FIG. It is a block diagram of the square circuit of FIG. It is a concrete circuit diagram of the square circuit of FIG. It is a block diagram of the cycle counter of FIG. It is a concrete circuit diagram of the cycle counter of FIG. It is a concrete circuit diagram of the division circuit of FIG. It is an operation waveform diagram of the square circuit of FIG. It is an operation waveform figure of the period counter of FIG. It is an operation waveform diagram of the division circuit of FIG. It is a block diagram of the block of the step-down switching power supply device of 2nd Example. It is a block diagram of the arithmetic circuit of FIG. It is a block diagram of the square circuit of the arithmetic circuit of FIG. It is a concrete circuit diagram of the square circuit of FIG.

<First Example>
FIG. 1 shows a step-up switching power supply device that performs DC / DC conversion under the control of a PWM / PFM mixed system. Cin is an input capacitor, MN1 is an NMOS switching transistor, L1 is an inductor, Rs1 is a sense resistor that detects the drain current of the switching transistor MN1, D1 is a rectifier diode, and Cout is an output capacitor.

Reference numeral 10 denotes a drive circuit for driving the switching transistor MN1 ON / OFF, which includes a control circuit 11 and an arithmetic circuit 12. The control circuit 11 takes in the control current Io indicating the load power output by the arithmetic circuit 12 and the output voltage Vout of the switching power supply device as feedback signals, and ON timing and OFF timing of the switching transistor MN1, that is, ON duration and OFF continuation. The time is controlled by the PWM and PFM methods, and the timing signal CK1 having a constant pulse width is output for each OFF timing. The arithmetic circuit 12 inputs the timing signal CK1 and the sense voltage Vs1 generated in the sense resistor Rs1 connected to the source of the switching transistor MN1 to calculate the exciting energy of the inductor L1 and outputs the control current Io described above. ..

In this switching power supply device, the voltage of the energy stored in the inductor L1 during the ON period of the switching transistor MN1 is added to the input voltage Vin during the OFF period of the switching transistor MN1, rectified by the diode D1, and smoothed by the output capacitor Cout. And output as the output voltage Vout.

FIG. 2 shows a block diagram of the arithmetic circuit 12. Reference numeral 13 denotes a T-FF circuit, which inputs a timing signal CK1 output from the control circuit 11 and outputs a timing signal CK2 obtained by dividing the timing signal CK1 by 1/2. Reference numeral 14 denotes a two-phase signal generator, which generates two-phase signals φ1 and φ2 having a dead time from the timing signal CK2 output from the T-FF circuit 13. Reference numeral 15 denotes a square circuit, which takes in the sense voltage Vc1 and outputs a current Isq, which is a square signal proportional to the square of the time of the current flowing through the sense resistor Rs1. The squared circuit 15 is reset by the clear signal CLR synchronized with the timing signal CK1. Reference numeral 16 denotes a cycle counter, which captures the timing signals φ1 and φ2 to output a current It, which is a periodic signal indicating the period of the timing signal CK1. Reference numeral 17 denotes a division circuit, in which the current Isq (first current) output from the square circuit 15 is divided by the current It (second current) output from the cycle counter 16 to divide the control signal Io (= Isq / It). To generate.

FIG. 3 shows a block diagram of the squared circuit 15 in the arithmetic circuit 12 of FIG. Reference numeral 151 denotes a voltage / current conversion circuit, which converts a sense voltage Vs1 into a current Icp. Cp is a capacitor (first capacitor) charged by the current Icp, SW1 is a switch for discharging the voltage Vcp charged in the capacitor Cp by the clear signal CLR, and 152 is the voltage Vcp of the capacitor Cp with timing signals φ1 and φ2. The sample hold circuit (first sample hold circuit) that alternately samples and holds, and 153 is a voltage / current conversion circuit (first voltage / current conversion circuit) that converts the output voltage Vsh of the sample hold circuit 152 into the current Isq. FIG. 4 shows a specific circuit of this squared circuit.

In FIG. 4, the voltage / current conversion circuit 151 is connected to the operational amplifier OP1 for inputting the sense voltage Vs1, the NMOS transistor MN2, the resistor R1, and the MOSFET transistors MP2 and MP3 connected to the current mirror so as to input the drain current of the transistor MN2. It is composed of and. The switch SW1 is composed of an NMOS transistor MN3.

Then, the operational amplifier OP1 controls the transistor MN2 so that the voltage generated in the resistor R1 matches the sense voltage Vs1, so that a current Icp proportional to the sense voltage Vs1 flows through the drains of the transistors MP2 and MP3 connected to the current mirror. When this current Icp is charged to the capacitor Cp, the voltage of the capacitor Cp becomes Vcp. This voltage Vcp is a square voltage proportional to the square of the time during which the current Icp is flowing, as described later.

The sample hold circuit 152 is composed of a buffer BF1, switches SW2, SW3, SW4, SW5, and capacitors Cs1 and Cs2. When the timing signal φ1 is “H” and the timing signal φ2 is “L”, the switches SW2 and SW3 are turned on, the switches SW4 and SW5 are turned off, the input voltage Vcp is charged to the capacitor Cs1, and the voltage becomes Vsh1. At the same time, the voltage Vsh2 charged in the capacitor Cs2 is output as the hold voltage Vsh.

When the timing signal φ1 is “L” and the timing signal φ2 is “H”, the switches SW2 and SW3 are turned off, the switches SW4 and SW5 are turned on, the input voltage Vcp is charged to the capacitor Cs2, and the voltage is Vsh2. At the same time, the voltage Vsh1 charged in the capacitor Cs1 is output as the hold voltage Vsh. In this way, the voltages Vsh1 and Vsh2 are alternately taken out as the hold voltage Vsh.

The voltage / current conversion circuit 153 includes an operational amplifier OP2 for inputting the output voltage Vsh of the sample hold circuit 152, an NMOS transistor MN4, a resistor R2, and a epitaxial transistor MP4 connected to a current mirror so as to input the drain current of the transistor MN4. It is composed of MP5 and.

Then, the operational amplifier OP2 controls the transistor MN4 so that the voltage generated in the resistor R2 matches the hold voltage Vsh, so that a current Isq proportional to the hold voltage Vsh flows through the drains of the transistors MP4 and MP5 connected to the current mirror.

FIG. 5 shows a specific circuit of the cycle counter 16 in the arithmetic circuit 12 of FIG. Ia is a current source that outputs a reference current Ia. Reference numerals 161 and 162 are time counters, and the time integration of the reference current Ia is alternately performed according to the time width of “H” of the timing signals φ1 and φ2. Reference numeral 163 is a sample hold circuit (second sample hold circuit) that holds a sample of the output voltage Vct of the time counters 161 and 162. Reference numeral 164 is a voltage / current conversion circuit (second voltage / current conversion circuit) that converts the hold voltage Vts output from the sample hold circuit 163 into a current It. FIG. 6 shows a specific circuit of the cycle counter 16.

In FIG. 6, the time counter 161 is composed of switches SW6, SW7, SW8 and a capacitor Ct1. The time counter 162 includes switches SW9, SW10, SW11 and a capacitor Ct2.

Then, in the time counter 161, when the timing signal φ1 is “H” and the timing signal φ2 is “L”, the switches SW6 and SW7 are turned on to charge the capacitor Ct1 with the reference current Ia, and the charging voltage Vct1 is the voltage Vct1. Output as. When the timing signal φ1 is “L” and the timing signal φ2 is “H”, the switch SW8 is turned on to discharge the voltage Vct1.

On the other hand, in the time counter 162, when the timing signal φ1 is “L” and the timing signal φ2 is “H”, the switches SW9 and SW10 are turned on to charge the capacitor Ct2 with the reference current Ia, and the charging voltage Vct2 is the voltage Vct. Output as. When the timing signal φ1 is “H” and the timing signal φ2 is “L”, the switch SW11 is turned on to discharge the voltage Vct2.

As a result, the voltage Vct1 of the capacitor Ct1 becomes the voltage corresponding to the “H” period of the timing signal φ1, and the voltage Vct2 of the capacitor Ct2 becomes the voltage corresponding to the “H” period of the timing signal φ2, and these alternately become the timing signal CK1. It is taken out as a voltage Vct indicating the period of.

The sample hold circuit 163 is composed of a buffer BF2, switches SW12, SW13, SW14, SW15, and capacitors Cts1 and Cts2. When the timing signal φ1 is “H” and the timing signal φ2 is “L”, the switches SW12 and SW13 are turned on, the switches SW14 and SW15 are turned off, the input voltage Vct is charged to the capacitor Cts1, and the voltage becomes Vts1. At the same time, the voltage Vts2 charged in the capacitor Cts2 is output as the hold voltage Vts.

When the timing signal φ1 is “L” and the timing signal φ2 is “H”, the switches SW12 and SW13 are turned off, the switches SW14 and SW15 are turned on, the input voltage Vct is charged to the capacitor Cts2, and the voltage becomes Vts2. At the same time, the voltage Vts1 charged in the capacitor Cts1 is output as the hold voltage Vts. In this way, the voltages Vts1 and Vts2 are alternately output as the voltage Vts.

The voltage / current conversion circuit 164 includes an operational amplifier OP3 that inputs the output voltage Vts of the sample hold circuit 163, an NMOS transistor MN5, a resistor R3, and current mirror-connected MOSFET transistors MP6 and MP7 that input the drain current of the transistor MN5. It is composed of.

Then, the operational amplifier OP3 controls the transistor MN5 so that the voltage generated in the resistor R3 matches the hold voltage Vts, so that a current It proportional to the sample hold voltage Vts flows through the drains of the transistors MP6 and MP7 connected to the current mirror. ..

FIG. 7 shows a specific circuit of the division circuit 17. The division circuit 17 is a current source Ib of the reference current Ib, current mirror-connected NPN transistors Q1 and Q2 input by the output current Isq of the square circuit 15, and a current mirror connection input by the output current It of the periodic counter 16. NPN transistors Q3 and Q4, NPN transistor Q5 whose base is connected to the collector of transistor Q4, current mirror-connected PNP transistors Q6 and Q7 that mirror the collector current of transistor Q5 to obtain output current Io, and transistor Q2. It includes NPN transistors Q8 and Q9 controlled by a collector current, and NPN transistors Q10 controlled by the transistor Q9 to control the transistor Q5.

Then, the difference between the emitter current of the transistor Q10 and the collector current of the transistor Q4 is input to the base of the transistor Q5 as the current corresponding to Isq / It, and the current corresponding to Isq / It flows through the collectors of the transistors Q6 and Q7.

Next, the operation of the arithmetic circuit 12 will be described. First, FIG. 8 shows a timing chart showing the operation of the squared circuit 15 shown in FIGS. 3 and 4. The sense voltage Vs1 is an excessive drain current Id that flows when the switching transistor MN1 in FIG. 1 is ON, which is converted into a voltage by the sense resistor Rs1, and the current corresponding to this voltage Vs1 is voltage / current conversion. It is output from the circuit 151 and charged to the capacitor Cp. The charging current Icp at this time is expressed by the following equation. Vin is the input voltage of the switching power supply, L1 is the inductance of the inductor L1, and t is the charging time.

During the period when the timing signal φ1 is “H”, the switch SW2 of the sample hold circuit 152 is turned on, and the voltage Vsh1 of the capacitor Cs1 becomes the same as the voltage Vcp of the capacitor Cp.

The voltage Vcp when the switching transistor MN1 is turned on and the capacitor Cp is charged is as shown in the following equation in proportion to the square of the charging time t, and at the same time becomes the voltage Vsh1.

The timing signal CK1 becomes "H" and the timing signal φ1 becomes "L" at the timing when the switching transistor MN1 is turned off, and is held by the charging voltage Vsh1 of the capacitor Cp immediately before the switching transistor MN1 is turned off. This voltage Vsh1 Is the output voltage Vsh of the sample hold circuit 152. Assuming that the time when the switching transistor MN1 is on is ton, the voltage Vsh1 is as follows.

On the other hand, since the clear signal CLR is synchronized with the timing signal CK1, when the clear signal CLR becomes “H”, the transistor MN3 which is the switch SW1 is turned on to discharge the charge of the capacitor Cp and drop the voltage Vcp to the ground level. Further, since the timing signal φ2 becomes “H”, the voltage Vsh2 of the capacitor Cs2 of the sample hold circuit 152 becomes the current voltage Vcp of the capacitor Cp.

The operation in which the switching transistor MN1 is turned on and the capacitor Cp is charged during the period when the timing signal φ2 is “H” is the same as when the timing signal φ1 is “H”. Then, when the timing signal CK1 becomes “H”, the timing signal φ2 becomes “L”, the voltage Vsh2 is held by the charging voltage Vcp of the capacitor Cp immediately before the switching transistor MN1 is turned off, and the timing signal φ1 becomes “H”. Then, the output voltage Vsh of the sample hold circuit 152 becomes the voltage Vsh2.

Since the timing signal φ1 becomes “H” again, the voltage of the capacitor Cp and the voltage of the voltage Vsh1 become equal. Hereinafter, since the same operation is repeated every time the switching transistor MN1 is turned on, the voltage / current conversion circuit 153 outputs a current Isq obtained by converting the output voltage Vsh of the sample hold circuit 152, which is determined each time, into a current.

Next, a timing chart showing the operation of the cycle counter 16 is shown in FIG. The relationship between “H” / “L” of the timing signals CK1 and CK2 and the timing signals φ1 and the timing signal φ2 is the same as in FIG. Since the timing signal CK1 rises to "H" when the switching transistor MN1 switches from ON to OFF, the period of the timing signal CK1 can be obtained by counting the time Tsw of the interval at which the timing signal CK1 rises to "H". ..

In FIG. 6, which shows a specific circuit of the cycle counter 2, the sample hold circuit 163 operates in the same manner as the sample hold circuit 152 of the square circuit 15 described above.

In FIG. 6, first, when the timing signal φ1 is “H”, the voltage Vct1 of the capacitor Ctl of the time counter 161 is constantly charged by the current Ia of the current source Ia.

The voltage Vct1 of the capacitor Ctl becomes the input voltage Vct of the sample hold circuit 163, and the voltage Vts1 of the capacitor Cts1 of the sample hold circuit 163 becomes equal to the voltage Vctl of the capacitor Ct1.

When the timing signal CK1 becomes “H” again, the timing signal φ1 becomes “L” and the timing signal φ2 becomes “H”. As a result, in the sample hold circuit 163, the voltage Vts1 holds the voltage immediately before the timing signal CK1 becomes “H”, that is, the voltage at the time when one cycle Tsw has elapsed. This voltage Vts1 becomes the output voltage Vts of the sample hold circuit 163.

On the other hand, when the timing signal φ2 becomes “H”, the electric charge of the capacitor Ctl is discharged, and the capacitor Ct2 is constantly charged by the current Ia. The voltage Vct at this time is the voltage Vct2 of the capacitor Ct2 of the time counter 162, and this voltage Vct2 becomes the voltage Vts2 of the capacitor Cts2 of the sample hold circuit 163. Further, when the timing signal CK1 becomes “H” again, the timing signal φ1 becomes “H” and the timing signal φ2 becomes “L”. Therefore, the voltage Vct2 at the time when one cycle Tsw elapses is held and becomes the voltage Vts2, and the sample is held. The output voltage Vts of the circuit 163 is obtained.

Hereinafter, the same operation is repeated every time the switching transistor MN1 is turned off, and the voltage / current conversion circuit 164 outputs a current It that is obtained by converting the output voltage Vts of the sample hold circuit 163 determined each time into a current.

As described above, the currents Isq and It obtained by converting the voltages Vsh and Vts of the square circuit 15 and the sample hold circuits 152 and 163 of the cycle counter 16 into currents are as follows. Ct = Ct1 = Ct2.

In the division circuit 17, the current Isq and the current It are divided, and the current Io is finally output from the arithmetic circuit 12.

Next, the relationship between the exciting energy PW generated in the inductor L1 when the switching transistor MN1 is turned on and the current Io output from the arithmetic circuit 12 will be described.

Assuming that the peak current of the inductor L1 when the switching transistor MN1 is ON is Ipk, the exciting energy PW is expressed as follows.

となるので、演算回路１２の出力電流Ｉｏは、式（８）から、

となる。ただし、

である。 On the other hand, the relationship between ton and Ipk is

Therefore, the output current Io of the arithmetic circuit 12 is calculated from the equation (8).

Will be. However,

Is.

That is, looking at the equations (11) and (12), since α is a constant, the output current Io of the arithmetic circuit 12 equivalently indicates the exciting energy PW of the equation (9) generated in the inductor L1. It becomes. As a result, as in the switching power supply shown in FIG. 1, the excitation energy of the inductor L1 is supplied to the load of the switching power supply by inputting the output current Io of the arithmetic circuit 12 to the control circuit 11. Can be fed back for the control of the switching transistor MN1 as a signal indicating. As a result, the input power of the switching power supply device can be controlled in a well-balanced manner according to the output power, which can be useful for improving the conversion efficiency.

<Second Example>
FIG. 11 shows a step-down switching power supply device that controls DC / DC conversion by a PWM / PFM mixed method. The same reference numerals are given to the same step-up switching power supply devices described in FIG. MP1 is a MOSFET switching transistor, L2 is an inductor, Rs2 is a sense resistor that detects the drain current of the switching transistor MP1, and D2 is a rectifier diode.

Reference numeral 20 denotes a drive circuit for driving the switching transistor MP1 ON / OFF, which includes a control circuit 21 and an arithmetic circuit 22. The control circuit 21 takes in the control current Io indicating the load power output by the arithmetic circuit 22 and the output voltage Vout of the switching power supply device as feedback signals, and determines the ON duration and OFF duration of the switching transistor MP1 by a PWM and PFM method. The timing signal CK1 having a constant pulse width is output at each OFF timing. The arithmetic circuit 22 inputs the timing signal CK1 and the sense voltage Vs2 generated in the sense resistor Rs2 connected to the source of the switching transistor MN1 to calculate the exciting energy of the inductor L2, and outputs the control current Io.

In this switching power supply device, the voltage of the energy stored in the inductor L2 during the ON period of the switching transistor MP1 is rectified by the diode D2 during the OFF period of the switching transistor MP1, smoothed by the output capacitor Cout, and the input voltage Vin is stepped down. Output as the output voltage Vout.

FIG. 12 shows a block diagram of the arithmetic circuit 22. The same elements as those in the arithmetic circuit 12 described with reference to FIG. 2 are designated by the same reference numerals, and duplicate description will be omitted. Reference numeral 25 denotes a square circuit, which inputs a sense voltage Vs2 and outputs a current Isq corresponding to the square of the ON period of the switching transistor MP1 as in the squared circuit 15.

FIG. 13 shows a block diagram of the square circuit 25 in the arithmetic circuit 22 of FIG. The same elements as those in the square circuit 15 described with reference to FIG. 3 are designated by the same reference numerals, and duplicate description will be omitted. FIG. 14 shows a specific circuit of the squared circuit 25. Reference numeral 251 denotes a voltage / current conversion circuit, which converts a sense voltage Vs2 into a current. The voltage / current conversion circuit 251 is composed of an operational amplifier OP4 for inputting a sense voltage Vs2, a MOSFET transistor MP8, and a resistor R4.

Then, the operational amplifier OP4 controls the transistor MP8 so that the voltage generated in the resistor R4 matches the sense voltage Vs2, so that a current proportional to the sense voltage Vs2 flows through the drain of the transistor MP8, and the square voltage Vcp flows through the capacitor Cp. Charged as.

As described above, the switching power supply device of the second embodiment differs from the switching power supply device of the first embodiment only in the configuration of the squared circuit 25 of the arithmetic circuit 22, and is similar to the switching power supply device of the first embodiment. By operating, the current Io indicating the exciting energy PW of the inductor L2 can be fed back to the control state of the switching transistor MP1 as a control signal indicating the load power. As a result, the input power of the switching power supply device can be controlled in a well-balanced manner according to the output power, which can be useful for improving the conversion efficiency.

<Other Examples>
In the above embodiment, the case where the arithmetic circuits 12 and 22 are applied to a PWM / PFM mixed type switching power supply device in which both the ON period and the OFF period of the switching transistor can be controlled has been described, but only the PWM method is used. It can be similarly applied to a switching power supply device to be controlled, a switching power supply device to be controlled only by the PFM method, a non-isolated converter, and an isolated converter. In a switching power supply device controlled only by the PWM method, the current It is a constant value, and in a switching power supply device controlled only by the PFM method, the current Isq is a constant value. Further, in the above-described embodiment, the cycle counter 16 updates and detects the period from the current OFF start point to the next OFF start point of the switching transistors MN1 and MP1, but the switching transistor is not limited to this. The period from the current ON start point of the MN1 and MP1 to the next ON start point may be updated and detected. Further, the division circuit 17 performs the calculation of Isq / It in the above-described embodiment, but the calculation is not limited to this, and the calculation of It / Isq may be performed. In this case, the signals Isq and It input in FIG. 7 may be exchanged, and the control circuits 11 and 21 may perform control with the reciprocal of the signals.

10: Drive circuit, 11: Control circuit, 12: Arithmetic circuit, 13: T-FF circuit, 14: 2-phase signal generator, 15: Square circuit, 16: Period counter, 17: Dividing circuit, 20: Drive circuit, 21: Control circuit, 22: Arithmetic circuit, 25: Square circuit 151: Voltage / current conversion circuit, 152: Sample hold circuit, 153: Voltage / current conversion circuit 161, 162: Time counter, 163: Sample hold circuit, 164: Voltage / current conversion circuit, 251: Voltage / current conversion circuit

Claims (6)

Energy is stored in the inductor by the current flowing by the input DC voltage during the ON period of the switching transistor, and the input DC voltage is boosted by rectifying and smoothing the voltage of the energy released from the inductor during the OFF period of the switching transistor. Alternatively, in a switching power supply device that outputs a stepped-down DC voltage to a load and controls the ON period and / or the OFF period of the switching transistor according to the state of the load.
A calculation circuit for calculating the load power and generating a control signal for controlling the ON period and / or the OFF period of the switching transistor is provided.
The arithmetic circuit includes a squared circuit that generates a squared signal proportional to the square of the ON period of the switching transistor, and a period from the current ON start point of the switching transistor to the next ON start point or the current OFF start point. The load is obtained by dividing a cycle counter that generates a cycle signal proportional to the cycle indicating the period from to the next OFF start point, the square signal generated by the square circuit, and the cycle signal generated by the cycle counter. A switching power supply device including a division circuit for generating the control signal indicating power. In the switching power supply device according to claim 1,
The squared circuit includes a first capacitor that is updated every ON period of the switching transistor and charged according to the current flowing through the switching transistor, and the first capacitor is used to square the ON period of the switching transistor. A switching power supply device, characterized in that a proportional squared voltage is generated as corresponding to the squared signal. In the switching power supply device according to claim 1,
The period counter is updated every period from the current ON start point of the switching transistor to the next ON start point, or is updated every period from the current OFF start point to the next OFF start point. A switching power supply device comprising a second capacitor charged with an electric current, wherein a periodic voltage proportional to the period is generated in the second capacitor as corresponding to the periodic signal. In the switching power supply device according to claim 2,
The squared circuit has a first sample hold circuit that sample-holds the squared voltage charged in the first capacitor each time the switching transistor is turned off, and converts the voltage held by the first sample hold circuit into a current. A switching power supply device including a first voltage / current conversion circuit, and outputting the squared signal determined each time the switching transistor is turned off from the first voltage / current conversion circuit. In the switching power supply device according to claim 3,
The cycle counter converts the periodic voltage charged in the second capacitor into a current by a second sample hold circuit that holds a sample each time the switching transistor is turned off and a voltage held by the second sample hold circuit. A switching power supply device including a second voltage / current conversion circuit that outputs a periodic signal determined each time the switching transistor is turned off from the second voltage / current conversion circuit. In the switching power supply device according to claim 1,
The division circuit inputs the squared signal output from the first voltage / current conversion circuit according to claim 4 and the periodic signal output from the second voltage / current conversion circuit according to claim 5. , The switching power supply device, characterized in that the control signal is generated by dividing the squared signal by the periodic signal or dividing the periodic signal by the squared signal.

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