JP6783839B2 - Photoelectric conversion device and imaging system - Google Patents

Description

The present invention relates to a photoelectric conversion device and an imaging system.

As a photoelectric conversion device used for an image sensor of a camera or the like, a MIS type (Metal Insulator Semiconductor) photoelectric conversion device has been proposed. In the photoelectric conversion device described in FIG. 1 of Patent Document 1, a transparent electrode is arranged above the photoelectric conversion film, and a pixel electrode is arranged below the photoelectric conversion film. An insulating film is arranged between the photoelectric conversion film and the pixel electrode. According to Patent Document 1, it is described that noise can be reduced because correlated double sampling (Correlated Double Sampling) is possible by such a configuration.

Patent Document 1 states that a compound semiconductor, a silicon crystal, an ionic bond crystal, or the like can be used as the photoelectric conversion film. Patent Document 2 describes that a material having a large light absorption coefficient, such as amorphous silicon or an organic material, is used for the photoelectric conversion film. According to Patent Document 2, high sensitivity can be achieved by using these materials.

WO2012 / 004923 Japanese Unexamined Patent Publication No. 2011-228621

The photoelectric conversion device disclosed in Patent Document 1 or Patent Document 2 needs further study from the viewpoint of noise reduction. This is because the photoelectric conversion film disclosed in Patent Document 1 or Patent Document 2 contains many defect levels.

For example, the dark current generated by the defect level can cause noise. Alternatively, the presence of defect levels makes depletion difficult. Therefore, when the signal from the photoelectric conversion film is read out, the photoelectric conversion film is not sufficiently depleted, and as a result, the electric charge not discharged from the photoelectric conversion film may remain on the photoelectric conversion film. If charges remain on the photoelectric conversion film when reading a signal from the photoelectric conversion film, noise may occur in the output signal.

In view of such problems, it is an object of the present invention to make it possible to reduce noise in a photoelectric conversion device.

The photoelectric conversion device of the embodiment according to one aspect of the present invention is a photoelectric conversion device including a pixel including a photoelectric conversion unit and an amplification unit that outputs a signal generated by the photoelectric conversion unit. The conversion unit is between the first electrode, the second electrode, the photoelectric conversion layer arranged between the first electrode and the second electrode, and the photoelectric conversion layer and the second electrode. It is characterized in that the photoelectric conversion layer contains quantum dots, including an insulating layer arranged in the above.

The photoelectric conversion device of the embodiment according to another aspect of the present invention is a photoelectric conversion device including a pixel including a photoelectric conversion unit and an amplification unit that outputs a signal generated by the photoelectric conversion unit. The conversion unit is between the first electrode, the second electrode, the photoelectric conversion layer arranged between the first electrode and the second electrode, and the photoelectric conversion layer and the second electrode. The photoelectric conversion layer includes a first member and a plurality of particles having a particle size in the range of 1 nm to 20 nm arranged in the first member. , Characterized by.

According to the present invention, noise can be reduced.

The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows typically the whole structure of the photoelectric conversion apparatus. The figure which shows the equivalent circuit of the column circuit of a photoelectric conversion device. The figure which shows typically the planar structure of the photoelectric conversion device. The figure which shows typically the cross-sectional structure of a photoelectric conversion device. The figure which shows typically the potential of the photoelectric conversion part of a photoelectric conversion device. The figure which shows the timing chart of the drive signal used for a photoelectric conversion device. The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows typically the whole structure of the photoelectric conversion apparatus. The figure which shows typically the planar structure of the photoelectric conversion device. The figure which shows typically the cross-sectional structure of a photoelectric conversion device. The figure which shows typically the potential of the photoelectric conversion part of a photoelectric conversion device. The figure which shows the timing chart of the drive signal used for a photoelectric conversion device. The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows the timing chart of the drive signal used for a photoelectric conversion device. The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows the timing chart of the drive signal used for a photoelectric conversion device. The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows the timing chart of the drive signal used for a photoelectric conversion device. The figure which shows typically the structure of the pixel of the photoelectric conversion apparatus. The figure which shows typically the structure of the photoelectric conversion layer. The block diagram of the Example of a photoelectric conversion system.

One embodiment of the present invention is a photoelectric conversion device. The pixels included in the photoelectric conversion device include a photoelectric conversion unit and an amplification unit that amplifies a signal generated by the photoelectric conversion unit. The photoelectric conversion device may include a plurality of pixels. Such a photoelectric conversion device is, for example, an image sensor. Alternatively, the photoelectric conversion device may include only one pixel. Such a photoelectric conversion device is, for example, a photodetector. FIG. 1 illustrates a pixel 100, a photoelectric conversion unit 101, and an amplification transistor 104.

The photoelectric conversion unit is arranged between the first electrode, the second electrode, the photoelectric conversion layer arranged between the first electrode and the second electrode, and the photoelectric conversion layer and the second electrode. Including an insulating layer. With such a configuration, the photoelectric conversion unit can accumulate the electric charge generated by the incident light as a signal electric charge. Further, the signal from the photoelectric conversion unit can be read out by controlling the voltage supplied to the pixel circuit including the photoelectric conversion unit. In FIG. 1, the first electrode 201, the photoelectric conversion layer 205, the insulating layer 207, and the second electrode 209 are exemplified.

The photoelectric conversion layer contains quantum dots. FIG. 21 illustrates the quantum dot 10. Quantum dots are, for example, particles having a particle size in the range of 1 nm to 20 nm. In some embodiments, the photoelectric conversion layer comprises a member made of a material different from the quantum dots. Then, the quantum dots are dispersed in the member. In some other embodiments, the photoelectric conversion layer comprises a coating layer that covers the quantum dots. In some other embodiments, the photoelectric conversion layer includes an embedding layer for embedding quantum dots. FIG. 21 illustrates a member 11, a coating layer 12, and an embedded layer 14 made of a material different from the quantum dots. These are collectively called a member on which quantum dots are arranged.

According to such a configuration, the electric charge generated by the photoelectric conversion is accumulated in the photoelectric conversion layer. Then, when reading the signal, the electric charge accumulated through the plurality of quantum dots can be discharged to the first electrode.

According to the configuration in which the photoelectric conversion layer includes quantum dots, the defect level of the photoelectric conversion layer can be reduced. This is because the size of the quantum dot is small, so that the lattice defects inside the quantum dot can be reduced. As a result, noise can be reduced.

In some embodiments, the material of the quantum dots is at least one of the Group IV elements such as tin (Sn), lead (Pb) and copper (Cu), and oxygen (O), sulfur (S), selenium ( It is a compound containing at least one of the elements of Group VI, such as Se) and tellurium (Te). For example, the material of the quantum dots may be PbS, PbSe, PbTe, or CuO. In the present specification, these compounds are referred to as group IV-VI compounds.

In some embodiments, the material of the quantum dots is at least one of the group III elements such as boron (B), aluminum (Al), gallium (Ga), indium (In) and thallium (Tl), and nitrogen ( It is a compound containing at least one of the group V elements such as N), phosphorus (P), arsenic and antimony (Sb). For example, the material of the quantum dots may be BN, GaAs, GaP, AlSb, InSb, InAs, or InGaAs. In the present specification, these compounds are referred to as Group III-V compounds.

In some embodiments, the material of the quantum dots is at least one of the Group II elements such as zinc (Zn), cadmium (Cd) and mercury (Hg), and oxygen (O), sulfur (S), selenium (S). A compound containing at least one of the VI group elements such as Se) and tellurium (Te). For example, the material of the quantum dots may be CdSe, CdTe, ZnS, or HgTe. These compounds are called II-VI group compounds.

In some embodiments, Group IV elements such as carbon (C), silicon (Si), and germanium (Ge) are used as the material for the quantum dots.

As the material of the quantum dots, PbS, PbSe, PbTe, CdS, CdSe, CdTe, C, Si, Ge and the like are suitable. According to such a configuration, noise can be further reduced.

The material of the member on which the quantum dots are arranged is a semiconductor material, an insulator material, or a conductive material. Specifically, the materials of the members on which the quantum dots are arranged are PbSO4, PbO, PbSeO4, SiO, SiN, SiON, In2O3, sulfur (S), compounds containing sulfur (S), carbon (C), and carbon. It can be selected from compounds containing (C) and the like. According to such a configuration, the sensitivity can be improved. In addition, the material of the member on which the quantum dots are arranged can be selected from AlAs, AlGaAs, AlGaAs, GaAs, GaSb, AlSb and the like. Alternatively, intrinsic silicon (Si) or silicon (Si) doped with low-concentration impurities may be used for the member in which the quantum dots are dispersed. Alternatively, an organic resin in which quantum dots are dispersed may be used.

The bandgap of the member on which the quantum dots are arranged is different from the bandgap of the quantum dots. For example, the bandgap of the member is wider than the bandgap of the quantum dots. According to such a configuration, a potential for confining the carriers generated by the photoelectric conversion in the quantum dots is formed.

Also, quantum dots can have a larger bandgap than the bandgap of a bulk structure made of the same material. Therefore, it is preferable that a material having a bandgap equal to or smaller than the bandgap of silicon (Si) is used for the quantum dots. Specifically, it is preferable that the band gap is 1.12 eV (electron volt) or less. For example, PbS, PbSe, PbTe, C, Si, Ge and the like are suitable. According to such a configuration, the sensitivity to long wavelength light such as red light can be improved.

In the present specification, the band gap of a certain material means the band gap when the bulk structure is formed by using the material alone. An example of a method for measuring the band gap of a material used for quantum dots will be described. First, the materials used for quantum dots are specified. Next, a sample is prepared from the same material as the specified material, and the wavelength of light that can be absorbed by the sample is measured. The longest wavelength L of the absorbed light is converted into energy E using E = h / L. h is Planck's constant. The obtained energy E is the band gap.

In addition, a shell may be formed around the quantum dots. Thereby, the quantum efficiency can be improved. Since the size of a quantum dot is small, more than half of the atoms contained in the quantum dot may be arranged on the surface of the quantum dot. Dangling bonds of atoms placed on the surface can form defect levels. Therefore, many defect levels can occur on the surface of quantum dots. If there are many defect levels, electron-hole recombination is likely to occur, and as a result, quantum efficiency may decrease. By forming a shell around the quantum dots, dangling bonds on the surface of the quantum dots can be reduced. Therefore, the quantum efficiency can be improved.

For example, a core-shell structure of a CdSe core and a ZnS shell may be formed by coating the surface of hydrophobic CdSe quantum dots with ZnS. Alternatively, the surface of the hydrophilic CdTe quantum dots may be coated with a thiol compound. By these methods, the electrons in the excitons generated when light is absorbed are confined in or near the core, and are less affected by the surface.

Further, it is preferable that the lattice constant of the core and the lattice constant of the shell are close to each other. Specifically, the ratio of the lattice constants of the two may be included in the range of 0.9 to 1.1. According to such a configuration, lattice defects can be reduced, and as a result, noise can be reduced.

In addition, quantum dots may have surface atoms that can serve as coordination sites. Since such quantum dots have high reactivity, aggregation is likely to occur. In order to stabilize the surface of the quantum dot, the surface of the quantum dot may be capped with a capping member. According to such a configuration, it is possible to prevent the aggregation of quantum dots. As a result, sensitivity is improved.

As the capping member, a base covalently bonded to a metal atom of a quantum dot, an organic polymer, or the like is used. For example, an organic molecule having an aliphatic hydrocarbon group having a linear structure or a branched structure having 2 to 30 carbon atoms, preferably 4 to 20 carbon atoms, and more preferably 6 to 18 carbon atoms. Is used. The capping member may have a functional group such as a carboxyl group, an amino group, an amide group, a nitrile group, a hydroxyl group, an ether group, a carbonyl group, a sulfonyl group, a phosphonyl group or a mercapto group. According to these functional groups, the coordination of the capping member can be easily controlled. The capping member may have a functional group different from the functional group for coordination.

Further, a quantum dot having a particle size in the range of 1 nm to 20 nm can quantumly confine an electron inside the quantum dot. Due to this quantum confinement effect, the quantum dots have a bandgap depending on the particle size. Therefore, according to such a configuration, the wavelength of the light to be detected can be selected according to the size of the quantum dots.

Hereinafter, examples of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the examples described below. An embodiment of the present invention is also a modification in which a part of the configuration of the embodiment described below is modified without exceeding the gist of the present invention. Further, an example in which a part of the configuration of any of the following examples is added to another example or an example in which a part of the configuration of another example is replaced is also an example of the present invention.

FIG. 1A schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. The pixel 100 includes a photoelectric conversion unit 101, a reset transistor 102, a first capacitance 103, an amplification transistor 104, and a selection transistor 105. Although FIG. 1A shows only one pixel 100, the photoelectric conversion device of this embodiment includes a plurality of pixels 100. Further, in FIG. 1A, the cross-sectional structure of the photoelectric conversion unit 101 is schematically shown.

The photoelectric conversion unit 101 includes a first electrode 201, a blocking layer 203, a photoelectric conversion layer 205, an insulating layer 207, and a second electrode 209. The first electrode 201 is included in the node A of FIG. 1 (a). The second electrode 209 is included in the node B of FIG. 1 (a). The first electrode 201 is connected to the voltage supply unit 110. The voltage supply unit 110 supplies a plurality of voltages Vs to the first electrode 209 of the photoelectric conversion unit 101. With such a configuration, the signal charge can be accumulated in the photoelectric conversion unit 101 and the signal charge can be discharged from the photoelectric conversion unit 101. The signal charge is discharged in order to read the signal generated by the photoelectric conversion unit 101.

The voltage supply unit 110 supplies at least a first voltage Vs1 and a second voltage Vs2 different from the first voltage Vs1 to the first electrode 201 of the photoelectric conversion unit 101. When the signal charge is Hall, the second voltage Vs2 is lower than the first voltage Vs1. When the signal charge is Hall, for example, the first voltage Vs1 is 5V and the second voltage Vs2 is 0V. When the signal charge is an electron, the second voltage Vs2 is higher than the first voltage Vs1. When the signal charge is an electron, for example, the first voltage Vs1 is 0V and the second voltage Vs2 is 5V. In this specification, unless otherwise specified, the voltage of the grounded node is set to 0V as a reference.

Node B in FIG. 1A includes a gate for the amplification transistor 104. The amplification transistor 104 is an amplification unit, and the gate of the amplification transistor 104 is an input node of the amplification unit. That is, the second electrode 209 of the photoelectric conversion unit 101 is electrically connected to the amplification unit. With such a configuration, the amplification unit can amplify and output the signal generated by the photoelectric conversion unit 101.

The second electrode 209 is electrically connected to the first terminal of the first capacitance 103. In this embodiment, the first terminal of the first capacitance 103 is included in the node B. That is, the second electrode 209 and the first terminal of the first capacitance 103 are short-circuited. The second terminal of the first capacitance 103 is included in the node C. The second terminal is capacitively coupled to the first terminal. From another point of view, the node C is capacitively coupled to the node B via the first capacitance 103. A predetermined voltage is supplied to the second terminal (node C) of the first capacitance 103. In this embodiment, the second terminal (node C) of the first capacitance 103 is grounded. That is, a voltage of 0 V is supplied to the second terminal of the first capacity 103.

The drain of the reset transistor 102 is connected to the node to which the reset voltage Vres is supplied. The source of the reset transistor 102 is connected to the second electrode 209 of the photoelectric conversion unit 101 and the gate of the amplification transistor 104. With such a configuration, the reset transistor 102 can reset the voltage of the node B to the reset voltage Vres. That is, the reset transistor 102 is a reset unit that supplies the reset voltage Vres to the second electrode 209. When the reset transistor 102 is turned off, the node B including the second electrode 209 of the photoelectric conversion unit 101 becomes electrically floating.

In this embodiment, by controlling the magnitude relationship between the voltage Vs supplied to the first electrode 201 of the photoelectric conversion unit 101 and the reset voltage Vres, the signal charge is accumulated in the photoelectric conversion unit 101 and the photoelectric conversion is performed. The signal charge from the unit 101 is discharged. The reset voltage Vres is an intermediate value between the first voltage Vs1 and the second voltage Vs2. For example, when the signal charge is Hall, the reset voltage Vres is lower than the first voltage Vs1 and higher than the second voltage Vs2. When the signal charge is electron, the reset voltage Vres is higher than the first voltage Vs1 and lower than the second voltage Vs2. The reset voltage Vres of this embodiment is 3.3V. This reset voltage Vres is lower than the power supply voltage and higher than the voltage supplied to the grounded node.

The drain of the amplification transistor 104 is connected to the node to which the power supply voltage is supplied. The source of the amplification transistor 104 is connected to the output line 130 via the selection transistor 105. A current source 160 is connected to the output line 130. The amplification transistor 104 and the current source 160 form a source follower circuit, and output the signal generated by the photoelectric conversion unit 101 to the output line 130. A column circuit 140 is further connected to the output line 130. The signal from the pixel 100 output to the output line 130 is input to the column circuit 140.

1 (b) and 1 (c) show an example of an equivalent circuit diagram of the photoelectric conversion unit 101. The photoelectric conversion unit 101 of this embodiment includes a photoelectric conversion layer configured to accumulate signal charges and an insulating layer. Therefore, the photoelectric conversion unit 101 includes a capacitance component between the first electrode 201 and the second electrode 209. The equivalent circuit of FIGS. 1B and 1C shows this capacitance component as a second capacitance 111 arranged between the first electrode 201 and the second electrode 209 of the photoelectric conversion unit 101. Note that FIG. 1B shows an example in which the photoelectric conversion unit 101 includes a blocking layer. Therefore, the blocking layer and the photoelectric conversion layer are indicated by the circuit symbol of the diode 112. FIG. 1C shows an example in which the photoelectric conversion layer does not include a blocking layer. Therefore, the photoelectric conversion layer is indicated by the circuit symbol of the resistor 113. The structure of the photoelectric conversion unit 101 will be described later.

FIG. 2 is a diagram schematically showing the entire circuit configuration of the photoelectric conversion device of this embodiment. The parts having the same functions as those in FIG. 1 are designated by the same reference numerals.

FIG. 2 shows 16 pixels 100 arranged in a matrix of 4 rows and 4 columns. A plurality of pixels 100 included in one row are connected to one output line 130. The row drive circuit 120 supplies the drive signal pRES and the drive signal pSEL to the pixel 100. The drive signal pRES is supplied to the gate of the reset transistor 102. The drive signal pSEL is supplied to the gate of the selection transistor 105. The reset transistor 102 and the selection transistor 105 are controlled by these drive signals. A plurality of pixels 100 included in one line are connected to a common drive signal line. The drive signal line is a wiring for transmitting the above-mentioned drive signal pRES, drive signal pSEL, and the like. In FIG. 2, in order to distinguish the drive signals supplied to different lines, reference numerals representing the lines such as (n) and (n + 1) are added. The same applies to other drawings.

FIG. 2 schematically shows the planar structure of the first electrode 201 of the photoelectric conversion unit 101. As shown in FIG. 2, the photoelectric conversion unit 101 of the plurality of pixels 100 included in one row includes a common first electrode 201. As described above, the voltage supply unit 110 supplies the voltage Vs to the first electrode 201. In this embodiment, the first electrode 201 is arranged for each row. Therefore, the row drive circuit 120 selects the row to which the voltage Vs is supplied from the voltage supply unit 110. In addition, in order to distinguish the voltage Vs supplied to different rows, symbols representing the rows such as (n) and (n + 1) are added.

With the configuration described above, in this embodiment, a plurality of pixels 100 can be driven row by row.

Each output line 130 is connected to a column circuit 140. The column drive circuit 150 drives the column circuit 140 for each row. Specifically, the column drive circuit 150 supplies the drive signal CSEL to the plurality of column circuits 140. In addition, in order to distinguish the drive signals supplied to different columns, reference numerals representing the columns such as (m) and (m + 1) are added. The same applies to other drawings. With such a configuration, the signals read in parallel for each row can be sequentially output to the output unit 170.

The column circuit 140 will be described in detail. FIG. 3 shows an equivalent circuit of the column circuit 140 in the m-th column and the m + 1-th column. The row circuits 140 in the other rows are not shown.

The signal of the output line 130 is amplified by the column amplifier 301. The output node of the column amplifier 301 is connected to the capacitive CTS via the S / H switch 303. Further, the output node of the column amplifier 301 is connected to the capacitance CTN via the S / H switch 305. The S / H switch 303 and the S / H switch 305 are controlled by the drive signal pTS and the drive signal pTN, respectively. With such a configuration, a noise signal including reset noise from the pixel 100 and an optical signal can be held. Therefore, the photoelectric conversion device of this embodiment can perform correlated double sampling.

The capacitance CTS is connected to the horizontal output line 311 via the horizontal transfer switch 307. The capacitance CTN is connected to the horizontal output line 313 via the horizontal transfer switch 309. The horizontal transfer switches 307 and 309 are controlled by the drive signal CSEL from the column drive circuit 150.

Both the horizontal output line 311 and the horizontal output line 313 are connected to the output unit 170. The output unit 170 outputs the difference between the signal of the horizontal output line 311 and the signal of the horizontal output line 313 to the analog-digital conversion unit 180. The analog-to-digital conversion unit 180 converts the input analog signal into a digital signal.

The column circuit 140 may be an analog-to-digital conversion circuit. In this case, the analog-to-digital conversion circuit has a holding unit that holds a digital signal such as a memory or a counter. The noise signal and the optical signal are converted into digital signals and held in the holding unit.

Next, the planar structure and the cross-sectional structure of the photoelectric conversion device of this embodiment will be described. FIG. 4 schematically shows the planar structure of the photoelectric conversion device. FIG. 5 schematically shows the cross-sectional structure of the photoelectric conversion device. FIG. 4 shows four pixels 100 arranged in a matrix of 2 rows and 2 columns. The cross section shown in FIG. 5A corresponds to the cross section along the broken line X1-X2 in FIG. The cross section shown in FIG. 5B corresponds to the cross section along the broken line Y1-Y2 in FIG. The parts having the same functions as those in FIG. 1 are designated by the same reference numerals. However, for transistors, the corresponding gate electrodes are coded. Further, the conductive members constituting the drive signal line are given the same reference numerals as the drive signals supplied to the drive signal line. For example, the conductive member with the reference numeral of pRES constitutes a drive signal line for supplying the drive signal pRES.

The photoelectric conversion device includes a semiconductor substrate 200. Various semiconductor regions such as a source region and a drain region of a pixel transistor are arranged on the semiconductor substrate 200. The pixel transistor is, for example, a reset transistor 102, an amplification transistor 104, and a selection transistor 105. On the semiconductor substrate 200, a plurality of wiring layers 202 including a gate electrode of a pixel transistor and a conductive member constituting the wiring are arranged. The photoelectric conversion unit 101 is arranged on the wiring layer 202.

As shown in FIGS. 5 (a) and 5 (b), the photoelectric conversion unit 101 of each pixel 100 includes a first electrode 201 (common electrode), a blocking layer 203, and a photoelectric conversion layer 205. It includes an insulating layer 207 and a second electrode 209 (pixel electrode). The photoelectric conversion layer 205 is arranged between the first electrode 201 and the second electrode 209. The blocking layer 203 is arranged between the first electrode 201 and the photoelectric conversion layer 205. The blocking layer 203 is provided to prevent the same conductive type charge as the signal charge accumulated in the photoelectric conversion layer 205 from being injected from the first electrode 201 into the photoelectric conversion layer 205. The insulating layer 207 is arranged between the photoelectric conversion layer 205 and the second electrode 209.

The first electrode 201 is electrically insulated row by row, as shown in FIG. On the other hand, as shown in FIG. 5A, the first electrode 209 of the plurality of pixels 100 included in one row is composed of a common conductive member. Therefore, the first electrode 201 is also called a common electrode. Since the planar structure of the first electrode 201 is shown in FIG. 2, the first electrode 201 is not shown in FIG.

As shown in FIGS. 4 and 5 (a), the second electrode 209 of each pixel 100 is electrically insulated from the second electrode 209 of the other pixel 100. Therefore, the second electrode 209 is also called an individual electrode. Further, the blocking layer 203, the photoelectric conversion layer 205, and the insulating layer 207 are each continuously arranged over the plurality of pixels 100. Therefore, in FIG. 4, the blocking layer 203, the photoelectric conversion layer 205, and the insulating layer 207 are not shown.

As shown in FIGS. 4 and 5 (a) and 5 (b), the first capacitance 103 includes an upper electrode 211 and a lower electrode 213. The upper electrode 211 and the lower electrode 213 face each other with an insulator in between. With such a configuration, the degree of freedom in designing the capacity value of the first capacity 103 can be increased. This is because the planar shapes of the upper electrode 211 and the lower electrode 213 can be easily determined by using a semiconductor process such as lithography. A structure other than this may be used for the first capacity 103. As another example, a PN junction capacitance having a capacitance value larger than a predetermined value may be used.

Further, the upper electrode 211 and the lower electrode 213 of the first capacitance 103 are arranged in the wiring layer below the second electrode 209 of the photoelectric conversion unit 101. The upper electrode 211 and the lower electrode 213 overlap with the first electrode 201 or the second electrode 209 at least partially in a plan view. According to such a configuration, the size of the pixel 100 can be reduced. Further, the upper electrode 211 and the lower electrode 213 each include a portion that does not overlap with either the reset transistor 102 or the amplification transistor 104.

The first capacity 103 of this embodiment is, for example, a MIM (Metal Insulator Metal) capacity. Specifically, the upper electrode 211 and the lower electrode 213 are each composed of a conductive member such as metal. Alternatively, the first capacitance 103 may be a PIP (Poly-Si Insulator Poly-Si) capacitance. Specifically, the upper electrode 211 and the lower electrode 213 are each made of polysilicon. Alternatively, the first capacitance 103 may be a MOS (Metal Oxide Semiconductor) capacitance. Specifically, the upper electrode 211 is made of a conductive member such as metal or polysilicon, and the lower electrode 213 is made of a semiconductor region.

As shown in FIGS. 5 (a) and 5 (b), the second electrode 209 of the photoelectric conversion unit 101 is connected to the gate of the amplification transistor 104 via the conductive member 219. Further, the second electrode 209 of the photoelectric conversion unit 101 is connected to the source region of the reset transistor 102 via the conductive member 219 and the conductive member 220. Further, the second electrode 209 is connected to the upper electrode 211 of the first capacitance 103 via the conductive member 219. The lower electrode 213 of the first capacitance 103 is connected to the semiconductor region 217 via the contact plug 215. The semiconductor region 217 is grounded.

FIG. 5B shows the reset transistor 102 and the gate electrode of the amplification transistor 104, respectively. A gate insulating film 230 is arranged between the gate electrode and the semiconductor substrate 200. The source region and the drain region of the pixel transistor are arranged on the semiconductor substrate 200. Since the semiconductor region 217 is grounded, the semiconductor region 217 may be electrically connected to the source region of the above-mentioned transistor and the well 240 in which the drain region is arranged.

The configuration of the photoelectric conversion unit 101 will be described in detail. The first electrode 201 of the photoelectric conversion unit 101 is composed of a conductive member having high light transmittance. For example, a compound containing indium and / or tin such as ITO (Indium TinOxide) and a compound such as ZnO are used as the material of the first electrode 201. According to such a configuration, a large amount of light can be incident on the photoelectric conversion layer 205. Therefore, the sensitivity can be improved. As another example, polysilicon or metal having a thickness such that a predetermined amount of light can be transmitted may be used as the first electrode 201. Since the metal has a low resistance, the embodiment in which the metal is used as the material of the first electrode 201 is advantageous for low power consumption or high speed of driving.

The blocking layer 203 prevents the electric charge of the same conductive type as the signal charge from being injected from the first electrode 201 into the photoelectric conversion layer 205. The photoelectric conversion layer 205 is depleted by the voltage Vs applied to the first electrode 201. Further, the inclination of the potential of the photoelectric conversion layer 205 is reversed according to the relationship between the voltage Vs applied to the first electrode 201 and the voltage of the second electrode 209 (node B). With such a configuration, the signal charge can be accumulated and the accumulated signal charge can be discharged. The operation of the photoelectric conversion unit 101 will be described later.

FIG. 21 is a diagram schematically showing the structure of the photoelectric conversion layer 205 of this embodiment. In this embodiment, the photoelectric conversion layer 205 includes quantum dots 10. The material of the quantum dots 10 is PbS. Since the defect level of the surface of the quantum dot 10 is sufficiently compensated, as a result, the defect level inside the quantum dot 10 and the surface of the quantum dot 10 are reduced. As the material of the quantum dot 10, various materials described above can be used in addition to PbS.

In the example shown in FIG. 21A, a plurality of quantum dots 10 are dispersed in a member 11 made of a material different from that of the quantum dots 10. In the example shown in FIG. 21B, the photoelectric conversion layer 205 is arranged between the coating layer 12 covering the plurality of quantum dots 10 and the coating layer 12 and the blocking layer 203 (not shown). It has a layer 13. In the example shown in FIG. 21 (c), the photoelectric conversion layer 205 has an embedded layer 14 for embedding the quantum dots 10. Si, SiO, SiN, AlAs, AlGaAs, AlGaAs, GaAs, GaSb, AlSb and the like are used for the member 11, the coating layer 12, and the embedded layer 14.

ZnO is used for the blocking layer 203 of this embodiment. In addition, for the blocking layer 203, an N-type or P-type semiconductor of the same type as the semiconductor used for the photoelectric conversion layer 205 and having a higher impurity concentration than the semiconductor used for the photoelectric conversion layer 205 may be used. it can. Since the position of the Fermi level differs depending on the impurity concentration, a potential barrier can be formed only for one of the electron and the hole. The conductive type of the blocking layer 203 is a conductive type in which a large number of carriers are the conductive type charges opposite to the signal charges.

Alternatively, the blocking layer 203 can be made of a material different from that of the photoelectric conversion layer 205. According to such a configuration, a heterojunction is formed. Since the band gap differs depending on the material, the potential barrier can be formed only for one of the electron and the hole.

An insulating layer 207 is arranged between the photoelectric conversion layer 205 and the second electrode 209. An insulating material is used for the insulating layer 207. For example, as the material of the insulating layer 207, an inorganic material such as silicon oxide, amorphous silicon oxide (hereinafter, a-SiO), silicon nitride, amorphous silicon nitride (a-SiN), or an organic material is used. The thickness of the insulating layer 207 is preferably such that the electric charge does not pass through due to the tunnel effect. With such a configuration, the leakage current can be reduced, so that noise can be reduced. Specifically, the thickness of the insulating layer 207 is preferably 50 nm or more.

When a-Si, a-SiO, and a-SiN are used for the blocking layer 203, the photoelectric conversion layer 205, and the insulating layer 207, hydrogenation treatment may be performed and the dangling bond may be terminated with hydrogen. With such a configuration, noise can be reduced.

The second electrode 209 is made of a conductive member such as metal. For the second electrode 209, the same material as the conductive member constituting the wiring or the conductive member constituting the pad electrode for connecting to the outside is used. According to such a configuration, the second electrode 209 and the conductive member or pad electrode constituting the wiring can be formed at the same time. Therefore, the manufacturing process can be simplified.

Next, the operation of the photoelectric conversion unit 101 in this embodiment will be described. FIG. 6 schematically shows an energy band in the photoelectric conversion unit 101. FIG. 6 shows the energy bands of the first electrode 201, the blocking layer 203, the photoelectric conversion layer 205, the insulating layer 207, and the second electrode 209. The vertical axis of FIG. 6 represents the potential for electrons. The higher the figure, the higher the potential for electrons. Therefore, the higher the upper part of FIG. 6, the lower the voltage. The energy levels of free electrons are shown for the first electrode 201 and the second electrode 209. For the blocking layer 203 and the photoelectric conversion layer 205, a band gap between the energy level of the conduction band and the energy level of the valence band is shown. For convenience, the potential of the photoelectric conversion layer 205 at the interface between the photoelectric conversion layer 205 and the insulating layer 207 is referred to as the surface potential of the photoelectric conversion layer 205, or simply the surface potential.

As the operation of the photoelectric conversion unit 101, the following steps (1) to (6) are repeated. (1) Reset the input node of the amplification unit, (2) Read the noise signal, (3) Discharge the signal charge from the photoelectric conversion unit, (4) Read the optical signal, (5) Before the start of signal charge accumulation Reset, (6) Accumulation of signal charge. Each step will be described below.

FIG. 6A shows the state of the photoelectric conversion unit 101 in steps (1) to (2). The first voltage Vs1 is supplied to the first electrode 201 from the voltage supply unit 110. The first voltage Vs1 is, for example, 5V. Holes indicated by white circles are accumulated in the photoelectric conversion layer 205 as signal charges generated during the exposure period. The surface potential of the photoelectric conversion layer 205 changes in the direction of decreasing (the direction of increasing the voltage) according to the amount of holes to be accumulated. When electrons are accumulated, the surface potential changes in the direction of increasing (the direction of decreasing the voltage) according to the amount of accumulated electrons.

In this state, the reset transistor 102 is turned on. As a result, the voltage of the node including the second electrode 209, that is, the node B of FIG. 1, is reset to the reset voltage Vres. In this embodiment, the node B includes the gate of the amplification transistor 104. Therefore, the voltage at the gate of the amplification transistor 104 is reset. The reset voltage Vres is, for example, 3.3V.

After that, the reset transistor 102 is turned off. As a result, the node B becomes electrically floating. At this time, reset noise (noise kTC1 in FIG. 6) due to the reset transistor 102 may occur.

The surface potential of the photoelectric conversion layer 205 can change according to the change in the voltage of the electrode 209 of 2 due to the reset operation. The direction of change in the voltage of the electrode 2 209 at this time is opposite to the direction of the change in the voltage of the electrode 2 209 caused by the accumulation of the signal charge. Therefore, the holes of the signal charge remain accumulated in the photoelectric conversion layer 205. Further, since the blocking layer blocks the injection of holes from the first electrode 201, the amount of signal charge accumulated in the photoelectric conversion layer 205 does not change.

When the selection transistor 105 is on, the amplification transistor 104 outputs a noise signal (Vres + kTC1) including reset noise from the pixel 100. The noise signal is held in the capacitance CTN of the column circuit 140.

6 (b) and 6 (c) show the state of the photoelectric conversion unit 101 in step (3). First, a second voltage Vs2 is supplied to the first electrode 201. Since the hole is used as the signal charge, the second voltage Vs2 is lower than the first voltage Vs1. The second voltage Vs2 is, for example, 0V.

At this time, the voltage of the second electrode 209 (node B) changes in the same direction as the change of the voltage of the first electrode 201. The amount of change in the voltage of the second electrode 209, dVB, is the capacitance value C1 of the first capacitance 103 connected to the second electrode 209 and the capacitance value C2 of the second capacitance 111 of the photoelectric conversion unit 101. It depends on the ratio. The amount of change in voltage of the second electrode 209 dVB is expressed as dVB = dVs × C2 / (C1 + C2) with respect to the amount of change in voltage of the first electrode 201 dVs. Note that the node B including the second electrode 209 may contain other capacitive components. However, the other capacitance components are sufficiently smaller than the capacitance value C1 of the first capacitance 103. Therefore, the capacity value of the node B may be regarded as equal to the capacity value C1 of the first capacity 103.

In this embodiment, the voltage change dVs of the first electrode 201 is sufficiently larger than the voltage change dVB of the second electrode 209. Therefore, the potential of the second electrode 209 is lower than the potential of the first electrode 201, and the inclination of the potential of the photoelectric conversion layer 205 is reversed. As a result, the electrons indicated by the black circles are injected from the first electrode 209 into the photoelectric conversion layer 205. Further, a part or all of the holes accumulated in the photoelectric conversion layer 205 as signal charges move toward the blocking layer 203. The moved holes are recombined with the majority carriers of the blocking layer 203 and disappear. As a result, the holes in the photoelectric conversion layer 205 are discharged from the photoelectric conversion layer 205. When the entire photoelectric conversion layer 205 is depleted, all the holes accumulated as signal charges are discharged.

Next, in the state shown in FIG. 6C, the first voltage Vs1 is supplied to the first electrode 201. As a result, the inclination of the potential of the photoelectric conversion layer 205 is reversed again. Therefore, the electrons injected into the photoelectric conversion layer 205 in the state of FIG. 6B are discharged from the photoelectric conversion layer 205. On the other hand, the blocking layer 203 prevents the injection of holes from the first electrode 201 into the photoelectric conversion layer 205. Therefore, the surface potential of the photoelectric conversion layer 205 changes according to the amount of accumulated holes. In response to the change in the surface potential, the voltage of the second electrode 209 changes from the reset state by the voltage Vp according to the amount of the disappeared holes. That is, a voltage Vp corresponding to the amount of holes accumulated as a signal charge appears at the node B. The voltage Vp corresponding to the amount of accumulated holes is called an optical signal component.

Here, the selection transistor 105 is turned on in the state shown in FIG. 6C. As a result, the amplification transistor 104 outputs an optical signal (Vp + Vres + kTC1) from the pixel 100. The optical signal is held in the capacitive CTS of the column circuit 140. The difference between the reset signal (Vres + kTC1) read in step (2) and the optical signal (Vp + Vres + kTC1) read in step (4) is a signal based on the voltage Vp according to the accumulated signal charge. ..

FIG. 6D shows the state of the photoelectric conversion unit 101 in step (5). The reset transistor 102 is turned on, and the voltage of the node B is reset to the reset voltage Vres. After that, the reset transistor 102 is turned off. In this way, by resetting the node B before starting the accumulation of the signal charge, the optical signal component of the previous frame accumulated in the node B can be removed. Therefore, it is possible to prevent the optical signals from accumulating on the node B and narrowing the dynamic range. It is not necessary to perform the reset before the start of the accumulation of the signal charge in step (5).

At this time as well, reset noise (noise kTC2 in FIG. 6) due to the reset transistor 102 may occur. However, the reset noise generated here can be removed by performing the reset operation in step (1) after the end of the accumulation period.

6 (e) and 6 (f) show the state of the photoelectric conversion unit 101 in step (6). The first voltage Vs1 is supplied to the first electrode 201, and the reset voltage Vres is supplied to the node B. Since the reset voltage Vres is lower than the first voltage Vs1, the electrons of the photoelectric conversion layer 205 are discharged to the first electrode 201. On the other hand, the holes of the photoelectric conversion layer 205 move toward the interface between the photoelectric conversion layer 205 and the insulating layer 207. However, since the holes cannot move to the insulating layer 207, they are accumulated in the photoelectric conversion layer 205. Further, as described above, the blocking layer 203 prevents the holes from being injected into the photoelectric conversion layer 205. Therefore, when light is incident on the photoelectric conversion layer 205 in this state, only the holes among the electron hole pairs generated by the photoelectric conversion are accumulated in the photoelectric conversion layer 205 as signal charges. After accumulating for a certain period of time, the operations of steps (1) to (6) are repeated.

The surface potential of the photoelectric conversion layer 205 changes depending on the accumulated holes. The voltage of the second electrode 209 rises in response to this change in surface potential. This is shown by Vp0 in FIG. 6 (f). At the time of resetting in FIG. 6A, the voltage of the second electrode 209 changes so as to cancel the changed voltage Vp0 as described above. That is, the voltage of the second electrode 209 drops. Therefore, the surface potential of the photoelectric conversion layer 205 changes in the increasing direction.

When the signal charge is an electron, the second voltage Vs2 is higher than the first voltage Vs1. Therefore, the slope of the potential in FIGS. 6A to 6F is reversed. Other operations are the same.

In the operation described with reference to FIG. 6, the accumulated signal charge is discharged by reversing the inclination of the potential of the photoelectric conversion layer 205 in the state of FIG. 6B. If the slope of the potential of the photoelectric conversion layer 205 cannot be reversed, an electric charge that is not discharged is generated, which may cause noise. Here, the larger the change amount dVs of the voltage of the first electrode 201 than the change amount dVB of the voltage of the second electrode 209 (node B), the easier it is to reverse the slope of the potential. That is, the noise can be reduced as the amount of change in voltage of the first electrode 201 dVs is larger than the amount of change in voltage of the second electrode 209 dVB.

As described above, there is a relationship of dVB = dVs × C2 / (C1 + C2) between the voltage change amount dVs of the first electrode 201 and the voltage change amount dVB of the node B. By modifying this equation, the amount of change in voltage of the first electrode 201, dVs, is expressed as dVs = dVB + (C1 / C2) × dVB. That is, the change amount dVs of the voltage of the first electrode 201 is larger than the change amount dVB of the voltage of the second electrode 209 by (C1 / C2) × dVB. Therefore, the larger the capacitance value C1 of the node B, the larger the difference between the voltage change amount dVs of the first electrode 201 and the voltage change amount dVB of the second electrode 209.

In this embodiment, the first capacitance 103 is connected to the second electrode 209. Therefore, the capacity value C1 of the node B can be increased. According to such a configuration, the change amount dVs of the voltage of the first electrode 201 can be made larger than the change amount dVB of the voltage of the second electrode 209. As a result, the photoelectric conversion layer 205 is easily depleted, so that the charges that are not discharged can be reduced. As described above, according to this embodiment, noise can be reduced.

As a comparative example, a configuration in which the first capacity 103 is not connected to the node B will be described. In this case, the capacitance of the node B may include a capacitance component due to the PN junction of the semiconductor region and a parasitic capacitance component with the wiring. However, these capacitance components are negligibly smaller than the capacitance value C2 of the second capacitance 111 of the photoelectric conversion unit 101. Therefore, C1 / C2 becomes almost zero. Therefore, when the second voltage Vs2 is supplied to the first electrode 201, the amount of change in the voltage of the first electrode 201 dVs and the amount of change in the voltage of the second electrode 209 dVB become substantially equal. Then, in the state of FIG. 6B, the slope of the potential may not be reversed. As a result, there is a possibility that a part of the holes accumulated as signal charges cannot be discharged. Compared to the comparative example, the amount of signal charge that is not emitted in this embodiment can be reduced, so that noise can be reduced.

Subsequently, the relationship between the capacitance value C1 of the first capacitance 103, the capacitance value C2 of the second capacitance 111 included in the photoelectric conversion unit 101, and the voltage supplied to each unit will be described.

In this embodiment, the photoelectric conversion unit 101 includes a blocking layer 203, a photoelectric conversion layer 205, and an insulating layer 207. The blocking layer 203 has a higher conductivity than the photoelectric conversion layer 205 and the insulating layer 207. Therefore, the capacitance value C2 of the second capacitance 111 included in the photoelectric conversion unit 101 is the combined capacitance of the capacitance component Ci by the photoelectric conversion layer 205 and the capacitance component Cins by the insulating layer 207. Specifically, the capacitance value C2 of the second capacitance 111 is represented by the following equation (1).
C2 = Ci × Cins / (Ci + Cins) ・ ・ ・ (1)

Area Ss of the second electrode 209 in plan view, thickness di of the photoelectric conversion layer 205, thickness dins of the insulating layer 207, relative permittivity Ei of the photoelectric conversion layer 205, relative permittivity Eins of the insulating layer 207, and Using the vacuum dielectric constant E0, the capacitive component Ci and the capacitive component Cins are represented by the following equations (2) and (3), respectively.
Ci = E0 x Ei x Ss / di ... (2)
Cins = E0 x Eins x Ss / dins ... (3)

Since the fringe electric field of the second electrode 209 can be almost ignored, only the area Ss of the second electrode 209 in a plan view needs to be considered as the area used for the calculation of the capacitance. The area Ss of the second electrode 209 in a plan view is, for example, the area of the second electrode 209 in FIG. Further, in FIG. 5, the thickness di of the photoelectric conversion layer 205 and the thickness dins of the insulating layer 207 are shown.

The capacitance value C1 of the first capacitance 103 is the area Sd of the upper electrode 211 or the lower electrode 213 in a plan view, the distance dd between the upper electrode 211 and the lower electrode 213, and the insulation between the upper electrode 211 and the lower electrode 213. It is expressed by the following equation (4) using the dielectric constant Ed of the layer.
C1 = E0 × Ed × Sd / dd ・ ・ ・ (4)

In this embodiment, by controlling the voltage Vs of the first electrode 201 (node A) to the first voltage Vs1 and the second voltage Vs2, the signal charge is accumulated and the photoelectric conversion layer 205 is depleted. The signal charge is discharged by. When the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 satisfy the relationship described below, the charge remaining on the photoelectric conversion layer 205 at the time of discharging the signal charge described above is reduced. Can be done. First, an embodiment in which the signal charge is Hall will be described.

Hereinafter, for the sake of simplicity, it is assumed that the capacity value C1 of the first capacity 103 is k times the capacity value C2 of the second capacity 111. That is, the capacitance value C1 and the capacitance value C2 have the relationship of the following equation (5).
C1 = k × C2 ・ ・ ・ (5)

As described above, the amount of change in voltage of the first electrode 201 dVs and the amount of change in voltage of the second electrode 209 (node B) dVB have a relationship represented by the following equation (6).
dVB = dVs × C2 / (C1 + C2) ・ ・ ・ (6)

From the equations (5) and (6), the following equation (7) can be obtained.
dVB = dVs / (1 + k) ... (7)

Here, in order to accumulate holes as signal charges, it is preferable that the first voltage Vs1 and the reset voltage Vres satisfy the relationship of the following equation (8).
Vs1> Vres ・ ・ ・ (8)

In order to transfer the hole of the signal charge, the first voltage Vs1, the reset voltage Vres, the voltage change amount dVs of the first electrode 201, and the voltage change amount dVB of the second electrode 209 are as follows. It is preferable to satisfy the relation of the equation (9).
Vs1 + dVs <Vres + dVB ... (9)

When the relationship of the formula (8) is satisfied, a slope of the potential for the hole to drift toward the insulating layer 207 can be formed in the photoelectric conversion layer 205. When the relationship of the equation (9) is satisfied, it becomes easy to reverse the inclination of the potential of the photoelectric conversion layer 205.

Equation (10) is obtained from Equation (7) and Equation (9).
Vs1-Vres + dVs <dVs / (1 + k) ... (10)

Here, since k> 0, the equation (10) is transformed into the following equation (11) by multiplying both sides of the equation (10) by (1 + k).
(1 + k) × (Vs1-Vres + dVs) <dVs ... (11)

Here, the amount of change in voltage of the first electrode 201, dVs, is expressed as dVs = Vs2-Vs1. Therefore, Vs1-Vres + dVs = Vs2-Vres. In the example where the signal charge is Hall, the reset voltage Vres is higher than the second voltage Vs2. That is, Vs2-Vres <0. Therefore, the relationship of the following equation (12) is satisfied.
Vs1-Vres + dVs <0 ... (12)

Therefore, if both sides of the equation (11) are divided by (Vs1-Vres + dVs), the direction of the inequality sign changes, and the relationship of the following equation (13) is obtained.
1 + k> dVs / (Vs1-Vres + dVs) ... (13)

From the formula (13), a relational expression represented by the following formula (14) can be obtained with respect to the capacity ratio k of the capacity value C1 and the capacity value C2.

When the relationship of the equation (14) is satisfied, the amount of electric charge that is not discharged can be reduced. Therefore, noise can be reduced.

In this embodiment, the first voltage Vs1 is 5V and the reset voltage Vres is 3.3V. Since the second voltage Vs2 is 0V, the amount of change dVs in the voltage of the first electrode 201 is −5V. Therefore, the value of k is set to a value larger than 0.52. Specifically, in this embodiment, the capacity value C1 of the first capacity 103 is 4 fF, and the capacity value C2 of the second capacity 111 is 1 fF. That is, k = 4. According to such a configuration, noise can be further reduced.

In this embodiment, in a plan view, the area Sd of either the upper electrode 211 or the lower electrode 213 of the first capacitance 103 and the area Ss of the second electrode 209 have a relationship of Sd> 0.5 × Ss. Fulfill. According to such a configuration, the above-mentioned capacity ratio relationship can be easily obtained.

Further, the larger the value of k, the greater the effect of noise reduction. Therefore, when the capacitance value C1 of the first capacitance 103 is equal to or larger than the capacitance value C2 of the second capacitance 111, the effect of noise reduction can be further enhanced.

The amount of change in the voltage of the first electrode 209, dVs, is expressed as dVs = Vs2-Vs1 by using the first voltage Vs1 and the second voltage Vs2. Therefore, equation (14) is modified as in equation (15).

In particular, when the second voltage Vs2 is 0V, the equation (15) can be simplified as in the equation (16).

Next, an embodiment in which the signal charge is an electron will be described. When the signal charge is an electron, the direction of the inequality sign in equations (8) and (9) changes. Therefore, the direction of the inequality sign in equations (10) to (11) also changes. However, when the signal charge is an electron, the reset voltage Vres is lower than the second voltage Vs2. Therefore, Vs1-Vres + dVs = Vs2-Vres in the formula (11) is a positive value. That is, the relationship (Vs1-Vres + dVs)> 0 holds. Therefore, when both sides of the equation (11) are divided by (Vs1-Vres + dVs), the direction of the inequality sign does not change. As a result, the equation (14) and the equation (15) are obtained as in the case where the signal charge is Hall.

The left side of equation (15) can be rewritten to C1 / C2 using equation (5). Further, since (Vs2-Vres) / (Vs2-Vres) = 1, the following equation (17) can be obtained by dividing the right side of the equation (15).

Here, the relationship represented by the equation (17) will be described. First, the reset voltage Vres is an intermediate value between the first voltage Vs1 and the second voltage Vs2.

The closer the reset voltage Vres is to the first voltage Vs1, the smaller the value on the right side. That is, even if the capacitance value C1 of the first capacitance 103 is small, the inclination of the potential of the photoelectric conversion layer 205 can be reversed. When the difference between the reset voltage Vres and the first voltage Vs1 is small, the amount of electric charge that can be stored in the photoelectric conversion layer 205 becomes small.

On the other hand, the closer the reset voltage Vres is to the first voltage Vs2, the larger the value on the right side. That is, a large value is used for the capacity value C1 of the first capacity 103. At this time, since the difference between the reset voltage Vres and the first voltage Vs1 is large, the amount of electric charge that can be stored in the photoelectric conversion layer 205 can be increased.

In order to balance the saturated charge amount and the capacitance value C1 of the first capacitance 103, the reset voltage Vres sets the first voltage Vs1 and the second voltage Vs2 as the upper limit and the lower limit (or the lower limit and the upper limit), respectively. It is preferably contained in the range of 20% to 80% of the range. For example, when the first voltage Vs1 is 5V and the second voltage Vs2 is 0V, the reset voltage Vres may be included in the range of 1V to 4V.

When the photoelectric conversion device is used as an image sensor for a camera or the like, a low power supply voltage is used to reduce power consumption. For example, the power supply voltage supplied to the image sensor is often 5 V or less. Therefore, a value of 5 V or less is used for each voltage of the equations (14) to (17). In such a case, the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 satisfy the above-mentioned relationship, so that noise is reduced while driving the photoelectric conversion device with a low voltage. be able to.

As described above, noise can be reduced by the relationship between the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 included in the photoelectric conversion unit 101.

The numerical values given above are merely examples, and are not limited to these values.

Defect levels and the like may be present at the interface between the photoelectric conversion layer 205 and the insulating layer 207. In such a case, the flat band voltage may be considered based on a known technique.

Next, a method of driving the photoelectric conversion device of this embodiment will be described. FIG. 7 shows a timing chart of the drive signal used in the photoelectric conversion device of this embodiment. FIG. 7 shows a drive signal corresponding to the signal reading operation for the two lines of the nth line and the n + 1th line.

The drive signal pSEL is supplied to the gate of the selection transistor 105. The drive signal pRES is supplied to the gate of the reset transistor 102. The voltage signal Vs is supplied to the first electrode 201 of the photoelectric conversion unit 101. The drive signal pTS is supplied to the S / H switch 303. The drive signal pTN is supplied to the S / H switch 305. The drive signal CSEL is supplied to the column drive circuit 150.

When the drive signal pSEL, drive signal pRES, drive signal pTN, and drive signal pTS are at a high level, the corresponding transistor or switch is turned on. When the drive signal pSEL, drive signal pRES, drive signal pTN, and drive signal pTS are at low level, the corresponding transistor or switch is turned off. The voltage signal Vs includes a first voltage Vs1 and a second voltage Vs2.

The photoelectric conversion device of this embodiment performs a so-called rolling shutter operation. Before the time t1, the photoelectric conversion unit 101 of the pixel 100 on the nth row and the photoelectric conversion unit 101 of the pixel 100 on the n + 1th row are in a state of accumulating signal charges. Further, before the time t1, the voltage signal Vs (n) on the nth line and the voltage signal Vs (n + 1) on the n + 1th line are both the first voltage Vs1.

At time t1, the drive signal pSEL (n) becomes high level, and the selection transistor 105 of the pixel 100 on the nth row is turned on. As a result, the amplification transistor 104 of the pixel 100 on the nth row outputs a signal.

At time t1, the drive signal pRES (n) becomes high level, and the reset transistor 102 of the pixel 100 on the nth row is turned on. As a result, the voltage of the node B of the pixel 100 in the nth row is reset to the reset voltage Vres. After that, at time t2, the drive signal pRES (n) becomes low level and the reset transistor 102 is turned off. The state of the energy band of the photoelectric conversion unit 101 at this time is shown in FIG. 6A.

Next, the drive signal pTN (n) becomes high level at time t3 and low level at time t3. As a result, the noise signal including the reset noise (kTC1 in FIG. 6) is held in the capacitance CTN of the column circuit 140.

At time t5, the voltage signal Vs (n) transitions from the first voltage Vs1 to the second voltage Vs2. The state of the energy band of the photoelectric conversion unit 101 at this time is shown in FIG. 6 (b). Subsequently, at time t6, the voltage signal Vs (n) transitions from the second voltage Vs2 to the first voltage Vs1. The state of the energy band of the photoelectric conversion unit 101 at this time is shown in FIG. 6 (c). By the operation from time t5 to time t6, the signal charge is transferred as described above. Therefore, a voltage Vp is generated in the node B according to the amount of the stored signal charge.

The drive signal pTS (n) becomes high level at time t7 and low level at time t8. As a result, the optical signal including the voltage Vp and the reset noise (kTC1 in FIG. 6) is held in the capacitance CTS of the column circuit 140.

Subsequently, the drive signal pPRES (n) becomes high level at time t9 and low level at time t10. As a result, the voltage of the node B of the pixel 100 in the nth row is reset to the reset voltage Vres again. The state of the energy band of the photoelectric conversion unit 101 at this time is shown in FIG. 6 (d).

After that, the pixel 100 in the nth row starts accumulating the signal charge of the next frame. The state of the energy band of the photoelectric conversion unit 101 during the accumulation of the signal charge is shown in FIGS. 6 (e) and 6 (f).

At time t11, the drive signal pSEL (n) becomes low level, and the reading of the signal from the pixel 100 in the nth row to the column circuit 140 ends.

The noise signal and the optical signal read out to the column circuit 140 are output to the output unit 170 for each column based on the drive signal CSEL. The output unit 170 outputs the difference between the optical signal and the noise signal to the analog-digital conversion unit 180.

At time t12, the drive signal pSEL (n + 1) becomes high level, and the selection transistor 105 of the pixel 100 on the n + 1th line is turned on. After that, the signal is read from the pixel 100 on the n + 1th line. Since this operation is the same as the time t1 to the time t11, the description thereof will be omitted.

As described above, in the photoelectric conversion device of this embodiment, the photoelectric conversion layer 205 includes the quantum dots 10. According to such a configuration, the defect level of the photoelectric conversion layer can be reduced. This is because the size of the quantum dot is small, so that the lattice defects inside the quantum dot can be reduced. As a result, noise can be reduced.

Another embodiment will be described. In this embodiment, the node to which the voltage supply unit supplies the voltage is different from that in the first embodiment. Therefore, only the part different from the first embodiment will be described. The same parts as in the first embodiment will be omitted.

FIG. 8 schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. The parts having the same functions as those in FIG. 1A are designated by the same reference numerals. The equivalent circuit of the photoelectric conversion unit 101 of this embodiment is the same as that of the first embodiment. That is, FIGS. 1 (b) and 1 (c) show an example of the equivalent circuit of the photoelectric conversion unit 101 of this embodiment.

In this embodiment, the voltage Vd from the voltage supply unit 410 is supplied to the second terminal of the first capacity 103. The voltage supply unit 410 supplies at least the first voltage Vd1 and a second voltage Vd2 different from the first voltage Vd1 to the second terminal of the first capacitance 103.

When the signal charge is Hall, the second voltage Vd2 is higher than the first voltage Vd1. When the signal charge is Hall, for example, the first voltage Vd1 is 0V and the second voltage Vd2 is 5V. When the signal charge is an electron, the second voltage Vd2 is lower than the first voltage Vd1. When the signal charge is an electron, for example, the first voltage Vd1 is 5V and the second voltage Vd2 is 0V.

On the other hand, a predetermined voltage Vs is supplied to the first electrode 201 of the photoelectric conversion unit 101. In this embodiment, a voltage of 3 V is supplied to the first electrode 201 of the photoelectric conversion unit 101. In FIG. 1, the first electrode 201 is included in the node A.

Next, the reset voltage Vres supplied by the reset transistor 102 will be described. When the signal charge is Hall, the reset voltage Vres is a voltage lower than the voltage Vs supplied to the first electrode 201 of the photoelectric conversion unit 101. When the signal charge is an electron, the reset voltage Vres is a voltage higher than the voltage Vs supplied to the first electrode 201 of the photoelectric conversion unit 101.

In this embodiment, the voltage Vd of the node C is controlled to control the voltage of the node B coupled to the node C via the first capacitance 103. Therefore, the DC magnitude relationship between the voltage Vd supplied to the node C and the reset voltage Vres or Vs supplied to the node A is not particularly limited.

FIG. 9 is a diagram schematically showing the entire circuit configuration of the photoelectric conversion device of this embodiment. The parts having the same functions as those in FIG. 2 are designated by the same reference numerals.

FIG. 9 schematically shows the planar structure of the first electrode 201 of the photoelectric conversion unit 101. The first electrode 201 is included in the node A of FIG. As shown in FIG. 9, the photoelectric conversion unit 101 of the plurality of pixels 100 included in the plurality of rows and the plurality of columns includes a common first electrode 201. A voltage Vs is supplied to the first electrode 201.

In this embodiment, the voltage Vd supplied to the second terminal (node C) of the first capacitance 103 is controlled independently for each row. Therefore, the row drive circuit 120 selects the row to which the voltage Vd is supplied from the voltage supply unit 410. In addition, in order to distinguish the voltage Vd supplied to different rows, reference numerals representing the rows such as (n) and (n + 1) are added. With the configuration described above, in this embodiment, a plurality of pixels 100 can be driven row by row.

The configuration of the column circuit 140 of this embodiment is the same as that of the first embodiment. That is, FIG. 3 shows an equivalent circuit of the column circuit 140 of this embodiment. Further, as in the first embodiment, the column circuit 140 may be an analog-to-digital conversion circuit. In this case, the analog-to-digital conversion circuit has a holding unit that holds a digital signal such as a memory or a counter. The noise signal and the optical signal are converted into digital signals and held in the holding unit.

Next, the planar structure and the cross-sectional structure of the photoelectric conversion device of this embodiment will be described. FIG. 10 schematically shows the planar structure of the photoelectric conversion device. FIG. 11 schematically shows the cross-sectional structure of the photoelectric conversion device. The cross section shown in FIG. 11 corresponds to the cross section along the broken line X1-X2 in FIG. The same parts as those in FIG. 4 or 5 are designated by the same reference numerals.

As shown in FIGS. 10 and 11, the lower electrode 213 of the first capacitance 103 is connected to the conductive member 420. The conductive member 420 constitutes a wiring for supplying the voltage Vd from the voltage supply unit 410. In this embodiment, the conductive members 420 are arranged row by row and are electrically insulated from the conductive members 420 in the other rows. With such a configuration, the voltage Vd of the second terminal (node C) of the first capacitance 103 can be controlled independently for each row.

Since the structure is the same as that of the first embodiment except for the above structure, the description thereof will be omitted.

Next, the operation of the photoelectric conversion unit 101 in this embodiment will be described. FIG. 12 schematically shows the energy band in the photoelectric conversion unit 101. FIG. 12 shows the energy bands of the first electrode 201, the blocking layer 203, the photoelectric conversion layer 205, the insulating layer 207, and the second electrode 209. The vertical axis of FIG. 12 represents the potential for electrons. The higher the figure, the higher the potential for electrons. Therefore, the voltage becomes lower toward the upper part of FIG. The energy levels of free electrons are shown for the first electrode 201 and the second electrode 209. For the blocking layer 203 and the photoelectric conversion layer 205, a band gap between the energy level of the conduction band and the energy level of the valence band is shown. For convenience, the potential of the photoelectric conversion layer 205 at the interface between the photoelectric conversion layer 205 and the insulating layer 207 is referred to as the surface potential of the photoelectric conversion layer 205, or simply the surface potential.

As the operation of the photoelectric conversion unit 101, the following steps (1) to (6) are repeated. (1) Reset the input node of the amplification unit, (2) Read the noise signal, (3) Discharge the signal charge from the photoelectric conversion unit, (4) Read the optical signal, (5) Before the start of signal charge accumulation Reset, (6) Accumulation of signal charge. Each step will be described below.

FIG. 12A shows the state of the photoelectric conversion unit 101 in steps (1) to (2). A voltage Vs is supplied to the first electrode 201. The first voltage Vs is, for example, 3V. Holes indicated by white circles are accumulated in the photoelectric conversion layer 205 as signal charges generated during the exposure period. The surface potential of the photoelectric conversion layer 205 changes in the direction of decreasing (the direction of increasing the voltage) according to the amount of accumulated holes. When electrons are accumulated, the surface potential changes in the direction of increasing (the direction in which the voltage decreases) according to the amount of accumulated electrons. Further, a first voltage Vd1 is supplied to the node C. The first voltage Vd1 is, for example, 0V.

In this state, the reset transistor 102 is turned on. As a result, the voltage of the node including the second electrode 209, that is, the node B in FIG. 8 is reset to the reset voltage Vres. In this embodiment, the node B includes the gate of the amplification transistor 104. Therefore, the voltage at the gate of the amplification transistor 104 is reset. The reset voltage Vres is, for example, 1V.

After that, the reset transistor 102 is turned off. As a result, the node B becomes electrically floating. At this time, reset noise (noise kTC1 in FIG. 12) due to the reset transistor 102 may occur.

The surface potential of the photoelectric conversion layer 205 can change according to the change in the voltage of the electrode 209 of 2 due to the reset operation. The direction of change in the voltage of the electrode 2 209 at this time is opposite to the direction of the change in the voltage of the electrode 2 209 caused by the accumulation of the signal charge. Therefore, the holes of the signal charge remain accumulated in the photoelectric conversion layer 205. Further, since the blocking layer blocks the injection of holes from the first electrode 201, the amount of signal charge accumulated in the photoelectric conversion layer 205 does not change.

When the selection transistor 105 is on, the amplification transistor 104 outputs a noise signal (Vres + kTC1) including reset noise from the pixel 100. The noise signal is held in the capacitance CTN of the column circuit 140.

12 (b) and 12 (c) show the state of the photoelectric conversion unit 101 in step (3). First, a second voltage Vd2 is supplied to the node C. Since the hole is used as the signal charge, the second voltage Vd2 is higher than the first voltage Vs1. The second voltage Vd2 is, for example, 5V.

At this time, the voltage of the second electrode 209 (node B) changes in the same direction as the change of the voltage of the node C. The amount of change in the voltage of the second electrode 209, dVB, is the capacitance value C1 of the first capacitance 103 connected to the second electrode 209 and the capacitance value C2 of the second capacitance 111 of the photoelectric conversion unit 101. It depends on the ratio. The amount of change in voltage of the second electrode 209 dVB is expressed as dVB = dVd × C1 / (C1 + C2) with respect to the amount of change in voltage of node C dVd. Note that the node B including the second electrode 209 may contain other capacitive components. However, the other capacitance components are sufficiently smaller than the capacitance value C1 of the first capacitance 103. Therefore, the capacity value of the node B may be regarded as equal to the capacity value C1 of the first capacity 103.

In this embodiment, the amount of change dVB in the voltage of the second electrode 209 is sufficiently larger than the difference (Vs-Vres) between the voltage Vs of the first electrode 209 and the reset voltage Vres. Therefore, the potential of the second electrode 209 is lower than the potential of the first electrode 201, and the inclination of the potential of the photoelectric conversion layer 205 is reversed. As a result, the electrons indicated by the black circles are injected from the first electrode 209 into the photoelectric conversion layer 205. Further, a part or all of the holes accumulated in the photoelectric conversion layer 205 as signal charges move toward the blocking layer 203. The moved holes are recombined with the majority carriers of the blocking layer 203 and disappear. As a result, the holes in the photoelectric conversion layer 205 are discharged from the photoelectric conversion layer 205. When the entire photoelectric conversion layer 205 is depleted, all the holes accumulated as signal charges are discharged.

Next, in the state shown in FIG. 12 (c), the first voltage Vd1 is supplied to the node C. As a result, the inclination of the potential of the photoelectric conversion layer 205 is reversed again. Therefore, the electrons injected into the photoelectric conversion layer 205 in the state of FIG. 12B are discharged from the photoelectric conversion layer 205. On the other hand, the blocking layer 203 prevents the injection of holes from the first electrode 201 into the photoelectric conversion layer 205. Therefore, the surface potential of the photoelectric conversion layer 205 changes according to the amount of accumulated holes. In response to the change in the surface potential, the voltage of the second electrode 209 changes from the reset state by the voltage Vp according to the amount of the disappeared holes. That is, a voltage Vp corresponding to the amount of holes accumulated as a signal charge appears at the node B. The voltage Vp corresponding to the amount of accumulated holes is called an optical signal component.

Here, the selection transistor 105 is turned on in the state shown in FIG. 12 (c). As a result, the amplification transistor 104 outputs an optical signal (Vp + Vres + kTC1) from the pixel 100. The optical signal is held in the capacitive CTS of the column circuit 140. The difference between the reset signal (Vres + kTC1) read in step (2) and the optical signal (Vp + Vres + kTC1) read in step (4) is a signal based on the voltage Vp according to the accumulated signal charge. ..

FIG. 12D shows the state of the photoelectric conversion unit 101 in step (5). The reset transistor 102 is turned on, and the voltage of the node B is reset to the reset voltage Vres. After that, the reset transistor 102 is turned off. In this way, by resetting the node B before starting the accumulation of the signal charge, the optical signal component of the previous frame accumulated in the node B can be removed. Therefore, it is possible to prevent the optical signals from accumulating on the node B and narrowing the dynamic range. It is not necessary to perform the reset before the start of the accumulation of the signal charge in step (5).

At this time as well, reset noise (noise kTC2 in FIG. 12) due to the reset transistor 102 may occur. However, the reset noise generated here can be removed by performing the reset operation in step (1) after the end of the accumulation period.

12 (e) and 12 (f) show the state of the photoelectric conversion unit 101 in step (6). The voltage Vs is supplied to the first electrode 201, and the reset voltage Vres is supplied to the node B. Since the reset voltage Vres is lower than the voltage Vs of the first electrode 201, the electrons of the photoelectric conversion layer 205 are discharged to the first electrode 201. On the other hand, the holes of the photoelectric conversion layer 205 move toward the interface between the photoelectric conversion layer 205 and the insulating layer 207. However, since the holes cannot move to the insulating layer 207, they are accumulated in the photoelectric conversion layer 205. Further, as described above, the blocking layer 203 prevents the holes from being injected into the photoelectric conversion layer 205. Therefore, when light is incident on the photoelectric conversion layer 205 in this state, only the holes among the electron hole pairs generated by the photoelectric conversion are accumulated in the photoelectric conversion layer 205 as signal charges. After accumulating for a certain period of time, the operations of steps (1) to (6) are repeated.

The surface potential of the photoelectric conversion layer 205 changes depending on the accumulated holes. The voltage of the second electrode 209 rises in response to this change in surface potential. This is shown by Vp0 in FIG. 6 (f). At the time of resetting in FIG. 6A, the voltage of the second electrode 209 changes so as to cancel the changed voltage Vp0 as described above. That is, the voltage of the second electrode 209 drops. Therefore, the surface potential of the photoelectric conversion layer 205 changes in the increasing direction.

When the signal charge is an electron, the second voltage Vd2 is lower than the first voltage Vd1. Therefore, the slope of the potential in FIGS. 12 (a) to 12 (f) is reversed. Other operations are the same.

In the operation described with reference to FIG. 12, the accumulated holes are discharged by reversing the inclination of the potential of the photoelectric conversion layer 205 in the state of FIG. 12B. If the slope of the potential of the photoelectric conversion layer 205 cannot be reversed, an electric charge that is not discharged is generated, which may cause noise. Here, as the amount of change in voltage of the second electrode 209 (node B) dVB is larger than the difference (Vs-Vres) between the voltage Vs of the first electrode 209 and the reset voltage Vres, the potential gradient is inverted. Cheap. That is, the noise can be reduced as the amount of change in the voltage of the second electrode 209 dVB is larger than the difference (Vs-Vres) between the voltage Vs of the first electrode 209 and the reset voltage Vres.

As described above, there is a relationship of dVB = dVd × C1 / (C1 + C2) between the change amount dVd of the voltage of the node C and the change amount dVB of the voltage of the node B. That is, the larger the capacitance value C1 of the node B, the larger the amount of change dVB of the voltage of the node B.

In this embodiment, the first capacitance 103 is connected to the second electrode 209. Therefore, the capacity value C1 of the node B can be increased. According to such a configuration, the amount of change in the voltage of the node B, dVB, can be increased. As a result, the photoelectric conversion layer 205 is easily depleted, so that the charges that are not discharged can be reduced. As described above, according to this embodiment, noise can be reduced.

As a comparative example, a configuration in which the first capacity 103 is not connected to the node B will be described. In this case, the capacitance of the node B may include a capacitance component due to the PN junction of the semiconductor region and a parasitic capacitance component with the wiring. However, these capacitance components are negligibly smaller than the capacitance value C2 of the second capacitance 111 of the photoelectric conversion unit 101. Therefore, C1 / (C1 + C2) becomes almost zero. Therefore, even if the voltage Vd of the node C is changed, the voltage of the node B hardly changes. Then, in the state of FIG. 12B, the slope of the potential may not be reversed. As a result, there is a possibility that a part of the holes accumulated as signal charges cannot be discharged. Compared to the comparative example, the amount of signal charge that is not emitted in this embodiment can be reduced, so that noise can be reduced.

Subsequently, the relationship between the capacitance value C1 of the first capacitance 103, the capacitance value C2 of the second capacitance 111 included in the photoelectric conversion unit 101, and the voltage supplied to each unit will be described. In this embodiment, the capacitance value C1 and the capacitance value C2 are represented by the formulas (4) and (1) of the first embodiment, respectively. A detailed description will be omitted here.

In this embodiment, by controlling the voltage Vd of the node C to the first voltage Vd1 and the second voltage Vd2, the signal charge is accumulated and the signal charge is discharged due to the depletion of the photoelectric conversion layer 205. ing. When the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 satisfy the relationship described below, the charge remaining on the photoelectric conversion layer 205 at the time of discharging the signal charge described above is reduced. Can be done. First, an embodiment in which the signal charge is Hall will be described.

Hereinafter, for the sake of simplicity, it is assumed that the capacity value C1 of the first capacity 103 is k times the capacity value C2 of the second capacity 111. That is, the capacitance value C1 and the capacitance value C2 have the relationship of the following equation (18).
C1 = k × C2 ・ ・ ・ (18)

As described above, the change amount dVd of the voltage of the node C and the change amount dVB of the voltage of the second electrode 209 (node B) have a relationship represented by the following equation (19).
dVB = dVd × C1 / (C1 + C2) ... (19)

From the equation (18) and the equation (19), the following equation (20) is obtained.
dVB = dVd × k / (1 + k) ・ ・ ・ (20)

Here, in order to accumulate holes as signal charges, it is preferable that the voltage Vs supplied to the first electrode 201 (node A) and the reset voltage Vres satisfy the relationship of the following equation (21). Vs> Vres ・ ・ ・ (21)

In order to transfer the hole of the signal charge, the voltage Vs of the first electrode 201 (node A), the reset voltage Vres, and the change amount dBB of the voltage of the second electrode 209 are of the following equation (22). It is good to satisfy the relationship.
Vs <Vres + dBB ... (22)

When the relationship of the formula (21) is satisfied, a slope of the potential for the hole to drift toward the insulating layer 207 can be formed in the photoelectric conversion layer 205. When the relationship of the equation (22) is satisfied, it becomes easy to reverse the inclination of the potential of the photoelectric conversion layer 205.

Equation (23) is obtained from Equation (20) and Equation (22).
Vs-Vres <dVd × k / (1 + k) ・ ・ ・ (23)

Here, in the example in which the signal charge is Hall, the second voltage Vd2 is higher than the first voltage Vd1. That is, the amount of change in the voltage of the node C dVd = Vd2-Vd1 is a positive value. Therefore, even if both sides of the equation (23) are divided by dVd, the direction of the inequality sign does not change.

Therefore, from the equation (23), a relational expression represented by the following equation (24) can be obtained with respect to the capacitance ratio k between the capacitance value C1 and the capacitance value C2.

When the relationship of the equation (24) is satisfied, the amount of electric charge that is not discharged can be reduced. Therefore, noise can be reduced.

In this embodiment, the voltage Vs of the first electrode 201 is 3V, and the reset voltage Vres is 1V. Since the first voltage Vd1 is 0V and the second voltage Vs2 is 5V, the amount of change dVd of the voltage of the node C is 5V. Therefore, k> 2/3 is set. Specifically, in this embodiment, the capacity value C1 of the first capacity 103 is 4 fF, and the capacity value C2 of the second capacity 111 is 1 fF. That is, k = 4. According to such a configuration, noise can be further reduced.

In this embodiment, in a plan view, the area Sd of either the upper electrode 211 or the lower electrode 213 of the first capacitance 103 and the area Ss of the second electrode 209 have a relationship of Sd> 0.5 × Ss. Fulfill. According to such a configuration, the above-mentioned capacity ratio relationship can be easily obtained.

Further, the larger the value of k, the greater the effect of noise reduction. Therefore, when the capacitance value C1 of the first capacitance 103 is equal to or larger than the capacitance value C2 of the second capacitance 111, the effect of noise reduction can be further enhanced.

The amount of change in the voltage of the node C dVd is expressed as dVd = Vd2-Vd1 using the first voltage Vd1 and the second voltage Vd2. Further, the left side of the equation (24) can be rewritten as C1 / (C1 + C2) using the equation (18). Therefore, equation (24) is modified as in equation (25).

Next, an embodiment in which the signal charge is an electron will be described. When the signal charge is an electron, the direction of the inequality sign in equations (21) and (22) changes. Therefore, the direction of the inequality sign in the following equation (23) also changes. That is, when the signal charge is an electron, the following equation (26) is obtained.
Vs-Vres> dVd × k / (1 + k) ・ ・ ・ (26)

However, in the embodiment where the signal charge is electron, the second voltage Vd2 is lower than the first voltage Vd1. That is, the amount of change in the voltage of the node C dVd = Vd2-Vd1 is a negative value. Therefore, dividing both sides of equation (26) by dVd changes the direction of the inequality sign. As a result, the equation (24) and the equation (25) are obtained as in the case where the signal charge is Hall.

Here, the relationship represented by the equation (15) will be described. The closer the reset voltage Vres is to the voltage Vs supplied to the first electrode 201 of the photoelectric conversion unit 101, the smaller the value on the right side. That is, even if the capacitance value C1 of the first capacitance 103 is small, the inclination of the potential of the photoelectric conversion layer 205 can be reversed. When the difference between the reset voltage Vres and the voltage Vs supplied to the first electrode 201 is small, the amount of electric charge that can be stored in the photoelectric conversion layer 205 becomes small.

On the other hand, the larger the difference between the reset voltage Vres and the voltage Vs, the larger the value on the right side. That is, a large value is used for the capacity value C1 of the first capacity 103. At this time, since the difference between the reset voltage Vres and the first voltage Vs1 is large, the amount of electric charge that can be stored in the photoelectric conversion layer 205 can be increased.

Due to the balance between the saturated charge amount and the capacitance value C1 of the first capacitance 103, the difference between the reset voltage Vres and the voltage Vs is 20% to 80% of the difference between the first voltage Vs1 and the second voltage Vs2. It is preferably contained in the range of%. For example, when the first voltage Vs1 is 0V and the second voltage Vs2 is 5V, the difference from the reset voltage Vres voltage Vs may be included in the range of 1V to 4V.

In particular, if the difference between the first voltage Vd1 and the second voltage Vd2 is increased, the capacitance value C1 of the first capacitance 103 can be reduced even if the difference between the reset voltage Vres voltage Vs is large. However, when the photoelectric conversion device is used as an image sensor for a camera or the like, a low power supply voltage is used to reduce power consumption. For example, the power supply voltage supplied to the image sensor is often 5 V or less. Therefore, a value of 5 V or less is used for each voltage of the equations (24) to (25). Therefore, it is difficult to increase the difference between the first voltage Vd1 and the second voltage Vd2. In such a case, the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 satisfy the above-mentioned relationship, so that noise is reduced while driving the photoelectric conversion device with a low voltage. be able to.

As described above, noise can be reduced by the relationship between the capacitance value C1 of the first capacitance 103 and the capacitance value C2 of the second capacitance 111 included in the photoelectric conversion unit 101.

The numerical values given above are merely examples, and are not limited to these values. Defect levels and the like may be present at the interface between the photoelectric conversion layer 205 and the insulating layer 207. In such a case, the flat band voltage may be considered based on a known technique.

Next, a method of driving the photoelectric conversion device of this embodiment will be described. FIG. 13 shows a timing chart of the drive signal used in the photoelectric conversion device of this embodiment. FIG. 13 shows a drive signal corresponding to the signal reading operation for the two lines of the nth line and the n + 1th line.

The difference from the driving method of the first embodiment is that the voltage signal Vd is supplied to the node C in FIG. FIG. 13 shows a timing chart of the voltage signal Vd. The voltage signal Vd includes a first voltage Vd1 and a second voltage Vd2. The period in which the voltage signal Vs is the first voltage Vs1 in the first embodiment corresponds to the period in which the voltage signal Vd is the first voltage Vd1 in the present embodiment. The period in which the voltage signal Vs is the second voltage Vs2 in the first embodiment corresponds to the period in which the voltage signal Vd is the second voltage Vd2 in the present embodiment.

The timing charts of the other drive signals are all the same as in FIG. Therefore, detailed description will be omitted.

As described above, in the photoelectric conversion device of this embodiment, the photoelectric conversion layer 205 includes the quantum dots 10. According to such a configuration, the defect level of the photoelectric conversion layer can be reduced. This is because the size of the quantum dot is small, so that the lattice defects inside the quantum dot can be reduced. As a result, noise can be reduced.

Another embodiment will be described. This embodiment is different from the first and second embodiments in that a switch is arranged between the photoelectric conversion unit and the input node of the amplification unit. Therefore, only the part different from the first or second embodiment will be described. The same parts as in either Example 1 or Example 2 will be omitted.

FIG. 14 schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. FIG. 14 shows four pixels 100 in 2 rows and 2 columns. The parts having the same functions as those in FIG. 1A are designated by the same reference numerals. The structure of the photoelectric conversion unit 101 is the same as that of the first embodiment. Therefore, FIG. 14 does not show the cross-sectional structure of the photoelectric conversion unit 101.

In this embodiment, the switch 501 is arranged in the electric path between the photoelectric conversion unit 101 and the first capacitance 103. In other words, the first capacitance 103 is electrically connected to the photoelectric conversion unit 101 via the switch 501. Further, the switch 501 is arranged in the electric path between the photoelectric conversion unit 101 and the amplification transistor 104. In other words, the amplification transistor 104 is electrically connected to the photoelectric conversion unit 101 via the switch 501. The gate of the amplification transistor 104 and the first terminal of the first capacitance are included in the node B.

The switch 501 controls the conduction between the photoelectric conversion unit 101 and the node B. Therefore, when both the switch 501 and the reset transistor 102 are turned off, the node B becomes electrically floating.

A drive signal pGS is supplied to the switch 501. In order to distinguish the drive signal pGS supplied to different lines, a code indicating a line such as (n) or (n + 1) is added.

The configuration of the pixel 100 of this embodiment is the same as that of the first embodiment except that the switch 501 is arranged. Further, the overall configuration of the photoelectric conversion device of this embodiment is also the same as that of the first embodiment.

With such a configuration, the exposure periods of all rows can be matched. A so-called global electronic shutter can be realized. Further, since the drive signal pGS is independently supplied for each row, it is possible to switch between the operation mode for the global electronic shutter and the operation mode for the rolling shutter.

As shown in FIG. 14, in this embodiment, the voltage Vs from the voltage supply unit 110 is supplied to the node A to which the first terminal of the photoelectric conversion unit 101 is connected. Similar to the first embodiment, the voltage supply unit 110 controls the voltage of the node A to at least the first voltage Vs1 and the second voltage Vs2. With such a configuration, the electric charge can be accumulated in the photoelectric conversion unit 101, and the electric charge can be discharged or transferred from the photoelectric conversion unit 101.

Next, a method of driving the photoelectric conversion device of this embodiment will be described. FIG. 15 shows a timing chart of the drive signal used in the photoelectric conversion device of this embodiment. FIG. 15 shows a drive signal corresponding to the signal reading operation for the two lines of the nth line and the n + 1th line.

The difference from the driving method of the first embodiment is that the driving signal pGS is supplied to the switch 501. FIG. 15 shows a timing chart of the drive signal pGS. The switch 501 is turned on when the drive signal pGS is at a high level. When the drive signal pGS is low level, the switch 501 turns off.

The photoelectric conversion device of this embodiment performs a global electronic shutter operation. Before the time t1, the photoelectric conversion unit 101 of the pixel 100 on the nth row and the photoelectric conversion unit 101 of the pixel 100 on the n + 1th row are in a state of accumulating signal charges. Further, before the time t1, the voltage signal Vs (n) on the nth line and the voltage signal Vs (n + 1) on the n + 1th line are both the first voltage Vs1.

At time t1, the drive signal pRES (n) and the drive signal pRES (n + 1) become high level, and the reset transistor 102 of the pixel 100 on the nth row is turned on. As a result, the voltage of the node B of the pixel 100 in the nth row and the voltage of the node B of the pixel 100 in the n + 1th row are reset to the reset voltage Vres, respectively. After that, at time t2, the drive signal pRES (n) and the drive signal pRES (n + 1) become low level, and the reset transistor 102 of each pixel 100 is turned off.

At time t3, the drive signal pGS (n) and the drive signal pGS (n + 1) become high level. As a result, the switch 501 is turned on. Therefore, at this time, the pixel 100 of this embodiment is in the same state as the equivalent circuit shown in FIG.

At time t4, the voltage signal Vs (n) and the voltage signal Vs (n + 1) transition from the first voltage Vs1 to the second voltage Vs2. Subsequently, at time t5, the voltage signal Vs (n) and the voltage signal Vs (n + 1) transition from the second voltage Vs2 to the first voltage Vs1. The signal charge is transferred by the operation from the time t4 to the time t5. Therefore, a voltage Vp is generated in the node B according to the amount of the stored signal charge. The operation at this time is the same as that described with reference to FIG. 6 of the first embodiment. That is, the state of the energy band of the photoelectric conversion unit 101 at this time is shown in FIGS. 6 (b) and 6 (c).

At time t6, the drive signal pGS (n) and the drive signal pGS (n + 1) become low level. As a result, the switch 501 is turned off. As a result, the continuity between the photoelectric conversion unit 101 and the node B is cut off. Therefore, the photoelectric conversion unit 101 can accumulate the signal charge of the next frame while the node B holds the voltage Vp corresponding to the amount of the signal charge of the previous frame. In this embodiment, the pixels 100 in a plurality of rows can perform the above operations in parallel. That is, the photoelectric conversion unit 101 of the pixels 100 in a plurality of rows can start accumulating signal charges at the same time.

In the subsequent operations, the optical signal is read line by line. At time t7, the drive signal pSEL (n) becomes high level. Further, at time t7, the action signal pTS (n) becomes high level. As a result, the amplification transistor 104 of the pixel 100 in the nth row outputs an optical signal. Then, the optical signal output from the pixel 100 in the nth row is held in the capacitance CTS. The optical signal held in the capacitance CTS is output to the output unit 170 for each column after time t9.

From time t10, the optical signal on the n + 1th line is read out. Since this operation is the same as the nth line, the description thereof will be omitted.

By the above operation, the signal can be read by the global electronic shutter operation. In FIG. 15, only the drive signals on the nth row and the n + 1th row are shown. However, the operations from time t1 to time t6 can be performed simultaneously on all lines.

Further, in the present embodiment, the drive signal shown in FIG. 7 may be supplied while keeping the drive signal pGS at a high level. As a result, the signal can be read out by the rolling shutter operation as in the first embodiment.

Also in this embodiment, since the photoelectric conversion layer 205 includes the quantum dots 10, the effect of reducing noise can be obtained.

Another embodiment will be described. This embodiment is different from the first and second embodiments in that a switch is arranged between the photoelectric conversion unit and the input node of the amplification unit. Further, the difference between the present embodiment and the third embodiment is that the voltage of the node A is controlled in the third embodiment, whereas the voltage of the node C is controlled in the present embodiment. Therefore, only the parts different from the first to third embodiments will be described. The same part as any one of the first to third embodiments will be omitted.

FIG. 16 schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. FIG. 14 shows four pixels 100 in 2 rows and 2 columns. The parts having the same functions as those in FIG. 8 are designated by the same reference numerals. The structure of the photoelectric conversion unit 101 is the same as that of the second embodiment. Therefore, FIG. 16 does not show the cross-sectional structure of the photoelectric conversion unit 101.

In this embodiment, the switch 501 is arranged in the electric path between the photoelectric conversion unit 101 and the first capacitance 103. In other words, the first capacitance 103 is electrically connected to the photoelectric conversion unit 101 via the switch 501. Further, the switch 501 is arranged in the electric path between the photoelectric conversion unit 101 and the amplification transistor 104. In other words, the amplification transistor 104 is electrically connected to the photoelectric conversion unit 101 via the switch 501. The gate of the amplification transistor 104 and the first terminal of the first capacitance are included in the node B.

The switch 501 controls the conduction between the photoelectric conversion unit 101 and the node B. Therefore, when both the switch 501 and the reset transistor 102 are turned off, the node B becomes electrically floating.

A drive signal pGS is supplied to the switch 501. In order to distinguish the drive signal pGS supplied to different lines, a code indicating a line such as (n) or (n + 1) is added.

The configuration of the pixel 100 of this embodiment is the same as that of the second embodiment except that the switch 501 is arranged. Further, the overall configuration of the photoelectric conversion device of this embodiment is also the same as that of the second embodiment.

With such a configuration, the exposure periods of all rows can be matched. A so-called global electronic shutter can be realized. Further, since the drive signal pGS is independently supplied for each row, it is possible to switch between the operation mode for the global electronic shutter and the operation mode for the rolling shutter.

As shown in FIG. 16, in this embodiment, the voltage Vd from the voltage supply unit 410 is supplied to the node C that is coupled to the node B via the first capacitance 103. Similar to the second embodiment, the voltage supply unit 410 controls the voltage of the node C to at least the first voltage Vd1 and the second voltage Vd2. With such a configuration, the electric charge can be accumulated in the photoelectric conversion unit 101, and the electric charge can be discharged or transferred from the photoelectric conversion unit 101.

Next, a method of driving the photoelectric conversion device of this embodiment will be described. FIG. 17 shows a timing chart of the drive signal used in the photoelectric conversion device of this embodiment. FIG. 17 shows a drive signal corresponding to the signal reading operation for the two lines of the nth line and the n + 1th line.

The difference from the driving method of the third embodiment is that the voltage signal Vd is supplied to the node C in FIG. FIG. 17 shows a timing chart of the voltage signal Vd. The voltage signal Vd includes a first voltage Vd1 and a second voltage Vd2. The period in which the voltage signal Vs is the first voltage Vs1 in the third embodiment corresponds to the period in which the voltage signal Vd is the first voltage Vd1 in the present embodiment. The period in which the voltage signal Vs is the second voltage Vs2 in the third embodiment corresponds to the period in which the voltage signal Vd is the second voltage Vd2 in the present embodiment.

The timing charts of the other drive signals are all the same as in FIG. Therefore, detailed description will be omitted.

As described above, in this embodiment, the signal can be read out by the global electronic shutter operation. Further, in the present embodiment, the drive signal shown in FIG. 7 may be supplied while keeping the drive signal pGS at a high level. As a result, the signal can be read out by the rolling shutter operation as in the first embodiment.

Also in this embodiment, since the photoelectric conversion layer 205 includes the quantum dots 10, the effect of reducing noise can be obtained.

Another embodiment will be described. The present embodiment is different from the first to fourth embodiments in that the pixels include a clamp circuit connected to the subsequent stage of the amplification unit. Therefore, only the parts different from those of Examples 1 to 4 will be described. The same part as any of Examples 1 to 4 will be omitted.

FIG. 18 schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. FIG. 18 shows four pixels 100 in 2 rows and 2 columns. The parts having the same functions as those in FIG. 1A are designated by the same reference numerals. The structure of the photoelectric conversion unit 101 is the same as that of any of Examples 1 to 4. Therefore, FIG. 18 does not show the cross-sectional structure of the photoelectric conversion unit 101.

In this embodiment, the pixel 100 has two amplification units. The first amplification unit is a source follower circuit including a first amplification transistor 611 and a current source 612. The second amplification unit includes a second amplification transistor 631. The second amplification transistor 631 is connected to the output line 130 via the selection transistor 105. The second amplification transistor 631 and the current source 160 connected to the output line 130 form a source follower circuit.

Pixel 100 has a clamp circuit for performing a global electronic shutter. The clamp circuit includes a clamp switch 621, a clamp capacitance 622, and a clamp voltage supply switch 623. The clamp switch 621 is arranged in an electric path between the node B to which the first capacitance 103 is connected and the input node of the second amplification unit of the pixel 100. The drive signal pGS is supplied to the clamp switch 621. The drive signal pCL is supplied to the clamp voltage supply switch 623.

The clamp circuit clamps the noise signal output by the first amplification unit. After that, the first amplification unit outputs an optical signal, so that the clamp circuit can remove noise such as reset noise included in the optical signal. With such a configuration, it is possible to realize the global electronic shutter operation while removing random noise such as reset noise.

Next, a method of driving the photoelectric conversion device of this embodiment will be described. FIG. 19 shows a timing chart of the drive signal used in the photoelectric conversion device of this embodiment. FIG. 19 shows a drive signal corresponding to the signal reading operation for the two lines of the nth line and the n + 1th line.

The difference from the driving method of the first embodiment is that the driving signal pGS is supplied to the switch 501. FIG. 19 shows a timing chart of the voltage signal Vd. When the drive signal is at a high level, the corresponding switch is turned on. When the drive signal is low level, the corresponding switch turns off.

At time t1, the drive signal pGS (n) and the drive signal pGS (n + 1) become high level. At time t2, the drive signal pRES (n) and the drive signal pRES (n + 1) become high level. Further, at time t2, the drive signal pCL (n) and the drive signal pCL (n + 1) become high levels. After that, at time t3, the drive signal pRES (n) and the drive signal pRES (n + 1) become low level. At time t4, the drive signal pCL (n) and the drive signal pCL (n + 1) become low level. As a result, the clamp circuit of the pixel 100 on the nth row and the n + 1st row clamps the noise signal.

Subsequently, from time t5 to time t6, the voltage signal Vd (n) and the voltage signal Vd (n + 1) become the second voltage Vd2. As a result, the accumulated signal charge is transferred. Since the clamp switch 621 is on, a voltage Vp corresponding to the amount of signal charge is generated in the clamp capacitance 622.

After that, at time t7, the drive signal pGS (n) and the drive signal pGS (n + 1) become low level. As a result, the clamp circuit of the pixel 100 is electrically separated from the photoelectric conversion unit 101.

In the subsequent operations, the optical signal is read line by line. Since this operation is the same as that of the third or fourth embodiment, the description thereof will be omitted.

By the above operation, the global electronic shutter operation can be realized. Further, in this embodiment, the pixel 100 has a clamp circuit. According to such a configuration, random noise such as reset noise can be reduced.

Another embodiment will be described. The present embodiment is different from the first to fifth embodiments in that the pixel includes a sample hold circuit connected to the subsequent stage of the amplification unit. Therefore, only the parts different from those of Examples 1 to 5 will be described. The same part as any one of Examples 1 to 5 will be omitted.

FIG. 20 schematically shows the configuration of the pixel 100 of the photoelectric conversion device of this embodiment. FIG. 20 shows four pixels 100 in 2 rows and 2 columns. The parts having the same functions as those in FIG. 1A or FIG. 18 are designated by the same reference numerals. The structure of the photoelectric conversion unit 101 is the same as that of any of Examples 1 to 5. Therefore, in FIG. 20, the cross-sectional structure of the photoelectric conversion unit 101 is not shown.

In this embodiment, the pixel 100 has two amplification units. The first amplification unit is a source follower circuit including a first amplification transistor 611 and a current source 612. The second amplification unit includes a second amplification transistor 631. The second amplification transistor 631 is connected to the output line 130 via the selection transistor 105. The second amplification transistor 631 and the current source 160 connected to the output line 130 form a source follower circuit.

The pixel 100 has a sample hold circuit (hereinafter, S / H circuit) for performing a global electronic shutter. The pixel 100 has an S / H circuit for a noise signal and an S / H circuit for an optical signal. The S / H circuit for the noise signal holds the noise signal output by the first amplification unit. The S / H circuit for the optical signal holds the optical signal output by the first amplification unit. The S / H circuit for the noise signal includes a capacitance 701, a first switch 711, and a second switch 721. The S / H circuit for optical signals includes a capacitance 702, a first switch 712, and a second switch 722.

With such a configuration, it is possible to realize the global electronic shutter operation while removing random noise such as reset noise.

Subsequently, the driving method of this embodiment will be described. Here, only the driving of the S / H circuit for performing the global electronic shutter operation will be described.

First, with the input node of the first amplification unit reset, the first switch 711 of the S / H circuit for the noise signal of the pixel 100 in all rows is turned on. As a result, the noise signal is held in the capacitance 701. Subsequently, the signal charge transfer operation is performed. This is the same as any one of Examples 1 to 4. Next, the first switch 712 of the S / H circuit for the optical signal of all the pixels 100 is turned on. As a result, the optical signal is held in the capacitance 702. Then, row by row, the second switches 721 and 722 are turned on. As a result, the signal from the pixel 100 is read out row by row. The signal output from the pixel is held in the column circuit 140 as in the first embodiment, and the difference processing for removing noise is performed.

By the above operation, the global electronic shutter operation can be realized. Further, in this embodiment, the pixel 100 has a sample hold circuit. According to such a configuration, random noise such as reset noise can be reduced.

Examples of the imaging system according to the present invention will be described. Examples of the imaging system include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. FIG. 22 shows a block diagram of a digital still camera as an example of an imaging system.

In FIG. 22, 1001 is a barrier for protecting the lens, 1002 is a lens for forming an optical image of a subject on a photoelectric conversion device 1004, and 1003 is a diaphragm for changing the amount of light passing through the lens 1002. Reference numeral 1004 is a photoelectric conversion device described in each of the above-described embodiments, and converts an optical image formed by the lens 1002 as image data. Here, it is assumed that an AD conversion unit is formed on the semiconductor substrate of the photoelectric conversion device 1004. Reference numeral 1007 is a signal processing unit that compresses various corrections and data into the imaging data output from the photoelectric conversion device 1004. In FIG. 22, 1008 is a timing generation unit that outputs various timing signals to the photoelectric conversion device 1004 and the signal processing unit 1007, and 1009 is an overall control unit that controls the entire digital still camera. 1010 is a frame memory unit for temporarily storing image data, 1011 is an interface unit for recording or reading on a recording medium, and 1012 is a detachable semiconductor memory or the like for recording or reading imaging data. It is a recording medium. Reference numeral 1013 is an interface unit for communicating with an external computer or the like. Here, the timing signal or the like may be input from the outside of the imaging system, and if the imaging system has at least a photoelectric conversion device 1004 and a signal processing unit 1007 that processes the imaging signal output from the photoelectric conversion device 1004. Good.

In this embodiment, the configuration in which the photoelectric conversion device 1004 and the AD conversion unit are provided on different semiconductor substrates has been described. However, the photoelectric conversion device 1004 and the AD conversion unit may be formed on the same semiconductor substrate. Further, the photoelectric conversion device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

Further, each pixel 100 may be configured to include a first photoelectric conversion unit 101A and a second photoelectric conversion unit 101B. The signal processing unit 1007 processes the electric charge-based signal generated by the first photoelectric conversion unit 101A and the charge-based signal generated by the second photoelectric conversion unit 101B, and the distance from the photoelectric conversion device 1004 to the subject. It may be configured to retrieve information.

In the embodiment of the imaging system, the photoelectric conversion device 1004 uses the photoelectric conversion devices of Examples 1 to 6. In this way, by applying the embodiment of the present invention to the imaging system, it is possible to acquire an image with reduced noise.

101 Photoelectric conversion unit 102 Reset transistor 103 First capacity 104 Amplification transistor 105 Selective transistor 111 Second capacity 201 First electrode 203 Blocking layer 205 Photoelectric conversion layer 207 Insulation layer 209 Second electrode

Claims (18)

A photoelectric conversion device having a pixel including a photoelectric conversion unit and an amplification transistor including a gate.
A semiconductor substrate in which the source and drain of the amplification transistor are formed, and
A wiring layer arranged between the semiconductor substrate and the photoelectric conversion unit is included.
The photoelectric conversion unit includes a first electrode, a second electrode, a layer containing quantum dots arranged between the first electrode and the second electrode, a layer containing the quantum dots, and the above. Including an insulating layer arranged between the second electrodes and having a thickness of 50 nm or more,
The second electrode and the gate are electrically connected to each other.
The source follower circuit is composed of the amplification transistor and the current source.
The wiring layer, the is connected to the second electrode, viewed contains at least partially overlap capacitance between the first electrode or the second electrode in plan view,
The capacitance includes an upper electrode and a lower electrode arranged between the upper electrode and the semiconductor substrate.
A photoelectric conversion device, characterized in that, in a plan view, the upper electrode and the lower electrode overlap at least partially with the first electrode or the second electrode . A photoelectric conversion device having a pixel including a photoelectric conversion unit and an amplification transistor including a gate.
A semiconductor substrate in which the source and drain of the amplification transistor are formed, and
A wiring layer arranged between the semiconductor substrate and the photoelectric conversion unit is included.
The photoelectric conversion unit includes a first electrode, a second electrode, a layer containing quantum dots arranged between the first electrode and the second electrode, a layer containing the quantum dots, and the above. Includes an insulating layer arranged between the second electrodes and provided to block the current path between the layer containing the quantum dots and the second electrode.
The second electrode and the gate are electrically connected to each other.
The source follower circuit is composed of the amplification transistor and the current source.
The wiring layer, the is connected to the second electrode, viewed contains at least partially overlap capacitance between the first electrode or the second electrode in plan view,
The capacitance includes an upper electrode and a lower electrode arranged between the upper electrode and the semiconductor substrate.
A photoelectric conversion device, characterized in that, in a plan view, the upper electrode and the lower electrode overlap at least partially with the first electrode or the second electrode . The photoelectric conversion unit is arranged between the first electrode and the layer containing the quantum dots, and has a large number of conductive charges opposite to the signal charges generated by ZnO or the layer containing the quantum dots. The photoelectric conversion device according to claim 1 or 2, further comprising a layer containing a semiconductor. The layer containing the quantum dots contains a member of a material different from the material constituting the quantum dots.
The quantum dots are dispersed in the member,
The photoelectric conversion device according to any one of claims 1 to 3, wherein the photoelectric conversion device is characterized in that. The bandgap of the different materials is larger than the bandgap of the materials that make up the quantum dots.
The photoelectric conversion device according to claim 4. The material constituting the quantum dot absorbs light having a wavelength longer than that of the longest wavelength light absorbed by the different materials.
The photoelectric conversion device according to claim 4 or 5. The layer containing the quantum dots includes a coating layer that covers the quantum dots.
The bandgap of the material constituting the coating layer is larger than the bandgap of the material constituting the quantum dot.
The photoelectric conversion device according to any one of claims 1 to 3, wherein the photoelectric conversion device is characterized in that. The layer containing the quantum dots includes a coating layer that covers the quantum dots.
The material constituting the quantum dot absorbs light having a wavelength longer than the light having the longest wavelength absorbed by the material constituting the coating layer.
The photoelectric conversion device according to any one of claims 1 to 3, wherein the photoelectric conversion device is characterized in that. The layer containing the quantum dots includes an embedded layer for embedding the quantum dots.
The bandgap of the material constituting the embedded layer is larger than the bandgap of the material constituting the quantum dot.
The photoelectric conversion device according to any one of claims 1 to 3, wherein the photoelectric conversion device is characterized in that. The layer containing the quantum dots includes an embedded layer for embedding the quantum dots.
The material constituting the quantum dot absorbs light having a wavelength longer than the light having the longest wavelength absorbed by the material constituting the embedded layer.
The photoelectric conversion device according to any one of claims 1 to 3, wherein the photoelectric conversion device is characterized in that. The quantum dots include quantum dots having a particle size in the range of 1 nm to 20 nm.
The photoelectric conversion device according to any one of claims 1 to 10, characterized in that. The layer containing the quantum dots includes a shell that encloses the quantum dots.
The ratio of the lattice constants of the materials constituting the quantum dots to the lattice constants of the materials constituting the shell is included in the range of 0.9 to 1.1.
The photoelectric conversion device according to any one of claims 1 to 11. The material constituting the quantum dot is selected from the group including PbS, PbSe, PbTe, CdS, CdSe, CdTe, C, Si and Ge.
The photoelectric conversion device according to any one of claims 1 to 12, characterized in that. The photoelectric conversion device according to any one of claims 1 to 13, wherein the upper electrode and the lower electrode are made of metal. The photoelectric conversion device according to any one of claims 1 to 13, wherein the capacity is a MIM (Metal Insulator Metal) capacity. The photoelectric conversion device according to any one of claims 1 to 15, wherein the second electrode is electrically connected to the gate via the capacitance. The photoelectric conversion device according to any one of claims 1 to 16 .
An imaging system including a signal processing device that processes a signal from the photoelectric conversion device. Includes two photoelectric conversion units for each pixel.
The signal processing device processes a signal based on the electric charge generated by the two photoelectric conversion units, and acquires distance information from the photoelectric conversion device to the subject.
The imaging system according to claim 17.