JP6783217B2 - Power semiconductor application system - Google Patents

Description

The present invention relates to a power semiconductor application device in which a plurality of power semiconductor devices are incorporated.

Patent Document 1 describes a power semiconductor module as a power semiconductor device provided with a means for outputting a usage history such as a temperature history to the outside, and a power conversion device as a power semiconductor application device incorporating a plurality of power semiconductor devices. Are listed.

Japanese Unexamined Patent Publication No. 2003-92871

The conventional power semiconductor application device incorporates a power semiconductor device having a means for outputting the temperature history to the outside, but the power semiconductor application device is not controlled based on the temperature history of the power semiconductor device. There was a problem. In view of the above problems, the present invention improves the efficiency of a power semiconductor application system including a plurality of power semiconductor application devices by controlling the power semiconductor application device based on the operating temperature of each power semiconductor application device. With the goal.

The power semiconductor application system of the present invention includes a plurality of power semiconductor application devices and a host control device for managing the plurality of power semiconductor application devices, and each power semiconductor application device incorporates a plurality of power semiconductor devices. The host control device includes an operating margin determining unit that determines the operating margin, which is an index indicating the margin until the limit operating temperature of each power semiconductor device is reached, based on the operating temperature of each power semiconductor device, and each power semiconductor. It includes a selection unit that selects at least one power semiconductor application device based on the minimum value of the operating margin of the plurality of power semiconductor devices in the application device.

The power semiconductor application system of the present invention includes a plurality of power semiconductor application devices and a host control device for managing the plurality of power semiconductor application devices, and each power semiconductor application device incorporates a plurality of power semiconductor devices. The host control device includes an operating margin determining unit that determines the operating margin, which is an index indicating the margin until the limit operating temperature of each power semiconductor device is reached, based on the operating temperature of each power semiconductor device, and each power semiconductor. It includes a selection unit that selects at least one power semiconductor application device based on the minimum value of the operating margin of the plurality of power semiconductor devices in the application device. By operating the power semiconductor application device selected by the selection unit next, the possibility of changing the power semiconductor application device during use can be reduced, and the efficiency of the power semiconductor application system can be improved.

It is a block diagram of the power semiconductor application system of Embodiment 1. It is a block diagram which shows the internal structure of a host control device. It is a figure which shows the input data. It is a figure which shows the device information. It is a flowchart which shows the operation of the host control device of Embodiment 1. It is a flowchart which shows the operation of the host control device of Embodiment 2. It is a figure which shows the input data of Embodiment 3. It is a figure which shows the device information of Embodiment 3. It is a figure which shows the input data of Embodiment 4. It is a figure which shows the device information of Embodiment 4. It is a block diagram of the host control apparatus of Embodiment 5. It is a figure which shows the input data of Embodiment 5. It is a figure which shows the device information of Embodiment 5. It is a flowchart which shows the operation of the host control device of Embodiment 5. It is a figure which shows the input data of Embodiment 6. It is a figure which shows the device information of Embodiment 6. It is a flowchart which shows the operation of the host control device of Embodiment 6. It is a figure which shows the hardware configuration of a host control device. It is a figure which shows the hardware configuration of a host control device.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is a block diagram of the power semiconductor application system of the first embodiment.

The power semiconductor application system of the first embodiment includes three power semiconductor application devices 1, 2, 3 and a host control device 4A. Power semiconductor devices 11, 12, and 13 are incorporated in the power semiconductor application device 1, and each of the power semiconductor devices 11, 12, and 13 externally outputs an ID number and a usage history, which are the only specific numbers that can identify the device. It is possible to output to. The configurations of the power semiconductor application devices 2 and 3 are the same as those of the power semiconductor application device 1. The power semiconductor application device 2 has power semiconductor devices 21 and 22, 23, and the power semiconductor application device 3 has power semiconductor devices 31 and 32. , 33 are incorporated respectively. The host control device 4A centrally manages the power semiconductor application devices 1, 2, and 3.

The power semiconductor device 11 is a three-phase inverter including upper and lower arms, and drives a servomotor 14. Similarly, other power semiconductor devices 12 to 13, 21 to 23, 31 to 33 are also three-phase inverters including upper and lower arms, and drive servomotors 15 to 16, 24 to 26, and 34 to 36, respectively.

Although FIG. 1 shows three power semiconductor application devices incorporating three power semiconductor devices, the number of power semiconductor application devices is not limited to three in the power semiconductor application system of the first embodiment. Any number of the above may be used. Further, the number of power semiconductor devices incorporated in each power semiconductor application device is not limited to three, and may be two or more. Further, the number of power semiconductor devices may be different for each power semiconductor application device. Further, a plurality of electric power semiconductor devices may drive one servomotor. Although the servo motor 14 is shown as a drive target of the power semiconductor application device 1 in FIG. 1, the drive target is not limited to the servo motor and may be any motor.

FIG. 2 is a block diagram showing an internal configuration of the host control device 4A in the power semiconductor application system of the first embodiment. The host control device 4A includes an input data storage unit 41, a device information storage unit 42, a temperature storage unit 43, an operation margin determination unit 44, a minimum operation margin update unit 45, and a ranking determination unit 46.

The input data storage unit 41 acquires and stores input data from the power semiconductor devices incorporated in the power semiconductor application devices 1, 2, and 3. As shown in FIG. 3, the input data is data in which the usage history of the power semiconductor device is associated with the ID number Nn which is the identification information of the power semiconductor device. The usage history of the power semiconductor device includes the junction temperature Tj (Nn) of the power semiconductor element of the power semiconductor device.

The device information storage unit 42 stores device information indicating the characteristics of the power semiconductor device incorporated in the power semiconductor application devices 1, 2, and 3. As shown in FIG. 4, the device information is data in which the limit junction temperature Tjmax (Nn) of the power semiconductor element possessed by the power semiconductor device is associated with the ID number Nn which is the identification information of the power semiconductor device.

<A-2. Operation>
FIG. 5 is a flowchart showing the operation of the host control device 4A of the first embodiment. Hereinafter, the operation of the configuration of each part of the host control device 4A shown in FIG. 2 will be described with reference to the flowchart of FIG.

In the flow of FIG. 5, the input data storage unit 41 takes in the ID number and the usage history as input data from the power semiconductor devices 11-13, 21-23, and 31-33 of the power semiconductor application devices 1, 2, and 3. To start with.

First, the operation margin determination unit 44 sets the minimum operation margins f (1) min to f (3) min of the power semiconductor application devices 1 to 3 as initial values (step S101). The minimum operating margin of a power semiconductor application device is the minimum operating margin of a plurality of power semiconductor devices incorporated in the power semiconductor application device.

Next, the operation margin determination unit 44 sets the ID number Nn of the processing target to the initial value (step S102). Here, the initial value of the ID number Nn is 11. Next, the operation margin determination unit 44 reads the junction temperature Tj (Nn) and the limit junction temperature Tjmax (Nn) corresponding to the ID number Nn (step S103).

Specifically, the operation margin determination unit 44 reads the junction temperature Tj (Nn) of the power semiconductor device Nn corresponding to the ID number Nn from the input data (step S103) and stores it in the temperature storage unit 43 (step S104). ). When Nn = 11, here, the junction temperature Tj (11) of the power semiconductor device 11 is read from the input data and stored in the temperature storage unit 43.

Further, the operation margin determination unit 44 reads the limit junction temperature Tjmax (Nn) of the power semiconductor device Nn corresponding to the ID number Nn from the device information storage unit 42. When Nn = 11, here, the limit junction temperature Tjmax (11) of the power semiconductor device 11 is read from the device information storage unit 42.

Then, the operation margin determination unit 44 calculates the temperature difference ΔTjm (Nn) between the limit junction temperature Tjmax (Nn) and the junction temperature Tj (Nn) of the power semiconductor device Nn (step S105). When Nn = 11, here, the temperature difference ΔTjm (11) between the limit junction temperature Tjmax (11) and the junction temperature Tj (11) of the power semiconductor device 11 is calculated. When the temperature difference ΔTjm (Nn) is defined by the equation (1), the temperature difference ΔTjm (11) is expressed by the equation (2).

Further, in step S105, the operation margin determination unit 44 calculates the decreasing slope −∂Tj (Nn) / ∂t of the junction temperature Tj (Nn). When Nn = 11, the decreasing slope −∂Tj (11) / ∂t of the junction temperature Tj (11) is calculated here. The decrease slope −∂Tj (Nn) / ∂t of the junction temperature Tj (Nn) is measured by using the previous junction temperature Tj (Nn) * read from the temperature storage unit 43 and the time Δt from the previous time to the present time. When defined by equation (3), −∂Tj (11) / ∂t is expressed by equation (4).

Next, the operation margin determination unit 44 calculates the operation margin f (Nn) of the power semiconductor device Nn (step S105). The function f (Nn) of the operating margin of the power semiconductor device Nn is expressed as a function using the temperature difference ΔTjm (Nn) and the decreasing slope of the junction temperature Tj (Nn) −∂Tj (Nn) / ∂t. ), The operating margin f (11) of the power semiconductor device 11 is represented by the equation (6).

For example, if f (Nn) is defined by the equation (7) with the waiting time until the start of operation as tw, the temperature difference between the junction temperature Tj (Nn) and the limit junction temperature Tjmax (Nn) at the start of operation is operated. It can be a margin. At this time, the operation margin f (11) is expressed by the equation (8). Hereinafter, equation (7) will be described as a function of the operating margin.

Next, the minimum operating margin updating unit 45 sets the operating margin f (Nn) of the power semiconductor device Nn to the minimum value of the operating margin of the power semiconductor device incorporated in the power semiconductor application device N, that is, the minimum operating margin. Compare with f (N) min (step S107). If f (Nn) <f (N) min, the minimum operation margin updating unit 45 replaces the value of f (N) min with the value of f (Nn) in step S108, and proceeds to step S109. If so, the process proceeds to step S109 as it is. When Nn = 11, in step S107, the operating margin f (11) of the power semiconductor device 11 is compared with the minimum value f (1) min of the operating margin of the power semiconductor devices 11, 12, and 13.

In step S109, the operation margin determination unit 44 determines whether or not the processing has been completed for all the ID numbers. If the processing is not completed for all the ID numbers, the operation margin determination unit 44 updates the ID numbers to be processed to the next number (step S110), and returns to step S103. Here, the next ID number is 12.

The operation margin determination unit 44 calculates the operation margin f (12) for the power semiconductor device 12 in the same manner as for the power semiconductor device 11 (step S106). Then, the minimum operation margin updating unit 45 compares the operation margin f (12) with f (1) min (step S107), and when f (12) <f (1) min, f (1) in step S108. ) Min is replaced with the value of f (12) and the process proceeds to step S109. If not, the process proceeds to step S109 as it is. When step S107 or step S108 is completed for the last ID number (Nn = 33), the operation margin determination unit 44 determines in step S109 that the processing for all ID numbers is completed.

Then, the ranking determination unit 46 ranks the power semiconductor application devices 1, 2, and 3 in descending order of the minimum operating margin f (N) min (step S111). That is, among the power semiconductor devices 11-13, 23, 23, 31-33 incorporated in the power semiconductor application devices 1, 2, and 3, the junction temperature Tj (Nn) at the start of operation and the limit junction temperature Tjmax ( The minimum value of the temperature difference from Nn) is compared as a representative value of each power semiconductor application device, and the power semiconductor application device is ranked in descending order of the representative value. Although the ranking determination unit 46 ranks the power semiconductor application devices here, one power semiconductor application device having the largest minimum operating margin f (N) min may be selected, or the minimum operating margin may be selected. One or more power semiconductor application devices in which the degree f (N) min exceeds the threshold value may be selected. That is, the ranking determination unit 46 functions as a selection unit that selects at least one power semiconductor application device based on the minimum operating margin f (N) min.

This completes the processing of the host control device 4A.

<A-3. Effect>
The power semiconductor application system of the first embodiment includes a plurality of power semiconductor application devices 1, 2, and 3 and a host control device 4A that manages a plurality of power semiconductor application devices 1, 2, and 3, and each power semiconductor application. A plurality of power semiconductor devices 11-13, 23, 23, 31-33 are incorporated in the devices 1, 2, and 3, and the host control device 4A is a power semiconductor device 11-13, 23, 23, 31-33. With the operation margin determination unit 44 that determines the operation margin f, which is an index indicating the margin until the limit operating temperature of each power semiconductor device 11-13, 23, 23, 31-33 is reached, based on the operation temperature of , At least one power semiconductor application device 1, 2, 3 based on the minimum value of the operating margin of the plurality of power semiconductor devices 11-13, 23, 23, 31-33 in each power semiconductor application device 1, 2, 3. It is provided with a ranking determination unit 46, which is a selection unit for selecting. Therefore, among the power semiconductor application devices that are dormant in the power semiconductor application system, the power semiconductor application device selected by the ranking determination unit 46, for example, the power semiconductor application device having the highest rank is set as the device to be operated next. As a result, it is possible to put in a power semiconductor application device having the most operating margin. Therefore, it is possible to reduce the possibility of changing the power semiconductor application device during use and improve the efficiency in the power semiconductor application system.

Further, the operation margin determination unit 44 determines the operation margin f based on the temperature difference between the operating temperature and the limit operating temperature of the electric power semiconductor device 11-13, 23, 23, 31-33 and the decrease inclination of the operating temperature. By determining, the operating margin f can be determined as an index indicating how much margin the power semiconductor device 11-13, 23, 23, 31-33 has before reaching the limit operating temperature.

Further, in the first embodiment, the operating temperature is the joining temperature, and the limit operating temperature is the limit joining temperature. Since the response speed of the joining temperature is faster than that of the case temperature and the like, the operating margin f (Nn) can be determined with high accuracy.

<B. Embodiment 2>
<B-1. Configuration, operation>
The configurations of the power semiconductor application system and the host control device of the second embodiment are as shown in FIGS. 1 and 2, respectively, and are the same as those of the first embodiment. FIG. 6 is a flowchart showing the operation of the host control device 4A of the second embodiment. Hereinafter, the operation of the host control device 4A will be described with reference to the flowchart of FIG.

Since the flow of FIG. 6 is obtained by adding step S112 to the flow of FIG. 5, only the differences from the flow of FIG. 5 will be described. After setting or updating the ID number Nn to be processed to the initial value in step S102 or step S110, the operation margin determination unit 44 determines whether or not the ID number Nn is a designated number (step S112). If the ID number Nn is a designated number, the operation margin determination unit 44 performs the processes after step S103 to calculate the operation margin. However, if the ID number Nn is not the specified number, the operation margin determination unit 44 updates the ID number Nn to be processed (step S110), and returns to step S112 again.

That is, the operation margin determination unit 44 calculates the operation margin only for the power semiconductor device having a predetermined ID number. For example, when the designated ID number is "an ID number having the last digit of 2", the operation margin determination unit 44 calculates the operation margins of the power semiconductor devices 12, 22, and 32. In this case, the operating margins of the power semiconductor devices 12, 22, and 32 are typical values of the power semiconductor application devices 1, 2, and 3. Then, the ranking determination unit 46 ranks the power semiconductor application devices 1, 2, and 3 in descending order of operating margin.

The second embodiment is the first embodiment in which the operation margin is calculated only for the electric power semiconductor device having the designated ID number. This modification is applicable not only to the first embodiment but also to the third to sixth embodiments described later.

<B-2. Effect>
In the second embodiment, the operation margin determination unit 44 determines the operation margin of the power semiconductor device having predetermined identification information. Therefore, the host control device 4A can select the power semiconductor application device to be operated next based only on the operating margin of the power semiconductor device of the part (ID number) required for the next operation. The efficiency of power semiconductor application systems can be improved.

<C. Embodiment 3>
<C-1. Configuration, operation>
The configurations of the power semiconductor application system and the host control device of the third embodiment are as shown in FIGS. 1 and 2, respectively, and are the same as those of the first embodiment.

FIG. 7 shows the input data acquired and stored by the input data storage unit 41 from the power semiconductor device in the third embodiment. FIG. 8 shows the device information stored in the device information storage unit 42 in the third embodiment. As shown in FIGS. 7 and 8, in the third embodiment, the chip temperature Tch (Nn) is included in the input data instead of the junction temperature Tj (Nn) of the first embodiment, and the limit junction temperature Tjmax (Nn) is set. Instead, the limit chip temperature Tchmax (Nn) is included in the input data.

That is, in the power semiconductor application system of the third embodiment, in the first embodiment or the second embodiment, the junction temperature Tj (Nn) is set to the chip temperature Tch (Nn) and the limit junction temperature Tjmax (Nn) is set to the limit chip temperature. For Tchmax (Nn), the temperature difference ΔTjm (Nn) between the limit junction temperature Tjmax (Nn) and the junction temperature Tj (Nn) is set to the temperature difference ΔTchm (Nn) between the limit chip temperature Tchmax (Nn) and the chip temperature Tch (Nn). ), The decreasing slope of the junction temperature Tj (Nn) −∂Tj (Nn) / ∂t is replaced with the decreasing inclination −∂Tch (Nn) / ∂t of the chip temperature Tch (Nn). The temperature difference ΔTchm (Nn) is defined by the formula (9), and the temperature difference ΔTchm (11) is represented by the formula (10).

The decrease slope −∂Tch (Nn) / ∂t of the chip temperature Tch (Nn) is set by using the previous chip temperature Tch (Nn) * read from the temperature storage unit 43 and the time Δt from the previous time to the present time. When defined by the equation (11), the decreasing slope −∂Tch (11) / ∂t of the chip temperature Tch (11) is expressed by the equation (12).

The operation margin determination unit 44 calculates the operation margin g (Nn) of the power semiconductor device Nn. The operating margin g (Nn) of the power semiconductor device Nn is set by the equation (13) as a function using the temperature difference ΔTchm (Nn) and the decreasing slope of the chip temperature Tch (Nn) −∂Tch (Nn) / ∂t. By definition, the operating margin g (11) of the power semiconductor device 11 is represented by the equation (14).

For example, if g (Nn) is defined by the equation (15) with the waiting time until the start of operation as tw, the temperature difference between the chip temperature Tch (Nn) and the limit chip temperature Tchmax (Nn) at the start of operation is operated. It can be a margin. At this time, the operation margin g (11) is represented by the equation (16).

<C-2. Effect>
In the third embodiment, the operation margin determination unit 44 is an index indicating the margin until the limit chip temperature of each power semiconductor device is reached, based on the usage history of the chip temperature of each power semiconductor device. (Nn) is determined. The chip temperature of a power semiconductor element in a power semiconductor device can be measured by mounting a temperature sensor on the surface of the power semiconductor element. Therefore, the configuration of the power semiconductor device can be simplified.

<D. Embodiment 4>
<D-1. Configuration, operation>
The configurations of the power semiconductor application system and the host control device of the fourth embodiment are as shown in FIGS. 1 and 2, respectively, and are the same as those of the first embodiment.

FIG. 9 shows the input data acquired and stored by the input data storage unit 41 from the power semiconductor device in the fourth embodiment. FIG. 10 shows the device information stored in the device information storage unit 42 in the fourth embodiment. As shown in FIGS. 9 and 10, in the fourth embodiment, the case temperature Tc (Nn) is included in the input data instead of the junction temperature Tj (Nn) of the first embodiment, and the limit junction temperature Tjmax (Nn) is set. Instead, the critical case temperature Tcmax (Nn) is included in the input data.

That is, in the power semiconductor application system of the fourth embodiment, in the first embodiment or the second embodiment, the junction temperature Tj (Nn) is set to the case temperature Tc (Nn) of the power semiconductor device, and the limit junction temperature Tjmax (Nn). The temperature difference between the limit junction temperature Tjmax (Nn) and the junction temperature Tj (Nn) is set to the limit case temperature Tcmax (Nn) of the electric power semiconductor device, and the temperature difference ΔTjm (Nn) is set to the limit case temperature Tcmax (Nn) and the case temperature Tc (Nn). ), The decrease gradient of the junction temperature Tj (Nn) −∂Tj (Nn) / ∂t is set to the decrease gradient of the case temperature Tc (Nn) −∂Tc (Nn) / ∂t. Each is replaced. The temperature difference ΔTcm (Nn) is defined by the formula (17), and the temperature difference ΔTcm (11) is represented by the formula (18).

Further, the decreasing slope −∂Tc (Nn) / ∂t of the case temperature Tc (Nn) of the power semiconductor device is set to the case temperature Tc (Nn) * of the previous power semiconductor device and the time Δt from the previous time to the present time. When defined by the equation (19), the decreasing slope −∂Tc (11) / ∂t of the case temperature Tc (11) is expressed by the equation (20).

The operation margin determination unit 44 calculates the operation margin h (Nn) of the power semiconductor device Nn. The operating margin h (Nn) is defined by Eq. (21) as a function using the temperature difference ΔTcm (Nn) and the decreasing slope of the case temperature Tc (Nn) −∂Tc (Nn) / ∂t. The operating margin h (11) of the device 11 is represented by the equation (22).

For example, if h (Nn) is defined by the equation (23) with the waiting time until the start of operation as tw, the temperature difference between the case temperature Tc (Nn) and the limit case temperature Tcmax (Nn) at the start of operation is operated. It can be a margin. At this time, the operation margin h (11) is expressed by the equation (24).

<D-2. Effect>
In the fourth embodiment, the operation margin determination unit 44 is an index indicating the margin until the limit case temperature of each power semiconductor device is reached based on the usage history of the case temperature of each power semiconductor device. (Nn) is determined. The case temperature of the power semiconductor device becomes substantially the same as the junction temperature of the power semiconductor element in the power semiconductor device after a certain pause time. Therefore, if there is a certain pause time, the case temperature can be used as a substitute for the joining temperature, and in this case, the limit case temperature can be used as a substitute for the limit joining temperature. Further, since the case temperature of the power semiconductor device can be measured by mounting a temperature sensor on the base plate of the power semiconductor device or a portion corresponding thereto, the configuration of the power semiconductor device can be simplified as compared with the third embodiment. ..

<E. Embodiment 5>
<E-1. Configuration, operation>
The configuration of the power semiconductor application system of the fifth embodiment is as shown in FIG. 1, and is the same as that of the power semiconductor application system of the first embodiment. FIG. 11 is a configuration diagram of the host control device 4B according to the fifth embodiment. In the host control device 4B of the fifth embodiment, the operation margin determination unit 44 includes the temperature calculation unit 441, and is the same as the host control device 4A of the first embodiment shown in FIG. 2 in other respects. ..

FIG. 12 shows the input data acquired and stored by the input data storage unit 41 from the power semiconductor device in the fifth embodiment. FIG. 13 shows the device information stored in the device information storage unit 42 in the fifth embodiment. As shown in FIG. 12, in the input data of the fifth embodiment, the usage history includes the collector current Ic (Nn), the switching frequency fsw (Nn), and the case temperature Tc (Nn). Further, as shown in FIG. 13, the device information includes the limit junction temperature Tjmax (Nn) of the power semiconductor element of the power semiconductor device, the collector-emitter saturation voltage VCEsat (Ic) (Nn), and the switching loss energy Esw (Ic). ) (Nn) and the junction-case thermal resistance Rth (jc) (Nn) are associated with the ID number Nn, which is the identification information of the power semiconductor device.

FIG. 14 is a flowchart showing the operation of the host control device 4B according to the fifth embodiment. Hereinafter, the operation of the host control device 4B of the fifth embodiment will be described with reference to the flowchart of FIG. Since the flow of FIG. 14 replaces step S103 of the flow of FIG. 5 with steps S113, S114, and S115, only the differences from the flow of FIG. 5 will be described.

After setting or updating the ID number Nn to be processed to the initial value in step S102 or step S110, the operation margin determination unit 44 records the collector current Ic (Nn) as the usage history of the power semiconductor device corresponding to the ID number Nn from the input data. ), The switching frequency fsw (Nn), and the case temperature Tc (Nn) are read (step S113).

Further, the operation margin determination unit 44 receives device information of the power semiconductor device corresponding to the ID number Nn from the device information storage unit 42, such as the limit junction temperature Tjmax (Nn) and the collector-emitter saturation voltage VCEsat (Ic) (Nn). , Switching loss energy Esw (Ic) (Nn), and junction-case thermal resistance Rth (j-c) (Nn) are read (step S114).

Next, the temperature calculation unit 441 calculates the junction temperature Tj (Nn) by the following formula based on the information read in step S113 and step S114 (step S115).

<E-2. Effect>
In the fifth embodiment, the operation margin determination unit 44 determines the power semiconductor device 11-13, 21-23-based on the usage history excluding the junction temperature Tj (Nn) of the power semiconductor device 11-13, 23, 23, 31-33. The junction temperature Tj (Nn) of 23, 31-33 is calculated, and the operating margin f (Nn) is determined based on the calculated junction temperature Tj (Nn). Therefore, even if the junction temperature of the power semiconductor device is not in the usage history, the operating margin of each power semiconductor device incorporated in the power semiconductor application device can be determined. Therefore, among the power semiconductor application devices that are dormant in the power semiconductor application system, the power semiconductor application device selected by the ranking determination unit 46, for example, the power semiconductor application device having the highest rank is set as the device to be operated next. As a result, it is possible to put in a power semiconductor application device having the most operating margin. Therefore, it is possible to reduce the possibility of changing the power semiconductor application device during use and improve the efficiency in the power semiconductor application system.

Further, the usage history of the power semiconductor device 11-13, 23, 23, 31-33 excluding the junction temperature Tj (Nn) is the collector current Ic (Nn) of the power semiconductor device 11-13, 23, 23, 31-33. , Switching frequency fsw (Nn) and case temperature Tc (Nn). That is, the operation margin determination unit 44 is a power semiconductor device based on the collector current Ic (Nn), the switching frequency fsw (Nn), and the case temperature Tc (Nn) of the power semiconductor device 11-13, 23, 23, 31-33. The junction temperature Tj (Nn) is calculated, and the operating margin f (Nn) is determined based on the calculated junction temperature Tj (Nn). Therefore, even if the junction temperature Tj (Nn) of the power semiconductor devices 11-13, 23, 23, and 31-33 is not in the usage history, each power semiconductor device 11- incorporated in the power semiconductor application devices 1, 2, and 3 The operating margin f (Nn) of 13, 21-23, 31-33 can be determined.

<F. Embodiment 6>
<F-1. Configuration, operation>
The configurations of the power semiconductor application system and the host control device of the sixth embodiment are as shown in FIGS. 1 and 11, respectively, and are the same as those of the fifth embodiment.

FIG. 15 shows the input data acquired and stored by the input data storage unit 41 from the power semiconductor device in the sixth embodiment. FIG. 16 shows the device information stored in the device information storage unit 42 in the sixth embodiment. As shown in FIG. 15, in the input data of the sixth embodiment, the usage history includes the occurrence loss P (Nn) and the case temperature Tc (Nn). Further, as shown in FIG. 16, the device information includes the limit junction temperature Tjmax (Nn) of the power semiconductor device and the thermal resistance between the junction and the case Rth (jc) (Nn) of the power semiconductor device. It is the data associated with the ID number Nn which is the identification information of.

FIG. 17 is a flowchart showing the operation of the host control device 4B according to the sixth embodiment. Hereinafter, the operation of the host control device 4B of the fifth embodiment will be described with reference to the flowchart of FIG. Since the flow of FIG. 17 replaces step S103 of the flow of FIG. 5 with steps S116, S117, and S118, only the differences from the flow of FIG. 5 will be described.

After setting or updating the ID number Nn to be processed to the initial value in step S102 or step S110, the operation margin determination unit 44 generates a loss P (Nn) as a usage history of the power semiconductor device corresponding to the ID number Nn from the input data. ) And the case temperature Tc (Nn) are read (step S116).

Further, the operation margin determination unit 44 receives device information of the power semiconductor device corresponding to the ID number Nn from the device information storage unit 42, such as the limit junction temperature Tjmax (Nn) and the junction-case thermal resistance Rth (j-c) ( Nn) is read (step S117).

Next, the temperature calculation unit 441 calculates the junction temperature Tj (Nn) by the following formula based on the information read in step S116 and step S117 (step S118).

<F-2. Effect>
In the sixth embodiment, the usage history excluding the junction temperature Tj (Nn) of the power semiconductor device 11-13, 23, 23, 31-33 is the occurrence loss of the power semiconductor device 11-13, 23, 23, 31-33. P (Nn) and case temperature Tc (Nn). That is, the operation margin determination unit 44 determines the junction temperature Tj (Nn) of the power semiconductor device based on the generated loss P (Nn) and the case temperature Tc (Nn) of the power semiconductor device 11-13, 23, 23, 31-33. Is calculated, and the operating margin f (Nn) is determined based on the calculated junction temperature Tj (Nn). Therefore, even if the junction temperature Tj (Nn) of the power semiconductor devices 11-13, 23, 23, and 31-33 is not in the usage history, each power semiconductor device 11- incorporated in the power semiconductor application devices 1, 2, and 3 The operating margin f (Nn) of 13, 21-23, 31-33 can be determined.

<G. Hardware configuration>
In the host control devices 4A and 4B described above, the input data storage unit 41, the device information storage unit 42, the temperature storage unit 43, the operation margin determination unit 44, the minimum operation margin update unit 45, and the ranking determination unit 46 are shown in FIG. It is realized by the processing circuit 81 shown in. That is, the processing circuit 81 includes an input data storage unit 41, a device information storage unit 42, a temperature storage unit 43, an operation margin determination unit 44, a minimum operation margin update unit 45, and a ranking determination unit 46 (hereinafter, “operation margin determination”). It is referred to as "part 44, etc."). Dedicated hardware may be applied to the processing circuit 81, or a processor that executes a program stored in the memory may be applied. The processor is, for example, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a DSP (Digital Signal Processor), or the like.

When the processing circuit 81 is dedicated hardware, the processing circuit 81 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field-Programmable). Gate Array), or a combination of these. Each function of each part such as the operation margin determination unit 44 may be realized by a plurality of processing circuits 81, or the functions of each part may be collectively realized by one processing circuit.

When the processing circuit 81 is a processor, the functions of the operation margin determination unit 44 and the like are realized by combining software and the like (software, firmware or software and firmware). Software and the like are described as programs and stored in memory. As shown in FIG. 19, the processor 82 applied to the processing circuit 81 realizes the functions of each part by reading and executing the program stored in the memory 83. That is, when the host control devices 4A and 4B are executed by the processing circuit 81, each power semiconductor device 11-13, 21 is based on the operating temperature of each power semiconductor device 11-13, 21-23, 31-33. A step of determining the operating margin f (Nn), which is an index indicating the margin until the limit operating temperature of -23, 31-33 is reached, and a plurality of power semiconductor devices in each power semiconductor application device 1, 2, 3. As a result, steps of selecting at least one power semiconductor application device 1, 2, 3 based on the minimum value of the operating margin f (Nn) of 11-13, 23, 23, 31-33 are executed. A memory 83 for storing a program to be used is provided. In other words, it can be said that this program causes the computer to execute the procedure or method of the operation margin determination unit 44 or the like. Here, the memory 83 includes, for example, non-volatile such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), and EEPROM (Electrically Erasable Programmable Read Only Memory). Or in volatile semiconductor memory, HDD (Hard Disk Drive), magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disk) and its drive device, etc., or any storage medium used in the future. There may be.

The configuration in which each function of the operation margin determination unit 44 and the like is realized by either hardware or software has been described above. However, the present invention is not limited to this, and a configuration may be configured in which a part of the operation margin determination unit 44 or the like is realized by dedicated hardware and another part is realized by software or the like. For example, the operation margin determination unit 44 realizes its function by a processing circuit as dedicated hardware, and the processing circuit 81 as a processor 82 reads and executes a program stored in the memory 83 in other cases. It is possible to realize the function by.

As described above, the processing circuit can realize each of the above-mentioned functions by hardware, software, or a combination thereof. A part of the configuration of the input data storage unit 41, the device information storage unit 42, and the temperature storage unit 43 are composed of the memory 83, but they may be composed of a single memory 83, or each of them. May consist of separate memories.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

1,2,3 Power semiconductor application device, 4A, 4B host control device, 11,12,13,21,22,23,31,32,33 Power semiconductor device, 14,15,16,24,25,26, 34, 35, 36 Servo motor, 41 Input data storage unit, 42 Device information storage unit, 43 Temperature storage unit, 44 Operation margin determination unit, 45 Minimum operation margin update unit, 46 Ranking determination unit, 81 Processing circuit, 82 CPU, 83 memory, 441 temperature calculation unit.

Claims (9)

With multiple power semiconductor application devices,
A host control device for managing the plurality of power semiconductor application devices is provided.
A plurality of power semiconductor devices are incorporated in each of the power semiconductor application devices.
The host control device is
Based on the operating temperature of each power semiconductor device, an operating margin determining unit that determines the operating margin, which is an index indicating the margin until reaching the limit operating temperature of each power semiconductor device,
Each power semiconductor application device includes a selection unit that selects at least one power semiconductor application device based on the minimum value of the operation margin of the plurality of power semiconductor devices.
Power semiconductor application system. The operating margin determining unit determines only the operating margin of the power semiconductor device having predetermined identification information.
The power semiconductor application system according to claim 1. The operating margin determining unit determines the operating margin based on the temperature difference between the operating temperature and the limit operating temperature of the power semiconductor device and the decrease slope of the operating temperature.
The power semiconductor application system according to claim 1 or 2. The operating temperature is the junction temperature, and the limit operating temperature is the marginal junction temperature.
The power semiconductor application system according to any one of claims 1 to 3. The operating temperature is the chip temperature, and the limit operating temperature is the limit chip temperature.
The power semiconductor application system according to any one of claims 1 to 3. The operating temperature is the case temperature, and the limit operating temperature is the limit case temperature.
The power semiconductor application system according to any one of claims 1 to 3. The operation margin determining unit calculates the junction temperature of the power semiconductor device based on the usage history excluding the junction temperature of the power semiconductor device, and determines the operation margin based on the calculated junction temperature.
The power semiconductor application system according to claim 4. The usage history excluding the junction temperature of the power semiconductor device is the collector current, switching frequency, and case temperature of the power semiconductor device.
The power semiconductor application system according to claim 7. The usage history excluding the junction temperature of the power semiconductor device is the generation loss and the case temperature of the power semiconductor device.
The power semiconductor application system according to claim 7.

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